arch/arm64/kvm/hyp/include/hyp/switch.h

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  */
   6
   7 #ifndef __ARM64_KVM_HYP_SWITCH_H__
   8 #define __ARM64_KVM_HYP_SWITCH_H__
   9
  10 #include <hyp/adjust_pc.h>
  11 #include <hyp/fault.h>
  12
  13 #include <linux/arm-smccc.h>
  14 #include <linux/kvm_host.h>
  15 #include <linux/types.h>
  16 #include <linux/jump_label.h>
  17 #include <uapi/linux/psci.h>
  18
  19 #include <kvm/arm_psci.h>
  20
  21 #include <asm/barrier.h>
  22 #include <asm/cpufeature.h>
  23 #include <asm/extable.h>
  24 #include <asm/kprobes.h>
  25 #include <asm/kvm_asm.h>
  26 #include <asm/kvm_emulate.h>
  27 #include <asm/kvm_hyp.h>
  28 #include <asm/kvm_mmu.h>
  29 #include <asm/kvm_nested.h>
  30 #include <asm/fpsimd.h>
  31 #include <asm/debug-monitors.h>
  32 #include <asm/processor.h>
  33
  34 struct kvm_exception_table_entry {
  35         int insn, fixup;
  36 };
  37
  38 extern struct kvm_exception_table_entry __start___kvm_ex_table;
  39 extern struct kvm_exception_table_entry __stop___kvm_ex_table;
  40
  41 /* Check whether the FP regs are owned by the guest */
  42 static inline bool guest_owns_fp_regs(struct kvm_vcpu *vcpu)
  43 {
  44         return vcpu->arch.fp_state == FP_STATE_GUEST_OWNED;
  45 }
  46
  47 /* Save the 32-bit only FPSIMD system register state */
  48 static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
  49 {
  50         if (!vcpu_el1_is_32bit(vcpu))
  51                 return;
  52
  53         __vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2);
  54 }
  55
  56 static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
  57 {
  58         /*
  59          * We are about to set CPTR_EL2.TFP to trap all floating point
  60          * register accesses to EL2, however, the ARM ARM clearly states that
  61          * traps are only taken to EL2 if the operation would not otherwise
  62          * trap to EL1.  Therefore, always make sure that for 32-bit guests,
  63          * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
  64          * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
  65          * it will cause an exception.
  66          */
  67         if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
  68                 write_sysreg(1 << 30, fpexc32_el2);
  69                 isb();
  70         }
  71 }
  72
  73 static inline bool __hfgxtr_traps_required(void)
  74 {
  75         if (cpus_have_final_cap(ARM64_SME))
  76                 return true;
  77
  78         if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38))
  79                 return true;
  80
  81         return false;
  82 }
  83
  84 static inline void __activate_traps_hfgxtr(void)
  85 {
  86         u64 r_clr = 0, w_clr = 0, r_set = 0, w_set = 0, tmp;
  87
  88         if (cpus_have_final_cap(ARM64_SME)) {
  89                 tmp = HFGxTR_EL2_nSMPRI_EL1_MASK | HFGxTR_EL2_nTPIDR2_EL0_MASK;
  90
  91                 r_clr |= tmp;
  92                 w_clr |= tmp;
  93         }
  94
  95         /*
  96          * Trap guest writes to TCR_EL1 to prevent it from enabling HA or HD.
  97          */
  98         if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38))
  99                 w_set |= HFGxTR_EL2_TCR_EL1_MASK;
 100
 101         sysreg_clear_set_s(SYS_HFGRTR_EL2, r_clr, r_set);
 102         sysreg_clear_set_s(SYS_HFGWTR_EL2, w_clr, w_set);
 103 }
 104
 105 static inline void __deactivate_traps_hfgxtr(void)
 106 {
 107         u64 r_clr = 0, w_clr = 0, r_set = 0, w_set = 0, tmp;
 108
 109         if (cpus_have_final_cap(ARM64_SME)) {
 110                 tmp = HFGxTR_EL2_nSMPRI_EL1_MASK | HFGxTR_EL2_nTPIDR2_EL0_MASK;
 111
 112                 r_set |= tmp;
 113                 w_set |= tmp;
 114         }
 115
 116         if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38))
 117                 w_clr |= HFGxTR_EL2_TCR_EL1_MASK;
 118
 119         sysreg_clear_set_s(SYS_HFGRTR_EL2, r_clr, r_set);
 120         sysreg_clear_set_s(SYS_HFGWTR_EL2, w_clr, w_set);
 121 }
 122
 123 static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
 124 {
 125         /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
 126         write_sysreg(1 << 15, hstr_el2);
 127
 128         /*
 129          * Make sure we trap PMU access from EL0 to EL2. Also sanitize
 130          * PMSELR_EL0 to make sure it never contains the cycle
 131          * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
 132          * EL1 instead of being trapped to EL2.
 133          */
 134         if (kvm_arm_support_pmu_v3()) {
 135                 struct kvm_cpu_context *hctxt;
 136
 137                 write_sysreg(0, pmselr_el0);
 138
 139                 hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
 140                 ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0);
 141                 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
 142                 vcpu_set_flag(vcpu, PMUSERENR_ON_CPU);
 143         }
 144
 145         vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2);
 146         write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2);
 147
 148         if (__hfgxtr_traps_required())
 149                 __activate_traps_hfgxtr();
 150 }
 151
 152 static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
 153 {
 154         write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2);
 155
 156         write_sysreg(0, hstr_el2);
 157         if (kvm_arm_support_pmu_v3()) {
 158                 struct kvm_cpu_context *hctxt;
 159
 160                 hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt;
 161                 write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0);
 162                 vcpu_clear_flag(vcpu, PMUSERENR_ON_CPU);
 163         }
 164
 165         if (__hfgxtr_traps_required())
 166                 __deactivate_traps_hfgxtr();
 167 }
 168
 169 static inline void ___activate_traps(struct kvm_vcpu *vcpu)
 170 {
 171         u64 hcr = vcpu->arch.hcr_el2;
 172
 173         if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
 174                 hcr |= HCR_TVM;
 175
 176         write_sysreg(hcr, hcr_el2);
 177
 178         if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
 179                 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2);
 180
 181         if (cpus_have_final_cap(ARM64_HAS_HCX))
 182                 write_sysreg_s(HCRX_GUEST_FLAGS, SYS_HCRX_EL2);
 183 }
 184
 185 static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
 186 {
 187         /*
 188          * If we pended a virtual abort, preserve it until it gets
 189          * cleared. See D1.14.3 (Virtual Interrupts) for details, but
 190          * the crucial bit is "On taking a vSError interrupt,
 191          * HCR_EL2.VSE is cleared to 0."
 192          */
 193         if (vcpu->arch.hcr_el2 & HCR_VSE) {
 194                 vcpu->arch.hcr_el2 &= ~HCR_VSE;
 195                 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
 196         }
 197
 198         if (cpus_have_final_cap(ARM64_HAS_HCX))
 199                 write_sysreg_s(HCRX_HOST_FLAGS, SYS_HCRX_EL2);
 200 }
 201
 202 static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
 203 {
 204         return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault);
 205 }
 206
 207 static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
 208 {
 209         sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
 210         __sve_restore_state(vcpu_sve_pffr(vcpu),
 211                             &vcpu->arch.ctxt.fp_regs.fpsr);
 212         write_sysreg_el1(__vcpu_sys_reg(vcpu, ZCR_EL1), SYS_ZCR);
 213 }
 214
 215 /*
 216  * We trap the first access to the FP/SIMD to save the host context and
 217  * restore the guest context lazily.
 218  * If FP/SIMD is not implemented, handle the trap and inject an undefined
 219  * instruction exception to the guest. Similarly for trapped SVE accesses.
 220  */
 221 static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
 222 {
 223         bool sve_guest;
 224         u8 esr_ec;
 225         u64 reg;
 226
 227         if (!system_supports_fpsimd())
 228                 return false;
 229
 230         sve_guest = vcpu_has_sve(vcpu);
 231         esr_ec = kvm_vcpu_trap_get_class(vcpu);
 232
 233         /* Only handle traps the vCPU can support here: */
 234         switch (esr_ec) {
 235         case ESR_ELx_EC_FP_ASIMD:
 236                 break;
 237         case ESR_ELx_EC_SVE:
 238                 if (!sve_guest)
 239                         return false;
 240                 break;
 241         default:
 242                 return false;
 243         }
 244
 245         /* Valid trap.  Switch the context: */
 246
 247         /* First disable enough traps to allow us to update the registers */
 248         if (has_vhe() || has_hvhe()) {
 249                 reg = CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN;
 250                 if (sve_guest)
 251                         reg |= CPACR_EL1_ZEN_EL0EN | CPACR_EL1_ZEN_EL1EN;
 252
 253                 sysreg_clear_set(cpacr_el1, 0, reg);
 254         } else {
 255                 reg = CPTR_EL2_TFP;
 256                 if (sve_guest)
 257                         reg |= CPTR_EL2_TZ;
 258
 259                 sysreg_clear_set(cptr_el2, reg, 0);
 260         }
 261         isb();
 262
 263         /* Write out the host state if it's in the registers */
 264         if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED)
 265                 __fpsimd_save_state(vcpu->arch.host_fpsimd_state);
 266
 267         /* Restore the guest state */
 268         if (sve_guest)
 269                 __hyp_sve_restore_guest(vcpu);
 270         else
 271                 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
 272
 273         /* Skip restoring fpexc32 for AArch64 guests */
 274         if (!(read_sysreg(hcr_el2) & HCR_RW))
 275                 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
 276
 277         vcpu->arch.fp_state = FP_STATE_GUEST_OWNED;
 278
 279         return true;
 280 }
 281
 282 static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
 283 {
 284         u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
 285         int rt = kvm_vcpu_sys_get_rt(vcpu);
 286         u64 val = vcpu_get_reg(vcpu, rt);
 287
 288         /*
 289          * The normal sysreg handling code expects to see the traps,
 290          * let's not do anything here.
 291          */
 292         if (vcpu->arch.hcr_el2 & HCR_TVM)
 293                 return false;
 294
 295         switch (sysreg) {
 296         case SYS_SCTLR_EL1:
 297                 write_sysreg_el1(val, SYS_SCTLR);
 298                 break;
 299         case SYS_TTBR0_EL1:
 300                 write_sysreg_el1(val, SYS_TTBR0);
 301                 break;
 302         case SYS_TTBR1_EL1:
 303                 write_sysreg_el1(val, SYS_TTBR1);
 304                 break;
 305         case SYS_TCR_EL1:
 306                 write_sysreg_el1(val, SYS_TCR);
 307                 break;
 308         case SYS_ESR_EL1:
 309                 write_sysreg_el1(val, SYS_ESR);
 310                 break;
 311         case SYS_FAR_EL1:
 312                 write_sysreg_el1(val, SYS_FAR);
 313                 break;
 314         case SYS_AFSR0_EL1:
 315                 write_sysreg_el1(val, SYS_AFSR0);
 316                 break;
 317         case SYS_AFSR1_EL1:
 318                 write_sysreg_el1(val, SYS_AFSR1);
 319                 break;
 320         case SYS_MAIR_EL1:
 321                 write_sysreg_el1(val, SYS_MAIR);
 322                 break;
 323         case SYS_AMAIR_EL1:
 324                 write_sysreg_el1(val, SYS_AMAIR);
 325                 break;
 326         case SYS_CONTEXTIDR_EL1:
 327                 write_sysreg_el1(val, SYS_CONTEXTIDR);
 328                 break;
 329         default:
 330                 return false;
 331         }
 332
 333         __kvm_skip_instr(vcpu);
 334         return true;
 335 }
 336
 337 static inline bool esr_is_ptrauth_trap(u64 esr)
 338 {
 339         switch (esr_sys64_to_sysreg(esr)) {
 340         case SYS_APIAKEYLO_EL1:
 341         case SYS_APIAKEYHI_EL1:
 342         case SYS_APIBKEYLO_EL1:
 343         case SYS_APIBKEYHI_EL1:
 344         case SYS_APDAKEYLO_EL1:
 345         case SYS_APDAKEYHI_EL1:
 346         case SYS_APDBKEYLO_EL1:
 347         case SYS_APDBKEYHI_EL1:
 348         case SYS_APGAKEYLO_EL1:
 349         case SYS_APGAKEYHI_EL1:
 350                 return true;
 351         }
 352
 353         return false;
 354 }
 355
 356 #define __ptrauth_save_key(ctxt, key)                                   \
 357         do {                                                            \
 358         u64 __val;                                                      \
 359         __val = read_sysreg_s(SYS_ ## key ## KEYLO_EL1);                \
 360         ctxt_sys_reg(ctxt, key ## KEYLO_EL1) = __val;                   \
 361         __val = read_sysreg_s(SYS_ ## key ## KEYHI_EL1);                \
 362         ctxt_sys_reg(ctxt, key ## KEYHI_EL1) = __val;                   \
 363 } while(0)
 364
 365 DECLARE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
 366
 367 static bool kvm_hyp_handle_ptrauth(struct kvm_vcpu *vcpu, u64 *exit_code)
 368 {
 369         struct kvm_cpu_context *ctxt;
 370         u64 val;
 371
 372         if (!vcpu_has_ptrauth(vcpu))
 373                 return false;
 374
 375         ctxt = this_cpu_ptr(&kvm_hyp_ctxt);
 376         __ptrauth_save_key(ctxt, APIA);
 377         __ptrauth_save_key(ctxt, APIB);
 378         __ptrauth_save_key(ctxt, APDA);
 379         __ptrauth_save_key(ctxt, APDB);
 380         __ptrauth_save_key(ctxt, APGA);
 381
 382         vcpu_ptrauth_enable(vcpu);
 383
 384         val = read_sysreg(hcr_el2);
 385         val |= (HCR_API | HCR_APK);
 386         write_sysreg(val, hcr_el2);
 387
 388         return true;
 389 }
 390
 391 static bool kvm_hyp_handle_cntpct(struct kvm_vcpu *vcpu)
 392 {
 393         struct arch_timer_context *ctxt;
 394         u32 sysreg;
 395         u64 val;
 396
 397         /*
 398          * We only get here for 64bit guests, 32bit guests will hit
 399          * the long and winding road all the way to the standard
 400          * handling. Yes, it sucks to be irrelevant.
 401          */
 402         sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
 403
 404         switch (sysreg) {
 405         case SYS_CNTPCT_EL0:
 406         case SYS_CNTPCTSS_EL0:
 407                 if (vcpu_has_nv(vcpu)) {
 408                         if (is_hyp_ctxt(vcpu)) {
 409                                 ctxt = vcpu_hptimer(vcpu);
 410                                 break;
 411                         }
 412
 413                         /* Check for guest hypervisor trapping */
 414                         val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
 415                         if (!vcpu_el2_e2h_is_set(vcpu))
 416                                 val = (val & CNTHCTL_EL1PCTEN) << 10;
 417
 418                         if (!(val & (CNTHCTL_EL1PCTEN << 10)))
 419                                 return false;
 420                 }
 421
 422                 ctxt = vcpu_ptimer(vcpu);
 423                 break;
 424         default:
 425                 return false;
 426         }
 427
 428         val = arch_timer_read_cntpct_el0();
 429
 430         if (ctxt->offset.vm_offset)
 431                 val -= *kern_hyp_va(ctxt->offset.vm_offset);
 432         if (ctxt->offset.vcpu_offset)
 433                 val -= *kern_hyp_va(ctxt->offset.vcpu_offset);
 434
 435         vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
 436         __kvm_skip_instr(vcpu);
 437         return true;
 438 }
 439
 440 static bool handle_ampere1_tcr(struct kvm_vcpu *vcpu)
 441 {
 442         u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
 443         int rt = kvm_vcpu_sys_get_rt(vcpu);
 444         u64 val = vcpu_get_reg(vcpu, rt);
 445
 446         if (sysreg != SYS_TCR_EL1)
 447                 return false;
 448
 449         /*
 450          * Affected parts do not advertise support for hardware Access Flag /
 451          * Dirty state management in ID_AA64MMFR1_EL1.HAFDBS, but the underlying
 452          * control bits are still functional. The architecture requires these be
 453          * RES0 on systems that do not implement FEAT_HAFDBS.
 454          *
 455          * Uphold the requirements of the architecture by masking guest writes
 456          * to TCR_EL1.{HA,HD} here.
 457          */
 458         val &= ~(TCR_HD | TCR_HA);
 459         write_sysreg_el1(val, SYS_TCR);
 460         return true;
 461 }
 462
 463 static bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
 464 {
 465         if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
 466             handle_tx2_tvm(vcpu))
 467                 return true;
 468
 469         if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) &&
 470             handle_ampere1_tcr(vcpu))
 471                 return true;
 472
 473         if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
 474             __vgic_v3_perform_cpuif_access(vcpu) == 1)
 475                 return true;
 476
 477         if (esr_is_ptrauth_trap(kvm_vcpu_get_esr(vcpu)))
 478                 return kvm_hyp_handle_ptrauth(vcpu, exit_code);
 479
 480         if (kvm_hyp_handle_cntpct(vcpu))
 481                 return true;
 482
 483         return false;
 484 }
 485
 486 static bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code)
 487 {
 488         if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
 489             __vgic_v3_perform_cpuif_access(vcpu) == 1)
 490                 return true;
 491
 492         return false;
 493 }
 494
 495 static bool kvm_hyp_handle_memory_fault(struct kvm_vcpu *vcpu, u64 *exit_code)
 496 {
 497         if (!__populate_fault_info(vcpu))
 498                 return true;
 499
 500         return false;
 501 }
 502 static bool kvm_hyp_handle_iabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
 503         __alias(kvm_hyp_handle_memory_fault);
 504 static bool kvm_hyp_handle_watchpt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
 505         __alias(kvm_hyp_handle_memory_fault);
 506
 507 static bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
 508 {
 509         if (kvm_hyp_handle_memory_fault(vcpu, exit_code))
 510                 return true;
 511
 512         if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 513                 bool valid;
 514
 515                 valid = kvm_vcpu_trap_get_fault_type(vcpu) == ESR_ELx_FSC_FAULT &&
 516                         kvm_vcpu_dabt_isvalid(vcpu) &&
 517                         !kvm_vcpu_abt_issea(vcpu) &&
 518                         !kvm_vcpu_abt_iss1tw(vcpu);
 519
 520                 if (valid) {
 521                         int ret = __vgic_v2_perform_cpuif_access(vcpu);
 522
 523                         if (ret == 1)
 524                                 return true;
 525
 526                         /* Promote an illegal access to an SError.*/
 527                         if (ret == -1)
 528                                 *exit_code = ARM_EXCEPTION_EL1_SERROR;
 529                 }
 530         }
 531
 532         return false;
 533 }
 534
 535 typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);
 536
 537 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu);
 538
 539 static void early_exit_filter(struct kvm_vcpu *vcpu, u64 *exit_code);
 540
 541 /*
 542  * Allow the hypervisor to handle the exit with an exit handler if it has one.
 543  *
 544  * Returns true if the hypervisor handled the exit, and control should go back
 545  * to the guest, or false if it hasn't.
 546  */
 547 static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
 548 {
 549         const exit_handler_fn *handlers = kvm_get_exit_handler_array(vcpu);
 550         exit_handler_fn fn;
 551
 552         fn = handlers[kvm_vcpu_trap_get_class(vcpu)];
 553
 554         if (fn)
 555                 return fn(vcpu, exit_code);
 556
 557         return false;
 558 }
 559
 560 static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code)
 561 {
 562         /*
 563          * Check for the conditions of Cortex-A510's #2077057. When these occur
 564          * SPSR_EL2 can't be trusted, but isn't needed either as it is
 565          * unchanged from the value in vcpu_gp_regs(vcpu)->pstate.
 566          * Are we single-stepping the guest, and took a PAC exception from the
 567          * active-not-pending state?
 568          */
 569         if (cpus_have_final_cap(ARM64_WORKAROUND_2077057)               &&
 570             vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP                 &&
 571             *vcpu_cpsr(vcpu) & DBG_SPSR_SS                              &&
 572             ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC)
 573                 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
 574
 575         vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
 576 }
 577
 578 /*
 579  * Return true when we were able to fixup the guest exit and should return to
 580  * the guest, false when we should restore the host state and return to the
 581  * main run loop.
 582  */
 583 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
 584 {
 585         /*
 586          * Save PSTATE early so that we can evaluate the vcpu mode
 587          * early on.
 588          */
 589         synchronize_vcpu_pstate(vcpu, exit_code);
 590
 591         /*
 592          * Check whether we want to repaint the state one way or
 593          * another.
 594          */
 595         early_exit_filter(vcpu, exit_code);
 596
 597         if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
 598                 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
 599
 600         if (ARM_SERROR_PENDING(*exit_code) &&
 601             ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
 602                 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
 603
 604                 /*
 605                  * HVC already have an adjusted PC, which we need to
 606                  * correct in order to return to after having injected
 607                  * the SError.
 608                  *
 609                  * SMC, on the other hand, is *trapped*, meaning its
 610                  * preferred return address is the SMC itself.
 611                  */
 612                 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
 613                         write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
 614         }
 615
 616         /*
 617          * We're using the raw exception code in order to only process
 618          * the trap if no SError is pending. We will come back to the
 619          * same PC once the SError has been injected, and replay the
 620          * trapping instruction.
 621          */
 622         if (*exit_code != ARM_EXCEPTION_TRAP)
 623                 goto exit;
 624
 625         /* Check if there's an exit handler and allow it to handle the exit. */
 626         if (kvm_hyp_handle_exit(vcpu, exit_code))
 627                 goto guest;
 628 exit:
 629         /* Return to the host kernel and handle the exit */
 630         return false;
 631
 632 guest:
 633         /* Re-enter the guest */
 634         asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
 635         return true;
 636 }
 637
 638 static inline void __kvm_unexpected_el2_exception(void)
 639 {
 640         extern char __guest_exit_panic[];
 641         unsigned long addr, fixup;
 642         struct kvm_exception_table_entry *entry, *end;
 643         unsigned long elr_el2 = read_sysreg(elr_el2);
 644
 645         entry = &__start___kvm_ex_table;
 646         end = &__stop___kvm_ex_table;
 647
 648         while (entry < end) {
 649                 addr = (unsigned long)&entry->insn + entry->insn;
 650                 fixup = (unsigned long)&entry->fixup + entry->fixup;
 651
 652                 if (addr != elr_el2) {
 653                         entry++;
 654                         continue;
 655                 }
 656
 657                 write_sysreg(fixup, elr_el2);
 658                 return;
 659         }
 660
 661         /* Trigger a panic after restoring the hyp context. */
 662         write_sysreg(__guest_exit_panic, elr_el2);
 663 }
 664
 665 #endif /* __ARM64_KVM_HYP_SWITCH_H__ */