2 * SMP initialisation and IPI support
3 * Based on arch/arm/kernel/smp.c
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/sched.h>
24 #include <linux/interrupt.h>
25 #include <linux/cache.h>
26 #include <linux/profile.h>
27 #include <linux/errno.h>
29 #include <linux/err.h>
30 #include <linux/cpu.h>
31 #include <linux/smp.h>
32 #include <linux/seq_file.h>
33 #include <linux/irq.h>
34 #include <linux/percpu.h>
35 #include <linux/clockchips.h>
36 #include <linux/completion.h>
39 #include <asm/atomic.h>
40 #include <asm/cacheflush.h>
41 #include <asm/cputype.h>
42 #include <asm/cpu_ops.h>
43 #include <asm/mmu_context.h>
44 #include <asm/pgtable.h>
45 #include <asm/pgalloc.h>
46 #include <asm/processor.h>
47 #include <asm/smp_plat.h>
48 #include <asm/sections.h>
49 #include <asm/tlbflush.h>
50 #include <asm/ptrace.h>
53 * as from 2.5, kernels no longer have an init_tasks structure
54 * so we need some other way of telling a new secondary core
55 * where to place its SVC stack
57 struct secondary_data secondary_data;
58 volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
67 static DEFINE_RAW_SPINLOCK(boot_lock);
70 * Write secondary_holding_pen_release in a way that is guaranteed to be
71 * visible to all observers, irrespective of whether they're taking part
72 * in coherency or not. This is necessary for the hotplug code to work
75 static void write_pen_release(u64 val)
77 void *start = (void *)&secondary_holding_pen_release;
78 unsigned long size = sizeof(secondary_holding_pen_release);
80 secondary_holding_pen_release = val;
81 __flush_dcache_area(start, size);
85 * Boot a secondary CPU, and assign it the specified idle task.
86 * This also gives us the initial stack to use for this CPU.
88 static int boot_secondary(unsigned int cpu, struct task_struct *idle)
90 unsigned long timeout;
93 * Set synchronisation state between this boot processor
94 * and the secondary one
96 raw_spin_lock(&boot_lock);
99 * Update the pen release flag.
101 write_pen_release(cpu_logical_map(cpu));
104 * Send an event, causing the secondaries to read pen_release.
108 timeout = jiffies + (1 * HZ);
109 while (time_before(jiffies, timeout)) {
110 if (secondary_holding_pen_release == INVALID_HWID)
116 * Now the secondary core is starting up let it run its
117 * calibrations, then wait for it to finish
119 raw_spin_unlock(&boot_lock);
121 return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0;
124 static DECLARE_COMPLETION(cpu_running);
126 int __cpu_up(unsigned int cpu, struct task_struct *idle)
131 * We need to tell the secondary core where to find its stack and the
134 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
135 __flush_dcache_area(&secondary_data, sizeof(secondary_data));
138 * Now bring the CPU into our world.
140 ret = boot_secondary(cpu, idle);
143 * CPU was successfully started, wait for it to come online or
146 wait_for_completion_timeout(&cpu_running,
147 msecs_to_jiffies(1000));
149 if (!cpu_online(cpu)) {
150 pr_crit("CPU%u: failed to come online\n", cpu);
154 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
157 secondary_data.stack = NULL;
163 * This is the secondary CPU boot entry. We're using this CPUs
164 * idle thread stack, but a set of temporary page tables.
166 asmlinkage void secondary_start_kernel(void)
168 struct mm_struct *mm = &init_mm;
169 unsigned int cpu = smp_processor_id();
171 printk("CPU%u: Booted secondary processor\n", cpu);
174 * All kernel threads share the same mm context; grab a
175 * reference and switch to it.
177 atomic_inc(&mm->mm_count);
178 current->active_mm = mm;
179 cpumask_set_cpu(cpu, mm_cpumask(mm));
182 * TTBR0 is only used for the identity mapping at this stage. Make it
183 * point to zero page to avoid speculatively fetching new entries.
185 cpu_set_reserved_ttbr0();
189 trace_hardirqs_off();
192 * Let the primary processor know we're out of the
193 * pen, then head off into the C entry point
195 write_pen_release(INVALID_HWID);
198 * Synchronise with the boot thread.
200 raw_spin_lock(&boot_lock);
201 raw_spin_unlock(&boot_lock);
204 * OK, now it's safe to let the boot CPU continue. Wait for
205 * the CPU migration code to notice that the CPU is online
206 * before we continue.
208 set_cpu_online(cpu, true);
209 complete(&cpu_running);
212 * Enable GIC and timers.
214 notify_cpu_starting(cpu);
220 * OK, it's off to the idle thread for us
222 cpu_startup_entry(CPUHP_ONLINE);
225 void __init smp_cpus_done(unsigned int max_cpus)
227 pr_info("SMP: Total of %d processors activated.\n", num_online_cpus());
230 void __init smp_prepare_boot_cpu(void)
234 static void (*smp_cross_call)(const struct cpumask *, unsigned int);
237 * Enumerate the possible CPU set from the device tree and build the
238 * cpu logical map array containing MPIDR values related to logical
239 * cpus. Assumes that cpu_logical_map(0) has already been initialized.
241 void __init smp_init_cpus(void)
243 const char *enable_method;
244 struct device_node *dn = NULL;
245 unsigned int i, cpu = 1;
246 bool bootcpu_valid = false;
248 while ((dn = of_find_node_by_type(dn, "cpu"))) {
253 * A cpu node with missing "reg" property is
254 * considered invalid to build a cpu_logical_map
257 cell = of_get_property(dn, "reg", NULL);
259 pr_err("%s: missing reg property\n", dn->full_name);
262 hwid = of_read_number(cell, of_n_addr_cells(dn));
265 * Non affinity bits must be set to 0 in the DT
267 if (hwid & ~MPIDR_HWID_BITMASK) {
268 pr_err("%s: invalid reg property\n", dn->full_name);
273 * Duplicate MPIDRs are a recipe for disaster. Scan
274 * all initialized entries and check for
275 * duplicates. If any is found just ignore the cpu.
276 * cpu_logical_map was initialized to INVALID_HWID to
277 * avoid matching valid MPIDR values.
279 for (i = 1; (i < cpu) && (i < NR_CPUS); i++) {
280 if (cpu_logical_map(i) == hwid) {
281 pr_err("%s: duplicate cpu reg properties in the DT\n",
288 * The numbering scheme requires that the boot CPU
289 * must be assigned logical id 0. Record it so that
290 * the logical map built from DT is validated and can
293 if (hwid == cpu_logical_map(0)) {
295 pr_err("%s: duplicate boot cpu reg property in DT\n",
300 bootcpu_valid = true;
303 * cpu_logical_map has already been
304 * initialized and the boot cpu doesn't need
305 * the enable-method so continue without
315 * We currently support only the "spin-table" enable-method.
317 enable_method = of_get_property(dn, "enable-method", NULL);
318 if (!enable_method) {
319 pr_err("%s: missing enable-method property\n",
324 cpu_ops[cpu] = cpu_get_ops(enable_method);
327 pr_err("%s: invalid enable-method property: %s\n",
328 dn->full_name, enable_method);
332 if (cpu_ops[cpu]->cpu_init(dn, cpu))
335 pr_debug("cpu logical map 0x%llx\n", hwid);
336 cpu_logical_map(cpu) = hwid;
343 pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
346 if (!bootcpu_valid) {
347 pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n");
352 * All the cpus that made it to the cpu_logical_map have been
353 * validated so set them as possible cpus.
355 for (i = 0; i < NR_CPUS; i++)
356 if (cpu_logical_map(i) != INVALID_HWID)
357 set_cpu_possible(i, true);
360 void __init smp_prepare_cpus(unsigned int max_cpus)
363 unsigned int cpu, ncores = num_possible_cpus();
366 * are we trying to boot more cores than exist?
368 if (max_cpus > ncores)
371 /* Don't bother if we're effectively UP */
376 * Initialise the present map (which describes the set of CPUs
377 * actually populated at the present time) and release the
378 * secondaries from the bootloader.
380 * Make sure we online at most (max_cpus - 1) additional CPUs.
383 for_each_possible_cpu(cpu) {
387 if (cpu == smp_processor_id())
393 err = cpu_ops[cpu]->cpu_prepare(cpu);
397 set_cpu_present(cpu, true);
403 void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
408 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
410 smp_cross_call(mask, IPI_CALL_FUNC);
413 void arch_send_call_function_single_ipi(int cpu)
415 smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
418 static const char *ipi_types[NR_IPI] = {
419 #define S(x,s) [x - IPI_RESCHEDULE] = s
420 S(IPI_RESCHEDULE, "Rescheduling interrupts"),
421 S(IPI_CALL_FUNC, "Function call interrupts"),
422 S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
423 S(IPI_CPU_STOP, "CPU stop interrupts"),
426 void show_ipi_list(struct seq_file *p, int prec)
430 for (i = 0; i < NR_IPI; i++) {
431 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i + IPI_RESCHEDULE,
432 prec >= 4 ? " " : "");
433 for_each_present_cpu(cpu)
434 seq_printf(p, "%10u ",
435 __get_irq_stat(cpu, ipi_irqs[i]));
436 seq_printf(p, " %s\n", ipi_types[i]);
440 u64 smp_irq_stat_cpu(unsigned int cpu)
445 for (i = 0; i < NR_IPI; i++)
446 sum += __get_irq_stat(cpu, ipi_irqs[i]);
451 static DEFINE_RAW_SPINLOCK(stop_lock);
454 * ipi_cpu_stop - handle IPI from smp_send_stop()
456 static void ipi_cpu_stop(unsigned int cpu)
458 if (system_state == SYSTEM_BOOTING ||
459 system_state == SYSTEM_RUNNING) {
460 raw_spin_lock(&stop_lock);
461 pr_crit("CPU%u: stopping\n", cpu);
463 raw_spin_unlock(&stop_lock);
466 set_cpu_online(cpu, false);
476 * Main handler for inter-processor interrupts
478 void handle_IPI(int ipinr, struct pt_regs *regs)
480 unsigned int cpu = smp_processor_id();
481 struct pt_regs *old_regs = set_irq_regs(regs);
483 if (ipinr >= IPI_RESCHEDULE && ipinr < IPI_RESCHEDULE + NR_IPI)
484 __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_RESCHEDULE]);
493 generic_smp_call_function_interrupt();
497 case IPI_CALL_FUNC_SINGLE:
499 generic_smp_call_function_single_interrupt();
510 pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
513 set_irq_regs(old_regs);
516 void smp_send_reschedule(int cpu)
518 smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
521 void smp_send_stop(void)
523 unsigned long timeout;
525 if (num_online_cpus() > 1) {
528 cpumask_copy(&mask, cpu_online_mask);
529 cpu_clear(smp_processor_id(), mask);
531 smp_cross_call(&mask, IPI_CPU_STOP);
534 /* Wait up to one second for other CPUs to stop */
535 timeout = USEC_PER_SEC;
536 while (num_online_cpus() > 1 && timeout--)
539 if (num_online_cpus() > 1)
540 pr_warning("SMP: failed to stop secondary CPUs\n");
546 int setup_profiling_timer(unsigned int multiplier)