1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARMv8 PMUv3 Performance Events handling code.
5 * Copyright (C) 2012 ARM Limited
6 * Author: Will Deacon <will.deacon@arm.com>
8 * This code is based heavily on the ARMv7 perf event code.
11 #include <asm/irq_regs.h>
12 #include <asm/perf_event.h>
13 #include <asm/sysreg.h>
16 #include <clocksource/arm_arch_timer.h>
18 #include <linux/acpi.h>
19 #include <linux/clocksource.h>
20 #include <linux/kvm_host.h>
22 #include <linux/perf/arm_pmu.h>
23 #include <linux/platform_device.h>
24 #include <linux/sched_clock.h>
25 #include <linux/smp.h>
27 /* ARMv8 Cortex-A53 specific event types. */
28 #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
30 /* ARMv8 Cavium ThunderX specific event types. */
31 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9
32 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA
33 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB
34 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC
35 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED
38 * ARMv8 Architectural defined events, not all of these may
39 * be supported on any given implementation. Unsupported events will
40 * be disabled at run-time based on the PMCEID registers.
42 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
43 PERF_MAP_ALL_UNSUPPORTED,
44 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
45 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
46 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
47 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
48 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
49 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
50 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
51 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
52 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
55 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
56 [PERF_COUNT_HW_CACHE_OP_MAX]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
58 PERF_CACHE_MAP_ALL_UNSUPPORTED,
60 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
61 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
63 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
64 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
66 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
67 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
69 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
70 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
72 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
73 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
75 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
76 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
79 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
80 [PERF_COUNT_HW_CACHE_OP_MAX]
81 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
82 PERF_CACHE_MAP_ALL_UNSUPPORTED,
84 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
86 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
87 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
90 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
91 [PERF_COUNT_HW_CACHE_OP_MAX]
92 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
93 PERF_CACHE_MAP_ALL_UNSUPPORTED,
95 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
96 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
97 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
100 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
101 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
103 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
104 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
107 static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
108 [PERF_COUNT_HW_CACHE_OP_MAX]
109 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
110 PERF_CACHE_MAP_ALL_UNSUPPORTED,
112 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
113 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
116 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
117 [PERF_COUNT_HW_CACHE_OP_MAX]
118 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
119 PERF_CACHE_MAP_ALL_UNSUPPORTED,
121 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
122 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
123 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
124 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
125 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
126 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
128 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
129 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
131 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
132 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
133 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
134 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
137 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
138 [PERF_COUNT_HW_CACHE_OP_MAX]
139 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
140 PERF_CACHE_MAP_ALL_UNSUPPORTED,
142 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
143 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
144 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
145 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
147 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
148 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
149 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
150 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
152 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
153 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
157 armv8pmu_events_sysfs_show(struct device *dev,
158 struct device_attribute *attr, char *page)
160 struct perf_pmu_events_attr *pmu_attr;
162 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
164 return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
167 #define ARMV8_EVENT_ATTR(name, config) \
168 PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config)
170 static struct attribute *armv8_pmuv3_event_attrs[] = {
171 ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),
172 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
173 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
174 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
175 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
176 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
177 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
178 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
179 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
180 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
181 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
182 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
183 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
184 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
185 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
186 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
187 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
188 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
189 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
190 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
191 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
192 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
193 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
194 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
195 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
196 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
197 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
198 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
199 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
200 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
201 /* Don't expose the chain event in /sys, since it's useless in isolation */
202 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
203 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
204 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
205 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
206 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
207 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
208 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
209 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
210 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
211 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
212 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
213 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
214 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
215 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
216 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
217 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
218 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
219 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
220 ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
221 ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
222 ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
223 ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
224 ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
225 ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
226 ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
227 ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
228 ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
229 ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
230 ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
231 ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
232 ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
233 ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
234 ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
235 ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
236 ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
237 ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
238 ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
239 ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
240 ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
241 ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
242 ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
243 ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
244 ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
245 ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
246 ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
247 ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
248 ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
249 ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
250 ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
255 armv8pmu_event_attr_is_visible(struct kobject *kobj,
256 struct attribute *attr, int unused)
258 struct device *dev = kobj_to_dev(kobj);
259 struct pmu *pmu = dev_get_drvdata(dev);
260 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
261 struct perf_pmu_events_attr *pmu_attr;
263 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
265 if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
266 test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
269 if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
270 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
272 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
273 test_bit(id, cpu_pmu->pmceid_ext_bitmap))
280 static const struct attribute_group armv8_pmuv3_events_attr_group = {
282 .attrs = armv8_pmuv3_event_attrs,
283 .is_visible = armv8pmu_event_attr_is_visible,
286 PMU_FORMAT_ATTR(event, "config:0-15");
287 PMU_FORMAT_ATTR(long, "config1:0");
288 PMU_FORMAT_ATTR(rdpmc, "config1:1");
290 static int sysctl_perf_user_access __read_mostly;
292 static inline bool armv8pmu_event_is_64bit(struct perf_event *event)
294 return event->attr.config1 & 0x1;
297 static inline bool armv8pmu_event_want_user_access(struct perf_event *event)
299 return event->attr.config1 & 0x2;
302 static struct attribute *armv8_pmuv3_format_attrs[] = {
303 &format_attr_event.attr,
304 &format_attr_long.attr,
305 &format_attr_rdpmc.attr,
309 static const struct attribute_group armv8_pmuv3_format_attr_group = {
311 .attrs = armv8_pmuv3_format_attrs,
314 static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
317 struct pmu *pmu = dev_get_drvdata(dev);
318 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
319 u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK;
321 return sysfs_emit(page, "0x%08x\n", slots);
324 static DEVICE_ATTR_RO(slots);
326 static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr,
329 struct pmu *pmu = dev_get_drvdata(dev);
330 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
331 u32 bus_slots = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_SLOTS_SHIFT)
332 & ARMV8_PMU_BUS_SLOTS_MASK;
334 return sysfs_emit(page, "0x%08x\n", bus_slots);
337 static DEVICE_ATTR_RO(bus_slots);
339 static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr,
342 struct pmu *pmu = dev_get_drvdata(dev);
343 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
344 u32 bus_width = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_WIDTH_SHIFT)
345 & ARMV8_PMU_BUS_WIDTH_MASK;
348 /* Encoded as Log2(number of bytes), plus one */
349 if (bus_width > 2 && bus_width < 13)
350 val = 1 << (bus_width - 1);
352 return sysfs_emit(page, "0x%08x\n", val);
355 static DEVICE_ATTR_RO(bus_width);
357 static struct attribute *armv8_pmuv3_caps_attrs[] = {
358 &dev_attr_slots.attr,
359 &dev_attr_bus_slots.attr,
360 &dev_attr_bus_width.attr,
364 static const struct attribute_group armv8_pmuv3_caps_attr_group = {
366 .attrs = armv8_pmuv3_caps_attrs,
370 * Perf Events' indices
372 #define ARMV8_IDX_CYCLE_COUNTER 0
373 #define ARMV8_IDX_COUNTER0 1
374 #define ARMV8_IDX_CYCLE_COUNTER_USER 32
377 * We unconditionally enable ARMv8.5-PMU long event counter support
378 * (64-bit events) where supported. Indicate if this arm_pmu has long
379 * event counter support.
381 static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu)
383 return (cpu_pmu->pmuver >= ID_AA64DFR0_PMUVER_8_5);
386 static inline bool armv8pmu_event_has_user_read(struct perf_event *event)
388 return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT;
392 * We must chain two programmable counters for 64 bit events,
393 * except when we have allocated the 64bit cycle counter (for CPU
394 * cycles event) or when user space counter access is enabled.
396 static inline bool armv8pmu_event_is_chained(struct perf_event *event)
398 int idx = event->hw.idx;
399 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
401 return !armv8pmu_event_has_user_read(event) &&
402 armv8pmu_event_is_64bit(event) &&
403 !armv8pmu_has_long_event(cpu_pmu) &&
404 (idx != ARMV8_IDX_CYCLE_COUNTER);
408 * ARMv8 low level PMU access
412 * Perf Event to low level counters mapping
414 #define ARMV8_IDX_TO_COUNTER(x) \
415 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
418 * This code is really good
421 #define PMEVN_CASE(n, case_macro) \
422 case n: case_macro(n); break
424 #define PMEVN_SWITCH(x, case_macro) \
427 PMEVN_CASE(0, case_macro); \
428 PMEVN_CASE(1, case_macro); \
429 PMEVN_CASE(2, case_macro); \
430 PMEVN_CASE(3, case_macro); \
431 PMEVN_CASE(4, case_macro); \
432 PMEVN_CASE(5, case_macro); \
433 PMEVN_CASE(6, case_macro); \
434 PMEVN_CASE(7, case_macro); \
435 PMEVN_CASE(8, case_macro); \
436 PMEVN_CASE(9, case_macro); \
437 PMEVN_CASE(10, case_macro); \
438 PMEVN_CASE(11, case_macro); \
439 PMEVN_CASE(12, case_macro); \
440 PMEVN_CASE(13, case_macro); \
441 PMEVN_CASE(14, case_macro); \
442 PMEVN_CASE(15, case_macro); \
443 PMEVN_CASE(16, case_macro); \
444 PMEVN_CASE(17, case_macro); \
445 PMEVN_CASE(18, case_macro); \
446 PMEVN_CASE(19, case_macro); \
447 PMEVN_CASE(20, case_macro); \
448 PMEVN_CASE(21, case_macro); \
449 PMEVN_CASE(22, case_macro); \
450 PMEVN_CASE(23, case_macro); \
451 PMEVN_CASE(24, case_macro); \
452 PMEVN_CASE(25, case_macro); \
453 PMEVN_CASE(26, case_macro); \
454 PMEVN_CASE(27, case_macro); \
455 PMEVN_CASE(28, case_macro); \
456 PMEVN_CASE(29, case_macro); \
457 PMEVN_CASE(30, case_macro); \
458 default: WARN(1, "Invalid PMEV* index\n"); \
462 #define RETURN_READ_PMEVCNTRN(n) \
463 return read_sysreg(pmevcntr##n##_el0)
464 static unsigned long read_pmevcntrn(int n)
466 PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
470 #define WRITE_PMEVCNTRN(n) \
471 write_sysreg(val, pmevcntr##n##_el0)
472 static void write_pmevcntrn(int n, unsigned long val)
474 PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
477 #define WRITE_PMEVTYPERN(n) \
478 write_sysreg(val, pmevtyper##n##_el0)
479 static void write_pmevtypern(int n, unsigned long val)
481 PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
484 static inline u32 armv8pmu_pmcr_read(void)
486 return read_sysreg(pmcr_el0);
489 static inline void armv8pmu_pmcr_write(u32 val)
491 val &= ARMV8_PMU_PMCR_MASK;
493 write_sysreg(val, pmcr_el0);
496 static inline int armv8pmu_has_overflowed(u32 pmovsr)
498 return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
501 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
503 return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
506 static inline u64 armv8pmu_read_evcntr(int idx)
508 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
510 return read_pmevcntrn(counter);
513 static inline u64 armv8pmu_read_hw_counter(struct perf_event *event)
515 int idx = event->hw.idx;
516 u64 val = armv8pmu_read_evcntr(idx);
518 if (armv8pmu_event_is_chained(event))
519 val = (val << 32) | armv8pmu_read_evcntr(idx - 1);
524 * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP
525 * is set the event counters also become 64-bit counters. Unless the
526 * user has requested a long counter (attr.config1) then we want to
527 * interrupt upon 32-bit overflow - we achieve this by applying a bias.
529 static bool armv8pmu_event_needs_bias(struct perf_event *event)
531 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
532 struct hw_perf_event *hwc = &event->hw;
535 if (armv8pmu_event_is_64bit(event))
538 if (armv8pmu_has_long_event(cpu_pmu) ||
539 idx == ARMV8_IDX_CYCLE_COUNTER)
545 static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value)
547 if (armv8pmu_event_needs_bias(event))
548 value |= GENMASK(63, 32);
553 static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value)
555 if (armv8pmu_event_needs_bias(event))
556 value &= ~GENMASK(63, 32);
561 static u64 armv8pmu_read_counter(struct perf_event *event)
563 struct hw_perf_event *hwc = &event->hw;
567 if (idx == ARMV8_IDX_CYCLE_COUNTER)
568 value = read_sysreg(pmccntr_el0);
570 value = armv8pmu_read_hw_counter(event);
572 return armv8pmu_unbias_long_counter(event, value);
575 static inline void armv8pmu_write_evcntr(int idx, u64 value)
577 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
579 write_pmevcntrn(counter, value);
582 static inline void armv8pmu_write_hw_counter(struct perf_event *event,
585 int idx = event->hw.idx;
587 if (armv8pmu_event_is_chained(event)) {
588 armv8pmu_write_evcntr(idx, upper_32_bits(value));
589 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value));
591 armv8pmu_write_evcntr(idx, value);
595 static void armv8pmu_write_counter(struct perf_event *event, u64 value)
597 struct hw_perf_event *hwc = &event->hw;
600 value = armv8pmu_bias_long_counter(event, value);
602 if (idx == ARMV8_IDX_CYCLE_COUNTER)
603 write_sysreg(value, pmccntr_el0);
605 armv8pmu_write_hw_counter(event, value);
608 static inline void armv8pmu_write_evtype(int idx, u32 val)
610 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
612 val &= ARMV8_PMU_EVTYPE_MASK;
613 write_pmevtypern(counter, val);
616 static inline void armv8pmu_write_event_type(struct perf_event *event)
618 struct hw_perf_event *hwc = &event->hw;
622 * For chained events, the low counter is programmed to count
623 * the event of interest and the high counter is programmed
624 * with CHAIN event code with filters set to count at all ELs.
626 if (armv8pmu_event_is_chained(event)) {
627 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN |
628 ARMV8_PMU_INCLUDE_EL2;
630 armv8pmu_write_evtype(idx - 1, hwc->config_base);
631 armv8pmu_write_evtype(idx, chain_evt);
633 if (idx == ARMV8_IDX_CYCLE_COUNTER)
634 write_sysreg(hwc->config_base, pmccfiltr_el0);
636 armv8pmu_write_evtype(idx, hwc->config_base);
640 static u32 armv8pmu_event_cnten_mask(struct perf_event *event)
642 int counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
643 u32 mask = BIT(counter);
645 if (armv8pmu_event_is_chained(event))
646 mask |= BIT(counter - 1);
650 static inline void armv8pmu_enable_counter(u32 mask)
653 * Make sure event configuration register writes are visible before we
654 * enable the counter.
657 write_sysreg(mask, pmcntenset_el0);
660 static inline void armv8pmu_enable_event_counter(struct perf_event *event)
662 struct perf_event_attr *attr = &event->attr;
663 u32 mask = armv8pmu_event_cnten_mask(event);
665 kvm_set_pmu_events(mask, attr);
667 /* We rely on the hypervisor switch code to enable guest counters */
668 if (!kvm_pmu_counter_deferred(attr))
669 armv8pmu_enable_counter(mask);
672 static inline void armv8pmu_disable_counter(u32 mask)
674 write_sysreg(mask, pmcntenclr_el0);
676 * Make sure the effects of disabling the counter are visible before we
677 * start configuring the event.
682 static inline void armv8pmu_disable_event_counter(struct perf_event *event)
684 struct perf_event_attr *attr = &event->attr;
685 u32 mask = armv8pmu_event_cnten_mask(event);
687 kvm_clr_pmu_events(mask);
689 /* We rely on the hypervisor switch code to disable guest counters */
690 if (!kvm_pmu_counter_deferred(attr))
691 armv8pmu_disable_counter(mask);
694 static inline void armv8pmu_enable_intens(u32 mask)
696 write_sysreg(mask, pmintenset_el1);
699 static inline void armv8pmu_enable_event_irq(struct perf_event *event)
701 u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
702 armv8pmu_enable_intens(BIT(counter));
705 static inline void armv8pmu_disable_intens(u32 mask)
707 write_sysreg(mask, pmintenclr_el1);
709 /* Clear the overflow flag in case an interrupt is pending. */
710 write_sysreg(mask, pmovsclr_el0);
714 static inline void armv8pmu_disable_event_irq(struct perf_event *event)
716 u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
717 armv8pmu_disable_intens(BIT(counter));
720 static inline u32 armv8pmu_getreset_flags(void)
725 value = read_sysreg(pmovsclr_el0);
727 /* Write to clear flags */
728 value &= ARMV8_PMU_OVSR_MASK;
729 write_sysreg(value, pmovsclr_el0);
734 static void armv8pmu_disable_user_access(void)
736 write_sysreg(0, pmuserenr_el0);
739 static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu)
742 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
744 /* Clear any unused counters to avoid leaking their contents */
745 for_each_clear_bit(i, cpuc->used_mask, cpu_pmu->num_events) {
746 if (i == ARMV8_IDX_CYCLE_COUNTER)
747 write_sysreg(0, pmccntr_el0);
749 armv8pmu_write_evcntr(i, 0);
752 write_sysreg(0, pmuserenr_el0);
753 write_sysreg(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR, pmuserenr_el0);
756 static void armv8pmu_enable_event(struct perf_event *event)
759 * Enable counter and interrupt, and set the counter to count
760 * the event that we're interested in.
766 armv8pmu_disable_event_counter(event);
771 armv8pmu_write_event_type(event);
774 * Enable interrupt for this counter
776 armv8pmu_enable_event_irq(event);
781 armv8pmu_enable_event_counter(event);
784 static void armv8pmu_disable_event(struct perf_event *event)
789 armv8pmu_disable_event_counter(event);
792 * Disable interrupt for this counter
794 armv8pmu_disable_event_irq(event);
797 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
799 struct perf_event_context *task_ctx =
800 this_cpu_ptr(cpu_pmu->pmu.pmu_cpu_context)->task_ctx;
802 if (sysctl_perf_user_access && task_ctx && task_ctx->nr_user)
803 armv8pmu_enable_user_access(cpu_pmu);
805 armv8pmu_disable_user_access();
807 /* Enable all counters */
808 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
811 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
813 /* Disable all counters */
814 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
817 static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
820 struct perf_sample_data data;
821 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
822 struct pt_regs *regs;
826 * Get and reset the IRQ flags
828 pmovsr = armv8pmu_getreset_flags();
831 * Did an overflow occur?
833 if (!armv8pmu_has_overflowed(pmovsr))
837 * Handle the counter(s) overflow(s)
839 regs = get_irq_regs();
842 * Stop the PMU while processing the counter overflows
843 * to prevent skews in group events.
845 armv8pmu_stop(cpu_pmu);
846 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
847 struct perf_event *event = cpuc->events[idx];
848 struct hw_perf_event *hwc;
850 /* Ignore if we don't have an event. */
855 * We have a single interrupt for all counters. Check that
856 * each counter has overflowed before we process it.
858 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
862 armpmu_event_update(event);
863 perf_sample_data_init(&data, 0, hwc->last_period);
864 if (!armpmu_event_set_period(event))
868 * Perf event overflow will queue the processing of the event as
869 * an irq_work which will be taken care of in the handling of
872 if (perf_event_overflow(event, &data, regs))
873 cpu_pmu->disable(event);
875 armv8pmu_start(cpu_pmu);
880 static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc,
881 struct arm_pmu *cpu_pmu)
885 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx++) {
886 if (!test_and_set_bit(idx, cpuc->used_mask))
892 static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
893 struct arm_pmu *cpu_pmu)
898 * Chaining requires two consecutive event counters, where
899 * the lower idx must be even.
901 for (idx = ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx += 2) {
902 if (!test_and_set_bit(idx, cpuc->used_mask)) {
903 /* Check if the preceding even counter is available */
904 if (!test_and_set_bit(idx - 1, cpuc->used_mask))
906 /* Release the Odd counter */
907 clear_bit(idx, cpuc->used_mask);
913 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
914 struct perf_event *event)
916 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
917 struct hw_perf_event *hwc = &event->hw;
918 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
920 /* Always prefer to place a cycle counter into the cycle counter. */
921 if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
922 if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
923 return ARMV8_IDX_CYCLE_COUNTER;
924 else if (armv8pmu_event_is_64bit(event) &&
925 armv8pmu_event_want_user_access(event) &&
926 !armv8pmu_has_long_event(cpu_pmu))
931 * Otherwise use events counters
933 if (armv8pmu_event_is_chained(event))
934 return armv8pmu_get_chain_idx(cpuc, cpu_pmu);
936 return armv8pmu_get_single_idx(cpuc, cpu_pmu);
939 static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc,
940 struct perf_event *event)
942 int idx = event->hw.idx;
944 clear_bit(idx, cpuc->used_mask);
945 if (armv8pmu_event_is_chained(event))
946 clear_bit(idx - 1, cpuc->used_mask);
949 static int armv8pmu_user_event_idx(struct perf_event *event)
951 if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event))
955 * We remap the cycle counter index to 32 to
956 * match the offset applied to the rest of
957 * the counter indices.
959 if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER)
960 return ARMV8_IDX_CYCLE_COUNTER_USER;
962 return event->hw.idx;
966 * Add an event filter to a given event.
968 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
969 struct perf_event_attr *attr)
971 unsigned long config_base = 0;
973 if (attr->exclude_idle)
977 * If we're running in hyp mode, then we *are* the hypervisor.
978 * Therefore we ignore exclude_hv in this configuration, since
979 * there's no hypervisor to sample anyway. This is consistent
980 * with other architectures (x86 and Power).
982 if (is_kernel_in_hyp_mode()) {
983 if (!attr->exclude_kernel && !attr->exclude_host)
984 config_base |= ARMV8_PMU_INCLUDE_EL2;
985 if (attr->exclude_guest)
986 config_base |= ARMV8_PMU_EXCLUDE_EL1;
987 if (attr->exclude_host)
988 config_base |= ARMV8_PMU_EXCLUDE_EL0;
990 if (!attr->exclude_hv && !attr->exclude_host)
991 config_base |= ARMV8_PMU_INCLUDE_EL2;
995 * Filter out !VHE kernels and guest kernels
997 if (attr->exclude_kernel)
998 config_base |= ARMV8_PMU_EXCLUDE_EL1;
1000 if (attr->exclude_user)
1001 config_base |= ARMV8_PMU_EXCLUDE_EL0;
1004 * Install the filter into config_base as this is used to
1005 * construct the event type.
1007 event->config_base = config_base;
1012 static int armv8pmu_filter_match(struct perf_event *event)
1014 unsigned long evtype = event->hw.config_base & ARMV8_PMU_EVTYPE_EVENT;
1015 return evtype != ARMV8_PMUV3_PERFCTR_CHAIN;
1018 static void armv8pmu_reset(void *info)
1020 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
1023 /* The counter and interrupt enable registers are unknown at reset. */
1024 armv8pmu_disable_counter(U32_MAX);
1025 armv8pmu_disable_intens(U32_MAX);
1027 /* Clear the counters we flip at guest entry/exit */
1028 kvm_clr_pmu_events(U32_MAX);
1031 * Initialize & Reset PMNC. Request overflow interrupt for
1032 * 64 bit cycle counter but cheat in armv8pmu_write_counter().
1034 pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC;
1036 /* Enable long event counter support where available */
1037 if (armv8pmu_has_long_event(cpu_pmu))
1038 pmcr |= ARMV8_PMU_PMCR_LP;
1040 armv8pmu_pmcr_write(pmcr);
1043 static int __armv8_pmuv3_map_event(struct perf_event *event,
1044 const unsigned (*extra_event_map)
1045 [PERF_COUNT_HW_MAX],
1046 const unsigned (*extra_cache_map)
1047 [PERF_COUNT_HW_CACHE_MAX]
1048 [PERF_COUNT_HW_CACHE_OP_MAX]
1049 [PERF_COUNT_HW_CACHE_RESULT_MAX])
1052 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
1054 hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
1055 &armv8_pmuv3_perf_cache_map,
1056 ARMV8_PMU_EVTYPE_EVENT);
1058 if (armv8pmu_event_is_64bit(event))
1059 event->hw.flags |= ARMPMU_EVT_64BIT;
1062 * User events must be allocated into a single counter, and so
1063 * must not be chained.
1065 * Most 64-bit events require long counter support, but 64-bit
1066 * CPU_CYCLES events can be placed into the dedicated cycle
1067 * counter when this is free.
1069 if (armv8pmu_event_want_user_access(event)) {
1070 if (!(event->attach_state & PERF_ATTACH_TASK))
1072 if (armv8pmu_event_is_64bit(event) &&
1073 (hw_event_id != ARMV8_PMUV3_PERFCTR_CPU_CYCLES) &&
1074 !armv8pmu_has_long_event(armpmu))
1077 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
1080 /* Only expose micro/arch events supported by this PMU */
1081 if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
1082 && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
1086 return armpmu_map_event(event, extra_event_map, extra_cache_map,
1087 ARMV8_PMU_EVTYPE_EVENT);
1090 static int armv8_pmuv3_map_event(struct perf_event *event)
1092 return __armv8_pmuv3_map_event(event, NULL, NULL);
1095 static int armv8_a53_map_event(struct perf_event *event)
1097 return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
1100 static int armv8_a57_map_event(struct perf_event *event)
1102 return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
1105 static int armv8_a73_map_event(struct perf_event *event)
1107 return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
1110 static int armv8_thunder_map_event(struct perf_event *event)
1112 return __armv8_pmuv3_map_event(event, NULL,
1113 &armv8_thunder_perf_cache_map);
1116 static int armv8_vulcan_map_event(struct perf_event *event)
1118 return __armv8_pmuv3_map_event(event, NULL,
1119 &armv8_vulcan_perf_cache_map);
1122 struct armv8pmu_probe_info {
1123 struct arm_pmu *pmu;
1127 static void __armv8pmu_probe_pmu(void *info)
1129 struct armv8pmu_probe_info *probe = info;
1130 struct arm_pmu *cpu_pmu = probe->pmu;
1136 dfr0 = read_sysreg(id_aa64dfr0_el1);
1137 pmuver = cpuid_feature_extract_unsigned_field(dfr0,
1138 ID_AA64DFR0_PMUVER_SHIFT);
1139 if (pmuver == ID_AA64DFR0_PMUVER_IMP_DEF || pmuver == 0)
1142 cpu_pmu->pmuver = pmuver;
1143 probe->present = true;
1145 /* Read the nb of CNTx counters supported from PMNC */
1146 cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
1147 & ARMV8_PMU_PMCR_N_MASK;
1149 /* Add the CPU cycles counter */
1150 cpu_pmu->num_events += 1;
1152 pmceid[0] = pmceid_raw[0] = read_sysreg(pmceid0_el0);
1153 pmceid[1] = pmceid_raw[1] = read_sysreg(pmceid1_el0);
1155 bitmap_from_arr32(cpu_pmu->pmceid_bitmap,
1156 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1158 pmceid[0] = pmceid_raw[0] >> 32;
1159 pmceid[1] = pmceid_raw[1] >> 32;
1161 bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap,
1162 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1164 /* store PMMIR_EL1 register for sysfs */
1165 if (pmuver >= ID_AA64DFR0_PMUVER_8_4 && (pmceid_raw[1] & BIT(31)))
1166 cpu_pmu->reg_pmmir = read_cpuid(PMMIR_EL1);
1168 cpu_pmu->reg_pmmir = 0;
1171 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
1173 struct armv8pmu_probe_info probe = {
1179 ret = smp_call_function_any(&cpu_pmu->supported_cpus,
1180 __armv8pmu_probe_pmu,
1185 return probe.present ? 0 : -ENODEV;
1188 static void armv8pmu_disable_user_access_ipi(void *unused)
1190 armv8pmu_disable_user_access();
1193 static int armv8pmu_proc_user_access_handler(struct ctl_table *table, int write,
1194 void *buffer, size_t *lenp, loff_t *ppos)
1196 int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
1197 if (ret || !write || sysctl_perf_user_access)
1200 on_each_cpu(armv8pmu_disable_user_access_ipi, NULL, 1);
1204 static struct ctl_table armv8_pmu_sysctl_table[] = {
1206 .procname = "perf_user_access",
1207 .data = &sysctl_perf_user_access,
1208 .maxlen = sizeof(unsigned int),
1210 .proc_handler = armv8pmu_proc_user_access_handler,
1211 .extra1 = SYSCTL_ZERO,
1212 .extra2 = SYSCTL_ONE,
1217 static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
1218 int (*map_event)(struct perf_event *event),
1219 const struct attribute_group *events,
1220 const struct attribute_group *format,
1221 const struct attribute_group *caps)
1223 int ret = armv8pmu_probe_pmu(cpu_pmu);
1227 cpu_pmu->handle_irq = armv8pmu_handle_irq;
1228 cpu_pmu->enable = armv8pmu_enable_event;
1229 cpu_pmu->disable = armv8pmu_disable_event;
1230 cpu_pmu->read_counter = armv8pmu_read_counter;
1231 cpu_pmu->write_counter = armv8pmu_write_counter;
1232 cpu_pmu->get_event_idx = armv8pmu_get_event_idx;
1233 cpu_pmu->clear_event_idx = armv8pmu_clear_event_idx;
1234 cpu_pmu->start = armv8pmu_start;
1235 cpu_pmu->stop = armv8pmu_stop;
1236 cpu_pmu->reset = armv8pmu_reset;
1237 cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
1238 cpu_pmu->filter_match = armv8pmu_filter_match;
1240 cpu_pmu->pmu.event_idx = armv8pmu_user_event_idx;
1242 cpu_pmu->name = name;
1243 cpu_pmu->map_event = map_event;
1244 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
1245 events : &armv8_pmuv3_events_attr_group;
1246 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
1247 format : &armv8_pmuv3_format_attr_group;
1248 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
1249 caps : &armv8_pmuv3_caps_attr_group;
1251 register_sysctl("kernel", armv8_pmu_sysctl_table);
1256 static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
1257 int (*map_event)(struct perf_event *event))
1259 return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
1262 #define PMUV3_INIT_SIMPLE(name) \
1263 static int name##_pmu_init(struct arm_pmu *cpu_pmu) \
1265 return armv8_pmu_init_nogroups(cpu_pmu, #name, armv8_pmuv3_map_event);\
1268 PMUV3_INIT_SIMPLE(armv8_pmuv3)
1270 PMUV3_INIT_SIMPLE(armv8_cortex_a34)
1271 PMUV3_INIT_SIMPLE(armv8_cortex_a55)
1272 PMUV3_INIT_SIMPLE(armv8_cortex_a65)
1273 PMUV3_INIT_SIMPLE(armv8_cortex_a75)
1274 PMUV3_INIT_SIMPLE(armv8_cortex_a76)
1275 PMUV3_INIT_SIMPLE(armv8_cortex_a77)
1276 PMUV3_INIT_SIMPLE(armv8_cortex_a78)
1277 PMUV3_INIT_SIMPLE(armv9_cortex_a510)
1278 PMUV3_INIT_SIMPLE(armv9_cortex_a710)
1279 PMUV3_INIT_SIMPLE(armv8_cortex_x1)
1280 PMUV3_INIT_SIMPLE(armv9_cortex_x2)
1281 PMUV3_INIT_SIMPLE(armv8_neoverse_e1)
1282 PMUV3_INIT_SIMPLE(armv8_neoverse_n1)
1283 PMUV3_INIT_SIMPLE(armv9_neoverse_n2)
1284 PMUV3_INIT_SIMPLE(armv8_neoverse_v1)
1286 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel)
1287 PMUV3_INIT_SIMPLE(armv8_nvidia_denver)
1289 static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
1291 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35",
1292 armv8_a53_map_event);
1295 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1297 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53",
1298 armv8_a53_map_event);
1301 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1303 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
1304 armv8_a57_map_event);
1307 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1309 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
1310 armv8_a57_map_event);
1313 static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
1315 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73",
1316 armv8_a73_map_event);
1319 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1321 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
1322 armv8_thunder_map_event);
1325 static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1327 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan",
1328 armv8_vulcan_map_event);
1331 static const struct of_device_id armv8_pmu_of_device_ids[] = {
1332 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init},
1333 {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init},
1334 {.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init},
1335 {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
1336 {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init},
1337 {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
1338 {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init},
1339 {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
1340 {.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init},
1341 {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init},
1342 {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init},
1343 {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init},
1344 {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init},
1345 {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init},
1346 {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init},
1347 {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init},
1348 {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init},
1349 {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init},
1350 {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init},
1351 {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init},
1352 {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init},
1353 {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
1354 {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
1355 {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init},
1356 {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init},
1360 static int armv8_pmu_device_probe(struct platform_device *pdev)
1362 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
1365 static struct platform_driver armv8_pmu_driver = {
1367 .name = ARMV8_PMU_PDEV_NAME,
1368 .of_match_table = armv8_pmu_of_device_ids,
1369 .suppress_bind_attrs = true,
1371 .probe = armv8_pmu_device_probe,
1374 static int __init armv8_pmu_driver_init(void)
1377 return platform_driver_register(&armv8_pmu_driver);
1379 return arm_pmu_acpi_probe(armv8_pmuv3_pmu_init);
1381 device_initcall(armv8_pmu_driver_init)
1383 void arch_perf_update_userpage(struct perf_event *event,
1384 struct perf_event_mmap_page *userpg, u64 now)
1386 struct clock_read_data *rd;
1390 userpg->cap_user_time = 0;
1391 userpg->cap_user_time_zero = 0;
1392 userpg->cap_user_time_short = 0;
1393 userpg->cap_user_rdpmc = armv8pmu_event_has_user_read(event);
1395 if (userpg->cap_user_rdpmc) {
1396 if (event->hw.flags & ARMPMU_EVT_64BIT)
1397 userpg->pmc_width = 64;
1399 userpg->pmc_width = 32;
1403 rd = sched_clock_read_begin(&seq);
1405 if (rd->read_sched_clock != arch_timer_read_counter)
1408 userpg->time_mult = rd->mult;
1409 userpg->time_shift = rd->shift;
1410 userpg->time_zero = rd->epoch_ns;
1411 userpg->time_cycles = rd->epoch_cyc;
1412 userpg->time_mask = rd->sched_clock_mask;
1415 * Subtract the cycle base, such that software that
1416 * doesn't know about cap_user_time_short still 'works'
1417 * assuming no wraps.
1419 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);
1420 userpg->time_zero -= ns;
1422 } while (sched_clock_read_retry(seq));
1424 userpg->time_offset = userpg->time_zero - now;
1427 * time_shift is not expected to be greater than 31 due to
1428 * the original published conversion algorithm shifting a
1429 * 32-bit value (now specifies a 64-bit value) - refer
1430 * perf_event_mmap_page documentation in perf_event.h.
1432 if (userpg->time_shift == 32) {
1433 userpg->time_shift = 31;
1434 userpg->time_mult >>= 1;
1438 * Internal timekeeping for enabled/running/stopped times
1439 * is always computed with the sched_clock.
1441 userpg->cap_user_time = 1;
1442 userpg->cap_user_time_zero = 1;
1443 userpg->cap_user_time_short = 1;