1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level CPU initialisation
4 * Based on arch/arm/kernel/head.S
6 * Copyright (C) 1994-2002 Russell King
7 * Copyright (C) 2003-2012 ARM Ltd.
8 * Authors: Catalin Marinas <catalin.marinas@arm.com>
9 * Will Deacon <will.deacon@arm.com>
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <linux/pgtable.h>
16 #include <asm/asm_pointer_auth.h>
17 #include <asm/assembler.h>
20 #include <asm/ptrace.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/cache.h>
23 #include <asm/cputype.h>
24 #include <asm/el2_setup.h>
26 #include <asm/image.h>
27 #include <asm/kernel-pgtable.h>
28 #include <asm/kvm_arm.h>
29 #include <asm/memory.h>
30 #include <asm/pgtable-hwdef.h>
34 #include <asm/sysreg.h>
35 #include <asm/thread_info.h>
38 #include "efi-header.S"
40 #if (PAGE_OFFSET & 0x1fffff) != 0
41 #error PAGE_OFFSET must be at least 2MB aligned
45 * Kernel startup entry point.
46 * ---------------------------
48 * The requirements are:
49 * MMU = off, D-cache = off, I-cache = on or off,
50 * x0 = physical address to the FDT blob.
52 * Note that the callee-saved registers are used for storing variables
53 * that are useful before the MMU is enabled. The allocations are described
54 * in the entry routines.
58 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
60 efi_signature_nop // special NOP to identity as PE/COFF executable
61 b primary_entry // branch to kernel start, magic
62 .quad 0 // Image load offset from start of RAM, little-endian
63 le64sym _kernel_size_le // Effective size of kernel image, little-endian
64 le64sym _kernel_flags_le // Informative flags, little-endian
68 .ascii ARM64_IMAGE_MAGIC // Magic number
69 .long .Lpe_header_offset // Offset to the PE header.
76 * The following callee saved general purpose registers are used on the
77 * primary lowlevel boot path:
79 * Register Scope Purpose
80 * x20 primary_entry() .. __primary_switch() CPU boot mode
81 * x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0
82 * x22 create_idmap() .. start_kernel() ID map VA of the DT blob
83 * x23 primary_entry() .. start_kernel() physical misalignment/KASLR offset
84 * x24 __primary_switch() linear map KASLR seed
85 * x25 primary_entry() .. start_kernel() supported VA size
86 * x28 create_idmap() callee preserved temp register
88 SYM_CODE_START(primary_entry)
90 bl init_kernel_el // w0=cpu_boot_mode
95 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
97 * On return, the CPU will be ready for the MMU to be turned on and
98 * the TCR will have been set.
101 mrs_s x0, SYS_ID_AA64MMFR2_EL1
102 tst x0, #0xf << ID_AA64MMFR2_EL1_VARange_SHIFT
104 mov x25, #VA_BITS_MIN
105 csel x25, x25, x0, eq
108 bl __cpu_setup // initialise processor
110 SYM_CODE_END(primary_entry)
113 * Preserve the arguments passed by the bootloader in x0 .. x3
115 SYM_CODE_START_LOCAL(preserve_boot_args)
116 mov x21, x0 // x21=FDT
118 adr_l x0, boot_args // record the contents of
119 stp x21, x1, [x0] // x0 .. x3 at kernel entry
120 stp x2, x3, [x0, #16]
122 dmb sy // needed before dc ivac with
125 add x1, x0, #0x20 // 4 x 8 bytes
126 b dcache_inval_poc // tail call
127 SYM_CODE_END(preserve_boot_args)
129 SYM_FUNC_START_LOCAL(clear_page_tables)
131 * Clear the init page tables.
137 b __pi_memset // tail call
138 SYM_FUNC_END(clear_page_tables)
141 * Macro to populate page table entries, these entries can be pointers to the next level
142 * or last level entries pointing to physical memory.
144 * tbl: page table address
145 * rtbl: pointer to page table or physical memory
146 * index: start index to write
147 * eindex: end index to write - [index, eindex] written to
148 * flags: flags for pagetable entry to or in
149 * inc: increment to rtbl between each entry
150 * tmp1: temporary variable
152 * Preserves: tbl, eindex, flags, inc
153 * Corrupts: index, tmp1
156 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1
157 .Lpe\@: phys_to_pte \tmp1, \rtbl
158 orr \tmp1, \tmp1, \flags // tmp1 = table entry
159 str \tmp1, [\tbl, \index, lsl #3]
160 add \rtbl, \rtbl, \inc // rtbl = pa next level
161 add \index, \index, #1
167 * Compute indices of table entries from virtual address range. If multiple entries
168 * were needed in the previous page table level then the next page table level is assumed
169 * to be composed of multiple pages. (This effectively scales the end index).
171 * vstart: virtual address of start of range
172 * vend: virtual address of end of range - we map [vstart, vend]
173 * shift: shift used to transform virtual address into index
174 * order: #imm 2log(number of entries in page table)
175 * istart: index in table corresponding to vstart
176 * iend: index in table corresponding to vend
177 * count: On entry: how many extra entries were required in previous level, scales
179 * On exit: returns how many extra entries required for next page table level
181 * Preserves: vstart, vend
182 * Returns: istart, iend, count
184 .macro compute_indices, vstart, vend, shift, order, istart, iend, count
185 ubfx \istart, \vstart, \shift, \order
186 ubfx \iend, \vend, \shift, \order
187 add \iend, \iend, \count, lsl \order
188 sub \count, \iend, \istart
192 * Map memory for specified virtual address range. Each level of page table needed supports
193 * multiple entries. If a level requires n entries the next page table level is assumed to be
194 * formed from n pages.
196 * tbl: location of page table
197 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
198 * vstart: virtual address of start of range
199 * vend: virtual address of end of range - we map [vstart, vend - 1]
200 * flags: flags to use to map last level entries
201 * phys: physical address corresponding to vstart - physical memory is contiguous
202 * order: #imm 2log(number of entries in PGD table)
204 * If extra_shift is set, an extra level will be populated if the end address does
205 * not fit in 'extra_shift' bits. This assumes vend is in the TTBR0 range.
207 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers
208 * Preserves: vstart, flags
209 * Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv
211 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, order, istart, iend, tmp, count, sv, extra_shift
213 add \rtbl, \tbl, #PAGE_SIZE
217 tst \vend, #~((1 << (\extra_shift)) - 1)
219 compute_indices \vstart, \vend, #\extra_shift, #(PAGE_SHIFT - 3), \istart, \iend, \count
221 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
225 compute_indices \vstart, \vend, #PGDIR_SHIFT, #\order, \istart, \iend, \count
227 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
230 #if SWAPPER_PGTABLE_LEVELS > 3
231 compute_indices \vstart, \vend, #PUD_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count
233 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
237 #if SWAPPER_PGTABLE_LEVELS > 2
238 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count
240 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
244 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count
245 bic \rtbl, \phys, #SWAPPER_BLOCK_SIZE - 1
246 populate_entries \tbl, \rtbl, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp
250 * Remap a subregion created with the map_memory macro with modified attributes
251 * or output address. The entire remapped region must have been covered in the
252 * invocation of map_memory.
254 * x0: last level table address (returned in first argument to map_memory)
255 * x1: start VA of the existing mapping
256 * x2: start VA of the region to update
257 * x3: end VA of the region to update (exclusive)
258 * x4: start PA associated with the region to update
259 * x5: attributes to set on the updated region
260 * x6: order of the last level mappings
262 SYM_FUNC_START_LOCAL(remap_region)
263 sub x3, x3, #1 // make end inclusive
265 // Get the index offset for the start of the last level table
267 bfi x1, xzr, #0, #PAGE_SHIFT - 3
269 // Derive the start and end indexes into the last level table
270 // associated with the provided region
277 lsl x6, x1, x6 // block size at this level
279 populate_entries x0, x4, x2, x3, x5, x6, x7
281 SYM_FUNC_END(remap_region)
283 SYM_FUNC_START_LOCAL(create_idmap)
286 * The ID map carries a 1:1 mapping of the physical address range
287 * covered by the loaded image, which could be anywhere in DRAM. This
288 * means that the required size of the VA (== PA) space is decided at
289 * boot time, and could be more than the configured size of the VA
290 * space for ordinary kernel and user space mappings.
292 * There are three cases to consider here:
293 * - 39 <= VA_BITS < 48, and the ID map needs up to 48 VA bits to cover
294 * the placement of the image. In this case, we configure one extra
295 * level of translation on the fly for the ID map only. (This case
296 * also covers 42-bit VA/52-bit PA on 64k pages).
298 * - VA_BITS == 48, and the ID map needs more than 48 VA bits. This can
299 * only happen when using 64k pages, in which case we need to extend
300 * the root level table rather than add a level. Note that we can
301 * treat this case as 'always extended' as long as we take care not
302 * to program an unsupported T0SZ value into the TCR register.
304 * - Combinations that would require two additional levels of
305 * translation are not supported, e.g., VA_BITS==36 on 16k pages, or
306 * VA_BITS==39/4k pages with 5-level paging, where the input address
307 * requires more than 47 or 48 bits, respectively.
310 #define IDMAP_PGD_ORDER (VA_BITS - PGDIR_SHIFT)
311 #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3)
314 * If VA_BITS < 48, we have to configure an additional table level.
315 * First, we have to verify our assumption that the current value of
316 * VA_BITS was chosen such that all translation levels are fully
317 * utilised, and that lowering T0SZ will always result in an additional
318 * translation level to be configured.
320 #if VA_BITS != EXTRA_SHIFT
321 #error "Mismatch between VA_BITS and page size/number of translation levels"
324 #define IDMAP_PGD_ORDER (PHYS_MASK_SHIFT - PGDIR_SHIFT)
327 * If VA_BITS == 48, we don't have to configure an additional
328 * translation level, but the top-level table has more entries.
331 adrp x0, init_idmap_pg_dir
333 adrp x6, _end + MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE
334 mov x7, SWAPPER_RX_MMUFLAGS
336 map_memory x0, x1, x3, x6, x7, x3, IDMAP_PGD_ORDER, x10, x11, x12, x13, x14, EXTRA_SHIFT
338 /* Remap the kernel page tables r/w in the ID map */
342 bic x4, x2, #SWAPPER_BLOCK_SIZE - 1
343 mov x5, SWAPPER_RW_MMUFLAGS
344 mov x6, #SWAPPER_BLOCK_SHIFT
347 /* Remap the FDT after the kernel image */
349 adrp x22, _end + SWAPPER_BLOCK_SIZE
350 bic x2, x22, #SWAPPER_BLOCK_SIZE - 1
351 bfi x22, x21, #0, #SWAPPER_BLOCK_SHIFT // remapped FDT address
352 add x3, x2, #MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE
353 bic x4, x21, #SWAPPER_BLOCK_SIZE - 1
354 mov x5, SWAPPER_RW_MMUFLAGS
355 mov x6, #SWAPPER_BLOCK_SHIFT
359 * Since the page tables have been populated with non-cacheable
360 * accesses (MMU disabled), invalidate those tables again to
361 * remove any speculatively loaded cache lines.
365 adrp x0, init_idmap_pg_dir
366 adrp x1, init_idmap_pg_end
369 SYM_FUNC_END(create_idmap)
371 SYM_FUNC_START_LOCAL(create_kernel_mapping)
373 mov_q x5, KIMAGE_VADDR // compile time __va(_text)
374 #ifdef CONFIG_RELOCATABLE
375 add x5, x5, x23 // add KASLR displacement
377 adrp x6, _end // runtime __pa(_end)
378 adrp x3, _text // runtime __pa(_text)
379 sub x6, x6, x3 // _end - _text
380 add x6, x6, x5 // runtime __va(_end)
381 mov x7, SWAPPER_RW_MMUFLAGS
383 map_memory x0, x1, x5, x6, x7, x3, (VA_BITS - PGDIR_SHIFT), x10, x11, x12, x13, x14
385 dsb ishst // sync with page table walker
387 SYM_FUNC_END(create_kernel_mapping)
390 * Initialize CPU registers with task-specific and cpu-specific context.
392 * Create a final frame record at task_pt_regs(current)->stackframe, so
393 * that the unwinder can identify the final frame record of any task by
394 * its location in the task stack. We reserve the entire pt_regs space
395 * for consistency with user tasks and kthreads.
397 .macro init_cpu_task tsk, tmp1, tmp2
400 ldr \tmp1, [\tsk, #TSK_STACK]
401 add sp, \tmp1, #THREAD_SIZE
402 sub sp, sp, #PT_REGS_SIZE
404 stp xzr, xzr, [sp, #S_STACKFRAME]
405 add x29, sp, #S_STACKFRAME
409 adr_l \tmp1, __per_cpu_offset
410 ldr w\tmp2, [\tsk, #TSK_TI_CPU]
411 ldr \tmp1, [\tmp1, \tmp2, lsl #3]
412 set_this_cpu_offset \tmp1
416 * The following fragment of code is executed with the MMU enabled.
418 * x0 = __pa(KERNEL_START)
420 SYM_FUNC_START_LOCAL(__primary_switched)
422 init_cpu_task x4, x5, x6
424 adr_l x8, vectors // load VBAR_EL1 with virtual
425 msr vbar_el1, x8 // vector table address
428 stp x29, x30, [sp, #-16]!
431 str_l x21, __fdt_pointer, x5 // Save FDT pointer
433 ldr_l x4, kimage_vaddr // Save the offset between
434 sub x4, x4, x0 // the kernel virtual and
435 str_l x4, kimage_voffset, x5 // physical mappings
438 bl set_cpu_boot_mode_flag
441 adr_l x0, __bss_start
446 dsb ishst // Make zero page visible to PTW
449 adr_l x8, vabits_actual // Set this early so KASAN early init
450 str x25, [x8] // ... observes the correct value
451 dc civac, x8 // Make visible to booting secondaries
454 #ifdef CONFIG_RANDOMIZE_BASE
455 adrp x5, memstart_offset_seed // Save KASLR linear map seed
456 strh w24, [x5, :lo12:memstart_offset_seed]
458 #if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS)
461 mov x0, x21 // pass FDT address in x0
462 bl early_fdt_map // Try mapping the FDT early
463 mov x0, x20 // pass the full boot status
464 bl init_feature_override // Parse cpu feature overrides
465 #ifdef CONFIG_UNWIND_PATCH_PAC_INTO_SCS
469 bl finalise_el2 // Prefer VHE if possible
470 ldp x29, x30, [sp], #16
473 SYM_FUNC_END(__primary_switched)
476 * end early head section, begin head code that is also used for
477 * hotplug and needs to have the same protections as the text region
479 .section ".idmap.text","awx"
482 * Starting from EL2 or EL1, configure the CPU to execute at the highest
483 * reachable EL supported by the kernel in a chosen default state. If dropping
484 * from EL2 to EL1, configure EL2 before configuring EL1.
486 * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if
487 * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET.
489 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x0 if
490 * booted in EL1 or EL2 respectively, with the top 32 bits containing
491 * potential context flags. These flags are *not* stored in __boot_cpu_mode.
493 SYM_FUNC_START(init_kernel_el)
495 cmp x0, #CurrentEL_EL2
498 SYM_INNER_LABEL(init_el1, SYM_L_LOCAL)
499 mov_q x0, INIT_SCTLR_EL1_MMU_OFF
502 mov_q x0, INIT_PSTATE_EL1
505 mov w0, #BOOT_CPU_MODE_EL1
508 SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
509 mov_q x0, HCR_HOST_NVHE_FLAGS
515 /* Hypervisor stub */
516 adr_l x0, __hyp_stub_vectors
520 mov_q x1, INIT_SCTLR_EL1_MMU_OFF
523 * Fruity CPUs seem to have HCR_EL2.E2H set to RES1,
524 * making it impossible to start in nVHE mode. Is that
525 * compliant with the architecture? Absolutely not!
531 /* Set a sane SCTLR_EL1, the VHE way */
532 msr_s SYS_SCTLR_EL12, x1
533 mov x2, #BOOT_CPU_FLAG_E2H
541 mov w0, #BOOT_CPU_MODE_EL2
544 SYM_FUNC_END(init_kernel_el)
547 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed
548 * in w0. See arch/arm64/include/asm/virt.h for more info.
550 SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag)
551 adr_l x1, __boot_cpu_mode
552 cmp w0, #BOOT_CPU_MODE_EL2
555 1: str w0, [x1] // Save CPU boot mode
557 SYM_FUNC_END(set_cpu_boot_mode_flag)
560 * This provides a "holding pen" for platforms to hold all secondary
561 * cores are held until we're ready for them to initialise.
563 SYM_FUNC_START(secondary_holding_pen)
564 bl init_kernel_el // w0=cpu_boot_mode
566 mov_q x1, MPIDR_HWID_BITMASK
568 adr_l x3, secondary_holding_pen_release
571 b.eq secondary_startup
574 SYM_FUNC_END(secondary_holding_pen)
577 * Secondary entry point that jumps straight into the kernel. Only to
578 * be used where CPUs are brought online dynamically by the kernel.
580 SYM_FUNC_START(secondary_entry)
581 bl init_kernel_el // w0=cpu_boot_mode
583 SYM_FUNC_END(secondary_entry)
585 SYM_FUNC_START_LOCAL(secondary_startup)
587 * Common entry point for secondary CPUs.
589 mov x20, x0 // preserve boot mode
591 bl __cpu_secondary_check52bitva
593 ldr_l x0, vabits_actual
595 bl __cpu_setup // initialise processor
596 adrp x1, swapper_pg_dir
597 adrp x2, idmap_pg_dir
599 ldr x8, =__secondary_switched
601 SYM_FUNC_END(secondary_startup)
603 SYM_FUNC_START_LOCAL(__secondary_switched)
605 bl set_cpu_boot_mode_flag
606 str_l xzr, __early_cpu_boot_status, x3
611 adr_l x0, secondary_data
612 ldr x2, [x0, #CPU_BOOT_TASK]
613 cbz x2, __secondary_too_slow
615 init_cpu_task x2, x1, x3
617 #ifdef CONFIG_ARM64_PTR_AUTH
618 ptrauth_keys_init_cpu x2, x3, x4, x5
621 bl secondary_start_kernel
623 SYM_FUNC_END(__secondary_switched)
625 SYM_FUNC_START_LOCAL(__secondary_too_slow)
628 b __secondary_too_slow
629 SYM_FUNC_END(__secondary_too_slow)
632 * The booting CPU updates the failed status @__early_cpu_boot_status,
633 * with MMU turned off.
635 * update_early_cpu_boot_status tmp, status
636 * - Corrupts tmp1, tmp2
637 * - Writes 'status' to __early_cpu_boot_status and makes sure
638 * it is committed to memory.
641 .macro update_early_cpu_boot_status status, tmp1, tmp2
643 adr_l \tmp1, __early_cpu_boot_status
646 dc ivac, \tmp1 // Invalidate potentially stale cache line
652 * x0 = SCTLR_EL1 value for turning on the MMU.
653 * x1 = TTBR1_EL1 value
654 * x2 = ID map root table address
656 * Returns to the caller via x30/lr. This requires the caller to be covered
657 * by the .idmap.text section.
659 * Checks if the selected granule size is supported by the CPU.
660 * If it isn't, park the CPU
662 SYM_FUNC_START(__enable_mmu)
663 mrs x3, ID_AA64MMFR0_EL1
664 ubfx x3, x3, #ID_AA64MMFR0_EL1_TGRAN_SHIFT, 4
665 cmp x3, #ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN
666 b.lt __no_granule_support
667 cmp x3, #ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX
668 b.gt __no_granule_support
670 msr ttbr0_el1, x2 // load TTBR0
671 load_ttbr1 x1, x1, x3
676 SYM_FUNC_END(__enable_mmu)
678 SYM_FUNC_START(__cpu_secondary_check52bitva)
680 ldr_l x0, vabits_actual
684 mrs_s x0, SYS_ID_AA64MMFR2_EL1
685 and x0, x0, #(0xf << ID_AA64MMFR2_EL1_VARange_SHIFT)
688 update_early_cpu_boot_status \
689 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1
696 SYM_FUNC_END(__cpu_secondary_check52bitva)
698 SYM_FUNC_START_LOCAL(__no_granule_support)
699 /* Indicate that this CPU can't boot and is stuck in the kernel */
700 update_early_cpu_boot_status \
701 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2
706 SYM_FUNC_END(__no_granule_support)
708 #ifdef CONFIG_RELOCATABLE
709 SYM_FUNC_START_LOCAL(__relocate_kernel)
711 * Iterate over each entry in the relocation table, and apply the
712 * relocations in place.
714 adr_l x9, __rela_start
715 adr_l x10, __rela_end
716 mov_q x11, KIMAGE_VADDR // default virtual offset
717 add x11, x11, x23 // actual virtual offset
721 ldp x12, x13, [x9], #24
723 cmp w13, #R_AARCH64_RELATIVE
725 add x14, x14, x23 // relocate
732 * Apply RELR relocations.
734 * RELR is a compressed format for storing relative relocations. The
735 * encoded sequence of entries looks like:
736 * [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ]
738 * i.e. start with an address, followed by any number of bitmaps. The
739 * address entry encodes 1 relocation. The subsequent bitmap entries
740 * encode up to 63 relocations each, at subsequent offsets following
741 * the last address entry.
743 * The bitmap entries must have 1 in the least significant bit. The
744 * assumption here is that an address cannot have 1 in lsb. Odd
745 * addresses are not supported. Any odd addresses are stored in the RELA
746 * section, which is handled above.
748 * Excluding the least significant bit in the bitmap, each non-zero
749 * bit in the bitmap represents a relocation to be applied to
750 * a corresponding machine word that follows the base address
751 * word. The second least significant bit represents the machine
752 * word immediately following the initial address, and each bit
753 * that follows represents the next word, in linear order. As such,
754 * a single bitmap can encode up to 63 relocations in a 64-bit object.
756 * In this implementation we store the address of the next RELR table
757 * entry in x9, the address being relocated by the current address or
758 * bitmap entry in x13 and the address being relocated by the current
761 adr_l x9, __relr_start
762 adr_l x10, __relr_end
767 tbnz x11, #0, 3f // branch to handle bitmaps
769 ldr x12, [x13] // relocate address entry
771 str x12, [x13], #8 // adjust to start of bitmap
777 tbz x11, #0, 5f // skip bit if not set
778 ldr x12, [x14] // relocate bit
782 5: add x14, x14, #8 // move to next bit's address
786 * Move to the next bitmap's address. 8 is the word size, and 63 is the
787 * number of significant bits in a bitmap entry.
789 add x13, x13, #(8 * 63)
796 SYM_FUNC_END(__relocate_kernel)
799 SYM_FUNC_START_LOCAL(__primary_switch)
800 adrp x1, reserved_pg_dir
801 adrp x2, init_idmap_pg_dir
803 #ifdef CONFIG_RELOCATABLE
804 adrp x23, KERNEL_START
805 and x23, x23, MIN_KIMG_ALIGN - 1
806 #ifdef CONFIG_RANDOMIZE_BASE
811 bl __pi_kaslr_early_init
812 and x24, x0, #SZ_2M - 1 // capture memstart offset seed
813 bic x0, x0, #SZ_2M - 1
814 orr x23, x23, x0 // record kernel offset
818 bl create_kernel_mapping
821 load_ttbr1 x1, x1, x2
822 #ifdef CONFIG_RELOCATABLE
825 ldr x8, =__primary_switched
826 adrp x0, KERNEL_START // __pa(KERNEL_START)
828 SYM_FUNC_END(__primary_switch)