1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
5 * Copyright (C) 2012 ARM Ltd.
6 * Authors: Catalin Marinas <catalin.marinas@arm.com>
7 * Will Deacon <will.deacon@arm.com>
10 #include <linux/arm-smccc.h>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
14 #include <asm/alternative.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cpufeature.h>
18 #include <asm/errno.h>
21 #include <asm/memory.h>
23 #include <asm/processor.h>
24 #include <asm/ptrace.h>
25 #include <asm/thread_info.h>
26 #include <asm/asm-uaccess.h>
27 #include <asm/unistd.h>
30 * Context tracking subsystem. Used to instrument transitions
31 * between user and kernel mode.
33 .macro ct_user_exit_irqoff
34 #ifdef CONFIG_CONTEXT_TRACKING
35 bl enter_from_user_mode
40 #ifdef CONFIG_CONTEXT_TRACKING
41 bl context_tracking_user_enter
46 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
60 .macro kernel_ventry, el, label, regsize = 64
62 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
63 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
72 alternative_else_nop_endif
75 sub sp, sp, #S_FRAME_SIZE
76 #ifdef CONFIG_VMAP_STACK
78 * Test whether the SP has overflowed, without corrupting a GPR.
79 * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT).
81 add sp, sp, x0 // sp' = sp + x0
82 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
83 tbnz x0, #THREAD_SHIFT, 0f
84 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
85 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
90 * Either we've just detected an overflow, or we've taken an exception
91 * while on the overflow stack. Either way, we won't return to
92 * userspace, and can clobber EL0 registers to free up GPRs.
95 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
98 /* Recover the original x0 value and stash it in tpidrro_el0 */
102 /* Switch to the overflow stack */
103 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
106 * Check whether we were already on the overflow stack. This may happen
107 * after panic() re-enables interrupts.
109 mrs x0, tpidr_el0 // sp of interrupted context
110 sub x0, sp, x0 // delta with top of overflow stack
111 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
112 b.ne __bad_stack // no? -> bad stack pointer
114 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
121 .macro tramp_alias, dst, sym
122 mov_q \dst, TRAMP_VALIAS
123 add \dst, \dst, #(\sym - .entry.tramp.text)
126 // This macro corrupts x0-x3. It is the caller's duty
127 // to save/restore them if required.
128 .macro apply_ssbd, state, tmp1, tmp2
129 #ifdef CONFIG_ARM64_SSBD
130 alternative_cb arm64_enable_wa2_handling
131 b .L__asm_ssbd_skip\@
133 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
134 cbz \tmp2, .L__asm_ssbd_skip\@
135 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
136 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
137 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
139 alternative_cb arm64_update_smccc_conduit
140 nop // Patched to SMC/HVC #0
146 .macro kernel_entry, el, regsize = 64
148 mov w0, w0 // zero upper 32 bits of x0
150 stp x0, x1, [sp, #16 * 0]
151 stp x2, x3, [sp, #16 * 1]
152 stp x4, x5, [sp, #16 * 2]
153 stp x6, x7, [sp, #16 * 3]
154 stp x8, x9, [sp, #16 * 4]
155 stp x10, x11, [sp, #16 * 5]
156 stp x12, x13, [sp, #16 * 6]
157 stp x14, x15, [sp, #16 * 7]
158 stp x16, x17, [sp, #16 * 8]
159 stp x18, x19, [sp, #16 * 9]
160 stp x20, x21, [sp, #16 * 10]
161 stp x22, x23, [sp, #16 * 11]
162 stp x24, x25, [sp, #16 * 12]
163 stp x26, x27, [sp, #16 * 13]
164 stp x28, x29, [sp, #16 * 14]
169 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
170 ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug
171 disable_step_tsk x19, x20 // exceptions when scheduling.
173 apply_ssbd 1, x22, x23
176 add x21, sp, #S_FRAME_SIZE
178 /* Save the task's original addr_limit and set USER_DS */
179 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
180 str x20, [sp, #S_ORIG_ADDR_LIMIT]
182 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
183 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
184 .endif /* \el == 0 */
187 stp lr, x21, [sp, #S_LR]
190 * In order to be able to dump the contents of struct pt_regs at the
191 * time the exception was taken (in case we attempt to walk the call
192 * stack later), chain it together with the stack frames.
195 stp xzr, xzr, [sp, #S_STACKFRAME]
197 stp x29, x22, [sp, #S_STACKFRAME]
199 add x29, sp, #S_STACKFRAME
201 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
203 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
204 * EL0, there is no need to check the state of TTBR0_EL1 since
205 * accesses are always enabled.
206 * Note that the meaning of this bit differs from the ARMv8.1 PAN
207 * feature as all TTBR0_EL1 accesses are disabled, not just those to
210 alternative_if ARM64_HAS_PAN
211 b 1f // skip TTBR0 PAN
212 alternative_else_nop_endif
216 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
217 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
218 b.eq 1f // TTBR0 access already disabled
219 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
222 __uaccess_ttbr0_disable x21
226 stp x22, x23, [sp, #S_PC]
228 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
231 str w21, [sp, #S_SYSCALLNO]
235 * Set sp_el0 to current thread_info.
242 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
243 mrs_s x20, SYS_ICC_PMR_EL1
244 str x20, [sp, #S_PMR_SAVE]
245 alternative_else_nop_endif
248 * Registers that may be useful after this macro is invoked:
253 * x23 - aborted PSTATE
257 .macro kernel_exit, el
261 /* Restore the task's original addr_limit. */
262 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
263 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
265 /* No need to restore UAO, it will be restored from SPSR_EL1 */
269 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
270 ldr x20, [sp, #S_PMR_SAVE]
271 msr_s SYS_ICC_PMR_EL1, x20
272 /* Ensure priority change is seen by redistributor */
274 alternative_else_nop_endif
276 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
281 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
283 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
286 alternative_if ARM64_HAS_PAN
287 b 2f // skip TTBR0 PAN
288 alternative_else_nop_endif
291 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
294 __uaccess_ttbr0_enable x0, x1
298 * Enable errata workarounds only if returning to user. The only
299 * workaround currently required for TTBR0_EL1 changes are for the
300 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
303 bl post_ttbr_update_workaround
307 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
313 ldr x23, [sp, #S_SP] // load return stack pointer
315 tst x22, #PSR_MODE32_BIT // native task?
318 #ifdef CONFIG_ARM64_ERRATUM_845719
319 alternative_if ARM64_WORKAROUND_845719
320 #ifdef CONFIG_PID_IN_CONTEXTIDR
321 mrs x29, contextidr_el1
322 msr contextidr_el1, x29
324 msr contextidr_el1, xzr
326 alternative_else_nop_endif
329 #ifdef CONFIG_ARM64_ERRATUM_1418040
330 alternative_if_not ARM64_WORKAROUND_1418040
332 alternative_else_nop_endif
334 * if (x22.mode32 == cntkctl_el1.el0vcten)
335 * cntkctl_el1.el0vcten = ~cntkctl_el1.el0vcten
338 eon x0, x1, x22, lsr #3
340 eor x1, x1, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN
347 msr elr_el1, x21 // set up the return data
349 ldp x0, x1, [sp, #16 * 0]
350 ldp x2, x3, [sp, #16 * 1]
351 ldp x4, x5, [sp, #16 * 2]
352 ldp x6, x7, [sp, #16 * 3]
353 ldp x8, x9, [sp, #16 * 4]
354 ldp x10, x11, [sp, #16 * 5]
355 ldp x12, x13, [sp, #16 * 6]
356 ldp x14, x15, [sp, #16 * 7]
357 ldp x16, x17, [sp, #16 * 8]
358 ldp x18, x19, [sp, #16 * 9]
359 ldp x20, x21, [sp, #16 * 10]
360 ldp x22, x23, [sp, #16 * 11]
361 ldp x24, x25, [sp, #16 * 12]
362 ldp x26, x27, [sp, #16 * 13]
363 ldp x28, x29, [sp, #16 * 14]
365 add sp, sp, #S_FRAME_SIZE // restore sp
368 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
369 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
372 tramp_alias x30, tramp_exit_native
375 tramp_alias x30, tramp_exit_compat
384 .macro irq_stack_entry
385 mov x19, sp // preserve the original sp
388 * Compare sp with the base of the task stack.
389 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
390 * and should switch to the irq stack.
392 ldr x25, [tsk, TSK_STACK]
394 and x25, x25, #~(THREAD_SIZE - 1)
397 ldr_this_cpu x25, irq_stack_ptr, x26
398 mov x26, #IRQ_STACK_SIZE
401 /* switch to the irq stack */
407 * x19 should be preserved between irq_stack_entry and
410 .macro irq_stack_exit
414 /* GPRs used by entry code */
415 tsk .req x28 // current thread_info
418 * Interrupt handling.
421 ldr_l x1, handle_arch_irq
428 #ifdef CONFIG_ARM64_PSEUDO_NMI
430 * Set res to 0 if irqs were unmasked in interrupted context.
431 * Otherwise set res to non-0 value.
433 .macro test_irqs_unmasked res:req, pmr:req
434 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
435 sub \res, \pmr, #GIC_PRIO_IRQON
442 .macro gic_prio_kentry_setup, tmp:req
443 #ifdef CONFIG_ARM64_PSEUDO_NMI
444 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
445 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON)
446 msr_s SYS_ICC_PMR_EL1, \tmp
447 alternative_else_nop_endif
451 .macro gic_prio_irq_setup, pmr:req, tmp:req
452 #ifdef CONFIG_ARM64_PSEUDO_NMI
453 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
454 orr \tmp, \pmr, #GIC_PRIO_PSR_I_SET
455 msr_s SYS_ICC_PMR_EL1, \tmp
456 alternative_else_nop_endif
465 .pushsection ".entry.text", "ax"
469 kernel_ventry 1, sync_invalid // Synchronous EL1t
470 kernel_ventry 1, irq_invalid // IRQ EL1t
471 kernel_ventry 1, fiq_invalid // FIQ EL1t
472 kernel_ventry 1, error_invalid // Error EL1t
474 kernel_ventry 1, sync // Synchronous EL1h
475 kernel_ventry 1, irq // IRQ EL1h
476 kernel_ventry 1, fiq_invalid // FIQ EL1h
477 kernel_ventry 1, error // Error EL1h
479 kernel_ventry 0, sync // Synchronous 64-bit EL0
480 kernel_ventry 0, irq // IRQ 64-bit EL0
481 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0
482 kernel_ventry 0, error // Error 64-bit EL0
485 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
486 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
487 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0
488 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
490 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
491 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
492 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
493 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
497 #ifdef CONFIG_VMAP_STACK
499 * We detected an overflow in kernel_ventry, which switched to the
500 * overflow stack. Stash the exception regs, and head to our overflow
504 /* Restore the original x0 value */
508 * Store the original GPRs to the new stack. The orginal SP (minus
509 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
511 sub sp, sp, #S_FRAME_SIZE
514 add x0, x0, #S_FRAME_SIZE
517 /* Stash the regs for handle_bad_stack */
523 #endif /* CONFIG_VMAP_STACK */
526 * Invalid mode handlers
528 .macro inv_entry, el, reason, regsize = 64
529 kernel_entry \el, \regsize
538 inv_entry 0, BAD_SYNC
539 ENDPROC(el0_sync_invalid)
543 ENDPROC(el0_irq_invalid)
547 ENDPROC(el0_fiq_invalid)
550 inv_entry 0, BAD_ERROR
551 ENDPROC(el0_error_invalid)
554 el0_fiq_invalid_compat:
555 inv_entry 0, BAD_FIQ, 32
556 ENDPROC(el0_fiq_invalid_compat)
560 inv_entry 1, BAD_SYNC
561 ENDPROC(el1_sync_invalid)
565 ENDPROC(el1_irq_invalid)
569 ENDPROC(el1_fiq_invalid)
572 inv_entry 1, BAD_ERROR
573 ENDPROC(el1_error_invalid)
581 mrs x1, esr_el1 // read the syndrome register
582 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
583 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
585 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
587 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
589 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
591 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
593 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
599 * Fall through to the Data abort case
603 * Data abort handling
606 inherit_daif pstate=x23, tmp=x2
608 mov x2, sp // struct pt_regs
614 * PC alignment exception handling. We don't handle SP alignment faults,
615 * since we will have hit a recursive exception when trying to push the
619 inherit_daif pstate=x23, tmp=x2
625 * Undefined instruction
627 inherit_daif pstate=x23, tmp=x2
633 * Debug exception handling
635 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
636 cinc x24, x24, eq // set bit '0'
637 tbz x24, #0, el1_inv // EL1 only
638 gic_prio_kentry_setup tmp=x3
640 mov x2, sp // struct pt_regs
641 bl do_debug_exception
644 // TODO: add support for undefined instructions in kernel mode
645 inherit_daif pstate=x23, tmp=x2
656 gic_prio_irq_setup pmr=x20, tmp=x1
659 #ifdef CONFIG_ARM64_PSEUDO_NMI
660 test_irqs_unmasked res=x0, pmr=x20
666 #ifdef CONFIG_TRACE_IRQFLAGS
667 bl trace_hardirqs_off
672 #ifdef CONFIG_PREEMPT
673 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count
674 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
676 * DA_F were cleared at start of handling. If anything is set in DAIF,
677 * we come back from an NMI, so skip preemption
681 alternative_else_nop_endif
682 cbnz x24, 1f // preempt count != 0 || NMI return path
683 bl arm64_preempt_schedule_irq // irq en/disable is done inside
687 #ifdef CONFIG_ARM64_PSEUDO_NMI
689 * When using IRQ priority masking, we can get spurious interrupts while
690 * PMR is set to GIC_PRIO_IRQOFF. An NMI might also have occurred in a
691 * section with interrupts disabled. Skip tracing in those cases.
693 test_irqs_unmasked res=x0, pmr=x20
699 #ifdef CONFIG_TRACE_IRQFLAGS
700 #ifdef CONFIG_ARM64_PSEUDO_NMI
701 test_irqs_unmasked res=x0, pmr=x20
717 mrs x25, esr_el1 // read the syndrome register
718 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
719 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
721 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
723 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
725 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
727 cmp x24, #ESR_ELx_EC_SVE // SVE access
729 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
731 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
732 ccmp x24, #ESR_ELx_EC_WFx, #4, ne
734 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
736 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
738 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
740 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
748 mrs x25, esr_el1 // read the syndrome register
749 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
750 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
752 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
754 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
756 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
758 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
760 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
762 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
764 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
766 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
768 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
770 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
772 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
774 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
778 gic_prio_kentry_setup tmp=x1
780 bl el0_svc_compat_handler
794 * Trapped CP15 (MRC, MCR, MRRC, MCRR) instructions
806 * Data abort handling
811 untagged_addr x0, x26
818 * Instruction abort handling
821 gic_prio_kentry_setup tmp=x0
824 #ifdef CONFIG_TRACE_IRQFLAGS
825 bl trace_hardirqs_off
830 bl do_el0_ia_bp_hardening
834 * Floating Point or Advanced SIMD access
844 * Scalable Vector Extension access
854 * Floating Point, Advanced SIMD or SVE exception
869 * Stack or PC alignment exception handling
871 gic_prio_kentry_setup tmp=x0
874 #ifdef CONFIG_TRACE_IRQFLAGS
875 bl trace_hardirqs_off
884 * Undefined instruction
893 * System instructions, for trapped cache maintenance instructions
903 * Debug exception handling
905 tbnz x24, #0, el0_inv // EL0 only
907 gic_prio_kentry_setup tmp=x3
912 bl do_debug_exception
929 gic_prio_irq_setup pmr=x20, tmp=x0
933 #ifdef CONFIG_TRACE_IRQFLAGS
934 bl trace_hardirqs_off
937 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
939 bl do_el0_irq_bp_hardening
944 #ifdef CONFIG_TRACE_IRQFLAGS
953 gic_prio_kentry_setup tmp=x2
964 gic_prio_kentry_setup tmp=x2
975 * Ok, we need to do extra processing, enter the slow path.
980 #ifdef CONFIG_TRACE_IRQFLAGS
981 bl trace_hardirqs_on // enabled while in userspace
983 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
986 * "slow" syscall return path.
990 gic_prio_kentry_setup tmp=x3
991 ldr x1, [tsk, #TSK_TI_FLAGS]
992 and x2, x1, #_TIF_WORK_MASK
993 cbnz x2, work_pending
995 enable_step_tsk x1, x2
996 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
1000 ENDPROC(ret_to_user)
1007 gic_prio_kentry_setup tmp=x1
1013 .popsection // .entry.text
1015 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1017 * Exception vectors trampoline.
1019 .pushsection ".entry.tramp.text", "ax"
1021 .macro tramp_map_kernel, tmp
1023 add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
1024 bic \tmp, \tmp, #USER_ASID_FLAG
1026 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
1027 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
1028 /* ASID already in \tmp[63:48] */
1029 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
1030 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
1031 /* 2MB boundary containing the vectors, so we nobble the walk cache */
1032 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
1036 alternative_else_nop_endif
1037 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
1040 .macro tramp_unmap_kernel, tmp
1042 sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
1043 orr \tmp, \tmp, #USER_ASID_FLAG
1046 * We avoid running the post_ttbr_update_workaround here because
1047 * it's only needed by Cavium ThunderX, which requires KPTI to be
1052 .macro tramp_ventry, regsize = 64
1056 msr tpidrro_el0, x30 // Restored in kernel_ventry
1059 * Defend against branch aliasing attacks by pushing a dummy
1060 * entry onto the return stack and using a RET instruction to
1061 * enter the full-fat kernel vectors.
1066 tramp_map_kernel x30
1067 #ifdef CONFIG_RANDOMIZE_BASE
1068 adr x30, tramp_vectors + PAGE_SIZE
1069 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
1074 prfm plil1strm, [x30, #(1b - tramp_vectors)]
1076 add x30, x30, #(1b - tramp_vectors)
1081 .macro tramp_exit, regsize = 64
1082 adr x30, tramp_vectors
1084 tramp_unmap_kernel x30
1093 ENTRY(tramp_vectors)
1107 ENTRY(tramp_exit_native)
1109 END(tramp_exit_native)
1111 ENTRY(tramp_exit_compat)
1113 END(tramp_exit_compat)
1116 .popsection // .entry.tramp.text
1117 #ifdef CONFIG_RANDOMIZE_BASE
1118 .pushsection ".rodata", "a"
1120 .globl __entry_tramp_data_start
1121 __entry_tramp_data_start:
1123 .popsection // .rodata
1124 #endif /* CONFIG_RANDOMIZE_BASE */
1125 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1128 * Register switch for AArch64. The callee-saved registers need to be saved
1129 * and restored. On entry:
1130 * x0 = previous task_struct (must be preserved across the switch)
1131 * x1 = next task_struct
1132 * Previous and next are guaranteed not to be the same.
1135 ENTRY(cpu_switch_to)
1136 mov x10, #THREAD_CPU_CONTEXT
1139 stp x19, x20, [x8], #16 // store callee-saved registers
1140 stp x21, x22, [x8], #16
1141 stp x23, x24, [x8], #16
1142 stp x25, x26, [x8], #16
1143 stp x27, x28, [x8], #16
1144 stp x29, x9, [x8], #16
1147 ldp x19, x20, [x8], #16 // restore callee-saved registers
1148 ldp x21, x22, [x8], #16
1149 ldp x23, x24, [x8], #16
1150 ldp x25, x26, [x8], #16
1151 ldp x27, x28, [x8], #16
1152 ldp x29, x9, [x8], #16
1157 ENDPROC(cpu_switch_to)
1158 NOKPROBE(cpu_switch_to)
1161 * This is how we return from a fork.
1163 ENTRY(ret_from_fork)
1165 cbz x19, 1f // not a kernel thread
1168 1: get_current_task tsk
1170 ENDPROC(ret_from_fork)
1171 NOKPROBE(ret_from_fork)
1173 #ifdef CONFIG_ARM_SDE_INTERFACE
1175 #include <asm/sdei.h>
1176 #include <uapi/linux/arm_sdei.h>
1178 .macro sdei_handler_exit exit_mode
1179 /* On success, this call never returns... */
1180 cmp \exit_mode, #SDEI_EXIT_SMC
1188 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1190 * The regular SDEI entry point may have been unmapped along with the rest of
1191 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
1192 * argument accessible.
1194 * This clobbers x4, __sdei_handler() will restore this from firmware's
1198 .pushsection ".entry.tramp.text", "ax"
1199 ENTRY(__sdei_asm_entry_trampoline)
1201 tbz x4, #USER_ASID_BIT, 1f
1203 tramp_map_kernel tmp=x4
1208 * Use reg->interrupted_regs.addr_limit to remember whether to unmap
1209 * the kernel on exit.
1211 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
1213 #ifdef CONFIG_RANDOMIZE_BASE
1214 adr x4, tramp_vectors + PAGE_SIZE
1215 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
1218 ldr x4, =__sdei_asm_handler
1221 ENDPROC(__sdei_asm_entry_trampoline)
1222 NOKPROBE(__sdei_asm_entry_trampoline)
1225 * Make the exit call and restore the original ttbr1_el1
1227 * x0 & x1: setup for the exit API call
1229 * x4: struct sdei_registered_event argument from registration time.
1231 ENTRY(__sdei_asm_exit_trampoline)
1232 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)]
1235 tramp_unmap_kernel tmp=x4
1237 1: sdei_handler_exit exit_mode=x2
1238 ENDPROC(__sdei_asm_exit_trampoline)
1239 NOKPROBE(__sdei_asm_exit_trampoline)
1241 .popsection // .entry.tramp.text
1242 #ifdef CONFIG_RANDOMIZE_BASE
1243 .pushsection ".rodata", "a"
1244 __sdei_asm_trampoline_next_handler:
1245 .quad __sdei_asm_handler
1246 .popsection // .rodata
1247 #endif /* CONFIG_RANDOMIZE_BASE */
1248 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1251 * Software Delegated Exception entry point.
1254 * x1: struct sdei_registered_event argument from registration time.
1255 * x2: interrupted PC
1256 * x3: interrupted PSTATE
1257 * x4: maybe clobbered by the trampoline
1259 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
1260 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
1263 ENTRY(__sdei_asm_handler)
1264 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
1265 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
1266 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
1267 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
1268 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
1269 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
1270 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
1271 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
1272 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
1273 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1274 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
1275 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
1276 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
1277 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1279 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1283 #ifdef CONFIG_VMAP_STACK
1285 * entry.S may have been using sp as a scratch register, find whether
1286 * this is a normal or critical event and switch to the appropriate
1287 * stack for this CPU.
1289 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
1291 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1293 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1294 2: mov x6, #SDEI_STACK_SIZE
1300 * We may have interrupted userspace, or a guest, or exit-from or
1301 * return-to either of these. We can't trust sp_el0, restore it.
1304 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
1307 /* If we interrupted the kernel point to the previous stack/frame. */
1311 csel x29, x29, xzr, eq // fp, or zero
1312 csel x4, x2, xzr, eq // elr, or zero
1314 stp x29, x4, [sp, #-16]!
1317 add x0, x19, #SDEI_EVENT_INTREGS
1322 /* restore regs >x17 that we clobbered */
1323 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
1324 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
1325 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
1326 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1329 mov x1, x0 // address to complete_and_resume
1330 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1332 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1333 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1336 ldr_l x2, sdei_exit_mode
1338 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1339 sdei_handler_exit exit_mode=x2
1340 alternative_else_nop_endif
1342 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1343 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
1346 ENDPROC(__sdei_asm_handler)
1347 NOKPROBE(__sdei_asm_handler)
1348 #endif /* CONFIG_ARM_SDE_INTERFACE */