1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
5 * Copyright (C) 2012 ARM Ltd.
6 * Authors: Catalin Marinas <catalin.marinas@arm.com>
7 * Will Deacon <will.deacon@arm.com>
10 #include <linux/arm-smccc.h>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
14 #include <asm/alternative.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asm_pointer_auth.h>
19 #include <asm/cpufeature.h>
20 #include <asm/errno.h>
23 #include <asm/memory.h>
25 #include <asm/processor.h>
26 #include <asm/ptrace.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-uaccess.h>
30 #include <asm/unistd.h>
33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
38 .macro kernel_ventry, el:req, ht:req, regsize:req, label:req
43 * This must be the first instruction of the EL0 vector entries. It is
44 * skipped by the trampoline vectors, to trigger the cleanup.
46 b .Lskip_tramp_vectors_cleanup\@
53 .Lskip_tramp_vectors_cleanup\@:
56 sub sp, sp, #PT_REGS_SIZE
57 #ifdef CONFIG_VMAP_STACK
59 * Test whether the SP has overflowed, without corrupting a GPR.
60 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT)
61 * should always be zero.
63 add sp, sp, x0 // sp' = sp + x0
64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
65 tbnz x0, #THREAD_SHIFT, 0f
66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
68 b el\el\ht\()_\regsize\()_\label
72 * Either we've just detected an overflow, or we've taken an exception
73 * while on the overflow stack. Either way, we won't return to
74 * userspace, and can clobber EL0 registers to free up GPRs.
77 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */
80 /* Recover the original x0 value and stash it in tpidrro_el0 */
84 /* Switch to the overflow stack */
85 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
88 * Check whether we were already on the overflow stack. This may happen
89 * after panic() re-enables interrupts.
91 mrs x0, tpidr_el0 // sp of interrupted context
92 sub x0, sp, x0 // delta with top of overflow stack
93 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
94 b.ne __bad_stack // no? -> bad stack pointer
96 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
100 b el\el\ht\()_\regsize\()_\label
101 .org .Lventry_start\@ + 128 // Did we overflow the ventry slot?
104 .macro tramp_alias, dst, sym, tmp
105 mov_q \dst, TRAMP_VALIAS
108 adr_l \tmp, .entry.tramp.text
113 * This macro corrupts x0-x3. It is the caller's duty to save/restore
116 .macro apply_ssbd, state, tmp1, tmp2
117 alternative_cb ARM64_ALWAYS_SYSTEM, spectre_v4_patch_fw_mitigation_enable
118 b .L__asm_ssbd_skip\@ // Patched to NOP
120 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
121 cbz \tmp2, .L__asm_ssbd_skip\@
122 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
123 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
124 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
126 alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit
127 nop // Patched to SMC/HVC #0
132 /* Check for MTE asynchronous tag check faults */
133 .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr
134 #ifdef CONFIG_ARM64_MTE
136 alternative_if_not ARM64_MTE
138 alternative_else_nop_endif
140 * Asynchronous tag check faults are only possible in ASYNC (2) or
141 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is
142 * set, so skip the check if it is unset.
144 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f
145 mrs_s \tmp, SYS_TFSRE0_EL1
146 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f
147 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */
148 mov \tmp, #_TIF_MTE_ASYNC_FAULT
149 add \ti_flags, tsk, #TSK_TI_FLAGS
150 stset \tmp, [\ti_flags]
155 /* Clear the MTE asynchronous tag check faults */
156 .macro clear_mte_async_tcf thread_sctlr
157 #ifdef CONFIG_ARM64_MTE
158 alternative_if ARM64_MTE
159 /* See comment in check_mte_async_tcf above. */
160 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f
162 msr_s SYS_TFSRE0_EL1, xzr
164 alternative_else_nop_endif
168 .macro mte_set_gcr, mte_ctrl, tmp
169 #ifdef CONFIG_ARM64_MTE
170 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16
171 orr \tmp, \tmp, #SYS_GCR_EL1_RRND
172 msr_s SYS_GCR_EL1, \tmp
176 .macro mte_set_kernel_gcr, tmp, tmp2
177 #ifdef CONFIG_KASAN_HW_TAGS
178 alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable
181 mov \tmp, KERNEL_GCR_EL1
182 msr_s SYS_GCR_EL1, \tmp
187 .macro mte_set_user_gcr, tsk, tmp, tmp2
188 #ifdef CONFIG_KASAN_HW_TAGS
189 alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable
192 ldr \tmp, [\tsk, #THREAD_MTE_CTRL]
194 mte_set_gcr \tmp, \tmp2
199 .macro kernel_entry, el, regsize = 64
201 alternative_insn nop, SET_PSTATE_DIT(1), ARM64_HAS_DIT
204 mov w0, w0 // zero upper 32 bits of x0
206 stp x0, x1, [sp, #16 * 0]
207 stp x2, x3, [sp, #16 * 1]
208 stp x4, x5, [sp, #16 * 2]
209 stp x6, x7, [sp, #16 * 3]
210 stp x8, x9, [sp, #16 * 4]
211 stp x10, x11, [sp, #16 * 5]
212 stp x12, x13, [sp, #16 * 6]
213 stp x14, x15, [sp, #16 * 7]
214 stp x16, x17, [sp, #16 * 8]
215 stp x18, x19, [sp, #16 * 9]
216 stp x20, x21, [sp, #16 * 10]
217 stp x22, x23, [sp, #16 * 11]
218 stp x24, x25, [sp, #16 * 12]
219 stp x26, x27, [sp, #16 * 13]
220 stp x28, x29, [sp, #16 * 14]
225 ldr_this_cpu tsk, __entry_task, x20
229 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions
232 ldr x19, [tsk, #TSK_TI_FLAGS]
233 disable_step_tsk x19, x20
235 /* Check for asynchronous tag check faults in user space */
236 ldr x0, [tsk, THREAD_SCTLR_USER]
237 check_mte_async_tcf x22, x23, x0
239 #ifdef CONFIG_ARM64_PTR_AUTH
240 alternative_if ARM64_HAS_ADDRESS_AUTH
242 * Enable IA for in-kernel PAC if the task had it disabled. Although
243 * this could be implemented with an unconditional MRS which would avoid
244 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76.
246 * Install the kernel IA key only if IA was enabled in the task. If IA
247 * was disabled on kernel exit then we would have left the kernel IA
248 * installed so there is no need to install it again.
250 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
251 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23
255 orr x0, x0, SCTLR_ELx_ENIA
258 alternative_else_nop_endif
261 apply_ssbd 1, x22, x23
263 mte_set_kernel_gcr x22, x23
266 * Any non-self-synchronizing system register updates required for
267 * kernel entry should be placed before this point.
269 alternative_if ARM64_MTE
272 alternative_else_nop_endif
273 alternative_if ARM64_HAS_ADDRESS_AUTH
275 alternative_else_nop_endif
280 add x21, sp, #PT_REGS_SIZE
282 .endif /* \el == 0 */
285 stp lr, x21, [sp, #S_LR]
288 * For exceptions from EL0, create a final frame record.
289 * For exceptions from EL1, create a synthetic frame record so the
290 * interrupted code shows up in the backtrace.
293 stp xzr, xzr, [sp, #S_STACKFRAME]
295 stp x29, x22, [sp, #S_STACKFRAME]
297 add x29, sp, #S_STACKFRAME
299 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
300 alternative_if_not ARM64_HAS_PAN
301 bl __swpan_entry_el\el
302 alternative_else_nop_endif
305 stp x22, x23, [sp, #S_PC]
307 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
310 str w21, [sp, #S_SYSCALLNO]
313 #ifdef CONFIG_ARM64_PSEUDO_NMI
315 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
316 mrs_s x20, SYS_ICC_PMR_EL1
317 str x20, [sp, #S_PMR_SAVE]
318 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET
319 msr_s SYS_ICC_PMR_EL1, x20
320 alternative_else_nop_endif
324 * Registers that may be useful after this macro is invoked:
329 * x23 - aborted PSTATE
333 .macro kernel_exit, el
338 #ifdef CONFIG_ARM64_PSEUDO_NMI
340 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
341 ldr x20, [sp, #S_PMR_SAVE]
342 msr_s SYS_ICC_PMR_EL1, x20
343 mrs_s x21, SYS_ICC_CTLR_EL1
344 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE
345 dsb sy // Ensure priority change is seen by redistributor
347 alternative_else_nop_endif
350 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
352 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
353 alternative_if_not ARM64_HAS_PAN
354 bl __swpan_exit_el\el
355 alternative_else_nop_endif
359 ldr x23, [sp, #S_SP] // load return stack pointer
361 tst x22, #PSR_MODE32_BIT // native task?
364 #ifdef CONFIG_ARM64_ERRATUM_845719
365 alternative_if ARM64_WORKAROUND_845719
366 #ifdef CONFIG_PID_IN_CONTEXTIDR
367 mrs x29, contextidr_el1
368 msr contextidr_el1, x29
370 msr contextidr_el1, xzr
372 alternative_else_nop_endif
377 /* Ignore asynchronous tag check faults in the uaccess routines */
378 ldr x0, [tsk, THREAD_SCTLR_USER]
379 clear_mte_async_tcf x0
381 #ifdef CONFIG_ARM64_PTR_AUTH
382 alternative_if ARM64_HAS_ADDRESS_AUTH
384 * IA was enabled for in-kernel PAC. Disable it now if needed, or
385 * alternatively install the user's IA. All other per-task keys and
386 * SCTLR bits were updated on task switch.
388 * No kernel C function calls after this.
390 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
391 __ptrauth_keys_install_user tsk, x0, x1, x2
395 bic x0, x0, SCTLR_ELx_ENIA
398 alternative_else_nop_endif
401 mte_set_user_gcr tsk, x0, x1
406 msr elr_el1, x21 // set up the return data
408 ldp x0, x1, [sp, #16 * 0]
409 ldp x2, x3, [sp, #16 * 1]
410 ldp x4, x5, [sp, #16 * 2]
411 ldp x6, x7, [sp, #16 * 3]
412 ldp x8, x9, [sp, #16 * 4]
413 ldp x10, x11, [sp, #16 * 5]
414 ldp x12, x13, [sp, #16 * 6]
415 ldp x14, x15, [sp, #16 * 7]
416 ldp x16, x17, [sp, #16 * 8]
417 ldp x18, x19, [sp, #16 * 9]
418 ldp x20, x21, [sp, #16 * 10]
419 ldp x22, x23, [sp, #16 * 11]
420 ldp x24, x25, [sp, #16 * 12]
421 ldp x26, x27, [sp, #16 * 13]
422 ldp x28, x29, [sp, #16 * 14]
425 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
427 add sp, sp, #PT_REGS_SIZE // restore sp
429 alternative_else_nop_endif
430 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
433 tramp_alias x30, tramp_exit_native, x29
436 tramp_alias x30, tramp_exit_compat, x29
441 add sp, sp, #PT_REGS_SIZE // restore sp
443 /* Ensure any device/NC reads complete */
444 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412
451 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
453 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
454 * EL0, there is no need to check the state of TTBR0_EL1 since
455 * accesses are always enabled.
456 * Note that the meaning of this bit differs from the ARMv8.1 PAN
457 * feature as all TTBR0_EL1 accesses are disabled, not just those to
460 SYM_CODE_START_LOCAL(__swpan_entry_el1)
462 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
463 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
464 b.eq 1f // TTBR0 access already disabled
465 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
466 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL)
467 __uaccess_ttbr0_disable x21
469 SYM_CODE_END(__swpan_entry_el1)
472 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
475 SYM_CODE_START_LOCAL(__swpan_exit_el1)
476 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
477 __uaccess_ttbr0_enable x0, x1
478 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
480 SYM_CODE_END(__swpan_exit_el1)
482 SYM_CODE_START_LOCAL(__swpan_exit_el0)
483 __uaccess_ttbr0_enable x0, x1
485 * Enable errata workarounds only if returning to user. The only
486 * workaround currently required for TTBR0_EL1 changes are for the
487 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
490 b post_ttbr_update_workaround
491 SYM_CODE_END(__swpan_exit_el0)
494 /* GPRs used by entry code */
495 tsk .req x28 // current thread_info
502 .pushsection ".entry.text", "ax"
505 SYM_CODE_START(vectors)
506 kernel_ventry 1, t, 64, sync // Synchronous EL1t
507 kernel_ventry 1, t, 64, irq // IRQ EL1t
508 kernel_ventry 1, t, 64, fiq // FIQ EL1t
509 kernel_ventry 1, t, 64, error // Error EL1t
511 kernel_ventry 1, h, 64, sync // Synchronous EL1h
512 kernel_ventry 1, h, 64, irq // IRQ EL1h
513 kernel_ventry 1, h, 64, fiq // FIQ EL1h
514 kernel_ventry 1, h, 64, error // Error EL1h
516 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
517 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
518 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
519 kernel_ventry 0, t, 64, error // Error 64-bit EL0
521 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
522 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
523 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
524 kernel_ventry 0, t, 32, error // Error 32-bit EL0
525 SYM_CODE_END(vectors)
527 #ifdef CONFIG_VMAP_STACK
528 SYM_CODE_START_LOCAL(__bad_stack)
530 * We detected an overflow in kernel_ventry, which switched to the
531 * overflow stack. Stash the exception regs, and head to our overflow
535 /* Restore the original x0 value */
539 * Store the original GPRs to the new stack. The orginal SP (minus
540 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
542 sub sp, sp, #PT_REGS_SIZE
545 add x0, x0, #PT_REGS_SIZE
548 /* Stash the regs for handle_bad_stack */
554 SYM_CODE_END(__bad_stack)
555 #endif /* CONFIG_VMAP_STACK */
558 .macro entry_handler el:req, ht:req, regsize:req, label:req
559 SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label)
560 kernel_entry \el, \regsize
562 bl el\el\ht\()_\regsize\()_\label\()_handler
568 SYM_CODE_END(el\el\ht\()_\regsize\()_\label)
572 * Early exception handlers
574 entry_handler 1, t, 64, sync
575 entry_handler 1, t, 64, irq
576 entry_handler 1, t, 64, fiq
577 entry_handler 1, t, 64, error
579 entry_handler 1, h, 64, sync
580 entry_handler 1, h, 64, irq
581 entry_handler 1, h, 64, fiq
582 entry_handler 1, h, 64, error
584 entry_handler 0, t, 64, sync
585 entry_handler 0, t, 64, irq
586 entry_handler 0, t, 64, fiq
587 entry_handler 0, t, 64, error
589 entry_handler 0, t, 32, sync
590 entry_handler 0, t, 32, irq
591 entry_handler 0, t, 32, fiq
592 entry_handler 0, t, 32, error
594 SYM_CODE_START_LOCAL(ret_to_kernel)
596 SYM_CODE_END(ret_to_kernel)
598 SYM_CODE_START_LOCAL(ret_to_user)
599 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step
600 enable_step_tsk x19, x2
601 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
602 bl stackleak_erase_on_task_stack
605 SYM_CODE_END(ret_to_user)
607 .popsection // .entry.text
609 // Move from tramp_pg_dir to swapper_pg_dir
610 .macro tramp_map_kernel, tmp
612 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
613 bic \tmp, \tmp, #USER_ASID_FLAG
615 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
616 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
617 /* ASID already in \tmp[63:48] */
618 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
619 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
620 /* 2MB boundary containing the vectors, so we nobble the walk cache */
621 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
625 alternative_else_nop_endif
626 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
629 // Move from swapper_pg_dir to tramp_pg_dir
630 .macro tramp_unmap_kernel, tmp
632 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
633 orr \tmp, \tmp, #USER_ASID_FLAG
636 * We avoid running the post_ttbr_update_workaround here because
637 * it's only needed by Cavium ThunderX, which requires KPTI to be
642 .macro tramp_data_read_var dst, var
643 #ifdef CONFIG_RELOCATABLE
644 ldr \dst, .L__tramp_data_\var
645 .ifndef .L__tramp_data_\var
646 .pushsection ".entry.tramp.rodata", "a", %progbits
654 * As !RELOCATABLE implies !RANDOMIZE_BASE the address is always a
655 * compile time constant (and hence not secret and not worth hiding).
657 * As statically allocated kernel code and data always live in the top
658 * 47 bits of the address space we can sign-extend bit 47 and avoid an
659 * instruction to load the upper 16 bits (which must be 0xFFFF).
661 movz \dst, :abs_g2_s:\var
662 movk \dst, :abs_g1_nc:\var
663 movk \dst, :abs_g0_nc:\var
667 #define BHB_MITIGATION_NONE 0
668 #define BHB_MITIGATION_LOOP 1
669 #define BHB_MITIGATION_FW 2
670 #define BHB_MITIGATION_INSN 3
672 .macro tramp_ventry, vector_start, regsize, kpti, bhb
676 msr tpidrro_el0, x30 // Restored in kernel_ventry
679 .if \bhb == BHB_MITIGATION_LOOP
681 * This sequence must appear before the first indirect branch. i.e. the
682 * ret out of tramp_ventry. It appears here because x30 is free.
684 __mitigate_spectre_bhb_loop x30
685 .endif // \bhb == BHB_MITIGATION_LOOP
687 .if \bhb == BHB_MITIGATION_INSN
690 .endif // \bhb == BHB_MITIGATION_INSN
694 * Defend against branch aliasing attacks by pushing a dummy
695 * entry onto the return stack and using a RET instruction to
696 * enter the full-fat kernel vectors.
702 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
703 tramp_data_read_var x30, vectors
704 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
705 prfm plil1strm, [x30, #(1b - \vector_start)]
706 alternative_else_nop_endif
714 .if \bhb == BHB_MITIGATION_FW
716 * The firmware sequence must appear before the first indirect branch.
717 * i.e. the ret out of tramp_ventry. But it also needs the stack to be
718 * mapped to save/restore the registers the SMC clobbers.
720 __mitigate_spectre_bhb_fw
721 .endif // \bhb == BHB_MITIGATION_FW
723 add x30, x30, #(1b - \vector_start + 4)
725 .org 1b + 128 // Did we overflow the ventry slot?
728 .macro tramp_exit, regsize = 64
729 tramp_data_read_var x30, this_cpu_vector
730 get_this_cpu_offset x29
735 tramp_unmap_kernel x29
739 add sp, sp, #PT_REGS_SIZE // restore sp
744 .macro generate_tramp_vector, kpti, bhb
749 tramp_ventry .Lvector_start\@, 64, \kpti, \bhb
752 tramp_ventry .Lvector_start\@, 32, \kpti, \bhb
756 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
758 * Exception vectors trampoline.
759 * The order must match __bp_harden_el1_vectors and the
760 * arm64_bp_harden_el1_vectors enum.
762 .pushsection ".entry.tramp.text", "ax"
764 SYM_CODE_START_NOALIGN(tramp_vectors)
765 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
766 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP
767 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW
768 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN
769 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
770 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE
771 SYM_CODE_END(tramp_vectors)
773 SYM_CODE_START(tramp_exit_native)
775 SYM_CODE_END(tramp_exit_native)
777 SYM_CODE_START(tramp_exit_compat)
779 SYM_CODE_END(tramp_exit_compat)
780 .popsection // .entry.tramp.text
781 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
784 * Exception vectors for spectre mitigations on entry from EL1 when
785 * kpti is not in use.
787 .macro generate_el1_vector, bhb
789 kernel_ventry 1, t, 64, sync // Synchronous EL1t
790 kernel_ventry 1, t, 64, irq // IRQ EL1t
791 kernel_ventry 1, t, 64, fiq // FIQ EL1h
792 kernel_ventry 1, t, 64, error // Error EL1t
794 kernel_ventry 1, h, 64, sync // Synchronous EL1h
795 kernel_ventry 1, h, 64, irq // IRQ EL1h
796 kernel_ventry 1, h, 64, fiq // FIQ EL1h
797 kernel_ventry 1, h, 64, error // Error EL1h
800 tramp_ventry .Lvector_start\@, 64, 0, \bhb
803 tramp_ventry .Lvector_start\@, 32, 0, \bhb
807 /* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */
808 .pushsection ".entry.text", "ax"
810 SYM_CODE_START(__bp_harden_el1_vectors)
811 #ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY
812 generate_el1_vector bhb=BHB_MITIGATION_LOOP
813 generate_el1_vector bhb=BHB_MITIGATION_FW
814 generate_el1_vector bhb=BHB_MITIGATION_INSN
815 #endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */
816 SYM_CODE_END(__bp_harden_el1_vectors)
821 * Register switch for AArch64. The callee-saved registers need to be saved
822 * and restored. On entry:
823 * x0 = previous task_struct (must be preserved across the switch)
824 * x1 = next task_struct
825 * Previous and next are guaranteed not to be the same.
828 SYM_FUNC_START(cpu_switch_to)
829 mov x10, #THREAD_CPU_CONTEXT
832 stp x19, x20, [x8], #16 // store callee-saved registers
833 stp x21, x22, [x8], #16
834 stp x23, x24, [x8], #16
835 stp x25, x26, [x8], #16
836 stp x27, x28, [x8], #16
837 stp x29, x9, [x8], #16
840 ldp x19, x20, [x8], #16 // restore callee-saved registers
841 ldp x21, x22, [x8], #16
842 ldp x23, x24, [x8], #16
843 ldp x25, x26, [x8], #16
844 ldp x27, x28, [x8], #16
845 ldp x29, x9, [x8], #16
849 ptrauth_keys_install_kernel x1, x8, x9, x10
853 SYM_FUNC_END(cpu_switch_to)
854 NOKPROBE(cpu_switch_to)
857 * This is how we return from a fork.
859 SYM_CODE_START(ret_from_fork)
861 cbz x19, 1f // not a kernel thread
864 1: get_current_task tsk
866 bl asm_exit_to_user_mode
868 SYM_CODE_END(ret_from_fork)
869 NOKPROBE(ret_from_fork)
872 * void call_on_irq_stack(struct pt_regs *regs,
873 * void (*func)(struct pt_regs *));
875 * Calls func(regs) using this CPU's irq stack and shadow irq stack.
877 SYM_FUNC_START(call_on_irq_stack)
878 #ifdef CONFIG_SHADOW_CALL_STACK
879 stp scs_sp, xzr, [sp, #-16]!
880 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17
882 /* Create a frame record to save our LR and SP (implicit in FP) */
883 stp x29, x30, [sp, #-16]!
886 ldr_this_cpu x16, irq_stack_ptr, x17
887 mov x15, #IRQ_STACK_SIZE
890 /* Move to the new stack and call the function there */
895 * Restore the SP from the FP, and restore the FP and LR from the frame
899 ldp x29, x30, [sp], #16
900 #ifdef CONFIG_SHADOW_CALL_STACK
901 ldp scs_sp, xzr, [sp], #16
904 SYM_FUNC_END(call_on_irq_stack)
905 NOKPROBE(call_on_irq_stack)
907 #ifdef CONFIG_ARM_SDE_INTERFACE
909 #include <asm/sdei.h>
910 #include <uapi/linux/arm_sdei.h>
912 .macro sdei_handler_exit exit_mode
913 /* On success, this call never returns... */
914 cmp \exit_mode, #SDEI_EXIT_SMC
922 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
924 * The regular SDEI entry point may have been unmapped along with the rest of
925 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
926 * argument accessible.
928 * This clobbers x4, __sdei_handler() will restore this from firmware's
931 .pushsection ".entry.tramp.text", "ax"
932 SYM_CODE_START(__sdei_asm_entry_trampoline)
934 tbz x4, #USER_ASID_BIT, 1f
936 tramp_map_kernel tmp=x4
941 * Remember whether to unmap the kernel on exit.
943 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
944 tramp_data_read_var x4, __sdei_asm_handler
946 SYM_CODE_END(__sdei_asm_entry_trampoline)
947 NOKPROBE(__sdei_asm_entry_trampoline)
950 * Make the exit call and restore the original ttbr1_el1
952 * x0 & x1: setup for the exit API call
954 * x4: struct sdei_registered_event argument from registration time.
956 SYM_CODE_START(__sdei_asm_exit_trampoline)
957 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
960 tramp_unmap_kernel tmp=x4
962 1: sdei_handler_exit exit_mode=x2
963 SYM_CODE_END(__sdei_asm_exit_trampoline)
964 NOKPROBE(__sdei_asm_exit_trampoline)
965 .popsection // .entry.tramp.text
966 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
969 * Software Delegated Exception entry point.
972 * x1: struct sdei_registered_event argument from registration time.
974 * x3: interrupted PSTATE
975 * x4: maybe clobbered by the trampoline
977 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
978 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
981 SYM_CODE_START(__sdei_asm_handler)
982 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
983 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
984 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
985 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
986 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
987 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
988 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
989 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
990 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
991 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
992 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
993 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
994 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
995 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
997 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
1001 #if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK)
1002 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
1005 #ifdef CONFIG_VMAP_STACK
1007 * entry.S may have been using sp as a scratch register, find whether
1008 * this is a normal or critical event and switch to the appropriate
1009 * stack for this CPU.
1012 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
1014 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
1015 2: mov x6, #SDEI_STACK_SIZE
1020 #ifdef CONFIG_SHADOW_CALL_STACK
1021 /* Use a separate shadow call stack for normal and critical events */
1023 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6
1025 3: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6
1030 * We may have interrupted userspace, or a guest, or exit-from or
1031 * return-to either of these. We can't trust sp_el0, restore it.
1034 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
1037 /* If we interrupted the kernel point to the previous stack/frame. */
1041 csel x29, x29, xzr, eq // fp, or zero
1042 csel x4, x2, xzr, eq // elr, or zero
1044 stp x29, x4, [sp, #-16]!
1047 add x0, x19, #SDEI_EVENT_INTREGS
1052 /* restore regs >x17 that we clobbered */
1053 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
1054 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
1055 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
1056 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1059 mov x1, x0 // address to complete_and_resume
1060 /* x0 = (x0 <= SDEI_EV_FAILED) ?
1061 * EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME
1063 cmp x0, #SDEI_EV_FAILED
1064 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1065 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1068 ldr_l x2, sdei_exit_mode
1070 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1071 sdei_handler_exit exit_mode=x2
1072 alternative_else_nop_endif
1074 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1075 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline, tmp=x3
1078 SYM_CODE_END(__sdei_asm_handler)
1079 NOKPROBE(__sdei_asm_handler)
1080 #endif /* CONFIG_ARM_SDE_INTERFACE */