2 * Record and handle CPU attributes.
4 * Copyright (C) 2014 ARM Ltd.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <asm/arch_timer.h>
18 #include <asm/cache.h>
20 #include <asm/cputype.h>
21 #include <asm/cpufeature.h>
22 #include <asm/fpsimd.h>
24 #include <linux/bitops.h>
25 #include <linux/bug.h>
26 #include <linux/compat.h>
27 #include <linux/elf.h>
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/personality.h>
31 #include <linux/preempt.h>
32 #include <linux/printk.h>
33 #include <linux/seq_file.h>
34 #include <linux/sched.h>
35 #include <linux/smp.h>
36 #include <linux/delay.h>
39 * In case the boot CPU is hotpluggable, we record its initial state and
40 * current state separately. Certain system registers may contain different
41 * values depending on configuration at or after reset.
43 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
44 static struct cpuinfo_arm64 boot_cpu_data;
46 static char *icache_policy_str[] = {
47 [0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN",
48 [ICACHE_POLICY_VIPT] = "VIPT",
49 [ICACHE_POLICY_PIPT] = "PIPT",
50 [ICACHE_POLICY_VPIPT] = "VPIPT",
53 unsigned long __icache_flags;
55 static const char *const hwcap_str[] = {
101 static const char *const compat_hwcap_str[] = {
127 static const char *const compat_hwcap2_str[] = {
135 #endif /* CONFIG_COMPAT */
137 static int c_show(struct seq_file *m, void *v)
140 bool compat = personality(current->personality) == PER_LINUX32;
142 for_each_online_cpu(i) {
143 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
144 u32 midr = cpuinfo->reg_midr;
147 * glibc reads /proc/cpuinfo to determine the number of
148 * online processors, looking for lines beginning with
149 * "processor". Give glibc what it expects.
151 seq_printf(m, "processor\t: %d\n", i);
153 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
154 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
156 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
157 loops_per_jiffy / (500000UL/HZ),
158 loops_per_jiffy / (5000UL/HZ) % 100);
161 * Dump out the common processor features in a single line.
162 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
163 * rather than attempting to parse this, but there's a body of
164 * software which does already (at least for 32-bit).
166 seq_puts(m, "Features\t:");
169 for (j = 0; compat_hwcap_str[j]; j++)
170 if (compat_elf_hwcap & (1 << j))
171 seq_printf(m, " %s", compat_hwcap_str[j]);
173 for (j = 0; compat_hwcap2_str[j]; j++)
174 if (compat_elf_hwcap2 & (1 << j))
175 seq_printf(m, " %s", compat_hwcap2_str[j]);
176 #endif /* CONFIG_COMPAT */
178 for (j = 0; hwcap_str[j]; j++)
179 if (cpu_have_feature(j))
180 seq_printf(m, " %s", hwcap_str[j]);
184 seq_printf(m, "CPU implementer\t: 0x%02x\n",
185 MIDR_IMPLEMENTOR(midr));
186 seq_printf(m, "CPU architecture: 8\n");
187 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
188 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
189 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
195 static void *c_start(struct seq_file *m, loff_t *pos)
197 return *pos < 1 ? (void *)1 : NULL;
200 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
206 static void c_stop(struct seq_file *m, void *v)
210 const struct seq_operations cpuinfo_op = {
218 static struct kobj_type cpuregs_kobj_type = {
219 .sysfs_ops = &kobj_sysfs_ops,
223 * The ARM ARM uses the phrase "32-bit register" to describe a register
224 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
225 * no statement is made as to whether the upper 32 bits will or will not
226 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
227 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
229 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
230 * registers, we expose them both as 64 bit values to cater for possible
231 * future expansion without an ABI break.
233 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj)
234 #define CPUREGS_ATTR_RO(_name, _field) \
235 static ssize_t _name##_show(struct kobject *kobj, \
236 struct kobj_attribute *attr, char *buf) \
238 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \
240 if (info->reg_midr) \
241 return sprintf(buf, "0x%016x\n", info->reg_##_field); \
245 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
247 CPUREGS_ATTR_RO(midr_el1, midr);
248 CPUREGS_ATTR_RO(revidr_el1, revidr);
250 static struct attribute *cpuregs_id_attrs[] = {
251 &cpuregs_attr_midr_el1.attr,
252 &cpuregs_attr_revidr_el1.attr,
256 static const struct attribute_group cpuregs_attr_group = {
257 .attrs = cpuregs_id_attrs,
258 .name = "identification"
261 static int cpuid_cpu_online(unsigned int cpu)
265 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
267 dev = get_cpu_device(cpu);
272 rc = kobject_add(&info->kobj, &dev->kobj, "regs");
275 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
277 kobject_del(&info->kobj);
282 static int cpuid_cpu_offline(unsigned int cpu)
285 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
287 dev = get_cpu_device(cpu);
290 if (info->kobj.parent) {
291 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
292 kobject_del(&info->kobj);
298 static int __init cpuinfo_regs_init(void)
302 for_each_possible_cpu(cpu) {
303 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
305 kobject_init(&info->kobj, &cpuregs_kobj_type);
308 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
309 cpuid_cpu_online, cpuid_cpu_offline);
311 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
316 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
318 unsigned int cpu = smp_processor_id();
319 u32 l1ip = CTR_L1IP(info->reg_ctr);
322 case ICACHE_POLICY_PIPT:
324 case ICACHE_POLICY_VPIPT:
325 set_bit(ICACHEF_VPIPT, &__icache_flags);
329 case ICACHE_POLICY_VIPT:
330 /* Assume aliasing */
331 set_bit(ICACHEF_ALIASING, &__icache_flags);
334 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
337 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
339 info->reg_cntfrq = arch_timer_get_cntfrq();
341 * Use the effective value of the CTR_EL0 than the raw value
342 * exposed by the CPU. CTR_E0.IDC field value must be interpreted
343 * with the CLIDR_EL1 fields to avoid triggering false warnings
344 * when there is a mismatch across the CPUs. Keep track of the
345 * effective value of the CTR_EL0 in our internal records for
346 * acurate sanity check and feature enablement.
348 info->reg_ctr = read_cpuid_effective_cachetype();
349 info->reg_dczid = read_cpuid(DCZID_EL0);
350 info->reg_midr = read_cpuid_id();
351 info->reg_revidr = read_cpuid(REVIDR_EL1);
353 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
354 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
355 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
356 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
357 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
358 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
359 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
360 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
361 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
362 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
364 /* Update the 32bit ID registers only if AArch32 is implemented */
365 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
366 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
367 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
368 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
369 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
370 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
371 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
372 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
373 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
374 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
375 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
376 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
377 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
378 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
380 info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
381 info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
382 info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
385 if (IS_ENABLED(CONFIG_ARM64_SVE) &&
386 id_aa64pfr0_sve(info->reg_id_aa64pfr0))
387 info->reg_zcr = read_zcr_features();
389 cpuinfo_detect_icache_policy(info);
392 void cpuinfo_store_cpu(void)
394 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
395 __cpuinfo_store_cpu(info);
396 update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
399 void __init cpuinfo_store_boot_cpu(void)
401 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
402 __cpuinfo_store_cpu(info);
404 boot_cpu_data = *info;
405 init_cpu_features(&boot_cpu_data);
408 device_initcall(cpuinfo_regs_init);