arch/arm64/kernel/cpuinfo.c

   1 /*
   2  * Record and handle CPU attributes.
   3  *
   4  * Copyright (C) 2014 ARM Ltd.
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17 #include <asm/arch_timer.h>
  18 #include <asm/cachetype.h>
  19 #include <asm/cpu.h>
  20 #include <asm/cputype.h>
  21 #include <asm/cpufeature.h>
  22
  23 #include <linux/bitops.h>
  24 #include <linux/bug.h>
  25 #include <linux/compat.h>
  26 #include <linux/elf.h>
  27 #include <linux/init.h>
  28 #include <linux/kernel.h>
  29 #include <linux/personality.h>
  30 #include <linux/preempt.h>
  31 #include <linux/printk.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/sched.h>
  34 #include <linux/smp.h>
  35 #include <linux/delay.h>
  36 #ifdef CONFIG_AMLOGIC_CPU_INFO
  37 #include <linux/amlogic/cpu_version.h>
  38 #endif
  39
  40 #ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
  41 #include <linux/amlogic/efuse.h>
  42 #endif
  43
  44 /*
  45  * In case the boot CPU is hotpluggable, we record its initial state and
  46  * current state separately. Certain system registers may contain different
  47  * values depending on configuration at or after reset.
  48  */
  49 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
  50 static struct cpuinfo_arm64 boot_cpu_data;
  51
  52 static char *icache_policy_str[] = {
  53         [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN",
  54         [ICACHE_POLICY_AIVIVT] = "AIVIVT",
  55         [ICACHE_POLICY_VIPT] = "VIPT",
  56         [ICACHE_POLICY_PIPT] = "PIPT",
  57 };
  58
  59 unsigned long __icache_flags;
  60
  61 static const char *const hwcap_str[] = {
  62         "fp",
  63         "asimd",
  64         "evtstrm",
  65         "aes",
  66         "pmull",
  67         "sha1",
  68         "sha2",
  69         "crc32",
  70         "atomics",
  71         "fphp",
  72         "asimdhp",
  73         NULL
  74 };
  75
  76 #ifdef CONFIG_COMPAT
  77 static const char *const compat_hwcap_str[] = {
  78         "swp",
  79         "half",
  80         "thumb",
  81         "26bit",
  82         "fastmult",
  83         "fpa",
  84         "vfp",
  85         "edsp",
  86         "java",
  87         "iwmmxt",
  88         "crunch",
  89         "thumbee",
  90         "neon",
  91         "vfpv3",
  92         "vfpv3d16",
  93         "tls",
  94         "vfpv4",
  95         "idiva",
  96         "idivt",
  97         "vfpd32",
  98         "lpae",
  99         "evtstrm",
 100         NULL
 101 };
 102
 103 static const char *const compat_hwcap2_str[] = {
 104         "aes",
 105         "pmull",
 106         "sha1",
 107         "sha2",
 108         "crc32",
 109         NULL
 110 };
 111 #endif /* CONFIG_COMPAT */
 112
 113 static int c_show(struct seq_file *m, void *v)
 114 {
 115         int i, j;
 116         bool compat = personality(current->personality) == PER_LINUX32;
 117 #ifdef CONFIG_AMLOGIC_CPU_INFO
 118         unsigned char chipid[CHIPID_LEN];
 119 #endif
 120
 121         for_each_online_cpu(i) {
 122                 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
 123                 u32 midr = cpuinfo->reg_midr;
 124
 125                 /*
 126                  * glibc reads /proc/cpuinfo to determine the number of
 127                  * online processors, looking for lines beginning with
 128                  * "processor".  Give glibc what it expects.
 129                  */
 130                 seq_printf(m, "processor\t: %d\n", i);
 131                 if (compat)
 132                         seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
 133                                    MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
 134
 135                 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
 136                            loops_per_jiffy / (500000UL/HZ),
 137                            loops_per_jiffy / (5000UL/HZ) % 100);
 138
 139                 /*
 140                  * Dump out the common processor features in a single line.
 141                  * Userspace should read the hwcaps with getauxval(AT_HWCAP)
 142                  * rather than attempting to parse this, but there's a body of
 143                  * software which does already (at least for 32-bit).
 144                  */
 145                 seq_puts(m, "Features\t:");
 146                 if (compat) {
 147 #ifdef CONFIG_COMPAT
 148                         for (j = 0; compat_hwcap_str[j]; j++)
 149                                 if (compat_elf_hwcap & (1 << j))
 150                                         seq_printf(m, " %s", compat_hwcap_str[j]);
 151
 152                         for (j = 0; compat_hwcap2_str[j]; j++)
 153                                 if (compat_elf_hwcap2 & (1 << j))
 154                                         seq_printf(m, " %s", compat_hwcap2_str[j]);
 155 #endif /* CONFIG_COMPAT */
 156                 } else {
 157                         for (j = 0; hwcap_str[j]; j++)
 158                                 if (elf_hwcap & (1 << j))
 159                                         seq_printf(m, " %s", hwcap_str[j]);
 160                 }
 161                 seq_puts(m, "\n");
 162
 163                 seq_printf(m, "CPU implementer\t: 0x%02x\n",
 164                            MIDR_IMPLEMENTOR(midr));
 165                 seq_printf(m, "CPU architecture: 8\n");
 166                 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
 167                 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
 168                 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
 169         }
 170 #ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
 171 #ifdef CONFIG_AMLOGIC_CPU_INFO
 172         cpuinfo_get_chipid(chipid, CHIPID_LEN);
 173         seq_puts(m, "CPU info\t: ");
 174         for (i = 0; i < 16; i++)
 175                 seq_printf(m, "%02x", chipid[i]);
 176         seq_puts(m, "\n");
 177 #endif
 178         {
 179                 int ret;
 180                 char uuid[32];
 181                 loff_t pos = 0;
 182
 183                 seq_puts(m, "Serial\t\t: ");
 184
 185                 ret = efuse_read_usr(uuid, sizeof(uuid), &pos);
 186                 if ((ret < 0) || (ret != sizeof(uuid))) {
 187                         seq_puts(m, "Unknown\n");
 188                 } else {
 189                         for (i = 0; i < sizeof(uuid); i++) {
 190                                 if ((i == 8) || (i == 12) || (i == 16) || (i == 20))
 191                                         seq_putc(m, '-');
 192                                 seq_printf(m, "%c", uuid[i]);
 193                         }
 194                         seq_putc(m, '\n');
 195                 }
 196         }
 197 #else
 198 #ifdef CONFIG_AMLOGIC_CPU_INFO
 199         cpuinfo_get_chipid(chipid, CHIPID_LEN);
 200         seq_puts(m, "Serial\t\t: ");
 201         for (i = 0; i < 16; i++)
 202                 seq_printf(m, "%02x", chipid[i]);
 203         seq_puts(m, "\n");
 204 #endif
 205 #endif
 206 #ifdef CONFIG_AMLOGIC_CPU_INFO
 207 #ifdef CONFIG_ARCH_MESON64_ODROID_COMMON
 208         seq_printf(m, "Hardware\t: %s\n", machine_name);
 209         seq_printf(m, "Revision\t: %04x\n\n", system_rev);
 210 #else
 211         seq_printf(m, "Hardware\t: %s\n", machine_model);
 212 #endif
 213 #endif
 214         return 0;
 215 }
 216
 217 static void *c_start(struct seq_file *m, loff_t *pos)
 218 {
 219         return *pos < 1 ? (void *)1 : NULL;
 220 }
 221
 222 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 223 {
 224         ++*pos;
 225         return NULL;
 226 }
 227
 228 static void c_stop(struct seq_file *m, void *v)
 229 {
 230 }
 231
 232 const struct seq_operations cpuinfo_op = {
 233         .start  = c_start,
 234         .next   = c_next,
 235         .stop   = c_stop,
 236         .show   = c_show
 237 };
 238
 239
 240 static struct kobj_type cpuregs_kobj_type = {
 241         .sysfs_ops = &kobj_sysfs_ops,
 242 };
 243
 244 /*
 245  * The ARM ARM uses the phrase "32-bit register" to describe a register
 246  * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
 247  * no statement is made as to whether the upper 32 bits will or will not
 248  * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
 249  * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
 250  *
 251  * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
 252  * registers, we expose them both as 64 bit values to cater for possible
 253  * future expansion without an ABI break.
 254  */
 255 #define kobj_to_cpuinfo(kobj)   container_of(kobj, struct cpuinfo_arm64, kobj)
 256 #define CPUREGS_ATTR_RO(_name, _field)                                          \
 257         static ssize_t _name##_show(struct kobject *kobj,                       \
 258                         struct kobj_attribute *attr, char *buf)                 \
 259         {                                                                       \
 260                 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj);             \
 261                                                                                 \
 262                 if (info->reg_midr)                                             \
 263                         return sprintf(buf, "0x%016x\n", info->reg_##_field);   \
 264                 else                                                            \
 265                         return 0;                                               \
 266         }                                                                       \
 267         static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
 268
 269 CPUREGS_ATTR_RO(midr_el1, midr);
 270 CPUREGS_ATTR_RO(revidr_el1, revidr);
 271
 272 static struct attribute *cpuregs_id_attrs[] = {
 273         &cpuregs_attr_midr_el1.attr,
 274         &cpuregs_attr_revidr_el1.attr,
 275         NULL
 276 };
 277
 278 static struct attribute_group cpuregs_attr_group = {
 279         .attrs = cpuregs_id_attrs,
 280         .name = "identification"
 281 };
 282
 283 static int cpuid_add_regs(int cpu)
 284 {
 285         int rc;
 286         struct device *dev;
 287         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 288
 289         dev = get_cpu_device(cpu);
 290         if (!dev) {
 291                 rc = -ENODEV;
 292                 goto out;
 293         }
 294         rc = kobject_add(&info->kobj, &dev->kobj, "regs");
 295         if (rc)
 296                 goto out;
 297         rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
 298         if (rc)
 299                 kobject_del(&info->kobj);
 300 out:
 301         return rc;
 302 }
 303
 304 static int cpuid_remove_regs(int cpu)
 305 {
 306         struct device *dev;
 307         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 308
 309         dev = get_cpu_device(cpu);
 310         if (!dev)
 311                 return -ENODEV;
 312         if (info->kobj.parent) {
 313                 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
 314                 kobject_del(&info->kobj);
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int cpuid_callback(struct notifier_block *nb,
 321                          unsigned long action, void *hcpu)
 322 {
 323         int rc = 0;
 324         unsigned long cpu = (unsigned long)hcpu;
 325
 326         switch (action & ~CPU_TASKS_FROZEN) {
 327         case CPU_ONLINE:
 328                 rc = cpuid_add_regs(cpu);
 329                 break;
 330         case CPU_DEAD:
 331                 rc = cpuid_remove_regs(cpu);
 332                 break;
 333         }
 334
 335         return notifier_from_errno(rc);
 336 }
 337
 338 static int __init cpuinfo_regs_init(void)
 339 {
 340         int cpu;
 341
 342         cpu_notifier_register_begin();
 343
 344         for_each_possible_cpu(cpu) {
 345                 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 346
 347                 kobject_init(&info->kobj, &cpuregs_kobj_type);
 348                 if (cpu_online(cpu))
 349                         cpuid_add_regs(cpu);
 350         }
 351         __hotcpu_notifier(cpuid_callback, 0);
 352
 353         cpu_notifier_register_done();
 354         return 0;
 355 }
 356 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
 357 {
 358         unsigned int cpu = smp_processor_id();
 359         u32 l1ip = CTR_L1IP(info->reg_ctr);
 360
 361         if (l1ip != ICACHE_POLICY_PIPT) {
 362                 /*
 363                  * VIPT caches are non-aliasing if the VA always equals the PA
 364                  * in all bit positions that are covered by the index. This is
 365                  * the case if the size of a way (# of sets * line size) does
 366                  * not exceed PAGE_SIZE.
 367                  */
 368                 u32 waysize = icache_get_numsets() * icache_get_linesize();
 369
 370                 if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE)
 371                         set_bit(ICACHEF_ALIASING, &__icache_flags);
 372         }
 373         if (l1ip == ICACHE_POLICY_AIVIVT)
 374                 set_bit(ICACHEF_AIVIVT, &__icache_flags);
 375
 376         pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
 377 }
 378
 379 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
 380 {
 381         info->reg_cntfrq = arch_timer_get_cntfrq();
 382         info->reg_ctr = read_cpuid_cachetype();
 383         info->reg_dczid = read_cpuid(DCZID_EL0);
 384         info->reg_midr = read_cpuid_id();
 385         info->reg_revidr = read_cpuid(REVIDR_EL1);
 386
 387         info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
 388         info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
 389         info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
 390         info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
 391         info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
 392         info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
 393         info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
 394         info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
 395         info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
 396
 397         /* Update the 32bit ID registers only if AArch32 is implemented */
 398         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 399                 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
 400                 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
 401                 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
 402                 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
 403                 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
 404                 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
 405                 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
 406                 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
 407                 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
 408                 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
 409                 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
 410                 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
 411                 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
 412
 413                 info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
 414                 info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
 415                 info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
 416         }
 417
 418         cpuinfo_detect_icache_policy(info);
 419 }
 420
 421 void cpuinfo_store_cpu(void)
 422 {
 423         struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
 424         __cpuinfo_store_cpu(info);
 425         update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
 426 }
 427
 428 void __init cpuinfo_store_boot_cpu(void)
 429 {
 430         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
 431         __cpuinfo_store_cpu(info);
 432
 433         boot_cpu_data = *info;
 434         init_cpu_features(&boot_cpu_data);
 435 }
 436
 437 device_initcall(cpuinfo_regs_init);