1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
5 * Copyright (C) 2015 ARM Ltd.
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
29 * Some implementation details worth remembering:
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
63 #define pr_fmt(fmt) "CPU features: " fmt
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/sort.h>
69 #include <linux/stop_machine.h>
70 #include <linux/sysfs.h>
71 #include <linux/types.h>
72 #include <linux/minmax.h>
74 #include <linux/cpu.h>
75 #include <linux/kasan.h>
76 #include <linux/percpu.h>
79 #include <asm/cpufeature.h>
80 #include <asm/cpu_ops.h>
81 #include <asm/fpsimd.h>
82 #include <asm/hwcap.h>
84 #include <asm/kvm_host.h>
85 #include <asm/mmu_context.h>
87 #include <asm/processor.h>
89 #include <asm/sysreg.h>
90 #include <asm/traps.h>
91 #include <asm/vectors.h>
94 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
95 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly;
98 #define COMPAT_ELF_HWCAP_DEFAULT \
99 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
100 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
101 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
103 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
104 unsigned int compat_elf_hwcap2 __read_mostly;
107 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
108 EXPORT_SYMBOL(cpu_hwcaps);
109 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
111 /* Need also bit for ARM64_CB_PATCH */
112 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
114 bool arm64_use_ng_mappings = false;
115 EXPORT_SYMBOL(arm64_use_ng_mappings);
117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
123 static bool __read_mostly allow_mismatched_32bit_el0;
126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
127 * seen at least one CPU capable of 32-bit EL0.
129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
132 * Mask of CPUs supporting 32-bit EL0.
133 * Only valid if arm64_mismatched_32bit_el0 is enabled.
135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
138 * Flag to indicate if we have computed the system wide
139 * capabilities based on the boot time active CPUs. This
140 * will be used to determine if a new booting CPU should
141 * go through the verification process to make sure that it
142 * supports the system capabilities, without using a hotplug
143 * notifier. This is also used to decide if we could use
144 * the fast path for checking constant CPU caps.
146 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
147 EXPORT_SYMBOL(arm64_const_caps_ready);
148 static inline void finalize_system_capabilities(void)
150 static_branch_enable(&arm64_const_caps_ready);
153 void dump_cpu_features(void)
155 /* file-wide pr_fmt adds "CPU features: " prefix */
156 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
159 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
160 EXPORT_SYMBOL(cpu_hwcap_keys);
162 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
165 .visible = VISIBLE, \
170 .safe_val = SAFE_VAL, \
173 /* Define a feature with unsigned values */
174 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
175 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
177 /* Define a feature with a signed value */
178 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
179 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
181 #define ARM64_FTR_END \
186 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
188 static bool __system_matches_cap(unsigned int n);
191 * NOTE: Any changes to the visibility of features should be kept in
192 * sync with the documentation of the CPU feature register ABI.
194 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0),
203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0),
204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0),
205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0),
212 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0),
214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
220 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0),
221 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
222 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0),
226 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
227 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0),
228 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
229 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0),
234 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
237 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
238 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
239 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0),
240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0),
241 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0),
245 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
256 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
257 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
265 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SME_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
271 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
272 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
278 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0),
281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0),
283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0),
285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0),
287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
288 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0),
289 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
290 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0),
291 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
292 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0),
293 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
294 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0),
295 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
296 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0),
300 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
301 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
302 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0),
303 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
304 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0),
305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
306 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0),
307 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
308 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0),
309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
310 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0),
311 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
312 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0),
313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
314 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0),
318 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
319 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
323 * Page size not being supported at Stage-2 is not fatal. You
324 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
325 * your favourite nesting hypervisor.
327 * There is a small corner case where the hypervisor explicitly
328 * advertises a given granule size at Stage-2 (value 2) on some
329 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
330 * vCPUs. Although this is not forbidden by the architecture, it
331 * indicates that the hypervisor is being silly (or buggy).
333 * We make no effort to cope with this and pretend that if these
334 * fields are inconsistent across vCPUs, then it isn't worth
335 * trying to bring KVM up.
337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
338 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
339 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
341 * We already refuse to boot CPUs that don't support our configured
342 * page size, so we can only detect mismatches for a page size other
343 * than the one we're currently using. Unfortunately, SoCs like this
344 * exist in the wild so, even though we don't like it, we'll have to go
345 * along with it and treat them as non-strict.
347 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
348 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
352 /* Linux shouldn't care about secure memory */
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
357 * Differing PARange is fine as long as all peripherals and memory are mapped
358 * within the minimum PARange of all CPUs
360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
364 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TIDCP1_SHIFT, 4, 0),
366 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
370 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
371 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
372 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
373 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
380 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
384 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
387 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
393 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
394 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
395 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
399 static const struct arm64_ftr_bits ftr_ctr[] = {
400 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
401 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
402 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1),
403 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0),
404 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0),
405 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1),
407 * Linux can handle differing I-cache policies. Userspace JITs will
408 * make use of *minLine.
409 * If we have differing I-cache policies, report it as the weakest - VIPT.
411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */
412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0),
416 static struct arm64_ftr_override __ro_after_init no_override = { };
418 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
419 .name = "SYS_CTR_EL0",
421 .override = &no_override,
424 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
425 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
430 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
436 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
437 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
443 * We can instantiate multiple PMU instances with different levels
446 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
451 static const struct arm64_ftr_bits ftr_mvfr2[] = {
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
457 static const struct arm64_ftr_bits ftr_dczid[] = {
458 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1),
459 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0),
463 static const struct arm64_ftr_bits ftr_gmid[] = {
464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0),
468 static const struct arm64_ftr_bits ftr_id_isar0[] = {
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
479 static const struct arm64_ftr_bits ftr_id_isar5[] = {
480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
489 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
499 * SpecSEI = 1 indicates that the PE might generate an SError on an
500 * external abort on speculative read. It is safe to assume that an
501 * SError might be generated than it will not be. Hence it has been
502 * classified as FTR_HIGHER_SAFE.
504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
508 static const struct arm64_ftr_bits ftr_id_isar4[] = {
509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
520 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
525 static const struct arm64_ftr_bits ftr_id_isar6[] = {
526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
536 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
546 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
558 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
564 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
565 /* [31:28] TraceFilt */
566 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0),
567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
576 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
577 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
581 static const struct arm64_ftr_bits ftr_zcr[] = {
582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
583 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0), /* LEN */
587 static const struct arm64_ftr_bits ftr_smcr[] = {
588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
589 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0), /* LEN */
594 * Common ftr bits for a 32bit register with all hidden, strict
595 * attributes, with 4bit feature fields and a default safe value of
596 * 0. Covers the following 32bit registers:
597 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
599 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
611 /* Table for a single 32bit feature value */
612 static const struct arm64_ftr_bits ftr_single32[] = {
613 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
617 static const struct arm64_ftr_bits ftr_raz[] = {
621 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \
623 .reg = &(struct arm64_ftr_reg){ \
626 .ftr_bits = &((table)[0]), \
629 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \
630 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
632 #define ARM64_FTR_REG(id, table) \
633 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
635 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
636 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override;
637 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
638 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override;
639 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override;
640 struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
641 struct arm64_ftr_override __ro_after_init id_aa64isar2_override;
643 static const struct __ftr_reg_entry {
645 struct arm64_ftr_reg *reg;
646 } arm64_ftr_regs[] = {
648 /* Op1 = 0, CRn = 0, CRm = 1 */
649 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
650 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
651 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
652 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
653 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
654 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
655 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
657 /* Op1 = 0, CRn = 0, CRm = 2 */
658 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
659 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
660 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
661 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
662 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
663 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
664 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
665 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
667 /* Op1 = 0, CRn = 0, CRm = 3 */
668 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
669 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
670 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
671 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
672 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
673 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
675 /* Op1 = 0, CRn = 0, CRm = 4 */
676 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0,
677 &id_aa64pfr0_override),
678 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
679 &id_aa64pfr1_override),
680 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0,
681 &id_aa64zfr0_override),
682 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0,
683 &id_aa64smfr0_override),
685 /* Op1 = 0, CRn = 0, CRm = 5 */
686 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
687 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
689 /* Op1 = 0, CRn = 0, CRm = 6 */
690 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
691 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
692 &id_aa64isar1_override),
693 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2,
694 &id_aa64isar2_override),
696 /* Op1 = 0, CRn = 0, CRm = 7 */
697 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
698 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
699 &id_aa64mmfr1_override),
700 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
702 /* Op1 = 0, CRn = 1, CRm = 2 */
703 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
704 ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr),
706 /* Op1 = 1, CRn = 0, CRm = 0 */
707 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
709 /* Op1 = 3, CRn = 0, CRm = 0 */
710 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
711 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
713 /* Op1 = 3, CRn = 14, CRm = 0 */
714 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
717 static int search_cmp_ftr_reg(const void *id, const void *regp)
719 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
723 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
724 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
725 * ascending order of sys_id, we use binary search to find a matching
728 * returns - Upon success, matching ftr_reg entry for id.
729 * - NULL on failure. It is upto the caller to decide
730 * the impact of a failure.
732 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
734 const struct __ftr_reg_entry *ret;
736 ret = bsearch((const void *)(unsigned long)sys_id,
738 ARRAY_SIZE(arm64_ftr_regs),
739 sizeof(arm64_ftr_regs[0]),
747 * get_arm64_ftr_reg - Looks up a feature register entry using
748 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
750 * returns - Upon success, matching ftr_reg entry for id.
751 * - NULL on failure but with an WARN_ON().
753 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
755 struct arm64_ftr_reg *reg;
757 reg = get_arm64_ftr_reg_nowarn(sys_id);
760 * Requesting a non-existent register search is an error. Warn
761 * and let the caller handle it.
767 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
770 u64 mask = arm64_ftr_mask(ftrp);
773 reg |= (ftr_val << ftrp->shift) & mask;
777 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
782 switch (ftrp->type) {
784 ret = ftrp->safe_val;
789 case FTR_HIGHER_OR_ZERO_SAFE:
793 case FTR_HIGHER_SAFE:
803 static void __init sort_ftr_regs(void)
807 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
808 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
809 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
813 * Features here must be sorted in descending order with respect
814 * to their shift values and should not overlap with each other.
816 for (; ftr_bits->width != 0; ftr_bits++, j++) {
817 unsigned int width = ftr_reg->ftr_bits[j].width;
818 unsigned int shift = ftr_reg->ftr_bits[j].shift;
819 unsigned int prev_shift;
821 WARN((shift + width) > 64,
822 "%s has invalid feature at shift %d\n",
823 ftr_reg->name, shift);
826 * Skip the first feature. There is nothing to
827 * compare against for now.
832 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
833 WARN((shift + width) > prev_shift,
834 "%s has feature overlap at shift %d\n",
835 ftr_reg->name, shift);
839 * Skip the first register. There is nothing to
840 * compare against for now.
845 * Registers here must be sorted in ascending order with respect
846 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
849 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id);
854 * Initialise the CPU feature register from Boot CPU values.
855 * Also initiliases the strict_mask for the register.
856 * Any bits that are not covered by an arm64_ftr_bits entry are considered
857 * RES0 for the system-wide value, and must strictly match.
859 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
862 u64 strict_mask = ~0x0ULL;
866 const struct arm64_ftr_bits *ftrp;
867 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
872 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
873 u64 ftr_mask = arm64_ftr_mask(ftrp);
874 s64 ftr_new = arm64_ftr_value(ftrp, new);
875 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
877 if ((ftr_mask & reg->override->mask) == ftr_mask) {
878 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
881 if (ftr_ovr != tmp) {
882 /* Unsafe, remove the override */
883 reg->override->mask &= ~ftr_mask;
884 reg->override->val &= ~ftr_mask;
886 str = "ignoring override";
887 } else if (ftr_new != tmp) {
888 /* Override was valid */
891 } else if (ftr_ovr == tmp) {
892 /* Override was the safe value */
897 pr_warn("%s[%d:%d]: %s to %llx\n",
899 ftrp->shift + ftrp->width - 1,
900 ftrp->shift, str, tmp);
901 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
902 reg->override->val &= ~ftr_mask;
903 pr_warn("%s[%d:%d]: impossible override, ignored\n",
905 ftrp->shift + ftrp->width - 1,
909 val = arm64_ftr_set_value(ftrp, val, ftr_new);
911 valid_mask |= ftr_mask;
913 strict_mask &= ~ftr_mask;
915 user_mask |= ftr_mask;
917 reg->user_val = arm64_ftr_set_value(ftrp,
925 reg->strict_mask = strict_mask;
926 reg->user_mask = user_mask;
929 extern const struct arm64_cpu_capabilities arm64_errata[];
930 static const struct arm64_cpu_capabilities arm64_features[];
933 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
935 for (; caps->matches; caps++) {
936 if (WARN(caps->capability >= ARM64_NCAPS,
937 "Invalid capability %d\n", caps->capability))
939 if (WARN(cpu_hwcaps_ptrs[caps->capability],
940 "Duplicate entry for capability %d\n",
943 cpu_hwcaps_ptrs[caps->capability] = caps;
947 static void __init init_cpu_hwcaps_indirect_list(void)
949 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
950 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
953 static void __init setup_boot_cpu_capabilities(void);
955 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
957 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
958 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
959 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
960 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
961 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
962 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
963 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
964 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
965 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
966 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
967 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
968 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
969 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
970 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
971 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
972 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
973 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
974 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
975 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
976 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
977 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
980 void __init init_cpu_features(struct cpuinfo_arm64 *info)
982 /* Before we start using the tables, make sure it is sorted */
985 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
986 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
987 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
988 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
989 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
990 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
991 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
992 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
993 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
994 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
995 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
996 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
997 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
998 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
999 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0);
1001 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
1002 init_32bit_cpu_features(&info->aarch32);
1004 if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1005 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1006 info->reg_zcr = read_zcr_features();
1007 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
1008 vec_init_vq_map(ARM64_VEC_SVE);
1011 if (IS_ENABLED(CONFIG_ARM64_SME) &&
1012 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1013 info->reg_smcr = read_smcr_features();
1015 * We mask out SMPS since even if the hardware
1016 * supports priorities the kernel does not at present
1017 * and we block access to them.
1019 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1020 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr);
1021 vec_init_vq_map(ARM64_VEC_SME);
1024 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
1025 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
1028 * Initialize the indirect array of CPU hwcaps capabilities pointers
1029 * before we handle the boot CPU below.
1031 init_cpu_hwcaps_indirect_list();
1034 * Detect and enable early CPU capabilities based on the boot CPU,
1035 * after we have initialised the CPU feature infrastructure.
1037 setup_boot_cpu_capabilities();
1040 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
1042 const struct arm64_ftr_bits *ftrp;
1044 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
1045 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
1046 s64 ftr_new = arm64_ftr_value(ftrp, new);
1048 if (ftr_cur == ftr_new)
1050 /* Find a safe value */
1051 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
1052 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
1057 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
1059 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1064 update_cpu_ftr_reg(regp, val);
1065 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1067 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
1068 regp->name, boot, cpu, val);
1072 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1074 const struct arm64_ftr_bits *ftrp;
1075 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1080 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1081 if (ftrp->shift == field) {
1082 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1088 WARN_ON(!ftrp->width);
1091 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1092 struct cpuinfo_arm64 *boot)
1094 static bool boot_cpu_32bit_regs_overridden = false;
1096 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1099 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1102 boot->aarch32 = info->aarch32;
1103 init_32bit_cpu_features(&boot->aarch32);
1104 boot_cpu_32bit_regs_overridden = true;
1107 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1108 struct cpuinfo_32bit *boot)
1111 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1114 * If we don't have AArch32 at EL1, then relax the strictness of
1115 * EL1-dependent register fields to avoid spurious sanity check fails.
1117 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1118 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
1119 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
1120 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
1121 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
1122 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
1123 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
1126 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1127 info->reg_id_dfr0, boot->reg_id_dfr0);
1128 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1129 info->reg_id_dfr1, boot->reg_id_dfr1);
1130 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1131 info->reg_id_isar0, boot->reg_id_isar0);
1132 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1133 info->reg_id_isar1, boot->reg_id_isar1);
1134 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1135 info->reg_id_isar2, boot->reg_id_isar2);
1136 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1137 info->reg_id_isar3, boot->reg_id_isar3);
1138 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1139 info->reg_id_isar4, boot->reg_id_isar4);
1140 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1141 info->reg_id_isar5, boot->reg_id_isar5);
1142 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1143 info->reg_id_isar6, boot->reg_id_isar6);
1146 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1147 * ACTLR formats could differ across CPUs and therefore would have to
1148 * be trapped for virtualization anyway.
1150 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1151 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1152 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1153 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1154 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1155 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1156 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1157 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1158 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1159 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1160 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1161 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1162 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1163 info->reg_id_pfr0, boot->reg_id_pfr0);
1164 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1165 info->reg_id_pfr1, boot->reg_id_pfr1);
1166 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1167 info->reg_id_pfr2, boot->reg_id_pfr2);
1168 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1169 info->reg_mvfr0, boot->reg_mvfr0);
1170 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1171 info->reg_mvfr1, boot->reg_mvfr1);
1172 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1173 info->reg_mvfr2, boot->reg_mvfr2);
1179 * Update system wide CPU feature registers with the values from a
1180 * non-boot CPU. Also performs SANITY checks to make sure that there
1181 * aren't any insane variations from that of the boot CPU.
1183 void update_cpu_features(int cpu,
1184 struct cpuinfo_arm64 *info,
1185 struct cpuinfo_arm64 *boot)
1190 * The kernel can handle differing I-cache policies, but otherwise
1191 * caches should look identical. Userspace JITs will make use of
1194 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1195 info->reg_ctr, boot->reg_ctr);
1198 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1199 * could result in too much or too little memory being zeroed if a
1200 * process is preempted and migrated between CPUs.
1202 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1203 info->reg_dczid, boot->reg_dczid);
1205 /* If different, timekeeping will be broken (especially with KVM) */
1206 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1207 info->reg_cntfrq, boot->reg_cntfrq);
1210 * The kernel uses self-hosted debug features and expects CPUs to
1211 * support identical debug features. We presently need CTX_CMPs, WRPs,
1212 * and BRPs to be identical.
1213 * ID_AA64DFR1 is currently RES0.
1215 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1216 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1217 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1218 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1220 * Even in big.LITTLE, processors should be identical instruction-set
1223 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1224 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1225 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1226 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1227 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1228 info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1231 * Differing PARange support is fine as long as all peripherals and
1232 * memory are mapped within the minimum PARange of all CPUs.
1233 * Linux should not care about secure memory.
1235 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1236 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1237 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1238 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1239 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1240 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1242 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1243 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1244 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1245 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1247 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1248 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1250 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu,
1251 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0);
1253 if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1254 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1255 info->reg_zcr = read_zcr_features();
1256 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1257 info->reg_zcr, boot->reg_zcr);
1259 /* Probe vector lengths */
1260 if (!system_capabilities_finalized())
1261 vec_update_vq_map(ARM64_VEC_SVE);
1264 if (IS_ENABLED(CONFIG_ARM64_SME) &&
1265 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1266 info->reg_smcr = read_smcr_features();
1268 * We mask out SMPS since even if the hardware
1269 * supports priorities the kernel does not at present
1270 * and we block access to them.
1272 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1273 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu,
1274 info->reg_smcr, boot->reg_smcr);
1276 /* Probe vector lengths */
1277 if (!system_capabilities_finalized())
1278 vec_update_vq_map(ARM64_VEC_SME);
1282 * The kernel uses the LDGM/STGM instructions and the number of tags
1283 * they read/write depends on the GMID_EL1.BS field. Check that the
1284 * value is the same on all CPUs.
1286 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1287 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1288 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1289 info->reg_gmid, boot->reg_gmid);
1293 * If we don't have AArch32 at all then skip the checks entirely
1294 * as the register values may be UNKNOWN and we're not going to be
1295 * using them for anything.
1297 * This relies on a sanitised view of the AArch64 ID registers
1298 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1300 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1301 lazy_init_32bit_cpu_features(info, boot);
1302 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1307 * Mismatched CPU features are a recipe for disaster. Don't even
1308 * pretend to support them.
1311 pr_warn_once("Unsupported CPU feature variation detected.\n");
1312 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1316 u64 read_sanitised_ftr_reg(u32 id)
1318 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1322 return regp->sys_val;
1324 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1326 #define read_sysreg_case(r) \
1327 case r: val = read_sysreg_s(r); break;
1330 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1331 * Read the system register on the current CPU
1333 u64 __read_sysreg_by_encoding(u32 sys_id)
1335 struct arm64_ftr_reg *regp;
1339 read_sysreg_case(SYS_ID_PFR0_EL1);
1340 read_sysreg_case(SYS_ID_PFR1_EL1);
1341 read_sysreg_case(SYS_ID_PFR2_EL1);
1342 read_sysreg_case(SYS_ID_DFR0_EL1);
1343 read_sysreg_case(SYS_ID_DFR1_EL1);
1344 read_sysreg_case(SYS_ID_MMFR0_EL1);
1345 read_sysreg_case(SYS_ID_MMFR1_EL1);
1346 read_sysreg_case(SYS_ID_MMFR2_EL1);
1347 read_sysreg_case(SYS_ID_MMFR3_EL1);
1348 read_sysreg_case(SYS_ID_MMFR4_EL1);
1349 read_sysreg_case(SYS_ID_MMFR5_EL1);
1350 read_sysreg_case(SYS_ID_ISAR0_EL1);
1351 read_sysreg_case(SYS_ID_ISAR1_EL1);
1352 read_sysreg_case(SYS_ID_ISAR2_EL1);
1353 read_sysreg_case(SYS_ID_ISAR3_EL1);
1354 read_sysreg_case(SYS_ID_ISAR4_EL1);
1355 read_sysreg_case(SYS_ID_ISAR5_EL1);
1356 read_sysreg_case(SYS_ID_ISAR6_EL1);
1357 read_sysreg_case(SYS_MVFR0_EL1);
1358 read_sysreg_case(SYS_MVFR1_EL1);
1359 read_sysreg_case(SYS_MVFR2_EL1);
1361 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1362 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1363 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1364 read_sysreg_case(SYS_ID_AA64SMFR0_EL1);
1365 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1366 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1367 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1368 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1369 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1370 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1371 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1372 read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1374 read_sysreg_case(SYS_CNTFRQ_EL0);
1375 read_sysreg_case(SYS_CTR_EL0);
1376 read_sysreg_case(SYS_DCZID_EL0);
1383 regp = get_arm64_ftr_reg(sys_id);
1385 val &= ~regp->override->mask;
1386 val |= (regp->override->val & regp->override->mask);
1392 #include <linux/irqchip/arm-gic-v3.h>
1395 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1397 int val = cpuid_feature_extract_field_width(reg, entry->field_pos,
1401 return val >= entry->min_field_value;
1405 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1409 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1410 if (scope == SCOPE_SYSTEM)
1411 val = read_sanitised_ftr_reg(entry->sys_reg);
1413 val = __read_sysreg_by_encoding(entry->sys_reg);
1415 return feature_matches(val, entry);
1418 const struct cpumask *system_32bit_el0_cpumask(void)
1420 if (!system_supports_32bit_el0())
1421 return cpu_none_mask;
1423 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1424 return cpu_32bit_el0_mask;
1426 return cpu_possible_mask;
1429 static int __init parse_32bit_el0_param(char *str)
1431 allow_mismatched_32bit_el0 = true;
1434 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1436 static ssize_t aarch32_el0_show(struct device *dev,
1437 struct device_attribute *attr, char *buf)
1439 const struct cpumask *mask = system_32bit_el0_cpumask();
1441 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1443 static const DEVICE_ATTR_RO(aarch32_el0);
1445 static int __init aarch32_el0_sysfs_init(void)
1447 if (!allow_mismatched_32bit_el0)
1450 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0);
1452 device_initcall(aarch32_el0_sysfs_init);
1454 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1456 if (!has_cpuid_feature(entry, scope))
1457 return allow_mismatched_32bit_el0;
1459 if (scope == SCOPE_SYSTEM)
1460 pr_info("detected: 32-bit EL0 Support\n");
1465 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1469 if (!has_cpuid_feature(entry, scope))
1472 has_sre = gic_enable_sre();
1474 pr_warn_once("%s present but disabled by higher exception level\n",
1480 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1482 u32 midr = read_cpuid_id();
1484 /* Cavium ThunderX pass 1.x and 2.x */
1485 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1486 MIDR_CPU_VAR_REV(0, 0),
1487 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1490 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1492 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1494 return cpuid_feature_extract_signed_field(pfr0,
1495 ID_AA64PFR0_FP_SHIFT) < 0;
1498 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1503 if (scope == SCOPE_SYSTEM)
1504 ctr = arm64_ftr_reg_ctrel0.sys_val;
1506 ctr = read_cpuid_effective_cachetype();
1508 return ctr & BIT(CTR_EL0_IDC_SHIFT);
1511 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1514 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1515 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1516 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1519 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT)))
1520 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1523 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1528 if (scope == SCOPE_SYSTEM)
1529 ctr = arm64_ftr_reg_ctrel0.sys_val;
1531 ctr = read_cpuid_cachetype();
1533 return ctr & BIT(CTR_EL0_DIC_SHIFT);
1536 static bool __maybe_unused
1537 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1540 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1541 * may share TLB entries with a CPU stuck in the crashed
1544 if (is_kdump_kernel())
1547 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1550 return has_cpuid_feature(entry, scope);
1554 * This check is triggered during the early boot before the cpufeature
1555 * is initialised. Checking the status on the local CPU allows the boot
1556 * CPU to detect the need for non-global mappings and thus avoiding a
1557 * pagetable re-write after all the CPUs are booted. This check will be
1558 * anyway run on individual CPUs, allowing us to get the consistent
1559 * state once the SMP CPUs are up and thus make the switch to non-global
1560 * mappings if required.
1562 bool kaslr_requires_kpti(void)
1564 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1568 * E0PD does a similar job to KPTI so can be used instead
1571 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1572 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1573 if (cpuid_feature_extract_unsigned_field(mmfr2,
1574 ID_AA64MMFR2_E0PD_SHIFT))
1579 * Systems affected by Cavium erratum 24756 are incompatible
1582 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1583 extern const struct midr_range cavium_erratum_27456_cpus[];
1585 if (is_midr_in_range_list(read_cpuid_id(),
1586 cavium_erratum_27456_cpus))
1590 return kaslr_offset() > 0;
1593 static bool __meltdown_safe = true;
1594 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1596 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1599 /* List of CPUs that are not vulnerable and don't need KPTI */
1600 static const struct midr_range kpti_safe_list[] = {
1601 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1602 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1603 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1604 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1605 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1606 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1607 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1608 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1609 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1610 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1611 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1612 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1613 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1614 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1615 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1618 char const *str = "kpti command line option";
1621 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1623 /* Defer to CPU feature registers */
1624 if (has_cpuid_feature(entry, scope))
1625 meltdown_safe = true;
1628 __meltdown_safe = false;
1631 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1632 * ThunderX leads to apparent I-cache corruption of kernel text, which
1633 * ends as well as you might imagine. Don't even try. We cannot rely
1634 * on the cpus_have_*cap() helpers here to detect the CPU erratum
1635 * because cpucap detection order may change. However, since we know
1636 * affected CPUs are always in a homogeneous configuration, it is
1637 * safe to rely on this_cpu_has_cap() here.
1639 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1640 str = "ARM64_WORKAROUND_CAVIUM_27456";
1644 /* Useful for KASLR robustness */
1645 if (kaslr_requires_kpti()) {
1646 if (!__kpti_forced) {
1652 if (cpu_mitigations_off() && !__kpti_forced) {
1653 str = "mitigations=off";
1657 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1658 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1663 if (__kpti_forced) {
1664 pr_info_once("kernel page table isolation forced %s by %s\n",
1665 __kpti_forced > 0 ? "ON" : "OFF", str);
1666 return __kpti_forced > 0;
1669 return !meltdown_safe;
1672 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1673 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT))
1676 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt,
1677 phys_addr_t size, pgprot_t prot,
1678 phys_addr_t (*pgtable_alloc)(int), int flags);
1680 static phys_addr_t kpti_ng_temp_alloc;
1682 static phys_addr_t kpti_ng_pgd_alloc(int shift)
1684 kpti_ng_temp_alloc -= PAGE_SIZE;
1685 return kpti_ng_temp_alloc;
1689 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1691 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long);
1692 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1693 kpti_remap_fn *remap_fn;
1695 int cpu = smp_processor_id();
1696 int levels = CONFIG_PGTABLE_LEVELS;
1697 int order = order_base_2(levels);
1698 u64 kpti_ng_temp_pgd_pa = 0;
1699 pgd_t *kpti_ng_temp_pgd;
1702 if (__this_cpu_read(this_cpu_vector) == vectors) {
1703 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1705 __this_cpu_write(this_cpu_vector, v);
1709 * We don't need to rewrite the page-tables if either we've done
1710 * it already or we have KASLR enabled and therefore have not
1711 * created any global mappings at all.
1713 if (arm64_use_ng_mappings)
1716 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1719 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
1720 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE);
1721 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd);
1724 // Create a minimal page table hierarchy that permits us to map
1725 // the swapper page tables temporarily as we traverse them.
1727 // The physical pages are laid out as follows:
1729 // +--------+-/-------+-/------ +-\\--------+
1730 // : PTE[] : | PMD[] : | PUD[] : || PGD[] :
1731 // +--------+-\-------+-\------ +-//--------+
1733 // The first page is mapped into this hierarchy at a PMD_SHIFT
1734 // aligned virtual address, so that we can manipulate the PTE
1735 // level entries while the mapping is active. The first entry
1736 // covers the PTE[] page itself, the remaining entries are free
1737 // to be used as a ad-hoc fixmap.
1739 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc),
1740 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL,
1741 kpti_ng_pgd_alloc, 0);
1744 cpu_install_idmap();
1745 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA);
1746 cpu_uninstall_idmap();
1749 free_pages(alloc, order);
1750 arm64_use_ng_mappings = true;
1755 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1758 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1760 static int __init parse_kpti(char *str)
1763 int ret = strtobool(str, &enabled);
1768 __kpti_forced = enabled ? 1 : -1;
1771 early_param("kpti", parse_kpti);
1773 #ifdef CONFIG_ARM64_HW_AFDBM
1774 static inline void __cpu_enable_hw_dbm(void)
1776 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1778 write_sysreg(tcr, tcr_el1);
1780 local_flush_tlb_all();
1783 static bool cpu_has_broken_dbm(void)
1785 /* List of CPUs which have broken DBM support. */
1786 static const struct midr_range cpus[] = {
1787 #ifdef CONFIG_ARM64_ERRATUM_1024718
1788 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1789 /* Kryo4xx Silver (rdpe => r1p0) */
1790 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1792 #ifdef CONFIG_ARM64_ERRATUM_2051678
1793 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
1798 return is_midr_in_range_list(read_cpuid_id(), cpus);
1801 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1803 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1804 !cpu_has_broken_dbm();
1807 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1809 if (cpu_can_use_dbm(cap))
1810 __cpu_enable_hw_dbm();
1813 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1816 static bool detected = false;
1818 * DBM is a non-conflicting feature. i.e, the kernel can safely
1819 * run a mix of CPUs with and without the feature. So, we
1820 * unconditionally enable the capability to allow any late CPU
1821 * to use the feature. We only enable the control bits on the
1822 * CPU, if it actually supports.
1824 * We have to make sure we print the "feature" detection only
1825 * when at least one CPU actually uses it. So check if this CPU
1826 * can actually use it and print the message exactly once.
1828 * This is safe as all CPUs (including secondary CPUs - due to the
1829 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1830 * goes through the "matches" check exactly once. Also if a CPU
1831 * matches the criteria, it is guaranteed that the CPU will turn
1832 * the DBM on, as the capability is unconditionally enabled.
1834 if (!detected && cpu_can_use_dbm(cap)) {
1836 pr_info("detected: Hardware dirty bit management\n");
1844 #ifdef CONFIG_ARM64_AMU_EXTN
1847 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1848 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1849 * information regarding all the events that it supports. When a CPU bit is
1850 * set in the cpumask, the user of this feature can only rely on the presence
1851 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1852 * counters are enabled or access to these counters is enabled by code
1853 * executed at higher exception levels (firmware).
1855 static struct cpumask amu_cpus __read_mostly;
1857 bool cpu_has_amu_feat(int cpu)
1859 return cpumask_test_cpu(cpu, &amu_cpus);
1862 int get_cpu_with_amu_feat(void)
1864 return cpumask_any(&amu_cpus);
1867 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1869 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1870 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1871 smp_processor_id());
1872 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1874 /* 0 reference values signal broken/disabled counters */
1875 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
1876 update_freq_counters_refs();
1880 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1884 * The AMU extension is a non-conflicting feature: the kernel can
1885 * safely run a mix of CPUs with and without support for the
1886 * activity monitors extension. Therefore, unconditionally enable
1887 * the capability to allow any late CPU to use the feature.
1889 * With this feature unconditionally enabled, the cpu_enable
1890 * function will be called for all CPUs that match the criteria,
1891 * including secondary and hotplugged, marking this feature as
1892 * present on that respective CPU. The enable function will also
1893 * print a detection message.
1899 int get_cpu_with_amu_feat(void)
1905 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1907 return is_kernel_in_hyp_mode();
1910 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1913 * Copy register values that aren't redirected by hardware.
1915 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1916 * this value to tpidr_el2 before we patch the code. Once we've done
1917 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1920 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1921 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1924 #ifdef CONFIG_ARM64_PAN
1925 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1928 * We modify PSTATE. This won't work from irq context as the PSTATE
1929 * is discarded once we return from the exception.
1931 WARN_ON_ONCE(in_interrupt());
1933 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1936 #endif /* CONFIG_ARM64_PAN */
1938 #ifdef CONFIG_ARM64_RAS_EXTN
1939 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1941 /* Firmware may have left a deferred SError in this register. */
1942 write_sysreg_s(0, SYS_DISR_EL1);
1944 #endif /* CONFIG_ARM64_RAS_EXTN */
1946 #ifdef CONFIG_ARM64_PTR_AUTH
1947 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1949 int boot_val, sec_val;
1951 /* We don't expect to be called with SCOPE_SYSTEM */
1952 WARN_ON(scope == SCOPE_SYSTEM);
1954 * The ptr-auth feature levels are not intercompatible with lower
1955 * levels. Hence we must match ptr-auth feature level of the secondary
1956 * CPUs with that of the boot CPU. The level of boot cpu is fetched
1957 * from the sanitised register whereas direct register read is done for
1958 * the secondary CPUs.
1959 * The sanitised feature state is guaranteed to match that of the
1960 * boot CPU as a mismatched secondary CPU is parked before it gets
1961 * a chance to update the state, with the capability.
1963 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1964 entry->field_pos, entry->sign);
1965 if (scope & SCOPE_BOOT_CPU)
1966 return boot_val >= entry->min_field_value;
1967 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
1968 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1969 entry->field_pos, entry->sign);
1970 return (sec_val >= entry->min_field_value) && (sec_val == boot_val);
1973 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1976 bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1977 bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope);
1978 bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope);
1980 return apa || apa3 || api;
1983 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1986 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1987 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5);
1988 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3);
1990 return gpa || gpa3 || gpi;
1992 #endif /* CONFIG_ARM64_PTR_AUTH */
1994 #ifdef CONFIG_ARM64_E0PD
1995 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1997 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1998 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
2000 #endif /* CONFIG_ARM64_E0PD */
2002 #ifdef CONFIG_ARM64_PSEUDO_NMI
2003 static bool enable_pseudo_nmi;
2005 static int __init early_enable_pseudo_nmi(char *p)
2007 return strtobool(p, &enable_pseudo_nmi);
2009 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
2011 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
2014 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
2018 #ifdef CONFIG_ARM64_BTI
2019 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
2022 * Use of X16/X17 for tail-calls and trampolines that jump to
2023 * function entry points using BR is a requirement for
2024 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
2025 * So, be strict and forbid other BRs using other registers to
2026 * jump onto a PACIxSP instruction:
2028 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
2031 #endif /* CONFIG_ARM64_BTI */
2033 #ifdef CONFIG_ARM64_MTE
2034 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
2036 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
2040 * Clear the tags in the zero page. This needs to be done via the
2041 * linear map which has the Tagged attribute.
2043 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
2044 mte_clear_page_tags(lm_alias(empty_zero_page));
2046 kasan_init_hw_tags_cpu();
2048 #endif /* CONFIG_ARM64_MTE */
2050 static void elf_hwcap_fixup(void)
2052 #ifdef CONFIG_ARM64_ERRATUM_1742098
2053 if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))
2054 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
2055 #endif /* ARM64_ERRATUM_1742098 */
2059 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
2061 return kvm_get_mode() == KVM_MODE_PROTECTED;
2063 #endif /* CONFIG_KVM */
2065 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused)
2067 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP);
2070 /* Internal helper functions to match cpu capability type */
2072 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
2074 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
2078 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
2080 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
2084 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
2086 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
2089 static const struct arm64_cpu_capabilities arm64_features[] = {
2091 .desc = "GIC system register CPU interface",
2092 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
2093 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2094 .matches = has_useable_gicv3_cpuif,
2095 .sys_reg = SYS_ID_AA64PFR0_EL1,
2096 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2098 .sign = FTR_UNSIGNED,
2099 .min_field_value = 1,
2102 .desc = "Enhanced Counter Virtualization",
2103 .capability = ARM64_HAS_ECV,
2104 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2105 .matches = has_cpuid_feature,
2106 .sys_reg = SYS_ID_AA64MMFR0_EL1,
2107 .field_pos = ID_AA64MMFR0_ECV_SHIFT,
2109 .sign = FTR_UNSIGNED,
2110 .min_field_value = 1,
2112 #ifdef CONFIG_ARM64_PAN
2114 .desc = "Privileged Access Never",
2115 .capability = ARM64_HAS_PAN,
2116 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2117 .matches = has_cpuid_feature,
2118 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2119 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
2121 .sign = FTR_UNSIGNED,
2122 .min_field_value = 1,
2123 .cpu_enable = cpu_enable_pan,
2125 #endif /* CONFIG_ARM64_PAN */
2126 #ifdef CONFIG_ARM64_EPAN
2128 .desc = "Enhanced Privileged Access Never",
2129 .capability = ARM64_HAS_EPAN,
2130 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2131 .matches = has_cpuid_feature,
2132 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2133 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
2135 .sign = FTR_UNSIGNED,
2136 .min_field_value = 3,
2138 #endif /* CONFIG_ARM64_EPAN */
2139 #ifdef CONFIG_ARM64_LSE_ATOMICS
2141 .desc = "LSE atomic instructions",
2142 .capability = ARM64_HAS_LSE_ATOMICS,
2143 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2144 .matches = has_cpuid_feature,
2145 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2146 .field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT,
2148 .sign = FTR_UNSIGNED,
2149 .min_field_value = 2,
2151 #endif /* CONFIG_ARM64_LSE_ATOMICS */
2153 .desc = "Software prefetching using PRFM",
2154 .capability = ARM64_HAS_NO_HW_PREFETCH,
2155 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2156 .matches = has_no_hw_prefetch,
2159 .desc = "Virtualization Host Extensions",
2160 .capability = ARM64_HAS_VIRT_HOST_EXTN,
2161 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2162 .matches = runs_at_el2,
2163 .cpu_enable = cpu_copy_el2regs,
2166 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
2167 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2168 .matches = has_32bit_el0,
2169 .sys_reg = SYS_ID_AA64PFR0_EL1,
2170 .sign = FTR_UNSIGNED,
2171 .field_pos = ID_AA64PFR0_EL0_SHIFT,
2173 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
2177 .desc = "32-bit EL1 Support",
2178 .capability = ARM64_HAS_32BIT_EL1,
2179 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2180 .matches = has_cpuid_feature,
2181 .sys_reg = SYS_ID_AA64PFR0_EL1,
2182 .sign = FTR_UNSIGNED,
2183 .field_pos = ID_AA64PFR0_EL1_SHIFT,
2185 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
2188 .desc = "Protected KVM",
2189 .capability = ARM64_KVM_PROTECTED_MODE,
2190 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2191 .matches = is_kvm_protected_mode,
2195 .desc = "Kernel page table isolation (KPTI)",
2196 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
2197 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2199 * The ID feature fields below are used to indicate that
2200 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2203 .sys_reg = SYS_ID_AA64PFR0_EL1,
2204 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
2206 .min_field_value = 1,
2207 .matches = unmap_kernel_at_el0,
2208 .cpu_enable = kpti_install_ng_mappings,
2211 /* FP/SIMD is not implemented */
2212 .capability = ARM64_HAS_NO_FPSIMD,
2213 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2214 .min_field_value = 0,
2215 .matches = has_no_fpsimd,
2217 #ifdef CONFIG_ARM64_PMEM
2219 .desc = "Data cache clean to Point of Persistence",
2220 .capability = ARM64_HAS_DCPOP,
2221 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2222 .matches = has_cpuid_feature,
2223 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2224 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,
2226 .min_field_value = 1,
2229 .desc = "Data cache clean to Point of Deep Persistence",
2230 .capability = ARM64_HAS_DCPODP,
2231 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2232 .matches = has_cpuid_feature,
2233 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2234 .sign = FTR_UNSIGNED,
2235 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,
2237 .min_field_value = 2,
2240 #ifdef CONFIG_ARM64_SVE
2242 .desc = "Scalable Vector Extension",
2243 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2244 .capability = ARM64_SVE,
2245 .sys_reg = SYS_ID_AA64PFR0_EL1,
2246 .sign = FTR_UNSIGNED,
2247 .field_pos = ID_AA64PFR0_SVE_SHIFT,
2249 .min_field_value = ID_AA64PFR0_SVE,
2250 .matches = has_cpuid_feature,
2251 .cpu_enable = sve_kernel_enable,
2253 #endif /* CONFIG_ARM64_SVE */
2254 #ifdef CONFIG_ARM64_RAS_EXTN
2256 .desc = "RAS Extension Support",
2257 .capability = ARM64_HAS_RAS_EXTN,
2258 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2259 .matches = has_cpuid_feature,
2260 .sys_reg = SYS_ID_AA64PFR0_EL1,
2261 .sign = FTR_UNSIGNED,
2262 .field_pos = ID_AA64PFR0_RAS_SHIFT,
2264 .min_field_value = ID_AA64PFR0_RAS_V1,
2265 .cpu_enable = cpu_clear_disr,
2267 #endif /* CONFIG_ARM64_RAS_EXTN */
2268 #ifdef CONFIG_ARM64_AMU_EXTN
2271 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
2272 * Therefore, don't provide .desc as we don't want the detection
2273 * message to be shown until at least one CPU is detected to
2274 * support the feature.
2276 .capability = ARM64_HAS_AMU_EXTN,
2277 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2279 .sys_reg = SYS_ID_AA64PFR0_EL1,
2280 .sign = FTR_UNSIGNED,
2281 .field_pos = ID_AA64PFR0_AMU_SHIFT,
2283 .min_field_value = ID_AA64PFR0_AMU,
2284 .cpu_enable = cpu_amu_enable,
2286 #endif /* CONFIG_ARM64_AMU_EXTN */
2288 .desc = "Data cache clean to the PoU not required for I/D coherence",
2289 .capability = ARM64_HAS_CACHE_IDC,
2290 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2291 .matches = has_cache_idc,
2292 .cpu_enable = cpu_emulate_effective_ctr,
2295 .desc = "Instruction cache invalidation not required for I/D coherence",
2296 .capability = ARM64_HAS_CACHE_DIC,
2297 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2298 .matches = has_cache_dic,
2301 .desc = "Stage-2 Force Write-Back",
2302 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2303 .capability = ARM64_HAS_STAGE2_FWB,
2304 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2305 .sign = FTR_UNSIGNED,
2306 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
2308 .min_field_value = 1,
2309 .matches = has_cpuid_feature,
2312 .desc = "ARMv8.4 Translation Table Level",
2313 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2314 .capability = ARM64_HAS_ARMv8_4_TTL,
2315 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2316 .sign = FTR_UNSIGNED,
2317 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
2319 .min_field_value = 1,
2320 .matches = has_cpuid_feature,
2323 .desc = "TLB range maintenance instructions",
2324 .capability = ARM64_HAS_TLB_RANGE,
2325 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2326 .matches = has_cpuid_feature,
2327 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2328 .field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT,
2330 .sign = FTR_UNSIGNED,
2331 .min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE,
2333 #ifdef CONFIG_ARM64_HW_AFDBM
2336 * Since we turn this on always, we don't want the user to
2337 * think that the feature is available when it may not be.
2338 * So hide the description.
2340 * .desc = "Hardware pagetable Dirty Bit Management",
2343 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2344 .capability = ARM64_HW_DBM,
2345 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2346 .sign = FTR_UNSIGNED,
2347 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
2349 .min_field_value = 2,
2350 .matches = has_hw_dbm,
2351 .cpu_enable = cpu_enable_hw_dbm,
2355 .desc = "CRC32 instructions",
2356 .capability = ARM64_HAS_CRC32,
2357 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2358 .matches = has_cpuid_feature,
2359 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2360 .field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT,
2362 .min_field_value = 1,
2365 .desc = "Speculative Store Bypassing Safe (SSBS)",
2366 .capability = ARM64_SSBS,
2367 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2368 .matches = has_cpuid_feature,
2369 .sys_reg = SYS_ID_AA64PFR1_EL1,
2370 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2372 .sign = FTR_UNSIGNED,
2373 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2375 #ifdef CONFIG_ARM64_CNP
2377 .desc = "Common not Private translations",
2378 .capability = ARM64_HAS_CNP,
2379 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2380 .matches = has_useable_cnp,
2381 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2382 .sign = FTR_UNSIGNED,
2383 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2385 .min_field_value = 1,
2386 .cpu_enable = cpu_enable_cnp,
2390 .desc = "Speculation barrier (SB)",
2391 .capability = ARM64_HAS_SB,
2392 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2393 .matches = has_cpuid_feature,
2394 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2395 .field_pos = ID_AA64ISAR1_EL1_SB_SHIFT,
2397 .sign = FTR_UNSIGNED,
2398 .min_field_value = 1,
2400 #ifdef CONFIG_ARM64_PTR_AUTH
2402 .desc = "Address authentication (architected QARMA5 algorithm)",
2403 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5,
2404 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2405 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2406 .sign = FTR_UNSIGNED,
2407 .field_pos = ID_AA64ISAR1_EL1_APA_SHIFT,
2409 .min_field_value = ID_AA64ISAR1_EL1_APA_PAuth,
2410 .matches = has_address_auth_cpucap,
2413 .desc = "Address authentication (architected QARMA3 algorithm)",
2414 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3,
2415 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2416 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2417 .sign = FTR_UNSIGNED,
2418 .field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT,
2420 .min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth,
2421 .matches = has_address_auth_cpucap,
2424 .desc = "Address authentication (IMP DEF algorithm)",
2425 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2426 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2427 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2428 .sign = FTR_UNSIGNED,
2429 .field_pos = ID_AA64ISAR1_EL1_API_SHIFT,
2431 .min_field_value = ID_AA64ISAR1_EL1_API_PAuth,
2432 .matches = has_address_auth_cpucap,
2435 .capability = ARM64_HAS_ADDRESS_AUTH,
2436 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2437 .matches = has_address_auth_metacap,
2440 .desc = "Generic authentication (architected QARMA5 algorithm)",
2441 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5,
2442 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2443 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2444 .sign = FTR_UNSIGNED,
2445 .field_pos = ID_AA64ISAR1_EL1_GPA_SHIFT,
2447 .min_field_value = ID_AA64ISAR1_EL1_GPA_IMP,
2448 .matches = has_cpuid_feature,
2451 .desc = "Generic authentication (architected QARMA3 algorithm)",
2452 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3,
2453 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2454 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2455 .sign = FTR_UNSIGNED,
2456 .field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT,
2458 .min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP,
2459 .matches = has_cpuid_feature,
2462 .desc = "Generic authentication (IMP DEF algorithm)",
2463 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2464 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2465 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2466 .sign = FTR_UNSIGNED,
2467 .field_pos = ID_AA64ISAR1_EL1_GPI_SHIFT,
2469 .min_field_value = ID_AA64ISAR1_EL1_GPI_IMP,
2470 .matches = has_cpuid_feature,
2473 .capability = ARM64_HAS_GENERIC_AUTH,
2474 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2475 .matches = has_generic_auth,
2477 #endif /* CONFIG_ARM64_PTR_AUTH */
2478 #ifdef CONFIG_ARM64_PSEUDO_NMI
2481 * Depends on having GICv3
2483 .desc = "IRQ priority masking",
2484 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2485 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2486 .matches = can_use_gic_priorities,
2487 .sys_reg = SYS_ID_AA64PFR0_EL1,
2488 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2490 .sign = FTR_UNSIGNED,
2491 .min_field_value = 1,
2494 #ifdef CONFIG_ARM64_E0PD
2497 .capability = ARM64_HAS_E0PD,
2498 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2499 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2500 .sign = FTR_UNSIGNED,
2502 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2503 .matches = has_cpuid_feature,
2504 .min_field_value = 1,
2505 .cpu_enable = cpu_enable_e0pd,
2509 .desc = "Random Number Generator",
2510 .capability = ARM64_HAS_RNG,
2511 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2512 .matches = has_cpuid_feature,
2513 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2514 .field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT,
2516 .sign = FTR_UNSIGNED,
2517 .min_field_value = 1,
2519 #ifdef CONFIG_ARM64_BTI
2521 .desc = "Branch Target Identification",
2522 .capability = ARM64_BTI,
2523 #ifdef CONFIG_ARM64_BTI_KERNEL
2524 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2526 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2528 .matches = has_cpuid_feature,
2529 .cpu_enable = bti_enable,
2530 .sys_reg = SYS_ID_AA64PFR1_EL1,
2531 .field_pos = ID_AA64PFR1_BT_SHIFT,
2533 .min_field_value = ID_AA64PFR1_BT_BTI,
2534 .sign = FTR_UNSIGNED,
2537 #ifdef CONFIG_ARM64_MTE
2539 .desc = "Memory Tagging Extension",
2540 .capability = ARM64_MTE,
2541 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2542 .matches = has_cpuid_feature,
2543 .sys_reg = SYS_ID_AA64PFR1_EL1,
2544 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2546 .min_field_value = ID_AA64PFR1_MTE,
2547 .sign = FTR_UNSIGNED,
2548 .cpu_enable = cpu_enable_mte,
2551 .desc = "Asymmetric MTE Tag Check Fault",
2552 .capability = ARM64_MTE_ASYMM,
2553 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2554 .matches = has_cpuid_feature,
2555 .sys_reg = SYS_ID_AA64PFR1_EL1,
2556 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2558 .min_field_value = ID_AA64PFR1_MTE_ASYMM,
2559 .sign = FTR_UNSIGNED,
2561 #endif /* CONFIG_ARM64_MTE */
2563 .desc = "RCpc load-acquire (LDAPR)",
2564 .capability = ARM64_HAS_LDAPR,
2565 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2566 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2567 .sign = FTR_UNSIGNED,
2568 .field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT,
2570 .matches = has_cpuid_feature,
2571 .min_field_value = 1,
2573 #ifdef CONFIG_ARM64_SME
2575 .desc = "Scalable Matrix Extension",
2576 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2577 .capability = ARM64_SME,
2578 .sys_reg = SYS_ID_AA64PFR1_EL1,
2579 .sign = FTR_UNSIGNED,
2580 .field_pos = ID_AA64PFR1_SME_SHIFT,
2582 .min_field_value = ID_AA64PFR1_SME,
2583 .matches = has_cpuid_feature,
2584 .cpu_enable = sme_kernel_enable,
2586 /* FA64 should be sorted after the base SME capability */
2589 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2590 .capability = ARM64_SME_FA64,
2591 .sys_reg = SYS_ID_AA64SMFR0_EL1,
2592 .sign = FTR_UNSIGNED,
2593 .field_pos = ID_AA64SMFR0_EL1_FA64_SHIFT,
2595 .min_field_value = ID_AA64SMFR0_EL1_FA64_IMP,
2596 .matches = has_cpuid_feature,
2597 .cpu_enable = fa64_kernel_enable,
2599 #endif /* CONFIG_ARM64_SME */
2601 .desc = "WFx with timeout",
2602 .capability = ARM64_HAS_WFXT,
2603 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2604 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2605 .sign = FTR_UNSIGNED,
2606 .field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT,
2608 .matches = has_cpuid_feature,
2609 .min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP,
2612 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality",
2613 .capability = ARM64_HAS_TIDCP1,
2614 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2615 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2616 .sign = FTR_UNSIGNED,
2617 .field_pos = ID_AA64MMFR1_TIDCP1_SHIFT,
2619 .min_field_value = ID_AA64MMFR1_TIDCP1_IMP,
2620 .matches = has_cpuid_feature,
2621 .cpu_enable = cpu_trap_el0_impdef,
2626 #define HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \
2627 .matches = has_cpuid_feature, \
2629 .field_pos = field, \
2630 .field_width = width, \
2632 .min_field_value = min_value,
2634 #define __HWCAP_CAP(name, cap_type, cap) \
2636 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2637 .hwcap_type = cap_type, \
2640 #define HWCAP_CAP(reg, field, width, s, min_value, cap_type, cap) \
2642 __HWCAP_CAP(#cap, cap_type, cap) \
2643 HWCAP_CPUID_MATCH(reg, field, width, s, min_value) \
2646 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2648 __HWCAP_CAP(#cap, cap_type, cap) \
2649 .matches = cpucap_multi_entry_cap_matches, \
2650 .match_list = list, \
2653 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2655 __HWCAP_CAP(#cap, cap_type, cap) \
2659 #ifdef CONFIG_ARM64_PTR_AUTH
2660 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2662 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_APA_SHIFT,
2664 ID_AA64ISAR1_EL1_APA_PAuth)
2667 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_APA3_SHIFT,
2668 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_APA3_PAuth)
2671 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_API_SHIFT,
2672 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_API_PAuth)
2677 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2679 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPA_SHIFT,
2680 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPA_IMP)
2683 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_GPA3_SHIFT,
2684 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_GPA3_IMP)
2687 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_GPI_SHIFT,
2688 4, FTR_UNSIGNED, ID_AA64ISAR1_EL1_GPI_IMP)
2694 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2695 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2696 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2697 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2698 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2699 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2700 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2701 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2702 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2703 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2704 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2705 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2706 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2707 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2708 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2709 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2710 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2711 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2712 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2713 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2714 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2715 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2716 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2717 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2718 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2719 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2720 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2721 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2722 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2723 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_SB_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2724 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2725 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_EBF16),
2726 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2727 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2728 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2729 #ifdef CONFIG_ARM64_SVE
2730 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2731 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SVEver_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2732 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2733 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_AES_PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2734 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BitPerm_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2735 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_BF16_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2736 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SHA3_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2737 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_SM4_IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2738 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_I8MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2739 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F32MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2740 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, FTR_UNSIGNED, ID_AA64ZFR0_EL1_F64MM_IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2742 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2743 #ifdef CONFIG_ARM64_BTI
2744 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2746 #ifdef CONFIG_ARM64_PTR_AUTH
2747 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2748 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2750 #ifdef CONFIG_ARM64_MTE
2751 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2752 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),
2753 #endif /* CONFIG_ARM64_MTE */
2754 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
2755 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
2756 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
2757 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
2758 #ifdef CONFIG_ARM64_SME
2759 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME),
2760 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_FA64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
2761 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I16I64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
2762 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F64F64_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
2763 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, FTR_UNSIGNED, ID_AA64SMFR0_EL1_I8I32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
2764 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
2765 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_B16F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
2766 HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_EL1_F32F32_IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
2767 #endif /* CONFIG_ARM64_SME */
2771 #ifdef CONFIG_COMPAT
2772 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2775 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2776 * in line with that of arm32 as in vfp_init(). We make sure that the
2777 * check is future proof, by making sure value is non-zero.
2781 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2782 if (scope == SCOPE_SYSTEM)
2783 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2785 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2787 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2788 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2789 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2793 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2794 #ifdef CONFIG_COMPAT
2795 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2796 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2797 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2798 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2799 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2800 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2801 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2802 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2803 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2804 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2809 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2811 switch (cap->hwcap_type) {
2813 cpu_set_feature(cap->hwcap);
2815 #ifdef CONFIG_COMPAT
2816 case CAP_COMPAT_HWCAP:
2817 compat_elf_hwcap |= (u32)cap->hwcap;
2819 case CAP_COMPAT_HWCAP2:
2820 compat_elf_hwcap2 |= (u32)cap->hwcap;
2829 /* Check if we have a particular HWCAP enabled */
2830 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2834 switch (cap->hwcap_type) {
2836 rc = cpu_have_feature(cap->hwcap);
2838 #ifdef CONFIG_COMPAT
2839 case CAP_COMPAT_HWCAP:
2840 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2842 case CAP_COMPAT_HWCAP2:
2843 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2854 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2856 /* We support emulation of accesses to CPU ID feature registers */
2857 cpu_set_named_feature(CPUID);
2858 for (; hwcaps->matches; hwcaps++)
2859 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2860 cap_set_elf_hwcap(hwcaps);
2863 static void update_cpu_capabilities(u16 scope_mask)
2866 const struct arm64_cpu_capabilities *caps;
2868 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2869 for (i = 0; i < ARM64_NCAPS; i++) {
2870 caps = cpu_hwcaps_ptrs[i];
2871 if (!caps || !(caps->type & scope_mask) ||
2872 cpus_have_cap(caps->capability) ||
2873 !caps->matches(caps, cpucap_default_scope(caps)))
2877 pr_info("detected: %s\n", caps->desc);
2878 cpus_set_cap(caps->capability);
2880 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2881 set_bit(caps->capability, boot_capabilities);
2886 * Enable all the available capabilities on this CPU. The capabilities
2887 * with BOOT_CPU scope are handled separately and hence skipped here.
2889 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2892 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2894 for_each_available_cap(i) {
2895 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2900 if (!(cap->type & non_boot_scope))
2903 if (cap->cpu_enable)
2904 cap->cpu_enable(cap);
2910 * Run through the enabled capabilities and enable() it on all active
2913 static void __init enable_cpu_capabilities(u16 scope_mask)
2916 const struct arm64_cpu_capabilities *caps;
2919 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2920 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2922 for (i = 0; i < ARM64_NCAPS; i++) {
2925 caps = cpu_hwcaps_ptrs[i];
2926 if (!caps || !(caps->type & scope_mask))
2928 num = caps->capability;
2929 if (!cpus_have_cap(num))
2932 /* Ensure cpus_have_const_cap(num) works */
2933 static_branch_enable(&cpu_hwcap_keys[num]);
2935 if (boot_scope && caps->cpu_enable)
2937 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2938 * before any secondary CPU boots. Thus, each secondary
2939 * will enable the capability as appropriate via
2940 * check_local_cpu_capabilities(). The only exception is
2941 * the boot CPU, for which the capability must be
2942 * enabled here. This approach avoids costly
2943 * stop_machine() calls for this case.
2945 caps->cpu_enable(caps);
2949 * For all non-boot scope capabilities, use stop_machine()
2950 * as it schedules the work allowing us to modify PSTATE,
2951 * instead of on_each_cpu() which uses an IPI, giving us a
2952 * PSTATE that disappears when we return.
2955 stop_machine(cpu_enable_non_boot_scope_capabilities,
2956 NULL, cpu_online_mask);
2960 * Run through the list of capabilities to check for conflicts.
2961 * If the system has already detected a capability, take necessary
2962 * action on this CPU.
2964 static void verify_local_cpu_caps(u16 scope_mask)
2967 bool cpu_has_cap, system_has_cap;
2968 const struct arm64_cpu_capabilities *caps;
2970 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2972 for (i = 0; i < ARM64_NCAPS; i++) {
2973 caps = cpu_hwcaps_ptrs[i];
2974 if (!caps || !(caps->type & scope_mask))
2977 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2978 system_has_cap = cpus_have_cap(caps->capability);
2980 if (system_has_cap) {
2982 * Check if the new CPU misses an advertised feature,
2983 * which is not safe to miss.
2985 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2988 * We have to issue cpu_enable() irrespective of
2989 * whether the CPU has it or not, as it is enabeld
2990 * system wide. It is upto the call back to take
2991 * appropriate action on this CPU.
2993 if (caps->cpu_enable)
2994 caps->cpu_enable(caps);
2997 * Check if the CPU has this capability if it isn't
2998 * safe to have when the system doesn't.
3000 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
3005 if (i < ARM64_NCAPS) {
3006 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
3007 smp_processor_id(), caps->capability,
3008 caps->desc, system_has_cap, cpu_has_cap);
3010 if (cpucap_panic_on_conflict(caps))
3018 * Check for CPU features that are used in early boot
3019 * based on the Boot CPU value.
3021 static void check_early_cpu_features(void)
3023 verify_cpu_asid_bits();
3025 verify_local_cpu_caps(SCOPE_BOOT_CPU);
3029 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
3032 for (; caps->matches; caps++)
3033 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
3034 pr_crit("CPU%d: missing HWCAP: %s\n",
3035 smp_processor_id(), caps->desc);
3040 static void verify_local_elf_hwcaps(void)
3042 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
3044 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
3045 __verify_local_elf_hwcaps(compat_elf_hwcaps);
3048 static void verify_sve_features(void)
3050 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
3051 u64 zcr = read_zcr_features();
3053 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
3054 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
3056 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) {
3057 pr_crit("CPU%d: SVE: vector length support mismatch\n",
3058 smp_processor_id());
3062 /* Add checks on other ZCR bits here if necessary */
3065 static void verify_sme_features(void)
3067 u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1);
3068 u64 smcr = read_smcr_features();
3070 unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK;
3071 unsigned int len = smcr & SMCR_ELx_LEN_MASK;
3073 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) {
3074 pr_crit("CPU%d: SME: vector length support mismatch\n",
3075 smp_processor_id());
3079 /* Add checks on other SMCR bits here if necessary */
3082 static void verify_hyp_capabilities(void)
3084 u64 safe_mmfr1, mmfr0, mmfr1;
3085 int parange, ipa_max;
3086 unsigned int safe_vmid_bits, vmid_bits;
3088 if (!IS_ENABLED(CONFIG_KVM))
3091 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
3092 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
3093 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
3095 /* Verify VMID bits */
3096 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
3097 vmid_bits = get_vmid_bits(mmfr1);
3098 if (vmid_bits < safe_vmid_bits) {
3099 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
3103 /* Verify IPA range */
3104 parange = cpuid_feature_extract_unsigned_field(mmfr0,
3105 ID_AA64MMFR0_PARANGE_SHIFT);
3106 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
3107 if (ipa_max < get_kvm_ipa_limit()) {
3108 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
3114 * Run through the enabled system capabilities and enable() it on this CPU.
3115 * The capabilities were decided based on the available CPUs at the boot time.
3116 * Any new CPU should match the system wide status of the capability. If the
3117 * new CPU doesn't have a capability which the system now has enabled, we
3118 * cannot do anything to fix it up and could cause unexpected failures. So
3121 static void verify_local_cpu_capabilities(void)
3124 * The capabilities with SCOPE_BOOT_CPU are checked from
3125 * check_early_cpu_features(), as they need to be verified
3126 * on all secondary CPUs.
3128 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3129 verify_local_elf_hwcaps();
3131 if (system_supports_sve())
3132 verify_sve_features();
3134 if (system_supports_sme())
3135 verify_sme_features();
3137 if (is_hyp_mode_available())
3138 verify_hyp_capabilities();
3141 void check_local_cpu_capabilities(void)
3144 * All secondary CPUs should conform to the early CPU features
3145 * in use by the kernel based on boot CPU.
3147 check_early_cpu_features();
3150 * If we haven't finalised the system capabilities, this CPU gets
3151 * a chance to update the errata work arounds and local features.
3152 * Otherwise, this CPU should verify that it has all the system
3153 * advertised capabilities.
3155 if (!system_capabilities_finalized())
3156 update_cpu_capabilities(SCOPE_LOCAL_CPU);
3158 verify_local_cpu_capabilities();
3161 static void __init setup_boot_cpu_capabilities(void)
3163 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
3164 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
3165 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
3166 enable_cpu_capabilities(SCOPE_BOOT_CPU);
3169 bool this_cpu_has_cap(unsigned int n)
3171 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
3172 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
3175 return cap->matches(cap, SCOPE_LOCAL_CPU);
3180 EXPORT_SYMBOL_GPL(this_cpu_has_cap);
3183 * This helper function is used in a narrow window when,
3184 * - The system wide safe registers are set with all the SMP CPUs and,
3185 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
3186 * In all other cases cpus_have_{const_}cap() should be used.
3188 static bool __maybe_unused __system_matches_cap(unsigned int n)
3190 if (n < ARM64_NCAPS) {
3191 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
3194 return cap->matches(cap, SCOPE_SYSTEM);
3199 void cpu_set_feature(unsigned int num)
3201 set_bit(num, elf_hwcap);
3204 bool cpu_have_feature(unsigned int num)
3206 return test_bit(num, elf_hwcap);
3208 EXPORT_SYMBOL_GPL(cpu_have_feature);
3210 unsigned long cpu_get_elf_hwcap(void)
3213 * We currently only populate the first 32 bits of AT_HWCAP. Please
3214 * note that for userspace compatibility we guarantee that bits 62
3215 * and 63 will always be returned as 0.
3217 return elf_hwcap[0];
3220 unsigned long cpu_get_elf_hwcap2(void)
3222 return elf_hwcap[1];
3225 static void __init setup_system_capabilities(void)
3228 * We have finalised the system-wide safe feature
3229 * registers, finalise the capabilities that depend
3230 * on it. Also enable all the available capabilities,
3231 * that are not enabled already.
3233 update_cpu_capabilities(SCOPE_SYSTEM);
3234 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3237 void __init setup_cpu_features(void)
3241 setup_system_capabilities();
3242 setup_elf_hwcaps(arm64_elf_hwcaps);
3244 if (system_supports_32bit_el0()) {
3245 setup_elf_hwcaps(compat_elf_hwcaps);
3249 if (system_uses_ttbr0_pan())
3250 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
3254 minsigstksz_setup();
3256 /* Advertise that we have computed the system capabilities */
3257 finalize_system_capabilities();
3260 * Check for sane CTR_EL0.CWG value.
3262 cwg = cache_type_cwg();
3264 pr_warn("No Cache Writeback Granule information, assuming %d\n",
3268 static int enable_mismatched_32bit_el0(unsigned int cpu)
3271 * The first 32-bit-capable CPU we detected and so can no longer
3272 * be offlined by userspace. -1 indicates we haven't yet onlined
3273 * a 32-bit-capable CPU.
3275 static int lucky_winner = -1;
3277 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
3278 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
3281 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
3282 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
3285 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
3288 if (lucky_winner >= 0)
3292 * We've detected a mismatch. We need to keep one of our CPUs with
3293 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
3294 * every CPU in the system for a 32-bit task.
3296 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
3298 get_cpu_device(lucky_winner)->offline_disabled = true;
3299 setup_elf_hwcaps(compat_elf_hwcaps);
3301 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
3306 static int __init init_32bit_el0_mask(void)
3308 if (!allow_mismatched_32bit_el0)
3311 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
3314 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
3315 "arm64/mismatched_32bit_el0:online",
3316 enable_mismatched_32bit_el0, NULL);
3318 subsys_initcall_sync(init_32bit_el0_mask);
3320 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
3322 cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir);
3326 * We emulate only the following system register space.
3327 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
3328 * See Table C5-6 System instruction encodings for System register accesses,
3329 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
3331 static inline bool __attribute_const__ is_emulated(u32 id)
3333 return (sys_reg_Op0(id) == 0x3 &&
3334 sys_reg_CRn(id) == 0x0 &&
3335 sys_reg_Op1(id) == 0x0 &&
3336 (sys_reg_CRm(id) == 0 ||
3337 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
3341 * With CRm == 0, reg should be one of :
3342 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3344 static inline int emulate_id_reg(u32 id, u64 *valp)
3348 *valp = read_cpuid_id();
3351 *valp = SYS_MPIDR_SAFE_VAL;
3353 case SYS_REVIDR_EL1:
3354 /* IMPLEMENTATION DEFINED values are emulated with 0 */
3364 static int emulate_sys_reg(u32 id, u64 *valp)
3366 struct arm64_ftr_reg *regp;
3368 if (!is_emulated(id))
3371 if (sys_reg_CRm(id) == 0)
3372 return emulate_id_reg(id, valp);
3374 regp = get_arm64_ftr_reg_nowarn(id);
3376 *valp = arm64_ftr_reg_user_value(regp);
3379 * The untracked registers are either IMPLEMENTATION DEFINED
3380 * (e.g, ID_AFR0_EL1) or reserved RAZ.
3386 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3391 rc = emulate_sys_reg(sys_reg, &val);
3393 pt_regs_write_reg(regs, rt, val);
3394 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3399 static int emulate_mrs(struct pt_regs *regs, u32 insn)
3404 * sys_reg values are defined as used in mrs/msr instruction.
3405 * shift the imm value to get the encoding.
3407 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3408 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3409 return do_emulate_mrs(regs, sys_reg, rt);
3412 static struct undef_hook mrs_hook = {
3413 .instr_mask = 0xffff0000,
3414 .instr_val = 0xd5380000,
3415 .pstate_mask = PSR_AA32_MODE_MASK,
3416 .pstate_val = PSR_MODE_EL0t,
3420 static int __init enable_mrs_emulation(void)
3422 register_undef_hook(&mrs_hook);
3426 core_initcall(enable_mrs_emulation);
3428 enum mitigation_state arm64_get_meltdown_state(void)
3430 if (__meltdown_safe)
3431 return SPECTRE_UNAFFECTED;
3433 if (arm64_kernel_unmapped_at_el0())
3434 return SPECTRE_MITIGATED;
3436 return SPECTRE_VULNERABLE;
3439 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3442 switch (arm64_get_meltdown_state()) {
3443 case SPECTRE_UNAFFECTED:
3444 return sprintf(buf, "Not affected\n");
3446 case SPECTRE_MITIGATED:
3447 return sprintf(buf, "Mitigation: PTI\n");
3450 return sprintf(buf, "Vulnerable\n");