arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/sort.h>
  24 #include <linux/stop_machine.h>
  25 #include <linux/types.h>
  26 #include <linux/mm.h>
  27 #include <asm/cpu.h>
  28 #include <asm/cpufeature.h>
  29 #include <asm/cpu_ops.h>
  30 #include <asm/mmu_context.h>
  31 #include <asm/processor.h>
  32 #include <asm/sysreg.h>
  33 #include <asm/traps.h>
  34 #include <asm/virt.h>
  35
  36 unsigned long elf_hwcap __read_mostly;
  37 EXPORT_SYMBOL_GPL(elf_hwcap);
  38
  39 #ifdef CONFIG_COMPAT
  40 #define COMPAT_ELF_HWCAP_DEFAULT        \
  41                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  42                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  43                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  44                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  45                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  46                                  COMPAT_HWCAP_LPAE)
  47 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  48 unsigned int compat_elf_hwcap2 __read_mostly;
  49 #endif
  50
  51 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  52 EXPORT_SYMBOL(cpu_hwcaps);
  53
  54 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  55 {
  56         /* file-wide pr_fmt adds "CPU features: " prefix */
  57         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  58         return 0;
  59 }
  60
  61 static struct notifier_block cpu_hwcaps_notifier = {
  62         .notifier_call = dump_cpu_hwcaps
  63 };
  64
  65 static int __init register_cpu_hwcaps_dumper(void)
  66 {
  67         atomic_notifier_chain_register(&panic_notifier_list,
  68                                        &cpu_hwcaps_notifier);
  69         return 0;
  70 }
  71 __initcall(register_cpu_hwcaps_dumper);
  72
  73 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  74 EXPORT_SYMBOL(cpu_hwcap_keys);
  75
  76 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  77         {                                               \
  78                 .sign = SIGNED,                         \
  79                 .visible = VISIBLE,                     \
  80                 .strict = STRICT,                       \
  81                 .type = TYPE,                           \
  82                 .shift = SHIFT,                         \
  83                 .width = WIDTH,                         \
  84                 .safe_val = SAFE_VAL,                   \
  85         }
  86
  87 /* Define a feature with unsigned values */
  88 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  89         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  90
  91 /* Define a feature with a signed value */
  92 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  93         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  94
  95 #define ARM64_FTR_END                                   \
  96         {                                               \
  97                 .width = 0,                             \
  98         }
  99
 100 /* meta feature for alternatives */
 101 static bool __maybe_unused
 102 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 103
 104
 105 /*
 106  * NOTE: Any changes to the visibility of features should be kept in
 107  * sync with the documentation of the CPU feature register ABI.
 108  */
 109 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 110         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 111         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 112         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 113         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 114         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 115         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 116         ARM64_FTR_END,
 117 };
 118
 119 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 120         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 121         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 122         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 124         ARM64_FTR_END,
 125 };
 126
 127 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 128         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 130         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 131         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 132         /* Linux doesn't care about the EL3 */
 133         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 135         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 136         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 137         ARM64_FTR_END,
 138 };
 139
 140 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 141         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 142         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 143         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 144         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 145         /* Linux shouldn't care about secure memory */
 146         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 147         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 148         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 149         /*
 150          * Differing PARange is fine as long as all peripherals and memory are mapped
 151          * within the minimum PARange of all CPUs
 152          */
 153         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 154         ARM64_FTR_END,
 155 };
 156
 157 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 158         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 159         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 160         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 161         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 162         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 163         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 164         ARM64_FTR_END,
 165 };
 166
 167 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 168         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 169         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 170         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 171         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 172         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 173         ARM64_FTR_END,
 174 };
 175
 176 static const struct arm64_ftr_bits ftr_ctr[] = {
 177         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1),   /* RAO */
 178         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),     /* CWG */
 179         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),      /* ERG */
 180         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),      /* DminLine */
 181         /*
 182          * Linux can handle differing I-cache policies. Userspace JITs will
 183          * make use of *minLine.
 184          * If we have differing I-cache policies, report it as the weakest - VIPT.
 185          */
 186         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 187         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* IminLine */
 188         ARM64_FTR_END,
 189 };
 190
 191 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 192         .name           = "SYS_CTR_EL0",
 193         .ftr_bits       = ftr_ctr
 194 };
 195
 196 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 197         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 28, 4, 0xf),        /* InnerShr */
 198         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 24, 4, 0),    /* FCSE */
 199         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 200         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 16, 4, 0),    /* TCM */
 201         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0),    /* ShareLvl */
 202         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0xf), /* OuterShr */
 203         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0),     /* PMSA */
 204         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0),     /* VMSA */
 205         ARM64_FTR_END,
 206 };
 207
 208 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 209         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 210         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 211         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 212         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 213         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 214         /*
 215          * We can instantiate multiple PMU instances with different levels
 216          * of support.
 217          */
 218         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 221         ARM64_FTR_END,
 222 };
 223
 224 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 225         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0),             /* FPMisc */
 226         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0),             /* SIMDMisc */
 227         ARM64_FTR_END,
 228 };
 229
 230 static const struct arm64_ftr_bits ftr_dczid[] = {
 231         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 232         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 233         ARM64_FTR_END,
 234 };
 235
 236
 237 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 238         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_RDM_SHIFT, 4, 0),
 239         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_CRC32_SHIFT, 4, 0),
 240         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA2_SHIFT, 4, 0),
 241         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SHA1_SHIFT, 4, 0),
 242         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_AES_SHIFT, 4, 0),
 243         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_ISAR5_SEVL_SHIFT, 4, 0),
 244         ARM64_FTR_END,
 245 };
 246
 247 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 248         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0),             /* ac2 */
 249         ARM64_FTR_END,
 250 };
 251
 252 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 253         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 12, 4, 0),    /* State3 */
 254         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 8, 4, 0),             /* State2 */
 255         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 4, 4, 0),             /* State1 */
 256         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 4, 0),             /* State0 */
 257         ARM64_FTR_END,
 258 };
 259
 260 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 261         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 262         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 264         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 265         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 266         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 267         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 268         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 269         ARM64_FTR_END,
 270 };
 271
 272 /*
 273  * Common ftr bits for a 32bit register with all hidden, strict
 274  * attributes, with 4bit feature fields and a default safe value of
 275  * 0. Covers the following 32bit registers:
 276  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 277  */
 278 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 279         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 280         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 281         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 282         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 283         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 284         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 285         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 286         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 287         ARM64_FTR_END,
 288 };
 289
 290 /* Table for a single 32bit feature value */
 291 static const struct arm64_ftr_bits ftr_single32[] = {
 292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 293         ARM64_FTR_END,
 294 };
 295
 296 static const struct arm64_ftr_bits ftr_raz[] = {
 297         ARM64_FTR_END,
 298 };
 299
 300 #define ARM64_FTR_REG(id, table) {              \
 301         .sys_id = id,                           \
 302         .reg =  &(struct arm64_ftr_reg){        \
 303                 .name = #id,                    \
 304                 .ftr_bits = &((table)[0]),      \
 305         }}
 306
 307 static const struct __ftr_reg_entry {
 308         u32                     sys_id;
 309         struct arm64_ftr_reg    *reg;
 310 } arm64_ftr_regs[] = {
 311
 312         /* Op1 = 0, CRn = 0, CRm = 1 */
 313         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 314         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 315         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 316         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 317         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 318         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 319         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 320
 321         /* Op1 = 0, CRn = 0, CRm = 2 */
 322         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 323         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 324         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 325         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 326         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 327         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 328         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 329
 330         /* Op1 = 0, CRn = 0, CRm = 3 */
 331         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 332         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 333         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 334
 335         /* Op1 = 0, CRn = 0, CRm = 4 */
 336         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 337         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
 338
 339         /* Op1 = 0, CRn = 0, CRm = 5 */
 340         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 341         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 342
 343         /* Op1 = 0, CRn = 0, CRm = 6 */
 344         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 345         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 346
 347         /* Op1 = 0, CRn = 0, CRm = 7 */
 348         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 349         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 350         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 351
 352         /* Op1 = 3, CRn = 0, CRm = 0 */
 353         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 354         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 355
 356         /* Op1 = 3, CRn = 14, CRm = 0 */
 357         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 358 };
 359
 360 static int search_cmp_ftr_reg(const void *id, const void *regp)
 361 {
 362         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 363 }
 364
 365 /*
 366  * get_arm64_ftr_reg - Lookup a feature register entry using its
 367  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 368  * ascending order of sys_id , we use binary search to find a matching
 369  * entry.
 370  *
 371  * returns - Upon success,  matching ftr_reg entry for id.
 372  *         - NULL on failure. It is upto the caller to decide
 373  *           the impact of a failure.
 374  */
 375 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 376 {
 377         const struct __ftr_reg_entry *ret;
 378
 379         ret = bsearch((const void *)(unsigned long)sys_id,
 380                         arm64_ftr_regs,
 381                         ARRAY_SIZE(arm64_ftr_regs),
 382                         sizeof(arm64_ftr_regs[0]),
 383                         search_cmp_ftr_reg);
 384         if (ret)
 385                 return ret->reg;
 386         return NULL;
 387 }
 388
 389 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 390                                s64 ftr_val)
 391 {
 392         u64 mask = arm64_ftr_mask(ftrp);
 393
 394         reg &= ~mask;
 395         reg |= (ftr_val << ftrp->shift) & mask;
 396         return reg;
 397 }
 398
 399 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 400                                 s64 cur)
 401 {
 402         s64 ret = 0;
 403
 404         switch (ftrp->type) {
 405         case FTR_EXACT:
 406                 ret = ftrp->safe_val;
 407                 break;
 408         case FTR_LOWER_SAFE:
 409                 ret = new < cur ? new : cur;
 410                 break;
 411         case FTR_HIGHER_SAFE:
 412                 ret = new > cur ? new : cur;
 413                 break;
 414         default:
 415                 BUG();
 416         }
 417
 418         return ret;
 419 }
 420
 421 static void __init sort_ftr_regs(void)
 422 {
 423         int i;
 424
 425         /* Check that the array is sorted so that we can do the binary search */
 426         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 427                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 428 }
 429
 430 /*
 431  * Initialise the CPU feature register from Boot CPU values.
 432  * Also initiliases the strict_mask for the register.
 433  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 434  * RES0 for the system-wide value, and must strictly match.
 435  */
 436 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 437 {
 438         u64 val = 0;
 439         u64 strict_mask = ~0x0ULL;
 440         u64 user_mask = 0;
 441         u64 valid_mask = 0;
 442
 443         const struct arm64_ftr_bits *ftrp;
 444         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 445
 446         BUG_ON(!reg);
 447
 448         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 449                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 450                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 451
 452                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 453
 454                 valid_mask |= ftr_mask;
 455                 if (!ftrp->strict)
 456                         strict_mask &= ~ftr_mask;
 457                 if (ftrp->visible)
 458                         user_mask |= ftr_mask;
 459                 else
 460                         reg->user_val = arm64_ftr_set_value(ftrp,
 461                                                             reg->user_val,
 462                                                             ftrp->safe_val);
 463         }
 464
 465         val &= valid_mask;
 466
 467         reg->sys_val = val;
 468         reg->strict_mask = strict_mask;
 469         reg->user_mask = user_mask;
 470 }
 471
 472 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 473 {
 474         /* Before we start using the tables, make sure it is sorted */
 475         sort_ftr_regs();
 476
 477         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 478         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 479         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 480         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 481         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 482         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 483         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 484         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 485         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 486         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 487         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 488         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 489
 490         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 491                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 492                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 493                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 494                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 495                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 496                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 497                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 498                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 499                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 500                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 501                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 502                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 503                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 504                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 505                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 506                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 507         }
 508
 509 }
 510
 511 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 512 {
 513         const struct arm64_ftr_bits *ftrp;
 514
 515         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 516                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 517                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 518
 519                 if (ftr_cur == ftr_new)
 520                         continue;
 521                 /* Find a safe value */
 522                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 523                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 524         }
 525
 526 }
 527
 528 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 529 {
 530         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 531
 532         BUG_ON(!regp);
 533         update_cpu_ftr_reg(regp, val);
 534         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 535                 return 0;
 536         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 537                         regp->name, boot, cpu, val);
 538         return 1;
 539 }
 540
 541 /*
 542  * Update system wide CPU feature registers with the values from a
 543  * non-boot CPU. Also performs SANITY checks to make sure that there
 544  * aren't any insane variations from that of the boot CPU.
 545  */
 546 void update_cpu_features(int cpu,
 547                          struct cpuinfo_arm64 *info,
 548                          struct cpuinfo_arm64 *boot)
 549 {
 550         int taint = 0;
 551
 552         /*
 553          * The kernel can handle differing I-cache policies, but otherwise
 554          * caches should look identical. Userspace JITs will make use of
 555          * *minLine.
 556          */
 557         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 558                                       info->reg_ctr, boot->reg_ctr);
 559
 560         /*
 561          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 562          * could result in too much or too little memory being zeroed if a
 563          * process is preempted and migrated between CPUs.
 564          */
 565         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 566                                       info->reg_dczid, boot->reg_dczid);
 567
 568         /* If different, timekeeping will be broken (especially with KVM) */
 569         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 570                                       info->reg_cntfrq, boot->reg_cntfrq);
 571
 572         /*
 573          * The kernel uses self-hosted debug features and expects CPUs to
 574          * support identical debug features. We presently need CTX_CMPs, WRPs,
 575          * and BRPs to be identical.
 576          * ID_AA64DFR1 is currently RES0.
 577          */
 578         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 579                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 580         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 581                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 582         /*
 583          * Even in big.LITTLE, processors should be identical instruction-set
 584          * wise.
 585          */
 586         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 587                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 588         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 589                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 590
 591         /*
 592          * Differing PARange support is fine as long as all peripherals and
 593          * memory are mapped within the minimum PARange of all CPUs.
 594          * Linux should not care about secure memory.
 595          */
 596         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 597                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 598         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 599                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 600         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 601                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 602
 603         /*
 604          * EL3 is not our concern.
 605          * ID_AA64PFR1 is currently RES0.
 606          */
 607         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 608                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 609         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 610                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 611
 612         /*
 613          * If we have AArch32, we care about 32-bit features for compat.
 614          * If the system doesn't support AArch32, don't update them.
 615          */
 616         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 617                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 618
 619                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 620                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 621                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 622                                         info->reg_id_isar0, boot->reg_id_isar0);
 623                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 624                                         info->reg_id_isar1, boot->reg_id_isar1);
 625                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 626                                         info->reg_id_isar2, boot->reg_id_isar2);
 627                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 628                                         info->reg_id_isar3, boot->reg_id_isar3);
 629                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 630                                         info->reg_id_isar4, boot->reg_id_isar4);
 631                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 632                                         info->reg_id_isar5, boot->reg_id_isar5);
 633
 634                 /*
 635                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 636                  * ACTLR formats could differ across CPUs and therefore would have to
 637                  * be trapped for virtualization anyway.
 638                  */
 639                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 640                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 641                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 642                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 643                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 644                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 645                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 646                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 647                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 648                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 649                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 650                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 651                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 652                                         info->reg_mvfr0, boot->reg_mvfr0);
 653                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 654                                         info->reg_mvfr1, boot->reg_mvfr1);
 655                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 656                                         info->reg_mvfr2, boot->reg_mvfr2);
 657         }
 658
 659         /*
 660          * Mismatched CPU features are a recipe for disaster. Don't even
 661          * pretend to support them.
 662          */
 663         if (taint) {
 664                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 665                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 666         }
 667 }
 668
 669 u64 read_sanitised_ftr_reg(u32 id)
 670 {
 671         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 672
 673         /* We shouldn't get a request for an unsupported register */
 674         BUG_ON(!regp);
 675         return regp->sys_val;
 676 }
 677
 678 #define read_sysreg_case(r)     \
 679         case r:         return read_sysreg_s(r)
 680
 681 /*
 682  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 683  * Read the system register on the current CPU
 684  */
 685 static u64 __read_sysreg_by_encoding(u32 sys_id)
 686 {
 687         switch (sys_id) {
 688         read_sysreg_case(SYS_ID_PFR0_EL1);
 689         read_sysreg_case(SYS_ID_PFR1_EL1);
 690         read_sysreg_case(SYS_ID_DFR0_EL1);
 691         read_sysreg_case(SYS_ID_MMFR0_EL1);
 692         read_sysreg_case(SYS_ID_MMFR1_EL1);
 693         read_sysreg_case(SYS_ID_MMFR2_EL1);
 694         read_sysreg_case(SYS_ID_MMFR3_EL1);
 695         read_sysreg_case(SYS_ID_ISAR0_EL1);
 696         read_sysreg_case(SYS_ID_ISAR1_EL1);
 697         read_sysreg_case(SYS_ID_ISAR2_EL1);
 698         read_sysreg_case(SYS_ID_ISAR3_EL1);
 699         read_sysreg_case(SYS_ID_ISAR4_EL1);
 700         read_sysreg_case(SYS_ID_ISAR5_EL1);
 701         read_sysreg_case(SYS_MVFR0_EL1);
 702         read_sysreg_case(SYS_MVFR1_EL1);
 703         read_sysreg_case(SYS_MVFR2_EL1);
 704
 705         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 706         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 707         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 708         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 709         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 710         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 711         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 712         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 713         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 714
 715         read_sysreg_case(SYS_CNTFRQ_EL0);
 716         read_sysreg_case(SYS_CTR_EL0);
 717         read_sysreg_case(SYS_DCZID_EL0);
 718
 719         default:
 720                 BUG();
 721                 return 0;
 722         }
 723 }
 724
 725 #include <linux/irqchip/arm-gic-v3.h>
 726
 727 static bool
 728 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 729 {
 730         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 731
 732         return val >= entry->min_field_value;
 733 }
 734
 735 static bool
 736 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 737 {
 738         u64 val;
 739
 740         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 741         if (scope == SCOPE_SYSTEM)
 742                 val = read_sanitised_ftr_reg(entry->sys_reg);
 743         else
 744                 val = __read_sysreg_by_encoding(entry->sys_reg);
 745
 746         return feature_matches(val, entry);
 747 }
 748
 749 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 750 {
 751         bool has_sre;
 752
 753         if (!has_cpuid_feature(entry, scope))
 754                 return false;
 755
 756         has_sre = gic_enable_sre();
 757         if (!has_sre)
 758                 pr_warn_once("%s present but disabled by higher exception level\n",
 759                              entry->desc);
 760
 761         return has_sre;
 762 }
 763
 764 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 765 {
 766         u32 midr = read_cpuid_id();
 767
 768         /* Cavium ThunderX pass 1.x and 2.x */
 769         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
 770                 MIDR_CPU_VAR_REV(0, 0),
 771                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 772 }
 773
 774 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
 775 {
 776         return is_kernel_in_hyp_mode();
 777 }
 778
 779 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
 780                            int __unused)
 781 {
 782         phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
 783
 784         /*
 785          * Activate the lower HYP offset only if:
 786          * - the idmap doesn't clash with it,
 787          * - the kernel is not running at EL2.
 788          */
 789         return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
 790 }
 791
 792 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 793 {
 794         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 795
 796         return cpuid_feature_extract_signed_field(pfr0,
 797                                         ID_AA64PFR0_FP_SHIFT) < 0;
 798 }
 799
 800 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 801 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 802
 803 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 804                                 int __unused)
 805 {
 806         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 807
 808         /* Forced on command line? */
 809         if (__kpti_forced) {
 810                 pr_info_once("kernel page table isolation forced %s by command line option\n",
 811                              __kpti_forced > 0 ? "ON" : "OFF");
 812                 return __kpti_forced > 0;
 813         }
 814
 815         /* Useful for KASLR robustness */
 816         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
 817                 return true;
 818
 819         /* Defer to CPU feature registers */
 820         return !cpuid_feature_extract_unsigned_field(pfr0,
 821                                                      ID_AA64PFR0_CSV3_SHIFT);
 822 }
 823
 824 static int __init parse_kpti(char *str)
 825 {
 826         bool enabled;
 827         int ret = strtobool(str, &enabled);
 828
 829         if (ret)
 830                 return ret;
 831
 832         __kpti_forced = enabled ? 1 : -1;
 833         return 0;
 834 }
 835 __setup("kpti=", parse_kpti);
 836 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
 837
 838 static const struct arm64_cpu_capabilities arm64_features[] = {
 839         {
 840                 .desc = "GIC system register CPU interface",
 841                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 842                 .def_scope = SCOPE_SYSTEM,
 843                 .matches = has_useable_gicv3_cpuif,
 844                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 845                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 846                 .sign = FTR_UNSIGNED,
 847                 .min_field_value = 1,
 848         },
 849 #ifdef CONFIG_ARM64_PAN
 850         {
 851                 .desc = "Privileged Access Never",
 852                 .capability = ARM64_HAS_PAN,
 853                 .def_scope = SCOPE_SYSTEM,
 854                 .matches = has_cpuid_feature,
 855                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 856                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 857                 .sign = FTR_UNSIGNED,
 858                 .min_field_value = 1,
 859                 .enable = cpu_enable_pan,
 860         },
 861 #endif /* CONFIG_ARM64_PAN */
 862 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 863         {
 864                 .desc = "LSE atomic instructions",
 865                 .capability = ARM64_HAS_LSE_ATOMICS,
 866                 .def_scope = SCOPE_SYSTEM,
 867                 .matches = has_cpuid_feature,
 868                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 869                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 870                 .sign = FTR_UNSIGNED,
 871                 .min_field_value = 2,
 872         },
 873 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 874         {
 875                 .desc = "Software prefetching using PRFM",
 876                 .capability = ARM64_HAS_NO_HW_PREFETCH,
 877                 .def_scope = SCOPE_SYSTEM,
 878                 .matches = has_no_hw_prefetch,
 879         },
 880 #ifdef CONFIG_ARM64_UAO
 881         {
 882                 .desc = "User Access Override",
 883                 .capability = ARM64_HAS_UAO,
 884                 .def_scope = SCOPE_SYSTEM,
 885                 .matches = has_cpuid_feature,
 886                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
 887                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
 888                 .min_field_value = 1,
 889                 /*
 890                  * We rely on stop_machine() calling uao_thread_switch() to set
 891                  * UAO immediately after patching.
 892                  */
 893         },
 894 #endif /* CONFIG_ARM64_UAO */
 895 #ifdef CONFIG_ARM64_PAN
 896         {
 897                 .capability = ARM64_ALT_PAN_NOT_UAO,
 898                 .def_scope = SCOPE_SYSTEM,
 899                 .matches = cpufeature_pan_not_uao,
 900         },
 901 #endif /* CONFIG_ARM64_PAN */
 902         {
 903                 .desc = "Virtualization Host Extensions",
 904                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
 905                 .def_scope = SCOPE_SYSTEM,
 906                 .matches = runs_at_el2,
 907         },
 908         {
 909                 .desc = "32-bit EL0 Support",
 910                 .capability = ARM64_HAS_32BIT_EL0,
 911                 .def_scope = SCOPE_SYSTEM,
 912                 .matches = has_cpuid_feature,
 913                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 914                 .sign = FTR_UNSIGNED,
 915                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
 916                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
 917         },
 918         {
 919                 .desc = "Reduced HYP mapping offset",
 920                 .capability = ARM64_HYP_OFFSET_LOW,
 921                 .def_scope = SCOPE_SYSTEM,
 922                 .matches = hyp_offset_low,
 923         },
 924 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 925         {
 926                 .desc = "Kernel page table isolation (KPTI)",
 927                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
 928                 .def_scope = SCOPE_SYSTEM,
 929                 .matches = unmap_kernel_at_el0,
 930         },
 931 #endif
 932         {
 933                 /* FP/SIMD is not implemented */
 934                 .capability = ARM64_HAS_NO_FPSIMD,
 935                 .def_scope = SCOPE_SYSTEM,
 936                 .min_field_value = 0,
 937                 .matches = has_no_fpsimd,
 938         },
 939 #ifdef CONFIG_ARM64_PMEM
 940         {
 941                 .desc = "Data cache clean to Point of Persistence",
 942                 .capability = ARM64_HAS_DCPOP,
 943                 .def_scope = SCOPE_SYSTEM,
 944                 .matches = has_cpuid_feature,
 945                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
 946                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
 947                 .min_field_value = 1,
 948         },
 949 #endif
 950         {},
 951 };
 952
 953 #define HWCAP_CAP(reg, field, s, min_value, type, cap)  \
 954         {                                                       \
 955                 .desc = #cap,                                   \
 956                 .def_scope = SCOPE_SYSTEM,                      \
 957                 .matches = has_cpuid_feature,                   \
 958                 .sys_reg = reg,                                 \
 959                 .field_pos = field,                             \
 960                 .sign = s,                                      \
 961                 .min_field_value = min_value,                   \
 962                 .hwcap_type = type,                             \
 963                 .hwcap = cap,                                   \
 964         }
 965
 966 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 967         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
 968         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
 969         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
 970         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
 971         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
 972         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
 973         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
 974         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
 975         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
 976         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
 977         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
 978         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
 979         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
 980         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
 981         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
 982         {},
 983 };
 984
 985 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
 986 #ifdef CONFIG_COMPAT
 987         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
 988         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
 989         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
 990         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
 991         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 992 #endif
 993         {},
 994 };
 995
 996 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
 997 {
 998         switch (cap->hwcap_type) {
 999         case CAP_HWCAP:
1000                 elf_hwcap |= cap->hwcap;
1001                 break;
1002 #ifdef CONFIG_COMPAT
1003         case CAP_COMPAT_HWCAP:
1004                 compat_elf_hwcap |= (u32)cap->hwcap;
1005                 break;
1006         case CAP_COMPAT_HWCAP2:
1007                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1008                 break;
1009 #endif
1010         default:
1011                 WARN_ON(1);
1012                 break;
1013         }
1014 }
1015
1016 /* Check if we have a particular HWCAP enabled */
1017 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1018 {
1019         bool rc;
1020
1021         switch (cap->hwcap_type) {
1022         case CAP_HWCAP:
1023                 rc = (elf_hwcap & cap->hwcap) != 0;
1024                 break;
1025 #ifdef CONFIG_COMPAT
1026         case CAP_COMPAT_HWCAP:
1027                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1028                 break;
1029         case CAP_COMPAT_HWCAP2:
1030                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1031                 break;
1032 #endif
1033         default:
1034                 WARN_ON(1);
1035                 rc = false;
1036         }
1037
1038         return rc;
1039 }
1040
1041 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1042 {
1043         /* We support emulation of accesses to CPU ID feature registers */
1044         elf_hwcap |= HWCAP_CPUID;
1045         for (; hwcaps->matches; hwcaps++)
1046                 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
1047                         cap_set_elf_hwcap(hwcaps);
1048 }
1049
1050 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1051                             const char *info)
1052 {
1053         for (; caps->matches; caps++) {
1054                 if (!caps->matches(caps, caps->def_scope))
1055                         continue;
1056
1057                 if (!cpus_have_cap(caps->capability) && caps->desc)
1058                         pr_info("%s %s\n", info, caps->desc);
1059                 cpus_set_cap(caps->capability);
1060         }
1061 }
1062
1063 /*
1064  * Run through the enabled capabilities and enable() it on all active
1065  * CPUs
1066  */
1067 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
1068 {
1069         for (; caps->matches; caps++) {
1070                 unsigned int num = caps->capability;
1071
1072                 if (!cpus_have_cap(num))
1073                         continue;
1074
1075                 /* Ensure cpus_have_const_cap(num) works */
1076                 static_branch_enable(&cpu_hwcap_keys[num]);
1077
1078                 if (caps->enable) {
1079                         /*
1080                          * Use stop_machine() as it schedules the work allowing
1081                          * us to modify PSTATE, instead of on_each_cpu() which
1082                          * uses an IPI, giving us a PSTATE that disappears when
1083                          * we return.
1084                          */
1085                         stop_machine(caps->enable, NULL, cpu_online_mask);
1086                 }
1087         }
1088 }
1089
1090 /*
1091  * Flag to indicate if we have computed the system wide
1092  * capabilities based on the boot time active CPUs. This
1093  * will be used to determine if a new booting CPU should
1094  * go through the verification process to make sure that it
1095  * supports the system capabilities, without using a hotplug
1096  * notifier.
1097  */
1098 static bool sys_caps_initialised;
1099
1100 static inline void set_sys_caps_initialised(void)
1101 {
1102         sys_caps_initialised = true;
1103 }
1104
1105 /*
1106  * Check for CPU features that are used in early boot
1107  * based on the Boot CPU value.
1108  */
1109 static void check_early_cpu_features(void)
1110 {
1111         verify_cpu_run_el();
1112         verify_cpu_asid_bits();
1113 }
1114
1115 static void
1116 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1117 {
1118
1119         for (; caps->matches; caps++)
1120                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1121                         pr_crit("CPU%d: missing HWCAP: %s\n",
1122                                         smp_processor_id(), caps->desc);
1123                         cpu_die_early();
1124                 }
1125 }
1126
1127 static void
1128 verify_local_cpu_features(const struct arm64_cpu_capabilities *caps)
1129 {
1130         for (; caps->matches; caps++) {
1131                 if (!cpus_have_cap(caps->capability))
1132                         continue;
1133                 /*
1134                  * If the new CPU misses an advertised feature, we cannot proceed
1135                  * further, park the cpu.
1136                  */
1137                 if (!caps->matches(caps, SCOPE_LOCAL_CPU)) {
1138                         pr_crit("CPU%d: missing feature: %s\n",
1139                                         smp_processor_id(), caps->desc);
1140                         cpu_die_early();
1141                 }
1142                 if (caps->enable)
1143                         caps->enable(NULL);
1144         }
1145 }
1146
1147 /*
1148  * Run through the enabled system capabilities and enable() it on this CPU.
1149  * The capabilities were decided based on the available CPUs at the boot time.
1150  * Any new CPU should match the system wide status of the capability. If the
1151  * new CPU doesn't have a capability which the system now has enabled, we
1152  * cannot do anything to fix it up and could cause unexpected failures. So
1153  * we park the CPU.
1154  */
1155 static void verify_local_cpu_capabilities(void)
1156 {
1157         verify_local_cpu_errata_workarounds();
1158         verify_local_cpu_features(arm64_features);
1159         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1160         if (system_supports_32bit_el0())
1161                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1162 }
1163
1164 void check_local_cpu_capabilities(void)
1165 {
1166         /*
1167          * All secondary CPUs should conform to the early CPU features
1168          * in use by the kernel based on boot CPU.
1169          */
1170         check_early_cpu_features();
1171
1172         /*
1173          * If we haven't finalised the system capabilities, this CPU gets
1174          * a chance to update the errata work arounds.
1175          * Otherwise, this CPU should verify that it has all the system
1176          * advertised capabilities.
1177          */
1178         if (!sys_caps_initialised)
1179                 update_cpu_errata_workarounds();
1180         else
1181                 verify_local_cpu_capabilities();
1182 }
1183
1184 static void __init setup_feature_capabilities(void)
1185 {
1186         update_cpu_capabilities(arm64_features, "detected feature:");
1187         enable_cpu_capabilities(arm64_features);
1188 }
1189
1190 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1191 EXPORT_SYMBOL(arm64_const_caps_ready);
1192
1193 static void __init mark_const_caps_ready(void)
1194 {
1195         static_branch_enable(&arm64_const_caps_ready);
1196 }
1197
1198 /*
1199  * Check if the current CPU has a given feature capability.
1200  * Should be called from non-preemptible context.
1201  */
1202 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1203                                unsigned int cap)
1204 {
1205         const struct arm64_cpu_capabilities *caps;
1206
1207         if (WARN_ON(preemptible()))
1208                 return false;
1209
1210         for (caps = cap_array; caps->desc; caps++)
1211                 if (caps->capability == cap && caps->matches)
1212                         return caps->matches(caps, SCOPE_LOCAL_CPU);
1213
1214         return false;
1215 }
1216
1217 extern const struct arm64_cpu_capabilities arm64_errata[];
1218
1219 bool this_cpu_has_cap(unsigned int cap)
1220 {
1221         return (__this_cpu_has_cap(arm64_features, cap) ||
1222                 __this_cpu_has_cap(arm64_errata, cap));
1223 }
1224
1225 void __init setup_cpu_features(void)
1226 {
1227         u32 cwg;
1228         int cls;
1229
1230         /* Set the CPU feature capabilies */
1231         setup_feature_capabilities();
1232         enable_errata_workarounds();
1233         mark_const_caps_ready();
1234         setup_elf_hwcaps(arm64_elf_hwcaps);
1235
1236         if (system_supports_32bit_el0())
1237                 setup_elf_hwcaps(compat_elf_hwcaps);
1238
1239         /* Advertise that we have computed the system capabilities */
1240         set_sys_caps_initialised();
1241
1242         /*
1243          * Check for sane CTR_EL0.CWG value.
1244          */
1245         cwg = cache_type_cwg();
1246         cls = cache_line_size();
1247         if (!cwg)
1248                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1249                         cls);
1250         if (L1_CACHE_BYTES < cls)
1251                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1252                         L1_CACHE_BYTES, cls);
1253 }
1254
1255 static bool __maybe_unused
1256 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1257 {
1258         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1259 }
1260
1261 /*
1262  * We emulate only the following system register space.
1263  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1264  * See Table C5-6 System instruction encodings for System register accesses,
1265  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1266  */
1267 static inline bool __attribute_const__ is_emulated(u32 id)
1268 {
1269         return (sys_reg_Op0(id) == 0x3 &&
1270                 sys_reg_CRn(id) == 0x0 &&
1271                 sys_reg_Op1(id) == 0x0 &&
1272                 (sys_reg_CRm(id) == 0 ||
1273                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1274 }
1275
1276 /*
1277  * With CRm == 0, reg should be one of :
1278  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1279  */
1280 static inline int emulate_id_reg(u32 id, u64 *valp)
1281 {
1282         switch (id) {
1283         case SYS_MIDR_EL1:
1284                 *valp = read_cpuid_id();
1285                 break;
1286         case SYS_MPIDR_EL1:
1287                 *valp = SYS_MPIDR_SAFE_VAL;
1288                 break;
1289         case SYS_REVIDR_EL1:
1290                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1291                 *valp = 0;
1292                 break;
1293         default:
1294                 return -EINVAL;
1295         }
1296
1297         return 0;
1298 }
1299
1300 static int emulate_sys_reg(u32 id, u64 *valp)
1301 {
1302         struct arm64_ftr_reg *regp;
1303
1304         if (!is_emulated(id))
1305                 return -EINVAL;
1306
1307         if (sys_reg_CRm(id) == 0)
1308                 return emulate_id_reg(id, valp);
1309
1310         regp = get_arm64_ftr_reg(id);
1311         if (regp)
1312                 *valp = arm64_ftr_reg_user_value(regp);
1313         else
1314                 /*
1315                  * The untracked registers are either IMPLEMENTATION DEFINED
1316                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
1317                  */
1318                 *valp = 0;
1319         return 0;
1320 }
1321
1322 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1323 {
1324         int rc;
1325         u32 sys_reg, dst;
1326         u64 val;
1327
1328         /*
1329          * sys_reg values are defined as used in mrs/msr instruction.
1330          * shift the imm value to get the encoding.
1331          */
1332         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1333         rc = emulate_sys_reg(sys_reg, &val);
1334         if (!rc) {
1335                 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1336                 pt_regs_write_reg(regs, dst, val);
1337                 regs->pc += 4;
1338         }
1339
1340         return rc;
1341 }
1342
1343 static struct undef_hook mrs_hook = {
1344         .instr_mask = 0xfff00000,
1345         .instr_val  = 0xd5300000,
1346         .pstate_mask = COMPAT_PSR_MODE_MASK,
1347         .pstate_val = PSR_MODE_EL0t,
1348         .fn = emulate_mrs,
1349 };
1350
1351 static int __init enable_mrs_emulation(void)
1352 {
1353         register_undef_hook(&mrs_hook);
1354         return 0;
1355 }
1356
1357 core_initcall(enable_mrs_emulation);