1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
5 * Copyright (C) 2015 ARM Ltd.
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
29 * Some implementation details worth remembering:
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
63 #define pr_fmt(fmt) "CPU features: " fmt
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/kstrtox.h>
69 #include <linux/sort.h>
70 #include <linux/stop_machine.h>
71 #include <linux/sysfs.h>
72 #include <linux/types.h>
73 #include <linux/minmax.h>
75 #include <linux/cpu.h>
76 #include <linux/kasan.h>
77 #include <linux/percpu.h>
80 #include <asm/cpufeature.h>
81 #include <asm/cpu_ops.h>
82 #include <asm/fpsimd.h>
83 #include <asm/hwcap.h>
85 #include <asm/kvm_host.h>
86 #include <asm/mmu_context.h>
88 #include <asm/processor.h>
90 #include <asm/sysreg.h>
91 #include <asm/traps.h>
92 #include <asm/vectors.h>
95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly;
99 #define COMPAT_ELF_HWCAP_DEFAULT \
100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
105 unsigned int compat_elf_hwcap2 __read_mostly;
108 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
109 EXPORT_SYMBOL(cpu_hwcaps);
110 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
112 DECLARE_BITMAP(boot_capabilities, ARM64_NCAPS);
114 bool arm64_use_ng_mappings = false;
115 EXPORT_SYMBOL(arm64_use_ng_mappings);
117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
123 static bool __read_mostly allow_mismatched_32bit_el0;
126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
127 * seen at least one CPU capable of 32-bit EL0.
129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
132 * Mask of CPUs supporting 32-bit EL0.
133 * Only valid if arm64_mismatched_32bit_el0 is enabled.
135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
137 void dump_cpu_features(void)
139 /* file-wide pr_fmt adds "CPU features: " prefix */
140 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
143 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
146 .visible = VISIBLE, \
151 .safe_val = SAFE_VAL, \
154 /* Define a feature with unsigned values */
155 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
156 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
158 /* Define a feature with a signed value */
159 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
160 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
162 #define ARM64_FTR_END \
167 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
169 static bool __system_matches_cap(unsigned int n);
172 * NOTE: Any changes to the visibility of features should be kept in
173 * sync with the documentation of the CPU feature register ABI.
175 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
176 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0),
177 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0),
178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0),
179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0),
180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0),
181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0),
182 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0),
183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0),
184 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0),
185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0),
189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0),
193 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
201 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
203 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0),
204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0),
205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
208 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
210 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0),
215 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
220 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
221 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
222 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0),
228 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0),
231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0),
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
236 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0),
237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0),
238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0),
239 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI),
240 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI),
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY),
244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY),
248 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
249 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
250 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),
251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0),
252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0),
253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI),
255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI),
256 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
257 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0),
261 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
267 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
269 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0),
270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
271 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0),
272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0),
274 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
275 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0),
276 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
277 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0),
278 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
279 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0),
283 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
284 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
285 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0),
286 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
287 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0),
288 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
289 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0),
290 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
291 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0),
292 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
293 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0),
294 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
295 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0),
296 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
297 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0),
298 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
299 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0),
300 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
301 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0),
302 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
303 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0),
304 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
305 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0),
306 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME),
307 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0),
311 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
312 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0),
313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0),
314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0),
316 * Page size not being supported at Stage-2 is not fatal. You
317 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
318 * your favourite nesting hypervisor.
320 * There is a small corner case where the hypervisor explicitly
321 * advertises a given granule size at Stage-2 (value 2) on some
322 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
323 * vCPUs. Although this is not forbidden by the architecture, it
324 * indicates that the hypervisor is being silly (or buggy).
326 * We make no effort to cope with this and pretend that if these
327 * fields are inconsistent across vCPUs, then it isn't worth
328 * trying to bring KVM up.
330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1),
331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1),
332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1),
334 * We already refuse to boot CPUs that don't support our configured
335 * page size, so we can only detect mismatches for a page size other
336 * than the one we're currently using. Unfortunately, SoCs like this
337 * exist in the wild so, even though we don't like it, we'll have to go
338 * along with it and treat them as non-strict.
340 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI),
341 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI),
342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI),
344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0),
345 /* Linux shouldn't care about secure memory */
346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0),
350 * Differing PARange is fine as long as all peripherals and memory are mapped
351 * within the minimum PARange of all CPUs
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0),
357 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),
359 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),
360 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),
361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),
362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),
363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0),
364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0),
365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0),
366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0),
367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0),
368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0),
369 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0),
373 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0),
375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0),
376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0),
377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0),
378 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0),
379 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0),
380 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0),
381 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0),
382 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0),
383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0),
384 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0),
385 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0),
386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0),
387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0),
388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0),
392 static const struct arm64_ftr_bits ftr_ctr[] = {
393 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
394 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
395 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1),
396 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0),
397 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0),
398 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1),
400 * Linux can handle differing I-cache policies. Userspace JITs will
401 * make use of *minLine.
402 * If we have differing I-cache policies, report it as the weakest - VIPT.
404 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */
405 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0),
409 static struct arm64_ftr_override __ro_after_init no_override = { };
411 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
412 .name = "SYS_CTR_EL0",
414 .override = &no_override,
417 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
418 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf),
419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0),
420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0),
421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0),
422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0),
423 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf),
424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0),
425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0),
429 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
430 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0),
431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0),
432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0),
433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0),
434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0),
436 * We can instantiate multiple PMU instances with different levels
439 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0),
440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6),
444 static const struct arm64_ftr_bits ftr_mvfr0[] = {
445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0),
446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0),
447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0),
448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0),
449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0),
450 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0),
451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0),
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0),
456 static const struct arm64_ftr_bits ftr_mvfr1[] = {
457 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0),
458 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0),
459 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0),
460 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0),
461 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0),
462 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0),
463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0),
464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0),
468 static const struct arm64_ftr_bits ftr_mvfr2[] = {
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0),
474 static const struct arm64_ftr_bits ftr_dczid[] = {
475 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1),
476 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0),
480 static const struct arm64_ftr_bits ftr_gmid[] = {
481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0),
485 static const struct arm64_ftr_bits ftr_id_isar0[] = {
486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0),
487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0),
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0),
489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0),
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0),
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0),
492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0),
496 static const struct arm64_ftr_bits ftr_id_isar5[] = {
497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0),
498 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0),
499 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0),
500 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0),
501 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0),
506 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0),
508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0),
509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0),
510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0),
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0),
516 * SpecSEI = 1 indicates that the PE might generate an SError on an
517 * external abort on speculative read. It is safe to assume that an
518 * SError might be generated than it will not be. Hence it has been
519 * classified as FTR_HIGHER_SAFE.
521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0),
525 static const struct arm64_ftr_bits ftr_id_isar4[] = {
526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0),
527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0),
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0),
529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0),
530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0),
531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0),
532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0),
533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0),
537 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0),
542 static const struct arm64_ftr_bits ftr_id_isar6[] = {
543 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0),
544 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0),
545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0),
546 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0),
547 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0),
548 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0),
549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0),
553 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0),
555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0),
556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0),
557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0),
558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0),
559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0),
563 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
564 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0),
565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0),
566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0),
567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0),
568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0),
569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0),
570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0),
571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0),
575 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
576 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0),
577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0),
581 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
582 /* [31:28] TraceFilt */
583 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0),
584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0),
585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),
586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),
587 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0),
588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0),
589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0),
593 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
594 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0),
598 static const struct arm64_ftr_bits ftr_zcr[] = {
599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
600 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_WIDTH, 0), /* LEN */
604 static const struct arm64_ftr_bits ftr_smcr[] = {
605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
606 SMCR_ELx_LEN_SHIFT, SMCR_ELx_LEN_WIDTH, 0), /* LEN */
611 * Common ftr bits for a 32bit register with all hidden, strict
612 * attributes, with 4bit feature fields and a default safe value of
613 * 0. Covers the following 32bit registers:
614 * id_isar[1-3], id_mmfr[1-3]
616 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
621 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
628 /* Table for a single 32bit feature value */
629 static const struct arm64_ftr_bits ftr_single32[] = {
630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
634 static const struct arm64_ftr_bits ftr_raz[] = {
638 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \
640 .reg = &(struct arm64_ftr_reg){ \
643 .ftr_bits = &((table)[0]), \
646 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \
647 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
649 #define ARM64_FTR_REG(id, table) \
650 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
652 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
653 struct arm64_ftr_override __ro_after_init id_aa64pfr0_override;
654 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
655 struct arm64_ftr_override __ro_after_init id_aa64zfr0_override;
656 struct arm64_ftr_override __ro_after_init id_aa64smfr0_override;
657 struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
658 struct arm64_ftr_override __ro_after_init id_aa64isar2_override;
660 static const struct __ftr_reg_entry {
662 struct arm64_ftr_reg *reg;
663 } arm64_ftr_regs[] = {
665 /* Op1 = 0, CRn = 0, CRm = 1 */
666 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
667 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
668 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
669 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
670 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
671 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
672 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
674 /* Op1 = 0, CRn = 0, CRm = 2 */
675 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
676 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
677 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
678 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
679 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
680 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
681 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
682 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
684 /* Op1 = 0, CRn = 0, CRm = 3 */
685 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0),
686 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1),
687 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
688 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
689 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
690 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
692 /* Op1 = 0, CRn = 0, CRm = 4 */
693 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0,
694 &id_aa64pfr0_override),
695 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
696 &id_aa64pfr1_override),
697 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0,
698 &id_aa64zfr0_override),
699 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0,
700 &id_aa64smfr0_override),
702 /* Op1 = 0, CRn = 0, CRm = 5 */
703 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
704 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
706 /* Op1 = 0, CRn = 0, CRm = 6 */
707 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
708 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
709 &id_aa64isar1_override),
710 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2,
711 &id_aa64isar2_override),
713 /* Op1 = 0, CRn = 0, CRm = 7 */
714 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
715 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
716 &id_aa64mmfr1_override),
717 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
719 /* Op1 = 0, CRn = 1, CRm = 2 */
720 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
721 ARM64_FTR_REG(SYS_SMCR_EL1, ftr_smcr),
723 /* Op1 = 1, CRn = 0, CRm = 0 */
724 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
726 /* Op1 = 3, CRn = 0, CRm = 0 */
727 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
728 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
730 /* Op1 = 3, CRn = 14, CRm = 0 */
731 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
734 static int search_cmp_ftr_reg(const void *id, const void *regp)
736 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
740 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
741 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
742 * ascending order of sys_id, we use binary search to find a matching
745 * returns - Upon success, matching ftr_reg entry for id.
746 * - NULL on failure. It is upto the caller to decide
747 * the impact of a failure.
749 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
751 const struct __ftr_reg_entry *ret;
753 ret = bsearch((const void *)(unsigned long)sys_id,
755 ARRAY_SIZE(arm64_ftr_regs),
756 sizeof(arm64_ftr_regs[0]),
764 * get_arm64_ftr_reg - Looks up a feature register entry using
765 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
767 * returns - Upon success, matching ftr_reg entry for id.
768 * - NULL on failure but with an WARN_ON().
770 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
772 struct arm64_ftr_reg *reg;
774 reg = get_arm64_ftr_reg_nowarn(sys_id);
777 * Requesting a non-existent register search is an error. Warn
778 * and let the caller handle it.
784 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
787 u64 mask = arm64_ftr_mask(ftrp);
790 reg |= (ftr_val << ftrp->shift) & mask;
794 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
799 switch (ftrp->type) {
801 ret = ftrp->safe_val;
806 case FTR_HIGHER_OR_ZERO_SAFE:
810 case FTR_HIGHER_SAFE:
820 static void __init sort_ftr_regs(void)
824 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
825 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
826 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
830 * Features here must be sorted in descending order with respect
831 * to their shift values and should not overlap with each other.
833 for (; ftr_bits->width != 0; ftr_bits++, j++) {
834 unsigned int width = ftr_reg->ftr_bits[j].width;
835 unsigned int shift = ftr_reg->ftr_bits[j].shift;
836 unsigned int prev_shift;
838 WARN((shift + width) > 64,
839 "%s has invalid feature at shift %d\n",
840 ftr_reg->name, shift);
843 * Skip the first feature. There is nothing to
844 * compare against for now.
849 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
850 WARN((shift + width) > prev_shift,
851 "%s has feature overlap at shift %d\n",
852 ftr_reg->name, shift);
856 * Skip the first register. There is nothing to
857 * compare against for now.
862 * Registers here must be sorted in ascending order with respect
863 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
866 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id);
871 * Initialise the CPU feature register from Boot CPU values.
872 * Also initiliases the strict_mask for the register.
873 * Any bits that are not covered by an arm64_ftr_bits entry are considered
874 * RES0 for the system-wide value, and must strictly match.
876 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
879 u64 strict_mask = ~0x0ULL;
883 const struct arm64_ftr_bits *ftrp;
884 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
889 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
890 u64 ftr_mask = arm64_ftr_mask(ftrp);
891 s64 ftr_new = arm64_ftr_value(ftrp, new);
892 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
894 if ((ftr_mask & reg->override->mask) == ftr_mask) {
895 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
898 if (ftr_ovr != tmp) {
899 /* Unsafe, remove the override */
900 reg->override->mask &= ~ftr_mask;
901 reg->override->val &= ~ftr_mask;
903 str = "ignoring override";
904 } else if (ftr_new != tmp) {
905 /* Override was valid */
908 } else if (ftr_ovr == tmp) {
909 /* Override was the safe value */
914 pr_warn("%s[%d:%d]: %s to %llx\n",
916 ftrp->shift + ftrp->width - 1,
917 ftrp->shift, str, tmp);
918 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
919 reg->override->val &= ~ftr_mask;
920 pr_warn("%s[%d:%d]: impossible override, ignored\n",
922 ftrp->shift + ftrp->width - 1,
926 val = arm64_ftr_set_value(ftrp, val, ftr_new);
928 valid_mask |= ftr_mask;
930 strict_mask &= ~ftr_mask;
932 user_mask |= ftr_mask;
934 reg->user_val = arm64_ftr_set_value(ftrp,
942 reg->strict_mask = strict_mask;
943 reg->user_mask = user_mask;
946 extern const struct arm64_cpu_capabilities arm64_errata[];
947 static const struct arm64_cpu_capabilities arm64_features[];
950 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
952 for (; caps->matches; caps++) {
953 if (WARN(caps->capability >= ARM64_NCAPS,
954 "Invalid capability %d\n", caps->capability))
956 if (WARN(cpu_hwcaps_ptrs[caps->capability],
957 "Duplicate entry for capability %d\n",
960 cpu_hwcaps_ptrs[caps->capability] = caps;
964 static void __init init_cpu_hwcaps_indirect_list(void)
966 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
967 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
970 static void __init setup_boot_cpu_capabilities(void);
972 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
974 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
975 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
976 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
977 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
978 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
979 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
980 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
981 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
982 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
983 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
984 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
985 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
986 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
987 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
988 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
989 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
990 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
991 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
992 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
993 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
994 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
997 void __init init_cpu_features(struct cpuinfo_arm64 *info)
999 /* Before we start using the tables, make sure it is sorted */
1002 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
1003 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
1004 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
1005 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
1006 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
1007 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
1008 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
1009 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
1010 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
1011 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
1012 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
1013 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
1014 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
1015 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
1016 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0);
1018 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
1019 init_32bit_cpu_features(&info->aarch32);
1021 if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1022 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1023 info->reg_zcr = read_zcr_features();
1024 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
1025 vec_init_vq_map(ARM64_VEC_SVE);
1028 if (IS_ENABLED(CONFIG_ARM64_SME) &&
1029 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1030 info->reg_smcr = read_smcr_features();
1032 * We mask out SMPS since even if the hardware
1033 * supports priorities the kernel does not at present
1034 * and we block access to them.
1036 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1037 init_cpu_ftr_reg(SYS_SMCR_EL1, info->reg_smcr);
1038 vec_init_vq_map(ARM64_VEC_SME);
1041 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
1042 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
1045 * Initialize the indirect array of CPU hwcaps capabilities pointers
1046 * before we handle the boot CPU below.
1048 init_cpu_hwcaps_indirect_list();
1051 * Detect and enable early CPU capabilities based on the boot CPU,
1052 * after we have initialised the CPU feature infrastructure.
1054 setup_boot_cpu_capabilities();
1057 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
1059 const struct arm64_ftr_bits *ftrp;
1061 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
1062 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
1063 s64 ftr_new = arm64_ftr_value(ftrp, new);
1065 if (ftr_cur == ftr_new)
1067 /* Find a safe value */
1068 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
1069 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
1074 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
1076 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1081 update_cpu_ftr_reg(regp, val);
1082 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1084 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
1085 regp->name, boot, cpu, val);
1089 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1091 const struct arm64_ftr_bits *ftrp;
1092 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1097 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1098 if (ftrp->shift == field) {
1099 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1105 WARN_ON(!ftrp->width);
1108 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1109 struct cpuinfo_arm64 *boot)
1111 static bool boot_cpu_32bit_regs_overridden = false;
1113 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1116 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1119 boot->aarch32 = info->aarch32;
1120 init_32bit_cpu_features(&boot->aarch32);
1121 boot_cpu_32bit_regs_overridden = true;
1124 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1125 struct cpuinfo_32bit *boot)
1128 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1131 * If we don't have AArch32 at EL1, then relax the strictness of
1132 * EL1-dependent register fields to avoid spurious sanity check fails.
1134 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1135 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT);
1136 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT);
1137 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT);
1138 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT);
1139 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT);
1140 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT);
1143 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1144 info->reg_id_dfr0, boot->reg_id_dfr0);
1145 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1146 info->reg_id_dfr1, boot->reg_id_dfr1);
1147 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1148 info->reg_id_isar0, boot->reg_id_isar0);
1149 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1150 info->reg_id_isar1, boot->reg_id_isar1);
1151 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1152 info->reg_id_isar2, boot->reg_id_isar2);
1153 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1154 info->reg_id_isar3, boot->reg_id_isar3);
1155 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1156 info->reg_id_isar4, boot->reg_id_isar4);
1157 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1158 info->reg_id_isar5, boot->reg_id_isar5);
1159 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1160 info->reg_id_isar6, boot->reg_id_isar6);
1163 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1164 * ACTLR formats could differ across CPUs and therefore would have to
1165 * be trapped for virtualization anyway.
1167 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1168 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1169 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1170 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1171 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1172 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1173 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1174 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1175 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1176 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1177 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1178 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1179 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1180 info->reg_id_pfr0, boot->reg_id_pfr0);
1181 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1182 info->reg_id_pfr1, boot->reg_id_pfr1);
1183 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1184 info->reg_id_pfr2, boot->reg_id_pfr2);
1185 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1186 info->reg_mvfr0, boot->reg_mvfr0);
1187 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1188 info->reg_mvfr1, boot->reg_mvfr1);
1189 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1190 info->reg_mvfr2, boot->reg_mvfr2);
1196 * Update system wide CPU feature registers with the values from a
1197 * non-boot CPU. Also performs SANITY checks to make sure that there
1198 * aren't any insane variations from that of the boot CPU.
1200 void update_cpu_features(int cpu,
1201 struct cpuinfo_arm64 *info,
1202 struct cpuinfo_arm64 *boot)
1207 * The kernel can handle differing I-cache policies, but otherwise
1208 * caches should look identical. Userspace JITs will make use of
1211 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1212 info->reg_ctr, boot->reg_ctr);
1215 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1216 * could result in too much or too little memory being zeroed if a
1217 * process is preempted and migrated between CPUs.
1219 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1220 info->reg_dczid, boot->reg_dczid);
1222 /* If different, timekeeping will be broken (especially with KVM) */
1223 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1224 info->reg_cntfrq, boot->reg_cntfrq);
1227 * The kernel uses self-hosted debug features and expects CPUs to
1228 * support identical debug features. We presently need CTX_CMPs, WRPs,
1229 * and BRPs to be identical.
1230 * ID_AA64DFR1 is currently RES0.
1232 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1233 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1234 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1235 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1237 * Even in big.LITTLE, processors should be identical instruction-set
1240 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1241 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1242 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1243 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1244 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1245 info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1248 * Differing PARange support is fine as long as all peripherals and
1249 * memory are mapped within the minimum PARange of all CPUs.
1250 * Linux should not care about secure memory.
1252 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1253 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1254 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1255 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1256 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1257 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1259 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1260 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1261 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1262 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1264 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1265 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1267 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu,
1268 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0);
1270 if (IS_ENABLED(CONFIG_ARM64_SVE) &&
1271 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) {
1272 info->reg_zcr = read_zcr_features();
1273 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1274 info->reg_zcr, boot->reg_zcr);
1276 /* Probe vector lengths */
1277 if (!system_capabilities_finalized())
1278 vec_update_vq_map(ARM64_VEC_SVE);
1281 if (IS_ENABLED(CONFIG_ARM64_SME) &&
1282 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) {
1283 info->reg_smcr = read_smcr_features();
1285 * We mask out SMPS since even if the hardware
1286 * supports priorities the kernel does not at present
1287 * and we block access to them.
1289 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS;
1290 taint |= check_update_ftr_reg(SYS_SMCR_EL1, cpu,
1291 info->reg_smcr, boot->reg_smcr);
1293 /* Probe vector lengths */
1294 if (!system_capabilities_finalized())
1295 vec_update_vq_map(ARM64_VEC_SME);
1299 * The kernel uses the LDGM/STGM instructions and the number of tags
1300 * they read/write depends on the GMID_EL1.BS field. Check that the
1301 * value is the same on all CPUs.
1303 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1304 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1305 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1306 info->reg_gmid, boot->reg_gmid);
1310 * If we don't have AArch32 at all then skip the checks entirely
1311 * as the register values may be UNKNOWN and we're not going to be
1312 * using them for anything.
1314 * This relies on a sanitised view of the AArch64 ID registers
1315 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1317 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1318 lazy_init_32bit_cpu_features(info, boot);
1319 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1324 * Mismatched CPU features are a recipe for disaster. Don't even
1325 * pretend to support them.
1328 pr_warn_once("Unsupported CPU feature variation detected.\n");
1329 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1333 u64 read_sanitised_ftr_reg(u32 id)
1335 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1339 return regp->sys_val;
1341 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1343 #define read_sysreg_case(r) \
1344 case r: val = read_sysreg_s(r); break;
1347 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1348 * Read the system register on the current CPU
1350 u64 __read_sysreg_by_encoding(u32 sys_id)
1352 struct arm64_ftr_reg *regp;
1356 read_sysreg_case(SYS_ID_PFR0_EL1);
1357 read_sysreg_case(SYS_ID_PFR1_EL1);
1358 read_sysreg_case(SYS_ID_PFR2_EL1);
1359 read_sysreg_case(SYS_ID_DFR0_EL1);
1360 read_sysreg_case(SYS_ID_DFR1_EL1);
1361 read_sysreg_case(SYS_ID_MMFR0_EL1);
1362 read_sysreg_case(SYS_ID_MMFR1_EL1);
1363 read_sysreg_case(SYS_ID_MMFR2_EL1);
1364 read_sysreg_case(SYS_ID_MMFR3_EL1);
1365 read_sysreg_case(SYS_ID_MMFR4_EL1);
1366 read_sysreg_case(SYS_ID_MMFR5_EL1);
1367 read_sysreg_case(SYS_ID_ISAR0_EL1);
1368 read_sysreg_case(SYS_ID_ISAR1_EL1);
1369 read_sysreg_case(SYS_ID_ISAR2_EL1);
1370 read_sysreg_case(SYS_ID_ISAR3_EL1);
1371 read_sysreg_case(SYS_ID_ISAR4_EL1);
1372 read_sysreg_case(SYS_ID_ISAR5_EL1);
1373 read_sysreg_case(SYS_ID_ISAR6_EL1);
1374 read_sysreg_case(SYS_MVFR0_EL1);
1375 read_sysreg_case(SYS_MVFR1_EL1);
1376 read_sysreg_case(SYS_MVFR2_EL1);
1378 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1379 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1380 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1381 read_sysreg_case(SYS_ID_AA64SMFR0_EL1);
1382 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1383 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1384 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1385 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1386 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1387 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1388 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1389 read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1391 read_sysreg_case(SYS_CNTFRQ_EL0);
1392 read_sysreg_case(SYS_CTR_EL0);
1393 read_sysreg_case(SYS_DCZID_EL0);
1400 regp = get_arm64_ftr_reg(sys_id);
1402 val &= ~regp->override->mask;
1403 val |= (regp->override->val & regp->override->mask);
1409 #include <linux/irqchip/arm-gic-v3.h>
1412 has_always(const struct arm64_cpu_capabilities *entry, int scope)
1418 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1420 int val = cpuid_feature_extract_field_width(reg, entry->field_pos,
1424 return val >= entry->min_field_value;
1428 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope)
1430 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1431 if (scope == SCOPE_SYSTEM)
1432 return read_sanitised_ftr_reg(entry->sys_reg);
1434 return __read_sysreg_by_encoding(entry->sys_reg);
1438 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1441 struct arm64_ftr_reg *regp;
1442 u64 val = read_scoped_sysreg(entry, scope);
1444 regp = get_arm64_ftr_reg(entry->sys_reg);
1448 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask,
1450 entry->field_width);
1454 return feature_matches(val, entry);
1458 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1460 u64 val = read_scoped_sysreg(entry, scope);
1461 return feature_matches(val, entry);
1464 const struct cpumask *system_32bit_el0_cpumask(void)
1466 if (!system_supports_32bit_el0())
1467 return cpu_none_mask;
1469 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1470 return cpu_32bit_el0_mask;
1472 return cpu_possible_mask;
1475 static int __init parse_32bit_el0_param(char *str)
1477 allow_mismatched_32bit_el0 = true;
1480 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1482 static ssize_t aarch32_el0_show(struct device *dev,
1483 struct device_attribute *attr, char *buf)
1485 const struct cpumask *mask = system_32bit_el0_cpumask();
1487 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1489 static const DEVICE_ATTR_RO(aarch32_el0);
1491 static int __init aarch32_el0_sysfs_init(void)
1493 if (!allow_mismatched_32bit_el0)
1496 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0);
1498 device_initcall(aarch32_el0_sysfs_init);
1500 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1502 if (!has_cpuid_feature(entry, scope))
1503 return allow_mismatched_32bit_el0;
1505 if (scope == SCOPE_SYSTEM)
1506 pr_info("detected: 32-bit EL0 Support\n");
1511 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1515 if (!has_cpuid_feature(entry, scope))
1518 has_sre = gic_enable_sre();
1520 pr_warn_once("%s present but disabled by higher exception level\n",
1526 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1528 u32 midr = read_cpuid_id();
1530 /* Cavium ThunderX pass 1.x and 2.x */
1531 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1532 MIDR_CPU_VAR_REV(0, 0),
1533 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1536 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1538 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1540 return cpuid_feature_extract_signed_field(pfr0,
1541 ID_AA64PFR0_EL1_FP_SHIFT) < 0;
1544 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1549 if (scope == SCOPE_SYSTEM)
1550 ctr = arm64_ftr_reg_ctrel0.sys_val;
1552 ctr = read_cpuid_effective_cachetype();
1554 return ctr & BIT(CTR_EL0_IDC_SHIFT);
1557 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1560 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1561 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1562 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1565 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT)))
1566 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1569 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1574 if (scope == SCOPE_SYSTEM)
1575 ctr = arm64_ftr_reg_ctrel0.sys_val;
1577 ctr = read_cpuid_cachetype();
1579 return ctr & BIT(CTR_EL0_DIC_SHIFT);
1582 static bool __maybe_unused
1583 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1586 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1587 * may share TLB entries with a CPU stuck in the crashed
1590 if (is_kdump_kernel())
1593 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1596 return has_cpuid_feature(entry, scope);
1600 * This check is triggered during the early boot before the cpufeature
1601 * is initialised. Checking the status on the local CPU allows the boot
1602 * CPU to detect the need for non-global mappings and thus avoiding a
1603 * pagetable re-write after all the CPUs are booted. This check will be
1604 * anyway run on individual CPUs, allowing us to get the consistent
1605 * state once the SMP CPUs are up and thus make the switch to non-global
1606 * mappings if required.
1608 bool kaslr_requires_kpti(void)
1610 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1614 * E0PD does a similar job to KPTI so can be used instead
1617 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1618 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1619 if (cpuid_feature_extract_unsigned_field(mmfr2,
1620 ID_AA64MMFR2_EL1_E0PD_SHIFT))
1625 * Systems affected by Cavium erratum 24756 are incompatible
1628 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1629 extern const struct midr_range cavium_erratum_27456_cpus[];
1631 if (is_midr_in_range_list(read_cpuid_id(),
1632 cavium_erratum_27456_cpus))
1636 return kaslr_enabled();
1639 static bool __meltdown_safe = true;
1640 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1642 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1645 /* List of CPUs that are not vulnerable and don't need KPTI */
1646 static const struct midr_range kpti_safe_list[] = {
1647 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1648 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1649 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1650 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1651 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1652 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1653 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1654 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1655 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1656 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1657 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1658 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1659 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1660 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1661 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1664 char const *str = "kpti command line option";
1667 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1669 /* Defer to CPU feature registers */
1670 if (has_cpuid_feature(entry, scope))
1671 meltdown_safe = true;
1674 __meltdown_safe = false;
1677 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1678 * ThunderX leads to apparent I-cache corruption of kernel text, which
1679 * ends as well as you might imagine. Don't even try. We cannot rely
1680 * on the cpus_have_*cap() helpers here to detect the CPU erratum
1681 * because cpucap detection order may change. However, since we know
1682 * affected CPUs are always in a homogeneous configuration, it is
1683 * safe to rely on this_cpu_has_cap() here.
1685 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1686 str = "ARM64_WORKAROUND_CAVIUM_27456";
1690 /* Useful for KASLR robustness */
1691 if (kaslr_requires_kpti()) {
1692 if (!__kpti_forced) {
1698 if (cpu_mitigations_off() && !__kpti_forced) {
1699 str = "mitigations=off";
1703 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1704 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1709 if (__kpti_forced) {
1710 pr_info_once("kernel page table isolation forced %s by %s\n",
1711 __kpti_forced > 0 ? "ON" : "OFF", str);
1712 return __kpti_forced > 0;
1715 return !meltdown_safe;
1718 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1719 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT))
1722 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt,
1723 phys_addr_t size, pgprot_t prot,
1724 phys_addr_t (*pgtable_alloc)(int), int flags);
1726 static phys_addr_t kpti_ng_temp_alloc;
1728 static phys_addr_t kpti_ng_pgd_alloc(int shift)
1730 kpti_ng_temp_alloc -= PAGE_SIZE;
1731 return kpti_ng_temp_alloc;
1735 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1737 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long);
1738 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1739 kpti_remap_fn *remap_fn;
1741 int cpu = smp_processor_id();
1742 int levels = CONFIG_PGTABLE_LEVELS;
1743 int order = order_base_2(levels);
1744 u64 kpti_ng_temp_pgd_pa = 0;
1745 pgd_t *kpti_ng_temp_pgd;
1748 if (__this_cpu_read(this_cpu_vector) == vectors) {
1749 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1751 __this_cpu_write(this_cpu_vector, v);
1755 * We don't need to rewrite the page-tables if either we've done
1756 * it already or we have KASLR enabled and therefore have not
1757 * created any global mappings at all.
1759 if (arm64_use_ng_mappings)
1762 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1765 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
1766 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE);
1767 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd);
1770 // Create a minimal page table hierarchy that permits us to map
1771 // the swapper page tables temporarily as we traverse them.
1773 // The physical pages are laid out as follows:
1775 // +--------+-/-------+-/------ +-\\--------+
1776 // : PTE[] : | PMD[] : | PUD[] : || PGD[] :
1777 // +--------+-\-------+-\------ +-//--------+
1779 // The first page is mapped into this hierarchy at a PMD_SHIFT
1780 // aligned virtual address, so that we can manipulate the PTE
1781 // level entries while the mapping is active. The first entry
1782 // covers the PTE[] page itself, the remaining entries are free
1783 // to be used as a ad-hoc fixmap.
1785 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc),
1786 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL,
1787 kpti_ng_pgd_alloc, 0);
1790 cpu_install_idmap();
1791 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA);
1792 cpu_uninstall_idmap();
1795 free_pages(alloc, order);
1796 arm64_use_ng_mappings = true;
1801 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1804 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1806 static int __init parse_kpti(char *str)
1809 int ret = kstrtobool(str, &enabled);
1814 __kpti_forced = enabled ? 1 : -1;
1817 early_param("kpti", parse_kpti);
1819 #ifdef CONFIG_ARM64_HW_AFDBM
1820 static inline void __cpu_enable_hw_dbm(void)
1822 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1824 write_sysreg(tcr, tcr_el1);
1826 local_flush_tlb_all();
1829 static bool cpu_has_broken_dbm(void)
1831 /* List of CPUs which have broken DBM support. */
1832 static const struct midr_range cpus[] = {
1833 #ifdef CONFIG_ARM64_ERRATUM_1024718
1834 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1835 /* Kryo4xx Silver (rdpe => r1p0) */
1836 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1838 #ifdef CONFIG_ARM64_ERRATUM_2051678
1839 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
1844 return is_midr_in_range_list(read_cpuid_id(), cpus);
1847 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1849 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1850 !cpu_has_broken_dbm();
1853 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1855 if (cpu_can_use_dbm(cap))
1856 __cpu_enable_hw_dbm();
1859 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1862 static bool detected = false;
1864 * DBM is a non-conflicting feature. i.e, the kernel can safely
1865 * run a mix of CPUs with and without the feature. So, we
1866 * unconditionally enable the capability to allow any late CPU
1867 * to use the feature. We only enable the control bits on the
1868 * CPU, if it actually supports.
1870 * We have to make sure we print the "feature" detection only
1871 * when at least one CPU actually uses it. So check if this CPU
1872 * can actually use it and print the message exactly once.
1874 * This is safe as all CPUs (including secondary CPUs - due to the
1875 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1876 * goes through the "matches" check exactly once. Also if a CPU
1877 * matches the criteria, it is guaranteed that the CPU will turn
1878 * the DBM on, as the capability is unconditionally enabled.
1880 if (!detected && cpu_can_use_dbm(cap)) {
1882 pr_info("detected: Hardware dirty bit management\n");
1890 #ifdef CONFIG_ARM64_AMU_EXTN
1893 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1894 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1895 * information regarding all the events that it supports. When a CPU bit is
1896 * set in the cpumask, the user of this feature can only rely on the presence
1897 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1898 * counters are enabled or access to these counters is enabled by code
1899 * executed at higher exception levels (firmware).
1901 static struct cpumask amu_cpus __read_mostly;
1903 bool cpu_has_amu_feat(int cpu)
1905 return cpumask_test_cpu(cpu, &amu_cpus);
1908 int get_cpu_with_amu_feat(void)
1910 return cpumask_any(&amu_cpus);
1913 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1915 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1916 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1917 smp_processor_id());
1918 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1920 /* 0 reference values signal broken/disabled counters */
1921 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
1922 update_freq_counters_refs();
1926 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1930 * The AMU extension is a non-conflicting feature: the kernel can
1931 * safely run a mix of CPUs with and without support for the
1932 * activity monitors extension. Therefore, unconditionally enable
1933 * the capability to allow any late CPU to use the feature.
1935 * With this feature unconditionally enabled, the cpu_enable
1936 * function will be called for all CPUs that match the criteria,
1937 * including secondary and hotplugged, marking this feature as
1938 * present on that respective CPU. The enable function will also
1939 * print a detection message.
1945 int get_cpu_with_amu_feat(void)
1951 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1953 return is_kernel_in_hyp_mode();
1956 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1959 * Copy register values that aren't redirected by hardware.
1961 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1962 * this value to tpidr_el2 before we patch the code. Once we've done
1963 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1966 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1967 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1970 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap,
1973 if (kvm_get_mode() != KVM_MODE_NV)
1976 if (!has_cpuid_feature(cap, scope)) {
1977 pr_warn("unavailable: %s\n", cap->desc);
1984 #ifdef CONFIG_ARM64_PAN
1985 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1988 * We modify PSTATE. This won't work from irq context as the PSTATE
1989 * is discarded once we return from the exception.
1991 WARN_ON_ONCE(in_interrupt());
1993 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1996 #endif /* CONFIG_ARM64_PAN */
1998 #ifdef CONFIG_ARM64_RAS_EXTN
1999 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
2001 /* Firmware may have left a deferred SError in this register. */
2002 write_sysreg_s(0, SYS_DISR_EL1);
2004 #endif /* CONFIG_ARM64_RAS_EXTN */
2006 #ifdef CONFIG_ARM64_PTR_AUTH
2007 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
2009 int boot_val, sec_val;
2011 /* We don't expect to be called with SCOPE_SYSTEM */
2012 WARN_ON(scope == SCOPE_SYSTEM);
2014 * The ptr-auth feature levels are not intercompatible with lower
2015 * levels. Hence we must match ptr-auth feature level of the secondary
2016 * CPUs with that of the boot CPU. The level of boot cpu is fetched
2017 * from the sanitised register whereas direct register read is done for
2018 * the secondary CPUs.
2019 * The sanitised feature state is guaranteed to match that of the
2020 * boot CPU as a mismatched secondary CPU is parked before it gets
2021 * a chance to update the state, with the capability.
2023 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
2024 entry->field_pos, entry->sign);
2025 if (scope & SCOPE_BOOT_CPU)
2026 return boot_val >= entry->min_field_value;
2027 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
2028 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
2029 entry->field_pos, entry->sign);
2030 return (sec_val >= entry->min_field_value) && (sec_val == boot_val);
2033 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
2036 bool api = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
2037 bool apa = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope);
2038 bool apa3 = has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope);
2040 return apa || apa3 || api;
2043 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
2046 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
2047 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5);
2048 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3);
2050 return gpa || gpa3 || gpi;
2052 #endif /* CONFIG_ARM64_PTR_AUTH */
2054 #ifdef CONFIG_ARM64_E0PD
2055 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
2057 if (this_cpu_has_cap(ARM64_HAS_E0PD))
2058 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
2060 #endif /* CONFIG_ARM64_E0PD */
2062 #ifdef CONFIG_ARM64_PSEUDO_NMI
2063 static bool enable_pseudo_nmi;
2065 static int __init early_enable_pseudo_nmi(char *p)
2067 return kstrtobool(p, &enable_pseudo_nmi);
2069 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
2071 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
2075 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU
2076 * feature, so will be detected earlier.
2078 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS);
2079 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS))
2082 return enable_pseudo_nmi;
2085 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry,
2089 * If we're not using priority masking then we won't be poking PMR_EL1,
2090 * and there's no need to relax synchronization of writes to it, and
2091 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from
2094 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU
2095 * feature, so will be detected earlier.
2097 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING);
2098 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING))
2102 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a
2103 * hint for interrupt distribution, a DSB is not necessary when
2104 * unmasking IRQs via PMR, and we can relax the barrier to a NOP.
2106 * Linux itself doesn't use 1:N distribution, so has no need to
2107 * set PMHE. The only reason to have it set is if EL3 requires it
2108 * (and we can't change it).
2110 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0;
2114 #ifdef CONFIG_ARM64_BTI
2115 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
2118 * Use of X16/X17 for tail-calls and trampolines that jump to
2119 * function entry points using BR is a requirement for
2120 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
2121 * So, be strict and forbid other BRs using other registers to
2122 * jump onto a PACIxSP instruction:
2124 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
2127 #endif /* CONFIG_ARM64_BTI */
2129 #ifdef CONFIG_ARM64_MTE
2130 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
2132 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
2137 * Clear the tags in the zero page. This needs to be done via the
2138 * linear map which has the Tagged attribute.
2140 if (try_page_mte_tagging(ZERO_PAGE(0))) {
2141 mte_clear_page_tags(lm_alias(empty_zero_page));
2142 set_page_mte_tagged(ZERO_PAGE(0));
2145 kasan_init_hw_tags_cpu();
2147 #endif /* CONFIG_ARM64_MTE */
2149 static void elf_hwcap_fixup(void)
2151 #ifdef CONFIG_ARM64_ERRATUM_1742098
2152 if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))
2153 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
2154 #endif /* ARM64_ERRATUM_1742098 */
2158 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
2160 return kvm_get_mode() == KVM_MODE_PROTECTED;
2162 #endif /* CONFIG_KVM */
2164 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused)
2166 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP);
2169 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused)
2174 /* Internal helper functions to match cpu capability type */
2176 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
2178 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
2182 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
2184 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
2188 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
2190 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
2193 static const struct arm64_cpu_capabilities arm64_features[] = {
2195 .capability = ARM64_ALWAYS_BOOT,
2196 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2197 .matches = has_always,
2200 .capability = ARM64_ALWAYS_SYSTEM,
2201 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2202 .matches = has_always,
2205 .desc = "GIC system register CPU interface",
2206 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS,
2207 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2208 .matches = has_useable_gicv3_cpuif,
2209 .sys_reg = SYS_ID_AA64PFR0_EL1,
2210 .field_pos = ID_AA64PFR0_EL1_GIC_SHIFT,
2212 .sign = FTR_UNSIGNED,
2213 .min_field_value = 1,
2216 .desc = "Enhanced Counter Virtualization",
2217 .capability = ARM64_HAS_ECV,
2218 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2219 .matches = has_cpuid_feature,
2220 .sys_reg = SYS_ID_AA64MMFR0_EL1,
2221 .field_pos = ID_AA64MMFR0_EL1_ECV_SHIFT,
2223 .sign = FTR_UNSIGNED,
2224 .min_field_value = 1,
2226 #ifdef CONFIG_ARM64_PAN
2228 .desc = "Privileged Access Never",
2229 .capability = ARM64_HAS_PAN,
2230 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2231 .matches = has_cpuid_feature,
2232 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2233 .field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
2235 .sign = FTR_UNSIGNED,
2236 .min_field_value = 1,
2237 .cpu_enable = cpu_enable_pan,
2239 #endif /* CONFIG_ARM64_PAN */
2240 #ifdef CONFIG_ARM64_EPAN
2242 .desc = "Enhanced Privileged Access Never",
2243 .capability = ARM64_HAS_EPAN,
2244 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2245 .matches = has_cpuid_feature,
2246 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2247 .field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
2249 .sign = FTR_UNSIGNED,
2250 .min_field_value = 3,
2252 #endif /* CONFIG_ARM64_EPAN */
2253 #ifdef CONFIG_ARM64_LSE_ATOMICS
2255 .desc = "LSE atomic instructions",
2256 .capability = ARM64_HAS_LSE_ATOMICS,
2257 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2258 .matches = has_cpuid_feature,
2259 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2260 .field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT,
2262 .sign = FTR_UNSIGNED,
2263 .min_field_value = 2,
2265 #endif /* CONFIG_ARM64_LSE_ATOMICS */
2267 .desc = "Software prefetching using PRFM",
2268 .capability = ARM64_HAS_NO_HW_PREFETCH,
2269 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2270 .matches = has_no_hw_prefetch,
2273 .desc = "Virtualization Host Extensions",
2274 .capability = ARM64_HAS_VIRT_HOST_EXTN,
2275 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2276 .matches = runs_at_el2,
2277 .cpu_enable = cpu_copy_el2regs,
2280 .desc = "Nested Virtualization Support",
2281 .capability = ARM64_HAS_NESTED_VIRT,
2282 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2283 .matches = has_nested_virt_support,
2284 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2285 .sign = FTR_UNSIGNED,
2286 .field_pos = ID_AA64MMFR2_EL1_NV_SHIFT,
2288 .min_field_value = ID_AA64MMFR2_EL1_NV_IMP,
2291 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
2292 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2293 .matches = has_32bit_el0,
2294 .sys_reg = SYS_ID_AA64PFR0_EL1,
2295 .sign = FTR_UNSIGNED,
2296 .field_pos = ID_AA64PFR0_EL1_EL0_SHIFT,
2298 .min_field_value = ID_AA64PFR0_EL1_ELx_32BIT_64BIT,
2302 .desc = "32-bit EL1 Support",
2303 .capability = ARM64_HAS_32BIT_EL1,
2304 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2305 .matches = has_cpuid_feature,
2306 .sys_reg = SYS_ID_AA64PFR0_EL1,
2307 .sign = FTR_UNSIGNED,
2308 .field_pos = ID_AA64PFR0_EL1_EL1_SHIFT,
2310 .min_field_value = ID_AA64PFR0_EL1_ELx_32BIT_64BIT,
2313 .desc = "Protected KVM",
2314 .capability = ARM64_KVM_PROTECTED_MODE,
2315 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2316 .matches = is_kvm_protected_mode,
2320 .desc = "Kernel page table isolation (KPTI)",
2321 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
2322 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2324 * The ID feature fields below are used to indicate that
2325 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2328 .sys_reg = SYS_ID_AA64PFR0_EL1,
2329 .field_pos = ID_AA64PFR0_EL1_CSV3_SHIFT,
2331 .min_field_value = 1,
2332 .matches = unmap_kernel_at_el0,
2333 .cpu_enable = kpti_install_ng_mappings,
2336 /* FP/SIMD is not implemented */
2337 .capability = ARM64_HAS_NO_FPSIMD,
2338 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2339 .min_field_value = 0,
2340 .matches = has_no_fpsimd,
2342 #ifdef CONFIG_ARM64_PMEM
2344 .desc = "Data cache clean to Point of Persistence",
2345 .capability = ARM64_HAS_DCPOP,
2346 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2347 .matches = has_cpuid_feature,
2348 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2349 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,
2351 .min_field_value = 1,
2354 .desc = "Data cache clean to Point of Deep Persistence",
2355 .capability = ARM64_HAS_DCPODP,
2356 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2357 .matches = has_cpuid_feature,
2358 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2359 .sign = FTR_UNSIGNED,
2360 .field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,
2362 .min_field_value = 2,
2365 #ifdef CONFIG_ARM64_SVE
2367 .desc = "Scalable Vector Extension",
2368 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2369 .capability = ARM64_SVE,
2370 .sys_reg = SYS_ID_AA64PFR0_EL1,
2371 .sign = FTR_UNSIGNED,
2372 .field_pos = ID_AA64PFR0_EL1_SVE_SHIFT,
2374 .min_field_value = ID_AA64PFR0_EL1_SVE_IMP,
2375 .matches = has_cpuid_feature,
2376 .cpu_enable = sve_kernel_enable,
2378 #endif /* CONFIG_ARM64_SVE */
2379 #ifdef CONFIG_ARM64_RAS_EXTN
2381 .desc = "RAS Extension Support",
2382 .capability = ARM64_HAS_RAS_EXTN,
2383 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2384 .matches = has_cpuid_feature,
2385 .sys_reg = SYS_ID_AA64PFR0_EL1,
2386 .sign = FTR_UNSIGNED,
2387 .field_pos = ID_AA64PFR0_EL1_RAS_SHIFT,
2389 .min_field_value = ID_AA64PFR0_EL1_RAS_IMP,
2390 .cpu_enable = cpu_clear_disr,
2392 #endif /* CONFIG_ARM64_RAS_EXTN */
2393 #ifdef CONFIG_ARM64_AMU_EXTN
2396 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
2397 * Therefore, don't provide .desc as we don't want the detection
2398 * message to be shown until at least one CPU is detected to
2399 * support the feature.
2401 .capability = ARM64_HAS_AMU_EXTN,
2402 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2404 .sys_reg = SYS_ID_AA64PFR0_EL1,
2405 .sign = FTR_UNSIGNED,
2406 .field_pos = ID_AA64PFR0_EL1_AMU_SHIFT,
2408 .min_field_value = ID_AA64PFR0_EL1_AMU_IMP,
2409 .cpu_enable = cpu_amu_enable,
2411 #endif /* CONFIG_ARM64_AMU_EXTN */
2413 .desc = "Data cache clean to the PoU not required for I/D coherence",
2414 .capability = ARM64_HAS_CACHE_IDC,
2415 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2416 .matches = has_cache_idc,
2417 .cpu_enable = cpu_emulate_effective_ctr,
2420 .desc = "Instruction cache invalidation not required for I/D coherence",
2421 .capability = ARM64_HAS_CACHE_DIC,
2422 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2423 .matches = has_cache_dic,
2426 .desc = "Stage-2 Force Write-Back",
2427 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2428 .capability = ARM64_HAS_STAGE2_FWB,
2429 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2430 .sign = FTR_UNSIGNED,
2431 .field_pos = ID_AA64MMFR2_EL1_FWB_SHIFT,
2433 .min_field_value = 1,
2434 .matches = has_cpuid_feature,
2437 .desc = "ARMv8.4 Translation Table Level",
2438 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2439 .capability = ARM64_HAS_ARMv8_4_TTL,
2440 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2441 .sign = FTR_UNSIGNED,
2442 .field_pos = ID_AA64MMFR2_EL1_TTL_SHIFT,
2444 .min_field_value = 1,
2445 .matches = has_cpuid_feature,
2448 .desc = "TLB range maintenance instructions",
2449 .capability = ARM64_HAS_TLB_RANGE,
2450 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2451 .matches = has_cpuid_feature,
2452 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2453 .field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT,
2455 .sign = FTR_UNSIGNED,
2456 .min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE,
2458 #ifdef CONFIG_ARM64_HW_AFDBM
2461 * Since we turn this on always, we don't want the user to
2462 * think that the feature is available when it may not be.
2463 * So hide the description.
2465 * .desc = "Hardware pagetable Dirty Bit Management",
2468 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2469 .capability = ARM64_HW_DBM,
2470 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2471 .sign = FTR_UNSIGNED,
2472 .field_pos = ID_AA64MMFR1_EL1_HAFDBS_SHIFT,
2474 .min_field_value = 2,
2475 .matches = has_hw_dbm,
2476 .cpu_enable = cpu_enable_hw_dbm,
2480 .desc = "CRC32 instructions",
2481 .capability = ARM64_HAS_CRC32,
2482 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2483 .matches = has_cpuid_feature,
2484 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2485 .field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT,
2487 .min_field_value = 1,
2490 .desc = "Speculative Store Bypassing Safe (SSBS)",
2491 .capability = ARM64_SSBS,
2492 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2493 .matches = has_cpuid_feature,
2494 .sys_reg = SYS_ID_AA64PFR1_EL1,
2495 .field_pos = ID_AA64PFR1_EL1_SSBS_SHIFT,
2497 .sign = FTR_UNSIGNED,
2498 .min_field_value = ID_AA64PFR1_EL1_SSBS_IMP,
2500 #ifdef CONFIG_ARM64_CNP
2502 .desc = "Common not Private translations",
2503 .capability = ARM64_HAS_CNP,
2504 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2505 .matches = has_useable_cnp,
2506 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2507 .sign = FTR_UNSIGNED,
2508 .field_pos = ID_AA64MMFR2_EL1_CnP_SHIFT,
2510 .min_field_value = 1,
2511 .cpu_enable = cpu_enable_cnp,
2515 .desc = "Speculation barrier (SB)",
2516 .capability = ARM64_HAS_SB,
2517 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2518 .matches = has_cpuid_feature,
2519 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2520 .field_pos = ID_AA64ISAR1_EL1_SB_SHIFT,
2522 .sign = FTR_UNSIGNED,
2523 .min_field_value = 1,
2525 #ifdef CONFIG_ARM64_PTR_AUTH
2527 .desc = "Address authentication (architected QARMA5 algorithm)",
2528 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5,
2529 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2530 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2531 .sign = FTR_UNSIGNED,
2532 .field_pos = ID_AA64ISAR1_EL1_APA_SHIFT,
2534 .min_field_value = ID_AA64ISAR1_EL1_APA_PAuth,
2535 .matches = has_address_auth_cpucap,
2538 .desc = "Address authentication (architected QARMA3 algorithm)",
2539 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3,
2540 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2541 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2542 .sign = FTR_UNSIGNED,
2543 .field_pos = ID_AA64ISAR2_EL1_APA3_SHIFT,
2545 .min_field_value = ID_AA64ISAR2_EL1_APA3_PAuth,
2546 .matches = has_address_auth_cpucap,
2549 .desc = "Address authentication (IMP DEF algorithm)",
2550 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2551 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2552 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2553 .sign = FTR_UNSIGNED,
2554 .field_pos = ID_AA64ISAR1_EL1_API_SHIFT,
2556 .min_field_value = ID_AA64ISAR1_EL1_API_PAuth,
2557 .matches = has_address_auth_cpucap,
2560 .capability = ARM64_HAS_ADDRESS_AUTH,
2561 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2562 .matches = has_address_auth_metacap,
2565 .desc = "Generic authentication (architected QARMA5 algorithm)",
2566 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5,
2567 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2568 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2569 .sign = FTR_UNSIGNED,
2570 .field_pos = ID_AA64ISAR1_EL1_GPA_SHIFT,
2572 .min_field_value = ID_AA64ISAR1_EL1_GPA_IMP,
2573 .matches = has_cpuid_feature,
2576 .desc = "Generic authentication (architected QARMA3 algorithm)",
2577 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3,
2578 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2579 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2580 .sign = FTR_UNSIGNED,
2581 .field_pos = ID_AA64ISAR2_EL1_GPA3_SHIFT,
2583 .min_field_value = ID_AA64ISAR2_EL1_GPA3_IMP,
2584 .matches = has_cpuid_feature,
2587 .desc = "Generic authentication (IMP DEF algorithm)",
2588 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2589 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2590 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2591 .sign = FTR_UNSIGNED,
2592 .field_pos = ID_AA64ISAR1_EL1_GPI_SHIFT,
2594 .min_field_value = ID_AA64ISAR1_EL1_GPI_IMP,
2595 .matches = has_cpuid_feature,
2598 .capability = ARM64_HAS_GENERIC_AUTH,
2599 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2600 .matches = has_generic_auth,
2602 #endif /* CONFIG_ARM64_PTR_AUTH */
2603 #ifdef CONFIG_ARM64_PSEUDO_NMI
2606 * Depends on having GICv3
2608 .desc = "IRQ priority masking",
2609 .capability = ARM64_HAS_GIC_PRIO_MASKING,
2610 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2611 .matches = can_use_gic_priorities,
2615 * Depends on ARM64_HAS_GIC_PRIO_MASKING
2617 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC,
2618 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2619 .matches = has_gic_prio_relaxed_sync,
2622 #ifdef CONFIG_ARM64_E0PD
2625 .capability = ARM64_HAS_E0PD,
2626 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2627 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2628 .sign = FTR_UNSIGNED,
2630 .field_pos = ID_AA64MMFR2_EL1_E0PD_SHIFT,
2631 .matches = has_cpuid_feature,
2632 .min_field_value = 1,
2633 .cpu_enable = cpu_enable_e0pd,
2637 .desc = "Random Number Generator",
2638 .capability = ARM64_HAS_RNG,
2639 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2640 .matches = has_cpuid_feature,
2641 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2642 .field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT,
2644 .sign = FTR_UNSIGNED,
2645 .min_field_value = 1,
2647 #ifdef CONFIG_ARM64_BTI
2649 .desc = "Branch Target Identification",
2650 .capability = ARM64_BTI,
2651 #ifdef CONFIG_ARM64_BTI_KERNEL
2652 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2654 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2656 .matches = has_cpuid_feature,
2657 .cpu_enable = bti_enable,
2658 .sys_reg = SYS_ID_AA64PFR1_EL1,
2659 .field_pos = ID_AA64PFR1_EL1_BT_SHIFT,
2661 .min_field_value = ID_AA64PFR1_EL1_BT_IMP,
2662 .sign = FTR_UNSIGNED,
2665 #ifdef CONFIG_ARM64_MTE
2667 .desc = "Memory Tagging Extension",
2668 .capability = ARM64_MTE,
2669 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2670 .matches = has_cpuid_feature,
2671 .sys_reg = SYS_ID_AA64PFR1_EL1,
2672 .field_pos = ID_AA64PFR1_EL1_MTE_SHIFT,
2674 .min_field_value = ID_AA64PFR1_EL1_MTE_MTE2,
2675 .sign = FTR_UNSIGNED,
2676 .cpu_enable = cpu_enable_mte,
2679 .desc = "Asymmetric MTE Tag Check Fault",
2680 .capability = ARM64_MTE_ASYMM,
2681 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2682 .matches = has_cpuid_feature,
2683 .sys_reg = SYS_ID_AA64PFR1_EL1,
2684 .field_pos = ID_AA64PFR1_EL1_MTE_SHIFT,
2686 .min_field_value = ID_AA64PFR1_EL1_MTE_MTE3,
2687 .sign = FTR_UNSIGNED,
2689 #endif /* CONFIG_ARM64_MTE */
2691 .desc = "RCpc load-acquire (LDAPR)",
2692 .capability = ARM64_HAS_LDAPR,
2693 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2694 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2695 .sign = FTR_UNSIGNED,
2696 .field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT,
2698 .matches = has_cpuid_feature,
2699 .min_field_value = 1,
2701 #ifdef CONFIG_ARM64_SME
2703 .desc = "Scalable Matrix Extension",
2704 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2705 .capability = ARM64_SME,
2706 .sys_reg = SYS_ID_AA64PFR1_EL1,
2707 .sign = FTR_UNSIGNED,
2708 .field_pos = ID_AA64PFR1_EL1_SME_SHIFT,
2710 .min_field_value = ID_AA64PFR1_EL1_SME_IMP,
2711 .matches = has_cpuid_feature,
2712 .cpu_enable = sme_kernel_enable,
2714 /* FA64 should be sorted after the base SME capability */
2717 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2718 .capability = ARM64_SME_FA64,
2719 .sys_reg = SYS_ID_AA64SMFR0_EL1,
2720 .sign = FTR_UNSIGNED,
2721 .field_pos = ID_AA64SMFR0_EL1_FA64_SHIFT,
2723 .min_field_value = ID_AA64SMFR0_EL1_FA64_IMP,
2724 .matches = has_cpuid_feature,
2725 .cpu_enable = fa64_kernel_enable,
2729 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2730 .capability = ARM64_SME2,
2731 .sys_reg = SYS_ID_AA64PFR1_EL1,
2732 .sign = FTR_UNSIGNED,
2733 .field_pos = ID_AA64PFR1_EL1_SME_SHIFT,
2734 .field_width = ID_AA64PFR1_EL1_SME_WIDTH,
2735 .min_field_value = ID_AA64PFR1_EL1_SME_SME2,
2736 .matches = has_cpuid_feature,
2737 .cpu_enable = sme2_kernel_enable,
2739 #endif /* CONFIG_ARM64_SME */
2741 .desc = "WFx with timeout",
2742 .capability = ARM64_HAS_WFXT,
2743 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2744 .sys_reg = SYS_ID_AA64ISAR2_EL1,
2745 .sign = FTR_UNSIGNED,
2746 .field_pos = ID_AA64ISAR2_EL1_WFxT_SHIFT,
2748 .matches = has_cpuid_feature,
2749 .min_field_value = ID_AA64ISAR2_EL1_WFxT_IMP,
2752 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality",
2753 .capability = ARM64_HAS_TIDCP1,
2754 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2755 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2756 .sign = FTR_UNSIGNED,
2757 .field_pos = ID_AA64MMFR1_EL1_TIDCP1_SHIFT,
2759 .min_field_value = ID_AA64MMFR1_EL1_TIDCP1_IMP,
2760 .matches = has_cpuid_feature,
2761 .cpu_enable = cpu_trap_el0_impdef,
2764 .desc = "Data independent timing control (DIT)",
2765 .capability = ARM64_HAS_DIT,
2766 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2767 .sys_reg = SYS_ID_AA64PFR0_EL1,
2768 .sign = FTR_UNSIGNED,
2769 .field_pos = ID_AA64PFR0_EL1_DIT_SHIFT,
2771 .min_field_value = ID_AA64PFR0_EL1_DIT_IMP,
2772 .matches = has_cpuid_feature,
2773 .cpu_enable = cpu_enable_dit,
2778 #define HWCAP_CPUID_MATCH(reg, field, min_value) \
2779 .matches = has_user_cpuid_feature, \
2780 .sys_reg = SYS_##reg, \
2781 .field_pos = reg##_##field##_SHIFT, \
2782 .field_width = reg##_##field##_WIDTH, \
2783 .sign = reg##_##field##_SIGNED, \
2784 .min_field_value = reg##_##field##_##min_value,
2786 #define __HWCAP_CAP(name, cap_type, cap) \
2788 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2789 .hwcap_type = cap_type, \
2792 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \
2794 __HWCAP_CAP(#cap, cap_type, cap) \
2795 HWCAP_CPUID_MATCH(reg, field, min_value) \
2798 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2800 __HWCAP_CAP(#cap, cap_type, cap) \
2801 .matches = cpucap_multi_entry_cap_matches, \
2802 .match_list = list, \
2805 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2807 __HWCAP_CAP(#cap, cap_type, cap) \
2811 #ifdef CONFIG_ARM64_PTR_AUTH
2812 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2814 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth)
2817 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth)
2820 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth)
2825 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2827 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP)
2830 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP)
2833 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP)
2839 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2840 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2841 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES),
2842 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2843 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2844 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2845 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2846 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2847 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2848 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2849 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3),
2850 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4),
2851 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2852 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2853 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2854 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2855 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG),
2856 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP),
2857 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2858 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2859 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2860 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT),
2861 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2862 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2863 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2864 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2865 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2866 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2867 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2868 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB),
2869 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16),
2870 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16),
2871 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH),
2872 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2873 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2874 #ifdef CONFIG_ARM64_SVE
2875 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE),
2876 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1),
2877 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2878 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2879 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2880 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2881 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2882 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16),
2883 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2884 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2885 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2886 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2887 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2889 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2890 #ifdef CONFIG_ARM64_BTI
2891 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI),
2893 #ifdef CONFIG_ARM64_PTR_AUTH
2894 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2895 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2897 #ifdef CONFIG_ARM64_MTE
2898 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE),
2899 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3),
2900 #endif /* CONFIG_ARM64_MTE */
2901 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV),
2902 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP),
2903 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC),
2904 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM),
2905 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES),
2906 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
2907 #ifdef CONFIG_ARM64_SME
2908 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME),
2909 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),
2910 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1),
2911 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2),
2912 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64),
2913 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64),
2914 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32),
2915 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16),
2916 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16),
2917 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32),
2918 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32),
2919 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32),
2920 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32),
2921 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32),
2922 #endif /* CONFIG_ARM64_SME */
2926 #ifdef CONFIG_COMPAT
2927 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2930 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2931 * in line with that of arm32 as in vfp_init(). We make sure that the
2932 * check is future proof, by making sure value is non-zero.
2936 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2937 if (scope == SCOPE_SYSTEM)
2938 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2940 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2942 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) &&
2943 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) &&
2944 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT);
2948 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2949 #ifdef CONFIG_COMPAT
2950 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2951 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2952 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2953 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2954 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2955 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP),
2956 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP),
2957 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2958 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2959 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2960 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2961 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2962 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP),
2963 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM),
2964 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB),
2965 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16),
2966 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM),
2967 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS),
2972 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2974 switch (cap->hwcap_type) {
2976 cpu_set_feature(cap->hwcap);
2978 #ifdef CONFIG_COMPAT
2979 case CAP_COMPAT_HWCAP:
2980 compat_elf_hwcap |= (u32)cap->hwcap;
2982 case CAP_COMPAT_HWCAP2:
2983 compat_elf_hwcap2 |= (u32)cap->hwcap;
2992 /* Check if we have a particular HWCAP enabled */
2993 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2997 switch (cap->hwcap_type) {
2999 rc = cpu_have_feature(cap->hwcap);
3001 #ifdef CONFIG_COMPAT
3002 case CAP_COMPAT_HWCAP:
3003 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
3005 case CAP_COMPAT_HWCAP2:
3006 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
3017 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
3019 /* We support emulation of accesses to CPU ID feature registers */
3020 cpu_set_named_feature(CPUID);
3021 for (; hwcaps->matches; hwcaps++)
3022 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
3023 cap_set_elf_hwcap(hwcaps);
3026 static void update_cpu_capabilities(u16 scope_mask)
3029 const struct arm64_cpu_capabilities *caps;
3031 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3032 for (i = 0; i < ARM64_NCAPS; i++) {
3033 caps = cpu_hwcaps_ptrs[i];
3034 if (!caps || !(caps->type & scope_mask) ||
3035 cpus_have_cap(caps->capability) ||
3036 !caps->matches(caps, cpucap_default_scope(caps)))
3040 pr_info("detected: %s\n", caps->desc);
3041 cpus_set_cap(caps->capability);
3043 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
3044 set_bit(caps->capability, boot_capabilities);
3049 * Enable all the available capabilities on this CPU. The capabilities
3050 * with BOOT_CPU scope are handled separately and hence skipped here.
3052 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
3055 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
3057 for_each_available_cap(i) {
3058 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
3063 if (!(cap->type & non_boot_scope))
3066 if (cap->cpu_enable)
3067 cap->cpu_enable(cap);
3073 * Run through the enabled capabilities and enable() it on all active
3076 static void __init enable_cpu_capabilities(u16 scope_mask)
3079 const struct arm64_cpu_capabilities *caps;
3082 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3083 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
3085 for (i = 0; i < ARM64_NCAPS; i++) {
3088 caps = cpu_hwcaps_ptrs[i];
3089 if (!caps || !(caps->type & scope_mask))
3091 num = caps->capability;
3092 if (!cpus_have_cap(num))
3095 if (boot_scope && caps->cpu_enable)
3097 * Capabilities with SCOPE_BOOT_CPU scope are finalised
3098 * before any secondary CPU boots. Thus, each secondary
3099 * will enable the capability as appropriate via
3100 * check_local_cpu_capabilities(). The only exception is
3101 * the boot CPU, for which the capability must be
3102 * enabled here. This approach avoids costly
3103 * stop_machine() calls for this case.
3105 caps->cpu_enable(caps);
3109 * For all non-boot scope capabilities, use stop_machine()
3110 * as it schedules the work allowing us to modify PSTATE,
3111 * instead of on_each_cpu() which uses an IPI, giving us a
3112 * PSTATE that disappears when we return.
3115 stop_machine(cpu_enable_non_boot_scope_capabilities,
3116 NULL, cpu_online_mask);
3120 * Run through the list of capabilities to check for conflicts.
3121 * If the system has already detected a capability, take necessary
3122 * action on this CPU.
3124 static void verify_local_cpu_caps(u16 scope_mask)
3127 bool cpu_has_cap, system_has_cap;
3128 const struct arm64_cpu_capabilities *caps;
3130 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
3132 for (i = 0; i < ARM64_NCAPS; i++) {
3133 caps = cpu_hwcaps_ptrs[i];
3134 if (!caps || !(caps->type & scope_mask))
3137 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
3138 system_has_cap = cpus_have_cap(caps->capability);
3140 if (system_has_cap) {
3142 * Check if the new CPU misses an advertised feature,
3143 * which is not safe to miss.
3145 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
3148 * We have to issue cpu_enable() irrespective of
3149 * whether the CPU has it or not, as it is enabeld
3150 * system wide. It is upto the call back to take
3151 * appropriate action on this CPU.
3153 if (caps->cpu_enable)
3154 caps->cpu_enable(caps);
3157 * Check if the CPU has this capability if it isn't
3158 * safe to have when the system doesn't.
3160 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
3165 if (i < ARM64_NCAPS) {
3166 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
3167 smp_processor_id(), caps->capability,
3168 caps->desc, system_has_cap, cpu_has_cap);
3170 if (cpucap_panic_on_conflict(caps))
3178 * Check for CPU features that are used in early boot
3179 * based on the Boot CPU value.
3181 static void check_early_cpu_features(void)
3183 verify_cpu_asid_bits();
3185 verify_local_cpu_caps(SCOPE_BOOT_CPU);
3189 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
3192 for (; caps->matches; caps++)
3193 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
3194 pr_crit("CPU%d: missing HWCAP: %s\n",
3195 smp_processor_id(), caps->desc);
3200 static void verify_local_elf_hwcaps(void)
3202 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
3204 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
3205 __verify_local_elf_hwcaps(compat_elf_hwcaps);
3208 static void verify_sve_features(void)
3210 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
3211 u64 zcr = read_zcr_features();
3213 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
3214 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
3216 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SVE)) {
3217 pr_crit("CPU%d: SVE: vector length support mismatch\n",
3218 smp_processor_id());
3222 /* Add checks on other ZCR bits here if necessary */
3225 static void verify_sme_features(void)
3227 u64 safe_smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1);
3228 u64 smcr = read_smcr_features();
3230 unsigned int safe_len = safe_smcr & SMCR_ELx_LEN_MASK;
3231 unsigned int len = smcr & SMCR_ELx_LEN_MASK;
3233 if (len < safe_len || vec_verify_vq_map(ARM64_VEC_SME)) {
3234 pr_crit("CPU%d: SME: vector length support mismatch\n",
3235 smp_processor_id());
3239 /* Add checks on other SMCR bits here if necessary */
3242 static void verify_hyp_capabilities(void)
3244 u64 safe_mmfr1, mmfr0, mmfr1;
3245 int parange, ipa_max;
3246 unsigned int safe_vmid_bits, vmid_bits;
3248 if (!IS_ENABLED(CONFIG_KVM))
3251 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
3252 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
3253 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
3255 /* Verify VMID bits */
3256 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
3257 vmid_bits = get_vmid_bits(mmfr1);
3258 if (vmid_bits < safe_vmid_bits) {
3259 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
3263 /* Verify IPA range */
3264 parange = cpuid_feature_extract_unsigned_field(mmfr0,
3265 ID_AA64MMFR0_EL1_PARANGE_SHIFT);
3266 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
3267 if (ipa_max < get_kvm_ipa_limit()) {
3268 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
3274 * Run through the enabled system capabilities and enable() it on this CPU.
3275 * The capabilities were decided based on the available CPUs at the boot time.
3276 * Any new CPU should match the system wide status of the capability. If the
3277 * new CPU doesn't have a capability which the system now has enabled, we
3278 * cannot do anything to fix it up and could cause unexpected failures. So
3281 static void verify_local_cpu_capabilities(void)
3284 * The capabilities with SCOPE_BOOT_CPU are checked from
3285 * check_early_cpu_features(), as they need to be verified
3286 * on all secondary CPUs.
3288 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3289 verify_local_elf_hwcaps();
3291 if (system_supports_sve())
3292 verify_sve_features();
3294 if (system_supports_sme())
3295 verify_sme_features();
3297 if (is_hyp_mode_available())
3298 verify_hyp_capabilities();
3301 void check_local_cpu_capabilities(void)
3304 * All secondary CPUs should conform to the early CPU features
3305 * in use by the kernel based on boot CPU.
3307 check_early_cpu_features();
3310 * If we haven't finalised the system capabilities, this CPU gets
3311 * a chance to update the errata work arounds and local features.
3312 * Otherwise, this CPU should verify that it has all the system
3313 * advertised capabilities.
3315 if (!system_capabilities_finalized())
3316 update_cpu_capabilities(SCOPE_LOCAL_CPU);
3318 verify_local_cpu_capabilities();
3321 static void __init setup_boot_cpu_capabilities(void)
3323 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
3324 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
3325 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
3326 enable_cpu_capabilities(SCOPE_BOOT_CPU);
3329 bool this_cpu_has_cap(unsigned int n)
3331 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
3332 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
3335 return cap->matches(cap, SCOPE_LOCAL_CPU);
3340 EXPORT_SYMBOL_GPL(this_cpu_has_cap);
3343 * This helper function is used in a narrow window when,
3344 * - The system wide safe registers are set with all the SMP CPUs and,
3345 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
3346 * In all other cases cpus_have_{const_}cap() should be used.
3348 static bool __maybe_unused __system_matches_cap(unsigned int n)
3350 if (n < ARM64_NCAPS) {
3351 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
3354 return cap->matches(cap, SCOPE_SYSTEM);
3359 void cpu_set_feature(unsigned int num)
3361 set_bit(num, elf_hwcap);
3364 bool cpu_have_feature(unsigned int num)
3366 return test_bit(num, elf_hwcap);
3368 EXPORT_SYMBOL_GPL(cpu_have_feature);
3370 unsigned long cpu_get_elf_hwcap(void)
3373 * We currently only populate the first 32 bits of AT_HWCAP. Please
3374 * note that for userspace compatibility we guarantee that bits 62
3375 * and 63 will always be returned as 0.
3377 return elf_hwcap[0];
3380 unsigned long cpu_get_elf_hwcap2(void)
3382 return elf_hwcap[1];
3385 static void __init setup_system_capabilities(void)
3388 * We have finalised the system-wide safe feature
3389 * registers, finalise the capabilities that depend
3390 * on it. Also enable all the available capabilities,
3391 * that are not enabled already.
3393 update_cpu_capabilities(SCOPE_SYSTEM);
3394 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
3397 void __init setup_cpu_features(void)
3401 setup_system_capabilities();
3402 setup_elf_hwcaps(arm64_elf_hwcaps);
3404 if (system_supports_32bit_el0()) {
3405 setup_elf_hwcaps(compat_elf_hwcaps);
3409 if (system_uses_ttbr0_pan())
3410 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
3414 minsigstksz_setup();
3417 * Check for sane CTR_EL0.CWG value.
3419 cwg = cache_type_cwg();
3421 pr_warn("No Cache Writeback Granule information, assuming %d\n",
3425 static int enable_mismatched_32bit_el0(unsigned int cpu)
3428 * The first 32-bit-capable CPU we detected and so can no longer
3429 * be offlined by userspace. -1 indicates we haven't yet onlined
3430 * a 32-bit-capable CPU.
3432 static int lucky_winner = -1;
3434 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
3435 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
3438 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
3439 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
3442 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
3445 if (lucky_winner >= 0)
3449 * We've detected a mismatch. We need to keep one of our CPUs with
3450 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
3451 * every CPU in the system for a 32-bit task.
3453 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
3455 get_cpu_device(lucky_winner)->offline_disabled = true;
3456 setup_elf_hwcaps(compat_elf_hwcaps);
3458 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
3463 static int __init init_32bit_el0_mask(void)
3465 if (!allow_mismatched_32bit_el0)
3468 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
3471 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
3472 "arm64/mismatched_32bit_el0:online",
3473 enable_mismatched_32bit_el0, NULL);
3475 subsys_initcall_sync(init_32bit_el0_mask);
3477 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
3479 cpu_replace_ttbr1(lm_alias(swapper_pg_dir), idmap_pg_dir);
3483 * We emulate only the following system register space.
3484 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]
3485 * See Table C5-6 System instruction encodings for System register accesses,
3486 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
3488 static inline bool __attribute_const__ is_emulated(u32 id)
3490 return (sys_reg_Op0(id) == 0x3 &&
3491 sys_reg_CRn(id) == 0x0 &&
3492 sys_reg_Op1(id) == 0x0 &&
3493 (sys_reg_CRm(id) == 0 ||
3494 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7))));
3498 * With CRm == 0, reg should be one of :
3499 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3501 static inline int emulate_id_reg(u32 id, u64 *valp)
3505 *valp = read_cpuid_id();
3508 *valp = SYS_MPIDR_SAFE_VAL;
3510 case SYS_REVIDR_EL1:
3511 /* IMPLEMENTATION DEFINED values are emulated with 0 */
3521 static int emulate_sys_reg(u32 id, u64 *valp)
3523 struct arm64_ftr_reg *regp;
3525 if (!is_emulated(id))
3528 if (sys_reg_CRm(id) == 0)
3529 return emulate_id_reg(id, valp);
3531 regp = get_arm64_ftr_reg_nowarn(id);
3533 *valp = arm64_ftr_reg_user_value(regp);
3536 * The untracked registers are either IMPLEMENTATION DEFINED
3537 * (e.g, ID_AFR0_EL1) or reserved RAZ.
3543 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3548 rc = emulate_sys_reg(sys_reg, &val);
3550 pt_regs_write_reg(regs, rt, val);
3551 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3556 bool try_emulate_mrs(struct pt_regs *regs, u32 insn)
3560 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn))
3564 * sys_reg values are defined as used in mrs/msr instruction.
3565 * shift the imm value to get the encoding.
3567 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3568 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3569 return do_emulate_mrs(regs, sys_reg, rt) == 0;
3572 enum mitigation_state arm64_get_meltdown_state(void)
3574 if (__meltdown_safe)
3575 return SPECTRE_UNAFFECTED;
3577 if (arm64_kernel_unmapped_at_el0())
3578 return SPECTRE_MITIGATED;
3580 return SPECTRE_VULNERABLE;
3583 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3586 switch (arm64_get_meltdown_state()) {
3587 case SPECTRE_UNAFFECTED:
3588 return sprintf(buf, "Not affected\n");
3590 case SPECTRE_MITIGATED:
3591 return sprintf(buf, "Mitigation: PTI\n");
3594 return sprintf(buf, "Vulnerable\n");