1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU specific errata definitions
5 * Copyright (C) 2014 ARM Ltd.
8 #include <linux/arm-smccc.h>
9 #include <linux/types.h>
10 #include <linux/cpu.h>
12 #include <asm/cputype.h>
13 #include <asm/cpufeature.h>
14 #include <asm/kvm_asm.h>
15 #include <asm/smp_plat.h>
17 static bool __maybe_unused
18 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
20 const struct arm64_midr_revidr *fix;
21 u32 midr = read_cpuid_id(), revidr;
23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
24 if (!is_midr_in_range(midr, &entry->midr_range))
27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
28 revidr = read_cpuid(REVIDR_EL1);
29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
36 static bool __maybe_unused
37 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
44 static bool __maybe_unused
45 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
51 model = read_cpuid_id();
52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
53 MIDR_ARCHITECTURE_MASK;
55 return model == entry->midr_range.model;
59 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
64 u64 ctr_raw, ctr_real;
66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
69 * We want to make sure that all the CPUs in the system expose
70 * a consistent CTR_EL0 to make sure that applications behaves
71 * correctly with migration.
73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
75 * 1) It is safe if the system doesn't support IDC, as CPU anyway
76 * reports IDC = 0, consistent with the rest.
78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0
79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability.
81 * So, we need to make sure either the raw CTR_EL0 or the effective
82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
84 ctr_raw = read_cpuid_cachetype() & mask;
85 ctr_real = read_cpuid_effective_cachetype() & mask;
87 return (ctr_real != sys) && (ctr_raw != sys);
91 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
94 bool enable_uct_trap = false;
96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
97 if ((read_cpuid_cachetype() & mask) !=
98 (arm64_ftr_reg_ctrel0.sys_val & mask))
99 enable_uct_trap = true;
101 /* ... or if the system is affected by an erratum */
102 if (cap->capability == ARM64_WORKAROUND_1542419)
103 enable_uct_trap = true;
106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
109 #ifdef CONFIG_ARM64_ERRATUM_1463225
111 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
114 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
118 static void __maybe_unused
119 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
121 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
124 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
125 .matches = is_affected_midr_range, \
126 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
128 #define CAP_MIDR_ALL_VERSIONS(model) \
129 .matches = is_affected_midr_range, \
130 .midr_range = MIDR_ALL_VERSIONS(model)
132 #define MIDR_FIXED(rev, revidr_mask) \
133 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
135 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
136 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
137 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
139 #define CAP_MIDR_RANGE_LIST(list) \
140 .matches = is_affected_midr_range_list, \
141 .midr_range_list = list
143 /* Errata affecting a range of revisions of given model variant */
144 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
145 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
147 /* Errata affecting a single variant/revision of a model */
148 #define ERRATA_MIDR_REV(model, var, rev) \
149 ERRATA_MIDR_RANGE(model, var, rev, var, rev)
151 /* Errata affecting all variants/revisions of a given a model */
152 #define ERRATA_MIDR_ALL_VERSIONS(model) \
153 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
154 CAP_MIDR_ALL_VERSIONS(model)
156 /* Errata affecting a list of midr ranges, with same work around */
157 #define ERRATA_MIDR_RANGE_LIST(midr_list) \
158 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
159 CAP_MIDR_RANGE_LIST(midr_list)
161 static const __maybe_unused struct midr_range tx2_family_cpus[] = {
162 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
163 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
167 static bool __maybe_unused
168 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
173 if (!is_affected_midr_range_list(entry, scope) ||
174 !is_hyp_mode_available())
177 for_each_possible_cpu(i) {
178 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
185 static bool __maybe_unused
186 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
189 u32 midr = read_cpuid_id();
190 bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
191 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
193 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
194 return is_midr_in_range(midr, &range) && has_dic;
197 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
198 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
199 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
201 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
204 .midr_range.model = MIDR_QCOM_KRYO,
205 .matches = is_kryo_midr,
208 #ifdef CONFIG_ARM64_ERRATUM_1286807
210 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
217 #ifdef CONFIG_CAVIUM_ERRATUM_27456
218 const struct midr_range cavium_erratum_27456_cpus[] = {
219 /* Cavium ThunderX, T88 pass 1.x - 2.1 */
220 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
221 /* Cavium ThunderX, T81 pass 1.0 */
222 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
227 #ifdef CONFIG_CAVIUM_ERRATUM_30115
228 static const struct midr_range cavium_erratum_30115_cpus[] = {
229 /* Cavium ThunderX, T88 pass 1.x - 2.2 */
230 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
231 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
232 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
233 /* Cavium ThunderX, T83 pass 1.0 */
234 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
239 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
240 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
242 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
245 .midr_range.model = MIDR_QCOM_KRYO,
246 .matches = is_kryo_midr,
252 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
253 static const struct midr_range workaround_clean_cache[] = {
254 #if defined(CONFIG_ARM64_ERRATUM_826319) || \
255 defined(CONFIG_ARM64_ERRATUM_827319) || \
256 defined(CONFIG_ARM64_ERRATUM_824069)
257 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
258 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
260 #ifdef CONFIG_ARM64_ERRATUM_819472
261 /* Cortex-A53 r0p[01] : ARM errata 819472 */
262 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
268 #ifdef CONFIG_ARM64_ERRATUM_1418040
270 * - 1188873 affects r0p0 to r2p0
271 * - 1418040 affects r0p0 to r3p1
273 static const struct midr_range erratum_1418040_list[] = {
274 /* Cortex-A76 r0p0 to r3p1 */
275 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
276 /* Neoverse-N1 r0p0 to r3p1 */
277 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
278 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
279 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
284 #ifdef CONFIG_ARM64_ERRATUM_845719
285 static const struct midr_range erratum_845719_list[] = {
286 /* Cortex-A53 r0p[01234] */
287 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
288 /* Brahma-B53 r0p[0] */
289 MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
290 /* Kryo2XX Silver rAp4 */
291 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
296 #ifdef CONFIG_ARM64_ERRATUM_843419
297 static const struct arm64_cpu_capabilities erratum_843419_list[] = {
299 /* Cortex-A53 r0p[01234] */
300 .matches = is_affected_midr_range,
301 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
302 MIDR_FIXED(0x4, BIT(8)),
305 /* Brahma-B53 r0p[0] */
306 .matches = is_affected_midr_range,
307 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
313 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
314 static const struct midr_range erratum_speculative_at_list[] = {
315 #ifdef CONFIG_ARM64_ERRATUM_1165522
316 /* Cortex A76 r0p0 to r2p0 */
317 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
319 #ifdef CONFIG_ARM64_ERRATUM_1319367
320 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
321 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
323 #ifdef CONFIG_ARM64_ERRATUM_1530923
324 /* Cortex A55 r0p0 to r2p0 */
325 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
326 /* Kryo4xx Silver (rdpe => r1p0) */
327 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
333 #ifdef CONFIG_ARM64_ERRATUM_1463225
334 static const struct midr_range erratum_1463225[] = {
335 /* Cortex-A76 r0p0 - r3p1 */
336 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
337 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
338 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
343 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
344 static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
345 #ifdef CONFIG_ARM64_ERRATUM_2139208
346 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
348 #ifdef CONFIG_ARM64_ERRATUM_2119858
349 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
350 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
354 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
356 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
357 static const struct midr_range tsb_flush_fail_cpus[] = {
358 #ifdef CONFIG_ARM64_ERRATUM_2067961
359 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
361 #ifdef CONFIG_ARM64_ERRATUM_2054223
362 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
366 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */
368 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
369 static struct midr_range trbe_write_out_of_range_cpus[] = {
370 #ifdef CONFIG_ARM64_ERRATUM_2253138
371 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
373 #ifdef CONFIG_ARM64_ERRATUM_2224489
374 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
375 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0),
379 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
381 const struct arm64_cpu_capabilities arm64_errata[] = {
382 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
384 .desc = "ARM errata 826319, 827319, 824069, or 819472",
385 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
386 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
387 .cpu_enable = cpu_enable_cache_maint_trap,
390 #ifdef CONFIG_ARM64_ERRATUM_832075
392 /* Cortex-A57 r0p0 - r1p2 */
393 .desc = "ARM erratum 832075",
394 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
395 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
400 #ifdef CONFIG_ARM64_ERRATUM_834220
402 /* Cortex-A57 r0p0 - r1p2 */
403 .desc = "ARM erratum 834220",
404 .capability = ARM64_WORKAROUND_834220,
405 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
410 #ifdef CONFIG_ARM64_ERRATUM_843419
412 .desc = "ARM erratum 843419",
413 .capability = ARM64_WORKAROUND_843419,
414 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
415 .matches = cpucap_multi_entry_cap_matches,
416 .match_list = erratum_843419_list,
419 #ifdef CONFIG_ARM64_ERRATUM_845719
421 .desc = "ARM erratum 845719",
422 .capability = ARM64_WORKAROUND_845719,
423 ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
426 #ifdef CONFIG_CAVIUM_ERRATUM_23154
428 /* Cavium ThunderX, pass 1.x */
429 .desc = "Cavium erratum 23154",
430 .capability = ARM64_WORKAROUND_CAVIUM_23154,
431 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
434 #ifdef CONFIG_CAVIUM_ERRATUM_27456
436 .desc = "Cavium erratum 27456",
437 .capability = ARM64_WORKAROUND_CAVIUM_27456,
438 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
441 #ifdef CONFIG_CAVIUM_ERRATUM_30115
443 .desc = "Cavium erratum 30115",
444 .capability = ARM64_WORKAROUND_CAVIUM_30115,
445 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
449 .desc = "Mismatched cache type (CTR_EL0)",
450 .capability = ARM64_MISMATCHED_CACHE_TYPE,
451 .matches = has_mismatched_cache_type,
452 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
453 .cpu_enable = cpu_enable_trap_ctr_access,
455 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
457 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
458 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
459 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
460 .matches = cpucap_multi_entry_cap_matches,
461 .match_list = qcom_erratum_1003_list,
464 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
466 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
467 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
468 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
469 .matches = cpucap_multi_entry_cap_matches,
470 .match_list = arm64_repeat_tlbi_list,
473 #ifdef CONFIG_ARM64_ERRATUM_858921
475 /* Cortex-A73 all versions */
476 .desc = "ARM erratum 858921",
477 .capability = ARM64_WORKAROUND_858921,
478 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
482 .desc = "Spectre-v2",
483 .capability = ARM64_SPECTRE_V2,
484 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
485 .matches = has_spectre_v2,
486 .cpu_enable = spectre_v2_enable_mitigation,
488 #ifdef CONFIG_RANDOMIZE_BASE
490 /* Must come after the Spectre-v2 entry */
491 .desc = "Spectre-v3a",
492 .capability = ARM64_SPECTRE_V3A,
493 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
494 .matches = has_spectre_v3a,
495 .cpu_enable = spectre_v3a_enable_mitigation,
499 .desc = "Spectre-v4",
500 .capability = ARM64_SPECTRE_V4,
501 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
502 .matches = has_spectre_v4,
503 .cpu_enable = spectre_v4_enable_mitigation,
506 .desc = "Spectre-BHB",
507 .capability = ARM64_SPECTRE_BHB,
508 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
509 .matches = is_spectre_bhb_affected,
510 .cpu_enable = spectre_bhb_enable_mitigation,
512 #ifdef CONFIG_ARM64_ERRATUM_1418040
514 .desc = "ARM erratum 1418040",
515 .capability = ARM64_WORKAROUND_1418040,
516 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
518 * We need to allow affected CPUs to come in late, but
519 * also need the non-affected CPUs to be able to come
520 * in at any point in time. Wonderful.
522 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
525 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
527 .desc = "ARM errata 1165522, 1319367, or 1530923",
528 .capability = ARM64_WORKAROUND_SPECULATIVE_AT,
529 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
532 #ifdef CONFIG_ARM64_ERRATUM_1463225
534 .desc = "ARM erratum 1463225",
535 .capability = ARM64_WORKAROUND_1463225,
536 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
537 .matches = has_cortex_a76_erratum_1463225,
538 .midr_range_list = erratum_1463225,
541 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
543 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
544 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
545 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
546 .matches = needs_tx2_tvm_workaround,
549 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
550 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
551 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
554 #ifdef CONFIG_ARM64_ERRATUM_1542419
556 /* we depend on the firmware portion for correctness */
557 .desc = "ARM erratum 1542419 (kernel portion)",
558 .capability = ARM64_WORKAROUND_1542419,
559 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
560 .matches = has_neoverse_n1_erratum_1542419,
561 .cpu_enable = cpu_enable_trap_ctr_access,
564 #ifdef CONFIG_ARM64_ERRATUM_1508412
566 /* we depend on the firmware portion for correctness */
567 .desc = "ARM erratum 1508412 (kernel portion)",
568 .capability = ARM64_WORKAROUND_1508412,
569 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
574 #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
577 .desc = "NVIDIA Carmel CNP erratum",
578 .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
579 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
582 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
585 * The erratum work around is handled within the TRBE
586 * driver and can be applied per-cpu. So, we can allow
587 * a late CPU to come online with this erratum.
589 .desc = "ARM erratum 2119858 or 2139208",
590 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
591 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
592 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
595 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
597 .desc = "ARM erratum 2067961 or 2054223",
598 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,
599 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),
602 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
604 .desc = "ARM erratum 2253138 or 2224489",
605 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,
606 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
607 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
610 #ifdef CONFIG_ARM64_ERRATUM_2077057
612 .desc = "ARM erratum 2077057",
613 .capability = ARM64_WORKAROUND_2077057,
614 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
617 #ifdef CONFIG_ARM64_ERRATUM_2064142
619 .desc = "ARM erratum 2064142",
620 .capability = ARM64_WORKAROUND_2064142,
622 /* Cortex-A510 r0p0 - r0p2 */
623 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
626 #ifdef CONFIG_ARM64_ERRATUM_2038923
628 .desc = "ARM erratum 2038923",
629 .capability = ARM64_WORKAROUND_2038923,
631 /* Cortex-A510 r0p0 - r0p2 */
632 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
635 #ifdef CONFIG_ARM64_ERRATUM_1902691
637 .desc = "ARM erratum 1902691",
638 .capability = ARM64_WORKAROUND_1902691,
640 /* Cortex-A510 r0p0 - r0p1 */
641 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1)