arch/arm64/kernel/cpu_errata.c

   1 /*
   2  * Contains CPU specific errata definitions
   3  *
   4  * Copyright (C) 2014 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/arm-smccc.h>
  20 #include <linux/psci.h>
  21 #include <linux/types.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cputype.h>
  24 #include <asm/cpufeature.h>
  25
  26 static bool __maybe_unused
  27 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
  28 {
  29         const struct arm64_midr_revidr *fix;
  30         u32 midr = read_cpuid_id(), revidr;
  31
  32         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  33         if (!is_midr_in_range(midr, &entry->midr_range))
  34                 return false;
  35
  36         midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
  37         revidr = read_cpuid(REVIDR_EL1);
  38         for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
  39                 if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
  40                         return false;
  41
  42         return true;
  43 }
  44
  45 static bool __maybe_unused
  46 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
  47                             int scope)
  48 {
  49         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  50         return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
  51 }
  52
  53 static bool __maybe_unused
  54 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
  55 {
  56         u32 model;
  57
  58         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  59
  60         model = read_cpuid_id();
  61         model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
  62                  MIDR_ARCHITECTURE_MASK;
  63
  64         return model == entry->midr_range.model;
  65 }
  66
  67 static bool
  68 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
  69                           int scope)
  70 {
  71         u64 mask = CTR_CACHE_MINLINE_MASK;
  72
  73         /* Skip matching the min line sizes for cache type check */
  74         if (entry->capability == ARM64_MISMATCHED_CACHE_TYPE)
  75                 mask ^= arm64_ftr_reg_ctrel0.strict_mask;
  76
  77         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  78         return (read_cpuid_cachetype() & mask) !=
  79                (arm64_ftr_reg_ctrel0.sys_val & mask);
  80 }
  81
  82 static void
  83 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
  84 {
  85         sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
  86 }
  87
  88 atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
  89
  90 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
  91 #include <asm/mmu_context.h>
  92 #include <asm/cacheflush.h>
  93
  94 DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
  95
  96 #ifdef CONFIG_KVM_INDIRECT_VECTORS
  97 extern char __smccc_workaround_1_smc_start[];
  98 extern char __smccc_workaround_1_smc_end[];
  99
 100 static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
 101                                 const char *hyp_vecs_end)
 102 {
 103         void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
 104         int i;
 105
 106         for (i = 0; i < SZ_2K; i += 0x80)
 107                 memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
 108
 109         __flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
 110 }
 111
 112 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
 113                                       const char *hyp_vecs_start,
 114                                       const char *hyp_vecs_end)
 115 {
 116         static DEFINE_SPINLOCK(bp_lock);
 117         int cpu, slot = -1;
 118
 119         spin_lock(&bp_lock);
 120         for_each_possible_cpu(cpu) {
 121                 if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
 122                         slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
 123                         break;
 124                 }
 125         }
 126
 127         if (slot == -1) {
 128                 slot = atomic_inc_return(&arm64_el2_vector_last_slot);
 129                 BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
 130                 __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
 131         }
 132
 133         __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
 134         __this_cpu_write(bp_hardening_data.fn, fn);
 135         spin_unlock(&bp_lock);
 136 }
 137 #else
 138 #define __smccc_workaround_1_smc_start          NULL
 139 #define __smccc_workaround_1_smc_end            NULL
 140
 141 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
 142                                       const char *hyp_vecs_start,
 143                                       const char *hyp_vecs_end)
 144 {
 145         __this_cpu_write(bp_hardening_data.fn, fn);
 146 }
 147 #endif  /* CONFIG_KVM_INDIRECT_VECTORS */
 148
 149 static void  install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
 150                                      bp_hardening_cb_t fn,
 151                                      const char *hyp_vecs_start,
 152                                      const char *hyp_vecs_end)
 153 {
 154         u64 pfr0;
 155
 156         if (!entry->matches(entry, SCOPE_LOCAL_CPU))
 157                 return;
 158
 159         pfr0 = read_cpuid(ID_AA64PFR0_EL1);
 160         if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
 161                 return;
 162
 163         __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
 164 }
 165
 166 #include <uapi/linux/psci.h>
 167 #include <linux/arm-smccc.h>
 168 #include <linux/psci.h>
 169
 170 static void call_smc_arch_workaround_1(void)
 171 {
 172         arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
 173 }
 174
 175 static void call_hvc_arch_workaround_1(void)
 176 {
 177         arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
 178 }
 179
 180 static void qcom_link_stack_sanitization(void)
 181 {
 182         u64 tmp;
 183
 184         asm volatile("mov       %0, x30         \n"
 185                      ".rept     16              \n"
 186                      "bl        . + 4           \n"
 187                      ".endr                     \n"
 188                      "mov       x30, %0         \n"
 189                      : "=&r" (tmp));
 190 }
 191
 192 static void
 193 enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
 194 {
 195         bp_hardening_cb_t cb;
 196         void *smccc_start, *smccc_end;
 197         struct arm_smccc_res res;
 198         u32 midr = read_cpuid_id();
 199
 200         if (!entry->matches(entry, SCOPE_LOCAL_CPU))
 201                 return;
 202
 203         if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
 204                 return;
 205
 206         switch (psci_ops.conduit) {
 207         case PSCI_CONDUIT_HVC:
 208                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 209                                   ARM_SMCCC_ARCH_WORKAROUND_1, &res);
 210                 if ((int)res.a0 < 0)
 211                         return;
 212                 cb = call_hvc_arch_workaround_1;
 213                 /* This is a guest, no need to patch KVM vectors */
 214                 smccc_start = NULL;
 215                 smccc_end = NULL;
 216                 break;
 217
 218         case PSCI_CONDUIT_SMC:
 219                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 220                                   ARM_SMCCC_ARCH_WORKAROUND_1, &res);
 221                 if ((int)res.a0 < 0)
 222                         return;
 223                 cb = call_smc_arch_workaround_1;
 224                 smccc_start = __smccc_workaround_1_smc_start;
 225                 smccc_end = __smccc_workaround_1_smc_end;
 226                 break;
 227
 228         default:
 229                 return;
 230         }
 231
 232         if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
 233             ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
 234                 cb = qcom_link_stack_sanitization;
 235
 236         install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
 237
 238         return;
 239 }
 240 #endif  /* CONFIG_HARDEN_BRANCH_PREDICTOR */
 241
 242 DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
 243
 244 int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
 245
 246 static const struct ssbd_options {
 247         const char      *str;
 248         int             state;
 249 } ssbd_options[] = {
 250         { "force-on",   ARM64_SSBD_FORCE_ENABLE, },
 251         { "force-off",  ARM64_SSBD_FORCE_DISABLE, },
 252         { "kernel",     ARM64_SSBD_KERNEL, },
 253 };
 254
 255 static int __init ssbd_cfg(char *buf)
 256 {
 257         int i;
 258
 259         if (!buf || !buf[0])
 260                 return -EINVAL;
 261
 262         for (i = 0; i < ARRAY_SIZE(ssbd_options); i++) {
 263                 int len = strlen(ssbd_options[i].str);
 264
 265                 if (strncmp(buf, ssbd_options[i].str, len))
 266                         continue;
 267
 268                 ssbd_state = ssbd_options[i].state;
 269                 return 0;
 270         }
 271
 272         return -EINVAL;
 273 }
 274 early_param("ssbd", ssbd_cfg);
 275
 276 void __init arm64_update_smccc_conduit(struct alt_instr *alt,
 277                                        __le32 *origptr, __le32 *updptr,
 278                                        int nr_inst)
 279 {
 280         u32 insn;
 281
 282         BUG_ON(nr_inst != 1);
 283
 284         switch (psci_ops.conduit) {
 285         case PSCI_CONDUIT_HVC:
 286                 insn = aarch64_insn_get_hvc_value();
 287                 break;
 288         case PSCI_CONDUIT_SMC:
 289                 insn = aarch64_insn_get_smc_value();
 290                 break;
 291         default:
 292                 return;
 293         }
 294
 295         *updptr = cpu_to_le32(insn);
 296 }
 297
 298 void __init arm64_enable_wa2_handling(struct alt_instr *alt,
 299                                       __le32 *origptr, __le32 *updptr,
 300                                       int nr_inst)
 301 {
 302         BUG_ON(nr_inst != 1);
 303         /*
 304          * Only allow mitigation on EL1 entry/exit and guest
 305          * ARCH_WORKAROUND_2 handling if the SSBD state allows it to
 306          * be flipped.
 307          */
 308         if (arm64_get_ssbd_state() == ARM64_SSBD_KERNEL)
 309                 *updptr = cpu_to_le32(aarch64_insn_gen_nop());
 310 }
 311
 312 void arm64_set_ssbd_mitigation(bool state)
 313 {
 314         if (!IS_ENABLED(CONFIG_ARM64_SSBD)) {
 315                 pr_info_once("SSBD disabled by kernel configuration\n");
 316                 return;
 317         }
 318
 319         if (this_cpu_has_cap(ARM64_SSBS)) {
 320                 if (state)
 321                         asm volatile(SET_PSTATE_SSBS(0));
 322                 else
 323                         asm volatile(SET_PSTATE_SSBS(1));
 324                 return;
 325         }
 326
 327         switch (psci_ops.conduit) {
 328         case PSCI_CONDUIT_HVC:
 329                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
 330                 break;
 331
 332         case PSCI_CONDUIT_SMC:
 333                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
 334                 break;
 335
 336         default:
 337                 WARN_ON_ONCE(1);
 338                 break;
 339         }
 340 }
 341
 342 static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
 343                                     int scope)
 344 {
 345         struct arm_smccc_res res;
 346         bool required = true;
 347         s32 val;
 348
 349         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
 350
 351         if (this_cpu_has_cap(ARM64_SSBS)) {
 352                 required = false;
 353                 goto out_printmsg;
 354         }
 355
 356         if (psci_ops.smccc_version == SMCCC_VERSION_1_0) {
 357                 ssbd_state = ARM64_SSBD_UNKNOWN;
 358                 return false;
 359         }
 360
 361         switch (psci_ops.conduit) {
 362         case PSCI_CONDUIT_HVC:
 363                 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 364                                   ARM_SMCCC_ARCH_WORKAROUND_2, &res);
 365                 break;
 366
 367         case PSCI_CONDUIT_SMC:
 368                 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
 369                                   ARM_SMCCC_ARCH_WORKAROUND_2, &res);
 370                 break;
 371
 372         default:
 373                 ssbd_state = ARM64_SSBD_UNKNOWN;
 374                 return false;
 375         }
 376
 377         val = (s32)res.a0;
 378
 379         switch (val) {
 380         case SMCCC_RET_NOT_SUPPORTED:
 381                 ssbd_state = ARM64_SSBD_UNKNOWN;
 382                 return false;
 383
 384         case SMCCC_RET_NOT_REQUIRED:
 385                 pr_info_once("%s mitigation not required\n", entry->desc);
 386                 ssbd_state = ARM64_SSBD_MITIGATED;
 387                 return false;
 388
 389         case SMCCC_RET_SUCCESS:
 390                 required = true;
 391                 break;
 392
 393         case 1: /* Mitigation not required on this CPU */
 394                 required = false;
 395                 break;
 396
 397         default:
 398                 WARN_ON(1);
 399                 return false;
 400         }
 401
 402         switch (ssbd_state) {
 403         case ARM64_SSBD_FORCE_DISABLE:
 404                 arm64_set_ssbd_mitigation(false);
 405                 required = false;
 406                 break;
 407
 408         case ARM64_SSBD_KERNEL:
 409                 if (required) {
 410                         __this_cpu_write(arm64_ssbd_callback_required, 1);
 411                         arm64_set_ssbd_mitigation(true);
 412                 }
 413                 break;
 414
 415         case ARM64_SSBD_FORCE_ENABLE:
 416                 arm64_set_ssbd_mitigation(true);
 417                 required = true;
 418                 break;
 419
 420         default:
 421                 WARN_ON(1);
 422                 break;
 423         }
 424
 425 out_printmsg:
 426         switch (ssbd_state) {
 427         case ARM64_SSBD_FORCE_DISABLE:
 428                 pr_info_once("%s disabled from command-line\n", entry->desc);
 429                 break;
 430
 431         case ARM64_SSBD_FORCE_ENABLE:
 432                 pr_info_once("%s forced from command-line\n", entry->desc);
 433                 break;
 434         }
 435
 436         return required;
 437 }
 438
 439 #ifdef CONFIG_ARM64_ERRATUM_1463225
 440 DEFINE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa);
 441
 442 static bool
 443 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
 444                                int scope)
 445 {
 446         u32 midr = read_cpuid_id();
 447         /* Cortex-A76 r0p0 - r3p1 */
 448         struct midr_range range = MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1);
 449
 450         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
 451         return is_midr_in_range(midr, &range) && is_kernel_in_hyp_mode();
 452 }
 453 #endif
 454
 455 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)       \
 456         .matches = is_affected_midr_range,                      \
 457         .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
 458
 459 #define CAP_MIDR_ALL_VERSIONS(model)                                    \
 460         .matches = is_affected_midr_range,                              \
 461         .midr_range = MIDR_ALL_VERSIONS(model)
 462
 463 #define MIDR_FIXED(rev, revidr_mask) \
 464         .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
 465
 466 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max)            \
 467         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                         \
 468         CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
 469
 470 #define CAP_MIDR_RANGE_LIST(list)                               \
 471         .matches = is_affected_midr_range_list,                 \
 472         .midr_range_list = list
 473
 474 /* Errata affecting a range of revisions of  given model variant */
 475 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max)      \
 476         ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
 477
 478 /* Errata affecting a single variant/revision of a model */
 479 #define ERRATA_MIDR_REV(model, var, rev)        \
 480         ERRATA_MIDR_RANGE(model, var, rev, var, rev)
 481
 482 /* Errata affecting all variants/revisions of a given a model */
 483 #define ERRATA_MIDR_ALL_VERSIONS(model)                         \
 484         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                 \
 485         CAP_MIDR_ALL_VERSIONS(model)
 486
 487 /* Errata affecting a list of midr ranges, with same work around */
 488 #define ERRATA_MIDR_RANGE_LIST(midr_list)                       \
 489         .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                 \
 490         CAP_MIDR_RANGE_LIST(midr_list)
 491
 492 /*
 493  * Generic helper for handling capabilties with multiple (match,enable) pairs
 494  * of call backs, sharing the same capability bit.
 495  * Iterate over each entry to see if at least one matches.
 496  */
 497 static bool __maybe_unused
 498 multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, int scope)
 499 {
 500         const struct arm64_cpu_capabilities *caps;
 501
 502         for (caps = entry->match_list; caps->matches; caps++)
 503                 if (caps->matches(caps, scope))
 504                         return true;
 505
 506         return false;
 507 }
 508
 509 /*
 510  * Take appropriate action for all matching entries in the shared capability
 511  * entry.
 512  */
 513 static void __maybe_unused
 514 multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
 515 {
 516         const struct arm64_cpu_capabilities *caps;
 517
 518         for (caps = entry->match_list; caps->matches; caps++)
 519                 if (caps->matches(caps, SCOPE_LOCAL_CPU) &&
 520                     caps->cpu_enable)
 521                         caps->cpu_enable(caps);
 522 }
 523
 524 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 525
 526 /*
 527  * List of CPUs where we need to issue a psci call to
 528  * harden the branch predictor.
 529  */
 530 static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
 531         MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 532         MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 533         MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 534         MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
 535         MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 536         MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 537         MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
 538         MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
 539         MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER),
 540         {},
 541 };
 542
 543 #endif
 544
 545 #ifdef CONFIG_HARDEN_EL2_VECTORS
 546
 547 static const struct midr_range arm64_harden_el2_vectors[] = {
 548         MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 549         MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 550         {},
 551 };
 552
 553 #endif
 554
 555 const struct arm64_cpu_capabilities arm64_errata[] = {
 556 #if     defined(CONFIG_ARM64_ERRATUM_826319) || \
 557         defined(CONFIG_ARM64_ERRATUM_827319) || \
 558         defined(CONFIG_ARM64_ERRATUM_824069)
 559         {
 560         /* Cortex-A53 r0p[012] */
 561                 .desc = "ARM errata 826319, 827319, 824069",
 562                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
 563                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
 564                 .cpu_enable = cpu_enable_cache_maint_trap,
 565         },
 566 #endif
 567 #ifdef CONFIG_ARM64_ERRATUM_819472
 568         {
 569         /* Cortex-A53 r0p[01] */
 570                 .desc = "ARM errata 819472",
 571                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
 572                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
 573                 .cpu_enable = cpu_enable_cache_maint_trap,
 574         },
 575 #endif
 576 #ifdef CONFIG_ARM64_ERRATUM_832075
 577         {
 578         /* Cortex-A57 r0p0 - r1p2 */
 579                 .desc = "ARM erratum 832075",
 580                 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
 581                 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
 582                                   0, 0,
 583                                   1, 2),
 584         },
 585 #endif
 586 #ifdef CONFIG_ARM64_ERRATUM_834220
 587         {
 588         /* Cortex-A57 r0p0 - r1p2 */
 589                 .desc = "ARM erratum 834220",
 590                 .capability = ARM64_WORKAROUND_834220,
 591                 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
 592                                   0, 0,
 593                                   1, 2),
 594         },
 595 #endif
 596 #ifdef CONFIG_ARM64_ERRATUM_843419
 597         {
 598         /* Cortex-A53 r0p[01234] */
 599                 .desc = "ARM erratum 843419",
 600                 .capability = ARM64_WORKAROUND_843419,
 601                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
 602                 MIDR_FIXED(0x4, BIT(8)),
 603         },
 604 #endif
 605 #ifdef CONFIG_ARM64_ERRATUM_845719
 606         {
 607         /* Cortex-A53 r0p[01234] */
 608                 .desc = "ARM erratum 845719",
 609                 .capability = ARM64_WORKAROUND_845719,
 610                 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
 611         },
 612 #endif
 613 #ifdef CONFIG_CAVIUM_ERRATUM_23154
 614         {
 615         /* Cavium ThunderX, pass 1.x */
 616                 .desc = "Cavium erratum 23154",
 617                 .capability = ARM64_WORKAROUND_CAVIUM_23154,
 618                 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
 619         },
 620 #endif
 621 #ifdef CONFIG_CAVIUM_ERRATUM_27456
 622         {
 623         /* Cavium ThunderX, T88 pass 1.x - 2.1 */
 624                 .desc = "Cavium erratum 27456",
 625                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
 626                 ERRATA_MIDR_RANGE(MIDR_THUNDERX,
 627                                   0, 0,
 628                                   1, 1),
 629         },
 630         {
 631         /* Cavium ThunderX, T81 pass 1.0 */
 632                 .desc = "Cavium erratum 27456",
 633                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
 634                 ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
 635         },
 636 #endif
 637 #ifdef CONFIG_CAVIUM_ERRATUM_30115
 638         {
 639         /* Cavium ThunderX, T88 pass 1.x - 2.2 */
 640                 .desc = "Cavium erratum 30115",
 641                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 642                 ERRATA_MIDR_RANGE(MIDR_THUNDERX,
 643                                       0, 0,
 644                                       1, 2),
 645         },
 646         {
 647         /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
 648                 .desc = "Cavium erratum 30115",
 649                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 650                 ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
 651         },
 652         {
 653         /* Cavium ThunderX, T83 pass 1.0 */
 654                 .desc = "Cavium erratum 30115",
 655                 .capability = ARM64_WORKAROUND_CAVIUM_30115,
 656                 ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
 657         },
 658 #endif
 659         {
 660                 .desc = "Mismatched cache line size",
 661                 .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
 662                 .matches = has_mismatched_cache_type,
 663                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 664                 .cpu_enable = cpu_enable_trap_ctr_access,
 665         },
 666         {
 667                 .desc = "Mismatched cache type",
 668                 .capability = ARM64_MISMATCHED_CACHE_TYPE,
 669                 .matches = has_mismatched_cache_type,
 670                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 671                 .cpu_enable = cpu_enable_trap_ctr_access,
 672         },
 673 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 674         {
 675                 .desc = "Qualcomm Technologies Falkor erratum 1003",
 676                 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
 677                 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
 678         },
 679         {
 680                 .desc = "Qualcomm Technologies Kryo erratum 1003",
 681                 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
 682                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 683                 .midr_range.model = MIDR_QCOM_KRYO,
 684                 .matches = is_kryo_midr,
 685         },
 686 #endif
 687 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
 688         {
 689                 .desc = "Qualcomm Technologies Falkor erratum 1009",
 690                 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
 691                 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
 692         },
 693 #endif
 694 #ifdef CONFIG_ARM64_ERRATUM_858921
 695         {
 696         /* Cortex-A73 all versions */
 697                 .desc = "ARM erratum 858921",
 698                 .capability = ARM64_WORKAROUND_858921,
 699                 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 700         },
 701 #endif
 702 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 703         {
 704                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
 705                 .cpu_enable = enable_smccc_arch_workaround_1,
 706                 ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
 707         },
 708 #endif
 709 #ifdef CONFIG_HARDEN_EL2_VECTORS
 710         {
 711                 .desc = "EL2 vector hardening",
 712                 .capability = ARM64_HARDEN_EL2_VECTORS,
 713                 ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
 714         },
 715 #endif
 716         {
 717                 .desc = "Speculative Store Bypass Disable",
 718                 .capability = ARM64_SSBD,
 719                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 720                 .matches = has_ssbd_mitigation,
 721         },
 722 #ifdef CONFIG_ARM64_ERRATUM_1463225
 723         {
 724                 .desc = "ARM erratum 1463225",
 725                 .capability = ARM64_WORKAROUND_1463225,
 726                 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 727                 .matches = has_cortex_a76_erratum_1463225,
 728         },
 729 #endif
 730         {
 731         }
 732 };
 733
 734 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
 735                             char *buf)
 736 {
 737         return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 738 }