arch/arm64/include/uapi/asm/kvm.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Copyright (C) 2012,2013 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  *
   6  * Derived from arch/arm/include/uapi/asm/kvm.h:
   7  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   8  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __ARM_KVM_H__
  24 #define __ARM_KVM_H__
  25
  26 #define KVM_SPSR_EL1    0
  27 #define KVM_SPSR_SVC    KVM_SPSR_EL1
  28 #define KVM_SPSR_ABT    1
  29 #define KVM_SPSR_UND    2
  30 #define KVM_SPSR_IRQ    3
  31 #define KVM_SPSR_FIQ    4
  32 #define KVM_NR_SPSR     5
  33
  34 #ifndef __ASSEMBLY__
  35 #include <linux/psci.h>
  36 #include <linux/types.h>
  37 #include <asm/ptrace.h>
  38 #include <asm/sve_context.h>
  39
  40 #define __KVM_HAVE_GUEST_DEBUG
  41 #define __KVM_HAVE_IRQ_LINE
  42 #define __KVM_HAVE_READONLY_MEM
  43 #define __KVM_HAVE_VCPU_EVENTS
  44
  45 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  46
  47 #define KVM_REG_SIZE(id)                                                \
  48         (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
  49
  50 struct kvm_regs {
  51         struct user_pt_regs regs;       /* sp = sp_el0 */
  52
  53         __u64   sp_el1;
  54         __u64   elr_el1;
  55
  56         __u64   spsr[KVM_NR_SPSR];
  57
  58         struct user_fpsimd_state fp_regs;
  59 };
  60
  61 /*
  62  * Supported CPU Targets - Adding a new target type is not recommended,
  63  * unless there are some special registers not supported by the
  64  * genericv8 syreg table.
  65  */
  66 #define KVM_ARM_TARGET_AEM_V8           0
  67 #define KVM_ARM_TARGET_FOUNDATION_V8    1
  68 #define KVM_ARM_TARGET_CORTEX_A57       2
  69 #define KVM_ARM_TARGET_XGENE_POTENZA    3
  70 #define KVM_ARM_TARGET_CORTEX_A53       4
  71 /* Generic ARM v8 target */
  72 #define KVM_ARM_TARGET_GENERIC_V8       5
  73
  74 #define KVM_ARM_NUM_TARGETS             6
  75
  76 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
  77 #define KVM_ARM_DEVICE_TYPE_SHIFT       0
  78 #define KVM_ARM_DEVICE_TYPE_MASK        GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \
  79                                                 KVM_ARM_DEVICE_TYPE_SHIFT)
  80 #define KVM_ARM_DEVICE_ID_SHIFT         16
  81 #define KVM_ARM_DEVICE_ID_MASK          GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \
  82                                                 KVM_ARM_DEVICE_ID_SHIFT)
  83
  84 /* Supported device IDs */
  85 #define KVM_ARM_DEVICE_VGIC_V2          0
  86
  87 /* Supported VGIC address types  */
  88 #define KVM_VGIC_V2_ADDR_TYPE_DIST      0
  89 #define KVM_VGIC_V2_ADDR_TYPE_CPU       1
  90
  91 #define KVM_VGIC_V2_DIST_SIZE           0x1000
  92 #define KVM_VGIC_V2_CPU_SIZE            0x2000
  93
  94 /* Supported VGICv3 address types  */
  95 #define KVM_VGIC_V3_ADDR_TYPE_DIST      2
  96 #define KVM_VGIC_V3_ADDR_TYPE_REDIST    3
  97 #define KVM_VGIC_ITS_ADDR_TYPE          4
  98 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION     5
  99
 100 #define KVM_VGIC_V3_DIST_SIZE           SZ_64K
 101 #define KVM_VGIC_V3_REDIST_SIZE         (2 * SZ_64K)
 102 #define KVM_VGIC_V3_ITS_SIZE            (2 * SZ_64K)
 103
 104 #define KVM_ARM_VCPU_POWER_OFF          0 /* CPU is started in OFF state */
 105 #define KVM_ARM_VCPU_EL1_32BIT          1 /* CPU running a 32bit VM */
 106 #define KVM_ARM_VCPU_PSCI_0_2           2 /* CPU uses PSCI v0.2 */
 107 #define KVM_ARM_VCPU_PMU_V3             3 /* Support guest PMUv3 */
 108 #define KVM_ARM_VCPU_SVE                4 /* enable SVE for this CPU */
 109 #define KVM_ARM_VCPU_PTRAUTH_ADDRESS    5 /* VCPU uses address authentication */
 110 #define KVM_ARM_VCPU_PTRAUTH_GENERIC    6 /* VCPU uses generic authentication */
 111
 112 struct kvm_vcpu_init {
 113         __u32 target;
 114         __u32 features[7];
 115 };
 116
 117 struct kvm_sregs {
 118 };
 119
 120 struct kvm_fpu {
 121 };
 122
 123 /*
 124  * See v8 ARM ARM D7.3: Debug Registers
 125  *
 126  * The architectural limit is 16 debug registers of each type although
 127  * in practice there are usually less (see ID_AA64DFR0_EL1).
 128  *
 129  * Although the control registers are architecturally defined as 32
 130  * bits wide we use a 64 bit structure here to keep parity with
 131  * KVM_GET/SET_ONE_REG behaviour which treats all system registers as
 132  * 64 bit values. It also allows for the possibility of the
 133  * architecture expanding the control registers without having to
 134  * change the userspace ABI.
 135  */
 136 #define KVM_ARM_MAX_DBG_REGS 16
 137 struct kvm_guest_debug_arch {
 138         __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
 139         __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
 140         __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
 141         __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
 142 };
 143
 144 #define KVM_DEBUG_ARCH_HSR_HIGH_VALID   (1 << 0)
 145 struct kvm_debug_exit_arch {
 146         __u32 hsr;
 147         __u32 hsr_high; /* ESR_EL2[61:32] */
 148         __u64 far;      /* used for watchpoints */
 149 };
 150
 151 /*
 152  * Architecture specific defines for kvm_guest_debug->control
 153  */
 154
 155 #define KVM_GUESTDBG_USE_SW_BP          (1 << 16)
 156 #define KVM_GUESTDBG_USE_HW             (1 << 17)
 157
 158 struct kvm_sync_regs {
 159         /* Used with KVM_CAP_ARM_USER_IRQ */
 160         __u64 device_irq_level;
 161 };
 162
 163 /*
 164  * PMU filter structure. Describe a range of events with a particular
 165  * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER.
 166  */
 167 struct kvm_pmu_event_filter {
 168         __u16   base_event;
 169         __u16   nevents;
 170
 171 #define KVM_PMU_EVENT_ALLOW     0
 172 #define KVM_PMU_EVENT_DENY      1
 173
 174         __u8    action;
 175         __u8    pad[3];
 176 };
 177
 178 /* for KVM_GET/SET_VCPU_EVENTS */
 179 struct kvm_vcpu_events {
 180         struct {
 181                 __u8 serror_pending;
 182                 __u8 serror_has_esr;
 183                 __u8 ext_dabt_pending;
 184                 /* Align it to 8 bytes */
 185                 __u8 pad[5];
 186                 __u64 serror_esr;
 187         } exception;
 188         __u32 reserved[12];
 189 };
 190
 191 struct kvm_arm_copy_mte_tags {
 192         __u64 guest_ipa;
 193         __u64 length;
 194         void __user *addr;
 195         __u64 flags;
 196         __u64 reserved[2];
 197 };
 198
 199 #define KVM_ARM_TAGS_TO_GUEST           0
 200 #define KVM_ARM_TAGS_FROM_GUEST         1
 201
 202 /* If you need to interpret the index values, here is the key: */
 203 #define KVM_REG_ARM_COPROC_MASK         0x000000000FFF0000
 204 #define KVM_REG_ARM_COPROC_SHIFT        16
 205
 206 /* Normal registers are mapped as coprocessor 16. */
 207 #define KVM_REG_ARM_CORE                (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
 208 #define KVM_REG_ARM_CORE_REG(name)      (offsetof(struct kvm_regs, name) / sizeof(__u32))
 209
 210 /* Some registers need more space to represent values. */
 211 #define KVM_REG_ARM_DEMUX               (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
 212 #define KVM_REG_ARM_DEMUX_ID_MASK       0x000000000000FF00
 213 #define KVM_REG_ARM_DEMUX_ID_SHIFT      8
 214 #define KVM_REG_ARM_DEMUX_ID_CCSIDR     (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
 215 #define KVM_REG_ARM_DEMUX_VAL_MASK      0x00000000000000FF
 216 #define KVM_REG_ARM_DEMUX_VAL_SHIFT     0
 217
 218 /* AArch64 system registers */
 219 #define KVM_REG_ARM64_SYSREG            (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
 220 #define KVM_REG_ARM64_SYSREG_OP0_MASK   0x000000000000c000
 221 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT  14
 222 #define KVM_REG_ARM64_SYSREG_OP1_MASK   0x0000000000003800
 223 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT  11
 224 #define KVM_REG_ARM64_SYSREG_CRN_MASK   0x0000000000000780
 225 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT  7
 226 #define KVM_REG_ARM64_SYSREG_CRM_MASK   0x0000000000000078
 227 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT  3
 228 #define KVM_REG_ARM64_SYSREG_OP2_MASK   0x0000000000000007
 229 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT  0
 230
 231 #define ARM64_SYS_REG_SHIFT_MASK(x,n) \
 232         (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
 233         KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
 234
 235 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
 236         (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
 237         ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
 238         ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
 239         ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
 240         ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
 241         ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
 242
 243 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
 244
 245 /* Physical Timer EL0 Registers */
 246 #define KVM_REG_ARM_PTIMER_CTL          ARM64_SYS_REG(3, 3, 14, 2, 1)
 247 #define KVM_REG_ARM_PTIMER_CVAL         ARM64_SYS_REG(3, 3, 14, 2, 2)
 248 #define KVM_REG_ARM_PTIMER_CNT          ARM64_SYS_REG(3, 3, 14, 0, 1)
 249
 250 /*
 251  * EL0 Virtual Timer Registers
 252  *
 253  * WARNING:
 254  *      KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
 255  *      with the appropriate register encodings.  Their values have been
 256  *      accidentally swapped.  As this is set API, the definitions here
 257  *      must be used, rather than ones derived from the encodings.
 258  */
 259 #define KVM_REG_ARM_TIMER_CTL           ARM64_SYS_REG(3, 3, 14, 3, 1)
 260 #define KVM_REG_ARM_TIMER_CVAL          ARM64_SYS_REG(3, 3, 14, 0, 2)
 261 #define KVM_REG_ARM_TIMER_CNT           ARM64_SYS_REG(3, 3, 14, 3, 2)
 262
 263 /* KVM-as-firmware specific pseudo-registers */
 264 #define KVM_REG_ARM_FW                  (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
 265 #define KVM_REG_ARM_FW_REG(r)           (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
 266                                          KVM_REG_ARM_FW | ((r) & 0xffff))
 267 #define KVM_REG_ARM_PSCI_VERSION        KVM_REG_ARM_FW_REG(0)
 268 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1     KVM_REG_ARM_FW_REG(1)
 269 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL           0
 270 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL               1
 271 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED        2
 272
 273 /*
 274  * Only two states can be presented by the host kernel:
 275  * - NOT_REQUIRED: the guest doesn't need to do anything
 276  * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
 277  *
 278  * All the other values are deprecated. The host still accepts all
 279  * values (they are ABI), but will narrow them to the above two.
 280  */
 281 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2     KVM_REG_ARM_FW_REG(2)
 282 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL           0
 283 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN             1
 284 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL               2
 285 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED        3
 286 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED             (1U << 4)
 287
 288 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3     KVM_REG_ARM_FW_REG(3)
 289 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL           0
 290 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL               1
 291 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED        2
 292
 293 /* SVE registers */
 294 #define KVM_REG_ARM64_SVE               (0x15 << KVM_REG_ARM_COPROC_SHIFT)
 295
 296 /* Z- and P-regs occupy blocks at the following offsets within this range: */
 297 #define KVM_REG_ARM64_SVE_ZREG_BASE     0
 298 #define KVM_REG_ARM64_SVE_PREG_BASE     0x400
 299 #define KVM_REG_ARM64_SVE_FFR_BASE      0x600
 300
 301 #define KVM_ARM64_SVE_NUM_ZREGS         __SVE_NUM_ZREGS
 302 #define KVM_ARM64_SVE_NUM_PREGS         __SVE_NUM_PREGS
 303
 304 #define KVM_ARM64_SVE_MAX_SLICES        32
 305
 306 #define KVM_REG_ARM64_SVE_ZREG(n, i)                                    \
 307         (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \
 308          KVM_REG_SIZE_U2048 |                                           \
 309          (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) |                 \
 310          ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
 311
 312 #define KVM_REG_ARM64_SVE_PREG(n, i)                                    \
 313         (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \
 314          KVM_REG_SIZE_U256 |                                            \
 315          (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) |                 \
 316          ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
 317
 318 #define KVM_REG_ARM64_SVE_FFR(i)                                        \
 319         (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \
 320          KVM_REG_SIZE_U256 |                                            \
 321          ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
 322
 323 /*
 324  * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
 325  * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
 326  * invariant layout which differs from the layout used for the FPSIMD
 327  * V-registers on big-endian systems: see sigcontext.h for more explanation.
 328  */
 329
 330 #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
 331 #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
 332
 333 /* Vector lengths pseudo-register: */
 334 #define KVM_REG_ARM64_SVE_VLS           (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \
 335                                          KVM_REG_SIZE_U512 | 0xffff)
 336 #define KVM_ARM64_SVE_VLS_WORDS \
 337         ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
 338
 339 /* Bitmap feature firmware registers */
 340 #define KVM_REG_ARM_FW_FEAT_BMAP                (0x0016 << KVM_REG_ARM_COPROC_SHIFT)
 341 #define KVM_REG_ARM_FW_FEAT_BMAP_REG(r)         (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
 342                                                 KVM_REG_ARM_FW_FEAT_BMAP |      \
 343                                                 ((r) & 0xffff))
 344
 345 #define KVM_REG_ARM_STD_BMAP                    KVM_REG_ARM_FW_FEAT_BMAP_REG(0)
 346
 347 enum {
 348         KVM_REG_ARM_STD_BIT_TRNG_V1_0   = 0,
 349 #ifdef __KERNEL__
 350         KVM_REG_ARM_STD_BMAP_BIT_COUNT,
 351 #endif
 352 };
 353
 354 #define KVM_REG_ARM_STD_HYP_BMAP                KVM_REG_ARM_FW_FEAT_BMAP_REG(1)
 355
 356 enum {
 357         KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0,
 358 #ifdef __KERNEL__
 359         KVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT,
 360 #endif
 361 };
 362
 363 #define KVM_REG_ARM_VENDOR_HYP_BMAP             KVM_REG_ARM_FW_FEAT_BMAP_REG(2)
 364
 365 enum {
 366         KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT    = 0,
 367         KVM_REG_ARM_VENDOR_HYP_BIT_PTP          = 1,
 368 #ifdef __KERNEL__
 369         KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT,
 370 #endif
 371 };
 372
 373 /* Device Control API: ARM VGIC */
 374 #define KVM_DEV_ARM_VGIC_GRP_ADDR       0
 375 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS  1
 376 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS   2
 377 #define   KVM_DEV_ARM_VGIC_CPUID_SHIFT  32
 378 #define   KVM_DEV_ARM_VGIC_CPUID_MASK   (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
 379 #define   KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
 380 #define   KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
 381                         (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
 382 #define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
 383 #define   KVM_DEV_ARM_VGIC_OFFSET_MASK  (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
 384 #define   KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
 385 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
 386 #define KVM_DEV_ARM_VGIC_GRP_CTRL       4
 387 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
 388 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
 389 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO  7
 390 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
 391 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT  10
 392 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
 393                         (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
 394 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK  0x3ff
 395 #define VGIC_LEVEL_INFO_LINE_LEVEL      0
 396
 397 #define   KVM_DEV_ARM_VGIC_CTRL_INIT            0
 398 #define   KVM_DEV_ARM_ITS_SAVE_TABLES           1
 399 #define   KVM_DEV_ARM_ITS_RESTORE_TABLES        2
 400 #define   KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES  3
 401 #define   KVM_DEV_ARM_ITS_CTRL_RESET            4
 402
 403 /* Device Control API on vcpu fd */
 404 #define KVM_ARM_VCPU_PMU_V3_CTRL        0
 405 #define   KVM_ARM_VCPU_PMU_V3_IRQ       0
 406 #define   KVM_ARM_VCPU_PMU_V3_INIT      1
 407 #define   KVM_ARM_VCPU_PMU_V3_FILTER    2
 408 #define   KVM_ARM_VCPU_PMU_V3_SET_PMU   3
 409 #define KVM_ARM_VCPU_TIMER_CTRL         1
 410 #define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER         0
 411 #define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER         1
 412 #define KVM_ARM_VCPU_PVTIME_CTRL        2
 413 #define   KVM_ARM_VCPU_PVTIME_IPA       0
 414
 415 /* KVM_IRQ_LINE irq field index values */
 416 #define KVM_ARM_IRQ_VCPU2_SHIFT         28
 417 #define KVM_ARM_IRQ_VCPU2_MASK          0xf
 418 #define KVM_ARM_IRQ_TYPE_SHIFT          24
 419 #define KVM_ARM_IRQ_TYPE_MASK           0xf
 420 #define KVM_ARM_IRQ_VCPU_SHIFT          16
 421 #define KVM_ARM_IRQ_VCPU_MASK           0xff
 422 #define KVM_ARM_IRQ_NUM_SHIFT           0
 423 #define KVM_ARM_IRQ_NUM_MASK            0xffff
 424
 425 /* irq_type field */
 426 #define KVM_ARM_IRQ_TYPE_CPU            0
 427 #define KVM_ARM_IRQ_TYPE_SPI            1
 428 #define KVM_ARM_IRQ_TYPE_PPI            2
 429
 430 /* out-of-kernel GIC cpu interrupt injection irq_number field */
 431 #define KVM_ARM_IRQ_CPU_IRQ             0
 432 #define KVM_ARM_IRQ_CPU_FIQ             1
 433
 434 /*
 435  * This used to hold the highest supported SPI, but it is now obsolete
 436  * and only here to provide source code level compatibility with older
 437  * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
 438  */
 439 #ifndef __KERNEL__
 440 #define KVM_ARM_IRQ_GIC_MAX             127
 441 #endif
 442
 443 /* One single KVM irqchip, ie. the VGIC */
 444 #define KVM_NR_IRQCHIPS          1
 445
 446 /* PSCI interface */
 447 #define KVM_PSCI_FN_BASE                0x95c1ba5e
 448 #define KVM_PSCI_FN(n)                  (KVM_PSCI_FN_BASE + (n))
 449
 450 #define KVM_PSCI_FN_CPU_SUSPEND         KVM_PSCI_FN(0)
 451 #define KVM_PSCI_FN_CPU_OFF             KVM_PSCI_FN(1)
 452 #define KVM_PSCI_FN_CPU_ON              KVM_PSCI_FN(2)
 453 #define KVM_PSCI_FN_MIGRATE             KVM_PSCI_FN(3)
 454
 455 #define KVM_PSCI_RET_SUCCESS            PSCI_RET_SUCCESS
 456 #define KVM_PSCI_RET_NI                 PSCI_RET_NOT_SUPPORTED
 457 #define KVM_PSCI_RET_INVAL              PSCI_RET_INVALID_PARAMS
 458 #define KVM_PSCI_RET_DENIED             PSCI_RET_DENIED
 459
 460 /* arm64-specific kvm_run::system_event flags */
 461 /*
 462  * Reset caused by a PSCI v1.1 SYSTEM_RESET2 call.
 463  * Valid only when the system event has a type of KVM_SYSTEM_EVENT_RESET.
 464  */
 465 #define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0)
 466
 467 /* run->fail_entry.hardware_entry_failure_reason codes. */
 468 #define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED     (1ULL << 0)
 469
 470 #endif
 471
 472 #endif /* __ARM_KVM_H__ */