2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * Derived from arch/arm/include/asm/kvm_host.h:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef __ARM64_KVM_HOST_H__
23 #define __ARM64_KVM_HOST_H__
25 #include <linux/types.h>
26 #include <linux/kvm_types.h>
27 #include <asm/cpufeature.h>
29 #include <asm/kvm_asm.h>
30 #include <asm/kvm_mmio.h>
32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
34 #define KVM_USER_MEM_SLOTS 512
35 #define KVM_HALT_POLL_NS_DEFAULT 500000
37 #include <kvm/arm_vgic.h>
38 #include <kvm/arm_arch_timer.h>
39 #include <kvm/arm_pmu.h>
41 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
43 #define KVM_VCPU_MAX_FEATURES 4
45 #define KVM_REQ_SLEEP \
46 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
47 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
49 int __attribute_const__ kvm_target_cpu(void);
50 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
51 int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext);
52 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
55 /* The VMID generation used for the virt. memory system */
59 /* 1-level 2nd stage table and lock */
63 /* VTTBR value associated with above pgd and vmid */
66 /* The last vcpu id that ran on each physical CPU */
67 int __percpu *last_vcpu_ran;
69 /* The maximum number of vCPUs depends on the used GIC model */
72 /* Interrupt controller */
73 struct vgic_dist vgic;
76 #define KVM_NR_MEM_OBJS 40
79 * We don't want allocation failures within the mmu code, so we preallocate
80 * enough memory for a single page fault in a cache.
82 struct kvm_mmu_memory_cache {
84 void *objects[KVM_NR_MEM_OBJS];
87 struct kvm_vcpu_fault_info {
88 u32 esr_el2; /* Hyp Syndrom Register */
89 u64 far_el2; /* Hyp Fault Address Register */
90 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
94 * 0 is reserved as an invalid value.
95 * Order should be kept in sync with the save/restore code.
99 MPIDR_EL1, /* MultiProcessor Affinity Register */
100 CSSELR_EL1, /* Cache Size Selection Register */
101 SCTLR_EL1, /* System Control Register */
102 ACTLR_EL1, /* Auxiliary Control Register */
103 CPACR_EL1, /* Coprocessor Access Control */
104 TTBR0_EL1, /* Translation Table Base Register 0 */
105 TTBR1_EL1, /* Translation Table Base Register 1 */
106 TCR_EL1, /* Translation Control Register */
107 ESR_EL1, /* Exception Syndrome Register */
108 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
109 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
110 FAR_EL1, /* Fault Address Register */
111 MAIR_EL1, /* Memory Attribute Indirection Register */
112 VBAR_EL1, /* Vector Base Address Register */
113 CONTEXTIDR_EL1, /* Context ID Register */
114 TPIDR_EL0, /* Thread ID, User R/W */
115 TPIDRRO_EL0, /* Thread ID, User R/O */
116 TPIDR_EL1, /* Thread ID, Privileged */
117 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
118 CNTKCTL_EL1, /* Timer Control Register (EL1) */
119 PAR_EL1, /* Physical Address Register */
120 MDSCR_EL1, /* Monitor Debug System Control Register */
121 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
123 /* Performance Monitors Registers */
124 PMCR_EL0, /* Control Register */
125 PMSELR_EL0, /* Event Counter Selection Register */
126 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
127 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
128 PMCCNTR_EL0, /* Cycle Counter Register */
129 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
130 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
131 PMCCFILTR_EL0, /* Cycle Count Filter Register */
132 PMCNTENSET_EL0, /* Count Enable Set Register */
133 PMINTENSET_EL1, /* Interrupt Enable Set Register */
134 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
135 PMSWINC_EL0, /* Software Increment Register */
136 PMUSERENR_EL0, /* User Enable Register */
138 /* 32bit specific registers. Keep them at the end of the range */
139 DACR32_EL2, /* Domain Access Control Register */
140 IFSR32_EL2, /* Instruction Fault Status Register */
141 FPEXC32_EL2, /* Floating-Point Exception Control Register */
142 DBGVCR32_EL2, /* Debug Vector Catch Register */
144 NR_SYS_REGS /* Nothing after this line! */
148 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
149 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
150 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
151 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
152 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
153 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
154 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
155 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
156 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
157 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
158 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
159 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
160 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
161 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
162 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
163 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
164 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
165 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
166 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
167 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
168 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
169 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
170 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
171 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
172 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
173 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
174 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
175 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
176 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
178 #define cp14_DBGDSCRext (MDSCR_EL1 * 2)
179 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
180 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
181 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
182 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
183 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
184 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
186 #define NR_COPRO_REGS (NR_SYS_REGS * 2)
188 struct kvm_cpu_context {
189 struct kvm_regs gp_regs;
191 u64 sys_regs[NR_SYS_REGS];
192 u32 copro[NR_COPRO_REGS];
196 typedef struct kvm_cpu_context kvm_cpu_context_t;
198 struct kvm_vcpu_arch {
199 struct kvm_cpu_context ctxt;
201 /* HYP configuration */
205 /* Exception Information */
206 struct kvm_vcpu_fault_info fault;
208 /* Guest debug state */
212 * We maintain more than a single set of debug registers to support
213 * debugging the guest from the host and to maintain separate host and
214 * guest state during world switches. vcpu_debug_state are the debug
215 * registers of the vcpu as the guest sees them. host_debug_state are
216 * the host registers which are saved and restored during
217 * world switches. external_debug_state contains the debug
218 * values we want to debug the guest. This is set via the
219 * KVM_SET_GUEST_DEBUG ioctl.
221 * debug_ptr points to the set of debug registers that should be loaded
222 * onto the hardware when running the guest.
224 struct kvm_guest_debug_arch *debug_ptr;
225 struct kvm_guest_debug_arch vcpu_debug_state;
226 struct kvm_guest_debug_arch external_debug_state;
228 /* Pointer to host CPU context */
229 kvm_cpu_context_t *host_cpu_context;
231 /* {Break,watch}point registers */
232 struct kvm_guest_debug_arch regs;
233 /* Statistical profiling extension */
238 struct vgic_cpu vgic_cpu;
239 struct arch_timer_cpu timer_cpu;
243 * Anything that is not used directly from assembly code goes
248 * Guest registers we preserve during guest debugging.
250 * These shadow registers are updated by the kvm_handle_sys_reg
251 * trap handler if the guest accesses or updates them while we
252 * are using guest debug.
256 } guest_debug_preserved;
258 /* vcpu power-off state */
261 /* Don't run the guest (internal implementation need) */
264 /* IO related fields */
265 struct kvm_decode mmio_decode;
267 /* Interrupt related fields */
268 u64 irq_lines; /* IRQ and FIQ levels */
270 /* Cache some mmu pages needed inside spinlock regions */
271 struct kvm_mmu_memory_cache mmu_page_cache;
273 /* Target CPU and feature flags */
275 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
277 /* Detect first run of a vcpu */
281 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
282 #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
284 * CP14 and CP15 live in the same array, as they are backed by the
285 * same system registers.
287 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
288 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
290 #ifdef CONFIG_CPU_BIG_ENDIAN
291 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r))
292 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1)
294 #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1)
295 #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r))
299 ulong remote_tlb_flush;
302 struct kvm_vcpu_stat {
303 u64 halt_successful_poll;
304 u64 halt_attempted_poll;
305 u64 halt_poll_invalid;
311 u64 mmio_exit_kernel;
315 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
316 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
317 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
318 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
319 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
321 #define KVM_ARCH_WANT_MMU_NOTIFIER
322 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
323 int kvm_unmap_hva_range(struct kvm *kvm,
324 unsigned long start, unsigned long end);
325 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
326 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
327 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
329 struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
330 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
331 void kvm_arm_halt_guest(struct kvm *kvm);
332 void kvm_arm_resume_guest(struct kvm *kvm);
334 u64 __kvm_call_hyp(void *hypfn, ...);
335 #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)
337 void force_vm_exit(const cpumask_t *mask);
338 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
340 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
341 int exception_index);
343 int kvm_perf_init(void);
344 int kvm_perf_teardown(void);
346 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
348 static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
349 unsigned long hyp_stack_ptr,
350 unsigned long vector_ptr)
353 * Call initialization code, and switch to the full blown HYP code.
354 * If the cpucaps haven't been finalized yet, something has gone very
355 * wrong, and hyp will crash and burn when it uses any
356 * cpus_have_const_cap() wrapper.
358 BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
359 __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr);
362 static inline void kvm_arch_hardware_unsetup(void) {}
363 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
364 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
365 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
366 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
368 void kvm_arm_init_debug(void);
369 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
370 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
371 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
372 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
373 struct kvm_device_attr *attr);
374 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
375 struct kvm_device_attr *attr);
376 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
377 struct kvm_device_attr *attr);
379 static inline void __cpu_init_stage2(void)
381 u32 parange = kvm_call_hyp(__init_stage2_translation);
383 WARN_ONCE(parange < 40,
384 "PARange is %d bits, unsupported configuration!", parange);
387 #endif /* __ARM64_KVM_HOST_H__ */