1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/include/asm/kvm_host.h:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
14 #include <linux/arm-smccc.h>
15 #include <linux/bitmap.h>
16 #include <linux/types.h>
17 #include <linux/jump_label.h>
18 #include <linux/kvm_types.h>
19 #include <linux/percpu.h>
20 #include <linux/psci.h>
21 #include <asm/arch_gicv3.h>
22 #include <asm/barrier.h>
23 #include <asm/cpufeature.h>
24 #include <asm/cputype.h>
25 #include <asm/daifflags.h>
26 #include <asm/fpsimd.h>
28 #include <asm/kvm_asm.h>
30 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
32 #define KVM_HALT_POLL_NS_DEFAULT 500000
34 #include <kvm/arm_vgic.h>
35 #include <kvm/arm_arch_timer.h>
36 #include <kvm/arm_pmu.h>
38 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
40 #define KVM_VCPU_MAX_FEATURES 7
42 #define KVM_REQ_SLEEP \
43 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
44 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
45 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
46 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3)
47 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4)
48 #define KVM_REQ_RELOAD_PMU KVM_ARCH_REQ(5)
49 #define KVM_REQ_SUSPEND KVM_ARCH_REQ(6)
51 #define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
52 KVM_DIRTY_LOG_INITIALLY_SET)
54 #define KVM_HAVE_MMU_RWLOCK
57 * Mode of operation configurable with kvm-arm.mode early param.
58 * See Documentation/admin-guide/kernel-parameters.txt for more information.
67 enum kvm_mode kvm_get_mode(void);
69 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
72 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
74 extern unsigned int __ro_after_init kvm_sve_max_vl;
75 int __init kvm_arm_init_sve(void);
77 u32 __attribute_const__ kvm_target_cpu(void);
78 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
79 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
81 struct kvm_hyp_memcache {
83 unsigned long nr_pages;
86 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
88 phys_addr_t (*to_pa)(void *virt))
95 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
96 void *(*to_va)(phys_addr_t phys))
98 phys_addr_t *p = to_va(mc->head);
109 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
110 unsigned long min_pages,
111 void *(*alloc_fn)(void *arg),
112 phys_addr_t (*to_pa)(void *virt),
115 while (mc->nr_pages < min_pages) {
116 phys_addr_t *p = alloc_fn(arg);
120 push_hyp_memcache(mc, p, to_pa);
126 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
127 void (*free_fn)(void *virt, void *arg),
128 void *(*to_va)(phys_addr_t phys),
132 free_fn(pop_hyp_memcache(mc, to_va), arg);
135 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
136 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages);
143 struct kvm_vmid vmid;
146 * stage2 entry level table
148 * Two kvm_s2_mmu structures in the same VM can point to the same
149 * pgd here. This happens when running a guest using a
150 * translation regime that isn't affected by its own stage-2
151 * translation, such as a non-VHE hypervisor running at vEL2, or
152 * for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the
153 * canonical stage-2 page tables.
155 phys_addr_t pgd_phys;
156 struct kvm_pgtable *pgt;
158 /* The last vcpu id that ran on each physical CPU */
159 int __percpu *last_vcpu_ran;
161 struct kvm_arch *arch;
164 struct kvm_arch_memory_slot {
168 * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
170 * @std_bmap: Bitmap of standard secure service calls
171 * @std_hyp_bmap: Bitmap of standard hypervisor service calls
172 * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
174 struct kvm_smccc_features {
175 unsigned long std_bmap;
176 unsigned long std_hyp_bmap;
177 unsigned long vendor_hyp_bmap;
180 typedef unsigned int pkvm_handle_t;
182 struct kvm_protected_vm {
183 pkvm_handle_t handle;
184 struct kvm_hyp_memcache teardown_mc;
188 struct kvm_s2_mmu mmu;
190 /* VTCR_EL2 value for this VM */
193 /* Interrupt controller */
194 struct vgic_dist vgic;
197 struct arch_timer_vm_data timer_data;
199 /* Mandated version of PSCI */
203 * If we encounter a data abort without valid instruction syndrome
204 * information, report this to user space. User space can (and
205 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
208 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER 0
209 /* Memory Tagging Extension enabled for the guest */
210 #define KVM_ARCH_FLAG_MTE_ENABLED 1
211 /* At least one vCPU has ran in the VM */
212 #define KVM_ARCH_FLAG_HAS_RAN_ONCE 2
214 * The following two bits are used to indicate the guest's EL1
215 * register width configuration. A value of KVM_ARCH_FLAG_EL1_32BIT
216 * bit is valid only when KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED is set.
217 * Otherwise, the guest's EL1 register width has not yet been
220 #define KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED 3
221 #define KVM_ARCH_FLAG_EL1_32BIT 4
222 /* PSCI SYSTEM_SUSPEND enabled for the guest */
223 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED 5
228 * VM-wide PMU filter, implemented as a bitmap and big enough for
229 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
231 unsigned long *pmu_filter;
232 struct arm_pmu *arm_pmu;
234 cpumask_var_t supported_cpus;
243 /* Hypercall features firmware registers' descriptor */
244 struct kvm_smccc_features smccc_feat;
247 * For an untrusted host VM, 'pkvm.handle' is used to lookup
248 * the associated pKVM instance in the hypervisor.
250 struct kvm_protected_vm pkvm;
253 struct kvm_vcpu_fault_info {
254 u64 esr_el2; /* Hyp Syndrom Register */
255 u64 far_el2; /* Hyp Fault Address Register */
256 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
257 u64 disr_el1; /* Deferred [SError] Status Register */
261 __INVALID_SYSREG__, /* 0 is reserved as an invalid value */
262 MPIDR_EL1, /* MultiProcessor Affinity Register */
263 CLIDR_EL1, /* Cache Level ID Register */
264 CSSELR_EL1, /* Cache Size Selection Register */
265 SCTLR_EL1, /* System Control Register */
266 ACTLR_EL1, /* Auxiliary Control Register */
267 CPACR_EL1, /* Coprocessor Access Control */
268 ZCR_EL1, /* SVE Control */
269 TTBR0_EL1, /* Translation Table Base Register 0 */
270 TTBR1_EL1, /* Translation Table Base Register 1 */
271 TCR_EL1, /* Translation Control Register */
272 ESR_EL1, /* Exception Syndrome Register */
273 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
274 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
275 FAR_EL1, /* Fault Address Register */
276 MAIR_EL1, /* Memory Attribute Indirection Register */
277 VBAR_EL1, /* Vector Base Address Register */
278 CONTEXTIDR_EL1, /* Context ID Register */
279 TPIDR_EL0, /* Thread ID, User R/W */
280 TPIDRRO_EL0, /* Thread ID, User R/O */
281 TPIDR_EL1, /* Thread ID, Privileged */
282 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
283 CNTKCTL_EL1, /* Timer Control Register (EL1) */
284 PAR_EL1, /* Physical Address Register */
285 MDSCR_EL1, /* Monitor Debug System Control Register */
286 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
287 OSLSR_EL1, /* OS Lock Status Register */
288 DISR_EL1, /* Deferred Interrupt Status Register */
290 /* Performance Monitors Registers */
291 PMCR_EL0, /* Control Register */
292 PMSELR_EL0, /* Event Counter Selection Register */
293 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
294 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
295 PMCCNTR_EL0, /* Cycle Counter Register */
296 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
297 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
298 PMCCFILTR_EL0, /* Cycle Count Filter Register */
299 PMCNTENSET_EL0, /* Count Enable Set Register */
300 PMINTENSET_EL1, /* Interrupt Enable Set Register */
301 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
302 PMUSERENR_EL0, /* User Enable Register */
304 /* Pointer Authentication Registers in a strict increasing order. */
326 /* Memory Tagging Extension registers */
327 RGSR_EL1, /* Random Allocation Tag Seed Register */
328 GCR_EL1, /* Tag Control Register */
329 TFSR_EL1, /* Tag Fault Status Register (EL1) */
330 TFSRE0_EL1, /* Tag Fault Status Register (EL0) */
332 /* 32bit specific registers. */
333 DACR32_EL2, /* Domain Access Control Register */
334 IFSR32_EL2, /* Instruction Fault Status Register */
335 FPEXC32_EL2, /* Floating-Point Exception Control Register */
336 DBGVCR32_EL2, /* Debug Vector Catch Register */
339 VPIDR_EL2, /* Virtualization Processor ID Register */
340 VMPIDR_EL2, /* Virtualization Multiprocessor ID Register */
341 SCTLR_EL2, /* System Control Register (EL2) */
342 ACTLR_EL2, /* Auxiliary Control Register (EL2) */
343 HCR_EL2, /* Hypervisor Configuration Register */
344 MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */
345 CPTR_EL2, /* Architectural Feature Trap Register (EL2) */
346 HSTR_EL2, /* Hypervisor System Trap Register */
347 HACR_EL2, /* Hypervisor Auxiliary Control Register */
348 TTBR0_EL2, /* Translation Table Base Register 0 (EL2) */
349 TTBR1_EL2, /* Translation Table Base Register 1 (EL2) */
350 TCR_EL2, /* Translation Control Register (EL2) */
351 VTTBR_EL2, /* Virtualization Translation Table Base Register */
352 VTCR_EL2, /* Virtualization Translation Control Register */
353 SPSR_EL2, /* EL2 saved program status register */
354 ELR_EL2, /* EL2 exception link register */
355 AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */
356 AFSR1_EL2, /* Auxiliary Fault Status Register 1 (EL2) */
357 ESR_EL2, /* Exception Syndrome Register (EL2) */
358 FAR_EL2, /* Fault Address Register (EL2) */
359 HPFAR_EL2, /* Hypervisor IPA Fault Address Register */
360 MAIR_EL2, /* Memory Attribute Indirection Register (EL2) */
361 AMAIR_EL2, /* Auxiliary Memory Attribute Indirection Register (EL2) */
362 VBAR_EL2, /* Vector Base Address Register (EL2) */
363 RVBAR_EL2, /* Reset Vector Base Address Register */
364 CONTEXTIDR_EL2, /* Context ID Register (EL2) */
365 TPIDR_EL2, /* EL2 Software Thread ID Register */
366 CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
367 SP_EL2, /* EL2 Stack Pointer */
369 NR_SYS_REGS /* Nothing after this line! */
372 struct kvm_cpu_context {
373 struct user_pt_regs regs; /* sp = sp_el0 */
380 struct user_fpsimd_state fp_regs;
382 u64 sys_regs[NR_SYS_REGS];
384 struct kvm_vcpu *__hyp_running_vcpu;
387 struct kvm_host_data {
388 struct kvm_cpu_context host_ctxt;
391 struct kvm_host_psci_config {
392 /* PSCI version used by host. */
395 /* Function IDs used by host if version is v0.1. */
396 struct psci_0_1_function_ids function_ids_0_1;
398 bool psci_0_1_cpu_suspend_implemented;
399 bool psci_0_1_cpu_on_implemented;
400 bool psci_0_1_cpu_off_implemented;
401 bool psci_0_1_migrate_implemented;
404 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
405 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
407 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
408 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
410 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
411 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
413 struct vcpu_reset_state {
420 struct kvm_vcpu_arch {
421 struct kvm_cpu_context ctxt;
424 * Guest floating point state
426 * The architecture has two main floating point extensions,
427 * the original FPSIMD and SVE. These have overlapping
428 * register views, with the FPSIMD V registers occupying the
429 * low 128 bits of the SVE Z registers. When the core
430 * floating point code saves the register state of a task it
431 * records which view it saved in fp_type.
434 enum fp_type fp_type;
435 unsigned int sve_max_vl;
438 /* Stage 2 paging state used by the hardware on next switch */
439 struct kvm_s2_mmu *hw_mmu;
441 /* Values of trap registers for the guest. */
446 /* Values of trap registers for the host before guest entry. */
449 /* Exception Information */
450 struct kvm_vcpu_fault_info fault;
452 /* Ownership of the FP regs */
456 FP_STATE_GUEST_OWNED,
459 /* Configuration flags, set once and for all before the vcpu can run */
462 /* Input flags to the hypervisor code, potentially cleared after use */
465 /* State flags for kernel bookkeeping, unused by the hypervisor code */
469 * Don't run the guest (internal implementation need).
471 * Contrary to the flags above, this is set/cleared outside of
472 * a vcpu context, and thus cannot be mixed with the flags
473 * themselves (or the flag accesses need to be made atomic).
478 * We maintain more than a single set of debug registers to support
479 * debugging the guest from the host and to maintain separate host and
480 * guest state during world switches. vcpu_debug_state are the debug
481 * registers of the vcpu as the guest sees them. host_debug_state are
482 * the host registers which are saved and restored during
483 * world switches. external_debug_state contains the debug
484 * values we want to debug the guest. This is set via the
485 * KVM_SET_GUEST_DEBUG ioctl.
487 * debug_ptr points to the set of debug registers that should be loaded
488 * onto the hardware when running the guest.
490 struct kvm_guest_debug_arch *debug_ptr;
491 struct kvm_guest_debug_arch vcpu_debug_state;
492 struct kvm_guest_debug_arch external_debug_state;
494 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */
495 struct task_struct *parent_task;
498 /* {Break,watch}point registers */
499 struct kvm_guest_debug_arch regs;
500 /* Statistical profiling extension */
502 /* Self-hosted trace */
507 struct vgic_cpu vgic_cpu;
508 struct arch_timer_cpu timer_cpu;
512 * Guest registers we preserve during guest debugging.
514 * These shadow registers are updated by the kvm_handle_sys_reg
515 * trap handler if the guest accesses or updates them while we
516 * are using guest debug.
521 } guest_debug_preserved;
523 /* vcpu power state */
524 struct kvm_mp_state mp_state;
526 /* Cache some mmu pages needed inside spinlock regions */
527 struct kvm_mmu_memory_cache mmu_page_cache;
529 /* Target CPU and feature flags */
531 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
533 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
536 /* Additional reset state */
537 struct vcpu_reset_state reset_state;
545 /* Per-vcpu CCSIDR override or NULL */
550 * Each 'flag' is composed of a comma-separated triplet:
552 * - the flag-set it belongs to in the vcpu->arch structure
553 * - the value for that flag
554 * - the mask for that flag
556 * __vcpu_single_flag() builds such a triplet for a single-bit flag.
557 * unpack_vcpu_flag() extract the flag value from the triplet for
558 * direct use outside of the flag accessors.
560 #define __vcpu_single_flag(_set, _f) _set, (_f), (_f)
562 #define __unpack_flag(_set, _f, _m) _f
563 #define unpack_vcpu_flag(...) __unpack_flag(__VA_ARGS__)
565 #define __build_check_flag(v, flagset, f, m) \
567 typeof(v->arch.flagset) *_fset; \
569 /* Check that the flags fit in the mask */ \
570 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \
571 /* Check that the flags fit in the type */ \
572 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
575 #define __vcpu_get_flag(v, flagset, f, m) \
577 __build_check_flag(v, flagset, f, m); \
579 v->arch.flagset & (m); \
582 #define __vcpu_set_flag(v, flagset, f, m) \
584 typeof(v->arch.flagset) *fset; \
586 __build_check_flag(v, flagset, f, m); \
588 fset = &v->arch.flagset; \
589 if (HWEIGHT(m) > 1) \
594 #define __vcpu_clear_flag(v, flagset, f, m) \
596 typeof(v->arch.flagset) *fset; \
598 __build_check_flag(v, flagset, f, m); \
600 fset = &v->arch.flagset; \
604 #define vcpu_get_flag(v, ...) __vcpu_get_flag((v), __VA_ARGS__)
605 #define vcpu_set_flag(v, ...) __vcpu_set_flag((v), __VA_ARGS__)
606 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
608 /* SVE exposed to guest */
609 #define GUEST_HAS_SVE __vcpu_single_flag(cflags, BIT(0))
610 /* SVE config completed */
611 #define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1))
612 /* PTRAUTH exposed to guest */
613 #define GUEST_HAS_PTRAUTH __vcpu_single_flag(cflags, BIT(2))
615 /* Exception pending */
616 #define PENDING_EXCEPTION __vcpu_single_flag(iflags, BIT(0))
618 * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
619 * be set together with an exception...
621 #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1))
622 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
623 #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1))
625 /* Helpers to encode exceptions with minimum fuss */
626 #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK)
627 #define __EXCEPT_SHIFT __builtin_ctzl(__EXCEPT_MASK_VAL)
628 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
631 * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
636 #define EXCEPT_AA32_UND __vcpu_except_flags(0)
637 #define EXCEPT_AA32_IABT __vcpu_except_flags(1)
638 #define EXCEPT_AA32_DABT __vcpu_except_flags(2)
640 #define EXCEPT_AA64_EL1_SYNC __vcpu_except_flags(0)
641 #define EXCEPT_AA64_EL1_IRQ __vcpu_except_flags(1)
642 #define EXCEPT_AA64_EL1_FIQ __vcpu_except_flags(2)
643 #define EXCEPT_AA64_EL1_SERR __vcpu_except_flags(3)
644 /* For AArch64 with NV: */
645 #define EXCEPT_AA64_EL2_SYNC __vcpu_except_flags(4)
646 #define EXCEPT_AA64_EL2_IRQ __vcpu_except_flags(5)
647 #define EXCEPT_AA64_EL2_FIQ __vcpu_except_flags(6)
648 #define EXCEPT_AA64_EL2_SERR __vcpu_except_flags(7)
649 /* Guest debug is live */
650 #define DEBUG_DIRTY __vcpu_single_flag(iflags, BIT(4))
651 /* Save SPE context if active */
652 #define DEBUG_STATE_SAVE_SPE __vcpu_single_flag(iflags, BIT(5))
653 /* Save TRBE context if active */
654 #define DEBUG_STATE_SAVE_TRBE __vcpu_single_flag(iflags, BIT(6))
655 /* vcpu running in HYP context */
656 #define VCPU_HYP_CONTEXT __vcpu_single_flag(iflags, BIT(7))
658 /* SVE enabled for host EL0 */
659 #define HOST_SVE_ENABLED __vcpu_single_flag(sflags, BIT(0))
660 /* SME enabled for EL0 */
661 #define HOST_SME_ENABLED __vcpu_single_flag(sflags, BIT(1))
662 /* Physical CPU not in supported_cpus */
663 #define ON_UNSUPPORTED_CPU __vcpu_single_flag(sflags, BIT(2))
664 /* WFIT instruction trapped */
665 #define IN_WFIT __vcpu_single_flag(sflags, BIT(3))
666 /* vcpu system registers loaded on physical CPU */
667 #define SYSREGS_ON_CPU __vcpu_single_flag(sflags, BIT(4))
668 /* Software step state is Active-pending */
669 #define DBG_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(5))
672 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
673 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \
674 sve_ffr_offset((vcpu)->arch.sve_max_vl))
676 #define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl)
678 #define vcpu_sve_state_size(vcpu) ({ \
680 unsigned int __vcpu_vq; \
682 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \
685 __vcpu_vq = vcpu_sve_max_vq(vcpu); \
686 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \
692 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
693 KVM_GUESTDBG_USE_SW_BP | \
694 KVM_GUESTDBG_USE_HW | \
695 KVM_GUESTDBG_SINGLESTEP)
697 #define vcpu_has_sve(vcpu) (system_supports_sve() && \
698 vcpu_get_flag(vcpu, GUEST_HAS_SVE))
700 #ifdef CONFIG_ARM64_PTR_AUTH
701 #define vcpu_has_ptrauth(vcpu) \
702 ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \
703 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \
704 vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH))
706 #define vcpu_has_ptrauth(vcpu) false
709 #define vcpu_on_unsupported_cpu(vcpu) \
710 vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
712 #define vcpu_set_on_unsupported_cpu(vcpu) \
713 vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
715 #define vcpu_clear_on_unsupported_cpu(vcpu) \
716 vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
718 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs)
721 * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
722 * memory backed version of a register, and not the one most recently
723 * accessed by a running VCPU. For example, for userspace access or
724 * for system registers that are never context switched, but only
727 #define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)])
729 #define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
731 #define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r)))
733 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
734 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
736 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
741 * System registers listed in the switch are not saved on every
742 * exit from the guest but are only saved on vcpu_put.
744 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
745 * should never be listed below, because the guest cannot modify its
746 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
747 * thread when emulating cross-VCPU communication.
753 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
754 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
755 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
756 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
757 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
758 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
759 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
760 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
761 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
762 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
763 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
764 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
765 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
766 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
767 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
768 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
769 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
770 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
771 case PAR_EL1: *val = read_sysreg_par(); break;
772 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
773 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
774 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
775 default: return false;
781 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
786 * System registers listed in the switch are not restored on every
787 * entry to the guest but are only restored on vcpu_load.
789 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
790 * should never be listed below, because the MPIDR should only be set
791 * once, before running the VCPU, and never changed later.
797 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
798 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
799 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
800 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
801 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
802 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
803 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
804 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
805 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
806 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
807 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
808 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
809 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
810 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
811 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
812 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
813 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
814 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
815 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
816 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
817 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
818 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
819 default: return false;
826 struct kvm_vm_stat_generic generic;
829 struct kvm_vcpu_stat {
830 struct kvm_vcpu_stat_generic generic;
835 u64 mmio_exit_kernel;
840 void kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
841 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
842 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
843 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
844 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
846 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
847 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
849 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
850 struct kvm_vcpu_events *events);
852 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
853 struct kvm_vcpu_events *events);
855 #define KVM_ARCH_WANT_MMU_NOTIFIER
857 void kvm_arm_halt_guest(struct kvm *kvm);
858 void kvm_arm_resume_guest(struct kvm *kvm);
860 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid)
862 #ifndef __KVM_NVHE_HYPERVISOR__
863 #define kvm_call_hyp_nvhe(f, ...) \
865 struct arm_smccc_res res; \
867 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \
868 ##__VA_ARGS__, &res); \
869 WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \
875 * The couple of isb() below are there to guarantee the same behaviour
876 * on VHE as on !VHE, where the eret to EL1 acts as a context
877 * synchronization event.
879 #define kvm_call_hyp(f, ...) \
885 kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
889 #define kvm_call_hyp_ret(f, ...) \
891 typeof(f(__VA_ARGS__)) ret; \
894 ret = f(__VA_ARGS__); \
897 ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \
902 #else /* __KVM_NVHE_HYPERVISOR__ */
903 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
904 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
905 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
906 #endif /* __KVM_NVHE_HYPERVISOR__ */
908 void force_vm_exit(const cpumask_t *mask);
910 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
911 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
913 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
914 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
915 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
916 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
917 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
918 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
919 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
921 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
923 int __init kvm_sys_reg_table_init(void);
926 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
927 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
929 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
930 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
933 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
934 * arrived in guest context. For arm64, any event that arrives while a vCPU is
935 * loaded is considered to be "in guest".
937 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
939 return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
942 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
943 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
944 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
946 bool kvm_arm_pvtime_supported(void);
947 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
948 struct kvm_device_attr *attr);
949 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
950 struct kvm_device_attr *attr);
951 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
952 struct kvm_device_attr *attr);
954 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
955 int __init kvm_arm_vmid_alloc_init(void);
956 void __init kvm_arm_vmid_alloc_free(void);
957 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
958 void kvm_arm_vmid_clear_active(void);
960 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
962 vcpu_arch->steal.base = INVALID_GPA;
965 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
967 return (vcpu_arch->steal.base != INVALID_GPA);
970 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
972 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
974 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
976 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
978 /* The host's MPIDR is immutable, so let's set it up at boot time */
979 ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
982 static inline bool kvm_system_needs_idmapped_vectors(void)
984 return cpus_have_const_cap(ARM64_SPECTRE_V3A);
987 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu);
989 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
990 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
992 void kvm_arm_init_debug(void);
993 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu);
994 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
995 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
996 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
998 #define kvm_vcpu_os_lock_enabled(vcpu) \
999 (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & SYS_OSLSR_OSLK))
1001 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1002 struct kvm_device_attr *attr);
1003 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1004 struct kvm_device_attr *attr);
1005 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1006 struct kvm_device_attr *attr);
1008 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1009 struct kvm_arm_copy_mte_tags *copy_tags);
1011 /* Guest/host FPSIMD coordination helpers */
1012 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1013 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1014 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1015 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1016 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1017 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu);
1019 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1021 return (!has_vhe() && attr->exclude_host);
1024 /* Flags for host debug state */
1025 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
1026 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
1029 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
1030 void kvm_clr_pmu_events(u32 clr);
1032 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
1033 static inline void kvm_clr_pmu_events(u32 clr) {}
1036 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
1037 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu);
1039 int __init kvm_set_ipa_limit(void);
1041 #define __KVM_HAVE_ARCH_VM_ALLOC
1042 struct kvm *kvm_arch_alloc_vm(void);
1044 static inline bool kvm_vm_is_protected(struct kvm *kvm)
1049 void kvm_init_protected_traps(struct kvm_vcpu *vcpu);
1051 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1052 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1054 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1056 #define kvm_has_mte(kvm) \
1057 (system_supports_mte() && \
1058 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1060 #define kvm_supports_32bit_el0() \
1061 (system_supports_32bit_el0() && \
1062 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1064 int kvm_trng_call(struct kvm_vcpu *vcpu);
1066 extern phys_addr_t hyp_mem_base;
1067 extern phys_addr_t hyp_mem_size;
1068 void __init kvm_hyp_reserve(void);
1070 static inline void kvm_hyp_reserve(void) { }
1073 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1074 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1076 #endif /* __ARM64_KVM_HOST_H__ */