arch/arm64/include/asm/kvm_host.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2012,2013 - ARM Ltd
   4  * Author: Marc Zyngier <marc.zyngier@arm.com>
   5  *
   6  * Derived from arch/arm/include/asm/kvm_host.h:
   7  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   8  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
   9  */
  10
  11 #ifndef __ARM64_KVM_HOST_H__
  12 #define __ARM64_KVM_HOST_H__
  13
  14 #include <linux/arm-smccc.h>
  15 #include <linux/bitmap.h>
  16 #include <linux/types.h>
  17 #include <linux/jump_label.h>
  18 #include <linux/kvm_types.h>
  19 #include <linux/maple_tree.h>
  20 #include <linux/percpu.h>
  21 #include <linux/psci.h>
  22 #include <asm/arch_gicv3.h>
  23 #include <asm/barrier.h>
  24 #include <asm/cpufeature.h>
  25 #include <asm/cputype.h>
  26 #include <asm/daifflags.h>
  27 #include <asm/fpsimd.h>
  28 #include <asm/kvm.h>
  29 #include <asm/kvm_asm.h>
  30
  31 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
  32
  33 #define KVM_HALT_POLL_NS_DEFAULT 500000
  34
  35 #include <kvm/arm_vgic.h>
  36 #include <kvm/arm_arch_timer.h>
  37 #include <kvm/arm_pmu.h>
  38
  39 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
  40
  41 #define KVM_VCPU_MAX_FEATURES 7
  42 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1)
  43
  44 #define KVM_REQ_SLEEP \
  45         KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
  46 #define KVM_REQ_IRQ_PENDING     KVM_ARCH_REQ(1)
  47 #define KVM_REQ_VCPU_RESET      KVM_ARCH_REQ(2)
  48 #define KVM_REQ_RECORD_STEAL    KVM_ARCH_REQ(3)
  49 #define KVM_REQ_RELOAD_GICv4    KVM_ARCH_REQ(4)
  50 #define KVM_REQ_RELOAD_PMU      KVM_ARCH_REQ(5)
  51 #define KVM_REQ_SUSPEND         KVM_ARCH_REQ(6)
  52
  53 #define KVM_DIRTY_LOG_MANUAL_CAPS   (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
  54                                      KVM_DIRTY_LOG_INITIALLY_SET)
  55
  56 #define KVM_HAVE_MMU_RWLOCK
  57
  58 /*
  59  * Mode of operation configurable with kvm-arm.mode early param.
  60  * See Documentation/admin-guide/kernel-parameters.txt for more information.
  61  */
  62 enum kvm_mode {
  63         KVM_MODE_DEFAULT,
  64         KVM_MODE_PROTECTED,
  65         KVM_MODE_NV,
  66         KVM_MODE_NONE,
  67 };
  68 #ifdef CONFIG_KVM
  69 enum kvm_mode kvm_get_mode(void);
  70 #else
  71 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
  72 #endif
  73
  74 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
  75
  76 extern unsigned int __ro_after_init kvm_sve_max_vl;
  77 int __init kvm_arm_init_sve(void);
  78
  79 u32 __attribute_const__ kvm_target_cpu(void);
  80 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
  81 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
  82
  83 struct kvm_hyp_memcache {
  84         phys_addr_t head;
  85         unsigned long nr_pages;
  86 };
  87
  88 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
  89                                      phys_addr_t *p,
  90                                      phys_addr_t (*to_pa)(void *virt))
  91 {
  92         *p = mc->head;
  93         mc->head = to_pa(p);
  94         mc->nr_pages++;
  95 }
  96
  97 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
  98                                      void *(*to_va)(phys_addr_t phys))
  99 {
 100         phys_addr_t *p = to_va(mc->head);
 101
 102         if (!mc->nr_pages)
 103                 return NULL;
 104
 105         mc->head = *p;
 106         mc->nr_pages--;
 107
 108         return p;
 109 }
 110
 111 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
 112                                        unsigned long min_pages,
 113                                        void *(*alloc_fn)(void *arg),
 114                                        phys_addr_t (*to_pa)(void *virt),
 115                                        void *arg)
 116 {
 117         while (mc->nr_pages < min_pages) {
 118                 phys_addr_t *p = alloc_fn(arg);
 119
 120                 if (!p)
 121                         return -ENOMEM;
 122                 push_hyp_memcache(mc, p, to_pa);
 123         }
 124
 125         return 0;
 126 }
 127
 128 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
 129                                        void (*free_fn)(void *virt, void *arg),
 130                                        void *(*to_va)(phys_addr_t phys),
 131                                        void *arg)
 132 {
 133         while (mc->nr_pages)
 134                 free_fn(pop_hyp_memcache(mc, to_va), arg);
 135 }
 136
 137 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
 138 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages);
 139
 140 struct kvm_vmid {
 141         atomic64_t id;
 142 };
 143
 144 struct kvm_s2_mmu {
 145         struct kvm_vmid vmid;
 146
 147         /*
 148          * stage2 entry level table
 149          *
 150          * Two kvm_s2_mmu structures in the same VM can point to the same
 151          * pgd here.  This happens when running a guest using a
 152          * translation regime that isn't affected by its own stage-2
 153          * translation, such as a non-VHE hypervisor running at vEL2, or
 154          * for vEL1/EL0 with vHCR_EL2.VM == 0.  In that case, we use the
 155          * canonical stage-2 page tables.
 156          */
 157         phys_addr_t     pgd_phys;
 158         struct kvm_pgtable *pgt;
 159
 160         /* The last vcpu id that ran on each physical CPU */
 161         int __percpu *last_vcpu_ran;
 162
 163 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0
 164         /*
 165          * Memory cache used to split
 166          * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It
 167          * is used to allocate stage2 page tables while splitting huge
 168          * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
 169          * influences both the capacity of the split page cache, and
 170          * how often KVM reschedules. Be wary of raising CHUNK_SIZE
 171          * too high.
 172          *
 173          * Protected by kvm->slots_lock.
 174          */
 175         struct kvm_mmu_memory_cache split_page_cache;
 176         uint64_t split_page_chunk_size;
 177
 178         struct kvm_arch *arch;
 179 };
 180
 181 struct kvm_arch_memory_slot {
 182 };
 183
 184 /**
 185  * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
 186  *
 187  * @std_bmap: Bitmap of standard secure service calls
 188  * @std_hyp_bmap: Bitmap of standard hypervisor service calls
 189  * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
 190  */
 191 struct kvm_smccc_features {
 192         unsigned long std_bmap;
 193         unsigned long std_hyp_bmap;
 194         unsigned long vendor_hyp_bmap;
 195 };
 196
 197 typedef unsigned int pkvm_handle_t;
 198
 199 struct kvm_protected_vm {
 200         pkvm_handle_t handle;
 201         struct kvm_hyp_memcache teardown_mc;
 202 };
 203
 204 struct kvm_arch {
 205         struct kvm_s2_mmu mmu;
 206
 207         /* VTCR_EL2 value for this VM */
 208         u64    vtcr;
 209
 210         /* Interrupt controller */
 211         struct vgic_dist        vgic;
 212
 213         /* Timers */
 214         struct arch_timer_vm_data timer_data;
 215
 216         /* Mandated version of PSCI */
 217         u32 psci_version;
 218
 219         /* Protects VM-scoped configuration data */
 220         struct mutex config_lock;
 221
 222         /*
 223          * If we encounter a data abort without valid instruction syndrome
 224          * information, report this to user space.  User space can (and
 225          * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
 226          * supported.
 227          */
 228 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER      0
 229         /* Memory Tagging Extension enabled for the guest */
 230 #define KVM_ARCH_FLAG_MTE_ENABLED                       1
 231         /* At least one vCPU has ran in the VM */
 232 #define KVM_ARCH_FLAG_HAS_RAN_ONCE                      2
 233         /* The vCPU feature set for the VM is configured */
 234 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED          3
 235         /* PSCI SYSTEM_SUSPEND enabled for the guest */
 236 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED            4
 237         /* VM counter offset */
 238 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET                 5
 239         /* Timer PPIs made immutable */
 240 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE              6
 241         /* SMCCC filter initialized for the VM */
 242 #define KVM_ARCH_FLAG_SMCCC_FILTER_CONFIGURED           7
 243         /* Initial ID reg values loaded */
 244 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED               8
 245         unsigned long flags;
 246
 247         /* VM-wide vCPU feature set */
 248         DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES);
 249
 250         /*
 251          * VM-wide PMU filter, implemented as a bitmap and big enough for
 252          * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
 253          */
 254         unsigned long *pmu_filter;
 255         struct arm_pmu *arm_pmu;
 256
 257         cpumask_var_t supported_cpus;
 258
 259         /* Hypercall features firmware registers' descriptor */
 260         struct kvm_smccc_features smccc_feat;
 261         struct maple_tree smccc_filter;
 262
 263         /*
 264          * Emulated CPU ID registers per VM
 265          * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it
 266          * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
 267          *
 268          * These emulated idregs are VM-wide, but accessed from the context of a vCPU.
 269          * Atomic access to multiple idregs are guarded by kvm_arch.config_lock.
 270          */
 271 #define IDREG_IDX(id)           (((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id))
 272 #define IDREG(kvm, id)          ((kvm)->arch.id_regs[IDREG_IDX(id)])
 273 #define KVM_ARM_ID_REG_NUM      (IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1)
 274         u64 id_regs[KVM_ARM_ID_REG_NUM];
 275
 276         /*
 277          * For an untrusted host VM, 'pkvm.handle' is used to lookup
 278          * the associated pKVM instance in the hypervisor.
 279          */
 280         struct kvm_protected_vm pkvm;
 281 };
 282
 283 struct kvm_vcpu_fault_info {
 284         u64 esr_el2;            /* Hyp Syndrom Register */
 285         u64 far_el2;            /* Hyp Fault Address Register */
 286         u64 hpfar_el2;          /* Hyp IPA Fault Address Register */
 287         u64 disr_el1;           /* Deferred [SError] Status Register */
 288 };
 289
 290 enum vcpu_sysreg {
 291         __INVALID_SYSREG__,   /* 0 is reserved as an invalid value */
 292         MPIDR_EL1,      /* MultiProcessor Affinity Register */
 293         CLIDR_EL1,      /* Cache Level ID Register */
 294         CSSELR_EL1,     /* Cache Size Selection Register */
 295         SCTLR_EL1,      /* System Control Register */
 296         ACTLR_EL1,      /* Auxiliary Control Register */
 297         CPACR_EL1,      /* Coprocessor Access Control */
 298         ZCR_EL1,        /* SVE Control */
 299         TTBR0_EL1,      /* Translation Table Base Register 0 */
 300         TTBR1_EL1,      /* Translation Table Base Register 1 */
 301         TCR_EL1,        /* Translation Control Register */
 302         ESR_EL1,        /* Exception Syndrome Register */
 303         AFSR0_EL1,      /* Auxiliary Fault Status Register 0 */
 304         AFSR1_EL1,      /* Auxiliary Fault Status Register 1 */
 305         FAR_EL1,        /* Fault Address Register */
 306         MAIR_EL1,       /* Memory Attribute Indirection Register */
 307         VBAR_EL1,       /* Vector Base Address Register */
 308         CONTEXTIDR_EL1, /* Context ID Register */
 309         TPIDR_EL0,      /* Thread ID, User R/W */
 310         TPIDRRO_EL0,    /* Thread ID, User R/O */
 311         TPIDR_EL1,      /* Thread ID, Privileged */
 312         AMAIR_EL1,      /* Aux Memory Attribute Indirection Register */
 313         CNTKCTL_EL1,    /* Timer Control Register (EL1) */
 314         PAR_EL1,        /* Physical Address Register */
 315         MDSCR_EL1,      /* Monitor Debug System Control Register */
 316         MDCCINT_EL1,    /* Monitor Debug Comms Channel Interrupt Enable Reg */
 317         OSLSR_EL1,      /* OS Lock Status Register */
 318         DISR_EL1,       /* Deferred Interrupt Status Register */
 319
 320         /* Performance Monitors Registers */
 321         PMCR_EL0,       /* Control Register */
 322         PMSELR_EL0,     /* Event Counter Selection Register */
 323         PMEVCNTR0_EL0,  /* Event Counter Register (0-30) */
 324         PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
 325         PMCCNTR_EL0,    /* Cycle Counter Register */
 326         PMEVTYPER0_EL0, /* Event Type Register (0-30) */
 327         PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
 328         PMCCFILTR_EL0,  /* Cycle Count Filter Register */
 329         PMCNTENSET_EL0, /* Count Enable Set Register */
 330         PMINTENSET_EL1, /* Interrupt Enable Set Register */
 331         PMOVSSET_EL0,   /* Overflow Flag Status Set Register */
 332         PMUSERENR_EL0,  /* User Enable Register */
 333
 334         /* Pointer Authentication Registers in a strict increasing order. */
 335         APIAKEYLO_EL1,
 336         APIAKEYHI_EL1,
 337         APIBKEYLO_EL1,
 338         APIBKEYHI_EL1,
 339         APDAKEYLO_EL1,
 340         APDAKEYHI_EL1,
 341         APDBKEYLO_EL1,
 342         APDBKEYHI_EL1,
 343         APGAKEYLO_EL1,
 344         APGAKEYHI_EL1,
 345
 346         ELR_EL1,
 347         SP_EL1,
 348         SPSR_EL1,
 349
 350         CNTVOFF_EL2,
 351         CNTV_CVAL_EL0,
 352         CNTV_CTL_EL0,
 353         CNTP_CVAL_EL0,
 354         CNTP_CTL_EL0,
 355
 356         /* Memory Tagging Extension registers */
 357         RGSR_EL1,       /* Random Allocation Tag Seed Register */
 358         GCR_EL1,        /* Tag Control Register */
 359         TFSR_EL1,       /* Tag Fault Status Register (EL1) */
 360         TFSRE0_EL1,     /* Tag Fault Status Register (EL0) */
 361
 362         /* 32bit specific registers. */
 363         DACR32_EL2,     /* Domain Access Control Register */
 364         IFSR32_EL2,     /* Instruction Fault Status Register */
 365         FPEXC32_EL2,    /* Floating-Point Exception Control Register */
 366         DBGVCR32_EL2,   /* Debug Vector Catch Register */
 367
 368         /* EL2 registers */
 369         VPIDR_EL2,      /* Virtualization Processor ID Register */
 370         VMPIDR_EL2,     /* Virtualization Multiprocessor ID Register */
 371         SCTLR_EL2,      /* System Control Register (EL2) */
 372         ACTLR_EL2,      /* Auxiliary Control Register (EL2) */
 373         HCR_EL2,        /* Hypervisor Configuration Register */
 374         MDCR_EL2,       /* Monitor Debug Configuration Register (EL2) */
 375         CPTR_EL2,       /* Architectural Feature Trap Register (EL2) */
 376         HSTR_EL2,       /* Hypervisor System Trap Register */
 377         HACR_EL2,       /* Hypervisor Auxiliary Control Register */
 378         TTBR0_EL2,      /* Translation Table Base Register 0 (EL2) */
 379         TTBR1_EL2,      /* Translation Table Base Register 1 (EL2) */
 380         TCR_EL2,        /* Translation Control Register (EL2) */
 381         VTTBR_EL2,      /* Virtualization Translation Table Base Register */
 382         VTCR_EL2,       /* Virtualization Translation Control Register */
 383         SPSR_EL2,       /* EL2 saved program status register */
 384         ELR_EL2,        /* EL2 exception link register */
 385         AFSR0_EL2,      /* Auxiliary Fault Status Register 0 (EL2) */
 386         AFSR1_EL2,      /* Auxiliary Fault Status Register 1 (EL2) */
 387         ESR_EL2,        /* Exception Syndrome Register (EL2) */
 388         FAR_EL2,        /* Fault Address Register (EL2) */
 389         HPFAR_EL2,      /* Hypervisor IPA Fault Address Register */
 390         MAIR_EL2,       /* Memory Attribute Indirection Register (EL2) */
 391         AMAIR_EL2,      /* Auxiliary Memory Attribute Indirection Register (EL2) */
 392         VBAR_EL2,       /* Vector Base Address Register (EL2) */
 393         RVBAR_EL2,      /* Reset Vector Base Address Register */
 394         CONTEXTIDR_EL2, /* Context ID Register (EL2) */
 395         TPIDR_EL2,      /* EL2 Software Thread ID Register */
 396         CNTHCTL_EL2,    /* Counter-timer Hypervisor Control register */
 397         SP_EL2,         /* EL2 Stack Pointer */
 398         CNTHP_CTL_EL2,
 399         CNTHP_CVAL_EL2,
 400         CNTHV_CTL_EL2,
 401         CNTHV_CVAL_EL2,
 402
 403         NR_SYS_REGS     /* Nothing after this line! */
 404 };
 405
 406 struct kvm_cpu_context {
 407         struct user_pt_regs regs;       /* sp = sp_el0 */
 408
 409         u64     spsr_abt;
 410         u64     spsr_und;
 411         u64     spsr_irq;
 412         u64     spsr_fiq;
 413
 414         struct user_fpsimd_state fp_regs;
 415
 416         u64 sys_regs[NR_SYS_REGS];
 417
 418         struct kvm_vcpu *__hyp_running_vcpu;
 419 };
 420
 421 struct kvm_host_data {
 422         struct kvm_cpu_context host_ctxt;
 423 };
 424
 425 struct kvm_host_psci_config {
 426         /* PSCI version used by host. */
 427         u32 version;
 428         u32 smccc_version;
 429
 430         /* Function IDs used by host if version is v0.1. */
 431         struct psci_0_1_function_ids function_ids_0_1;
 432
 433         bool psci_0_1_cpu_suspend_implemented;
 434         bool psci_0_1_cpu_on_implemented;
 435         bool psci_0_1_cpu_off_implemented;
 436         bool psci_0_1_migrate_implemented;
 437 };
 438
 439 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
 440 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
 441
 442 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
 443 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
 444
 445 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
 446 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
 447
 448 struct vcpu_reset_state {
 449         unsigned long   pc;
 450         unsigned long   r0;
 451         bool            be;
 452         bool            reset;
 453 };
 454
 455 struct kvm_vcpu_arch {
 456         struct kvm_cpu_context ctxt;
 457
 458         /*
 459          * Guest floating point state
 460          *
 461          * The architecture has two main floating point extensions,
 462          * the original FPSIMD and SVE.  These have overlapping
 463          * register views, with the FPSIMD V registers occupying the
 464          * low 128 bits of the SVE Z registers.  When the core
 465          * floating point code saves the register state of a task it
 466          * records which view it saved in fp_type.
 467          */
 468         void *sve_state;
 469         enum fp_type fp_type;
 470         unsigned int sve_max_vl;
 471         u64 svcr;
 472
 473         /* Stage 2 paging state used by the hardware on next switch */
 474         struct kvm_s2_mmu *hw_mmu;
 475
 476         /* Values of trap registers for the guest. */
 477         u64 hcr_el2;
 478         u64 mdcr_el2;
 479         u64 cptr_el2;
 480
 481         /* Values of trap registers for the host before guest entry. */
 482         u64 mdcr_el2_host;
 483
 484         /* Exception Information */
 485         struct kvm_vcpu_fault_info fault;
 486
 487         /* Ownership of the FP regs */
 488         enum {
 489                 FP_STATE_FREE,
 490                 FP_STATE_HOST_OWNED,
 491                 FP_STATE_GUEST_OWNED,
 492         } fp_state;
 493
 494         /* Configuration flags, set once and for all before the vcpu can run */
 495         u8 cflags;
 496
 497         /* Input flags to the hypervisor code, potentially cleared after use */
 498         u8 iflags;
 499
 500         /* State flags for kernel bookkeeping, unused by the hypervisor code */
 501         u8 sflags;
 502
 503         /*
 504          * Don't run the guest (internal implementation need).
 505          *
 506          * Contrary to the flags above, this is set/cleared outside of
 507          * a vcpu context, and thus cannot be mixed with the flags
 508          * themselves (or the flag accesses need to be made atomic).
 509          */
 510         bool pause;
 511
 512         /*
 513          * We maintain more than a single set of debug registers to support
 514          * debugging the guest from the host and to maintain separate host and
 515          * guest state during world switches. vcpu_debug_state are the debug
 516          * registers of the vcpu as the guest sees them.  host_debug_state are
 517          * the host registers which are saved and restored during
 518          * world switches. external_debug_state contains the debug
 519          * values we want to debug the guest. This is set via the
 520          * KVM_SET_GUEST_DEBUG ioctl.
 521          *
 522          * debug_ptr points to the set of debug registers that should be loaded
 523          * onto the hardware when running the guest.
 524          */
 525         struct kvm_guest_debug_arch *debug_ptr;
 526         struct kvm_guest_debug_arch vcpu_debug_state;
 527         struct kvm_guest_debug_arch external_debug_state;
 528
 529         struct user_fpsimd_state *host_fpsimd_state;    /* hyp VA */
 530         struct task_struct *parent_task;
 531
 532         struct {
 533                 /* {Break,watch}point registers */
 534                 struct kvm_guest_debug_arch regs;
 535                 /* Statistical profiling extension */
 536                 u64 pmscr_el1;
 537                 /* Self-hosted trace */
 538                 u64 trfcr_el1;
 539         } host_debug_state;
 540
 541         /* VGIC state */
 542         struct vgic_cpu vgic_cpu;
 543         struct arch_timer_cpu timer_cpu;
 544         struct kvm_pmu pmu;
 545
 546         /*
 547          * Guest registers we preserve during guest debugging.
 548          *
 549          * These shadow registers are updated by the kvm_handle_sys_reg
 550          * trap handler if the guest accesses or updates them while we
 551          * are using guest debug.
 552          */
 553         struct {
 554                 u32     mdscr_el1;
 555                 bool    pstate_ss;
 556         } guest_debug_preserved;
 557
 558         /* vcpu power state */
 559         struct kvm_mp_state mp_state;
 560         spinlock_t mp_state_lock;
 561
 562         /* Cache some mmu pages needed inside spinlock regions */
 563         struct kvm_mmu_memory_cache mmu_page_cache;
 564
 565         /* Target CPU and feature flags */
 566         int target;
 567         DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
 568
 569         /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
 570         u64 vsesr_el2;
 571
 572         /* Additional reset state */
 573         struct vcpu_reset_state reset_state;
 574
 575         /* Guest PV state */
 576         struct {
 577                 u64 last_steal;
 578                 gpa_t base;
 579         } steal;
 580
 581         /* Per-vcpu CCSIDR override or NULL */
 582         u32 *ccsidr;
 583 };
 584
 585 /*
 586  * Each 'flag' is composed of a comma-separated triplet:
 587  *
 588  * - the flag-set it belongs to in the vcpu->arch structure
 589  * - the value for that flag
 590  * - the mask for that flag
 591  *
 592  *  __vcpu_single_flag() builds such a triplet for a single-bit flag.
 593  * unpack_vcpu_flag() extract the flag value from the triplet for
 594  * direct use outside of the flag accessors.
 595  */
 596 #define __vcpu_single_flag(_set, _f)    _set, (_f), (_f)
 597
 598 #define __unpack_flag(_set, _f, _m)     _f
 599 #define unpack_vcpu_flag(...)           __unpack_flag(__VA_ARGS__)
 600
 601 #define __build_check_flag(v, flagset, f, m)                    \
 602         do {                                                    \
 603                 typeof(v->arch.flagset) *_fset;                 \
 604                                                                 \
 605                 /* Check that the flags fit in the mask */      \
 606                 BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m))); \
 607                 /* Check that the flags fit in the type */      \
 608                 BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m)); \
 609         } while (0)
 610
 611 #define __vcpu_get_flag(v, flagset, f, m)                       \
 612         ({                                                      \
 613                 __build_check_flag(v, flagset, f, m);           \
 614                                                                 \
 615                 READ_ONCE(v->arch.flagset) & (m);               \
 616         })
 617
 618 /*
 619  * Note that the set/clear accessors must be preempt-safe in order to
 620  * avoid nesting them with load/put which also manipulate flags...
 621  */
 622 #ifdef __KVM_NVHE_HYPERVISOR__
 623 /* the nVHE hypervisor is always non-preemptible */
 624 #define __vcpu_flags_preempt_disable()
 625 #define __vcpu_flags_preempt_enable()
 626 #else
 627 #define __vcpu_flags_preempt_disable()  preempt_disable()
 628 #define __vcpu_flags_preempt_enable()   preempt_enable()
 629 #endif
 630
 631 #define __vcpu_set_flag(v, flagset, f, m)                       \
 632         do {                                                    \
 633                 typeof(v->arch.flagset) *fset;                  \
 634                                                                 \
 635                 __build_check_flag(v, flagset, f, m);           \
 636                                                                 \
 637                 fset = &v->arch.flagset;                        \
 638                 __vcpu_flags_preempt_disable();                 \
 639                 if (HWEIGHT(m) > 1)                             \
 640                         *fset &= ~(m);                          \
 641                 *fset |= (f);                                   \
 642                 __vcpu_flags_preempt_enable();                  \
 643         } while (0)
 644
 645 #define __vcpu_clear_flag(v, flagset, f, m)                     \
 646         do {                                                    \
 647                 typeof(v->arch.flagset) *fset;                  \
 648                                                                 \
 649                 __build_check_flag(v, flagset, f, m);           \
 650                                                                 \
 651                 fset = &v->arch.flagset;                        \
 652                 __vcpu_flags_preempt_disable();                 \
 653                 *fset &= ~(m);                                  \
 654                 __vcpu_flags_preempt_enable();                  \
 655         } while (0)
 656
 657 #define vcpu_get_flag(v, ...)   __vcpu_get_flag((v), __VA_ARGS__)
 658 #define vcpu_set_flag(v, ...)   __vcpu_set_flag((v), __VA_ARGS__)
 659 #define vcpu_clear_flag(v, ...) __vcpu_clear_flag((v), __VA_ARGS__)
 660
 661 /* SVE exposed to guest */
 662 #define GUEST_HAS_SVE           __vcpu_single_flag(cflags, BIT(0))
 663 /* SVE config completed */
 664 #define VCPU_SVE_FINALIZED      __vcpu_single_flag(cflags, BIT(1))
 665 /* PTRAUTH exposed to guest */
 666 #define GUEST_HAS_PTRAUTH       __vcpu_single_flag(cflags, BIT(2))
 667
 668 /* Exception pending */
 669 #define PENDING_EXCEPTION       __vcpu_single_flag(iflags, BIT(0))
 670 /*
 671  * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
 672  * be set together with an exception...
 673  */
 674 #define INCREMENT_PC            __vcpu_single_flag(iflags, BIT(1))
 675 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
 676 #define EXCEPT_MASK             __vcpu_single_flag(iflags, GENMASK(3, 1))
 677
 678 /* Helpers to encode exceptions with minimum fuss */
 679 #define __EXCEPT_MASK_VAL       unpack_vcpu_flag(EXCEPT_MASK)
 680 #define __EXCEPT_SHIFT          __builtin_ctzl(__EXCEPT_MASK_VAL)
 681 #define __vcpu_except_flags(_f) iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
 682
 683 /*
 684  * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
 685  * values:
 686  *
 687  * For AArch32 EL1:
 688  */
 689 #define EXCEPT_AA32_UND         __vcpu_except_flags(0)
 690 #define EXCEPT_AA32_IABT        __vcpu_except_flags(1)
 691 #define EXCEPT_AA32_DABT        __vcpu_except_flags(2)
 692 /* For AArch64: */
 693 #define EXCEPT_AA64_EL1_SYNC    __vcpu_except_flags(0)
 694 #define EXCEPT_AA64_EL1_IRQ     __vcpu_except_flags(1)
 695 #define EXCEPT_AA64_EL1_FIQ     __vcpu_except_flags(2)
 696 #define EXCEPT_AA64_EL1_SERR    __vcpu_except_flags(3)
 697 /* For AArch64 with NV: */
 698 #define EXCEPT_AA64_EL2_SYNC    __vcpu_except_flags(4)
 699 #define EXCEPT_AA64_EL2_IRQ     __vcpu_except_flags(5)
 700 #define EXCEPT_AA64_EL2_FIQ     __vcpu_except_flags(6)
 701 #define EXCEPT_AA64_EL2_SERR    __vcpu_except_flags(7)
 702 /* Guest debug is live */
 703 #define DEBUG_DIRTY             __vcpu_single_flag(iflags, BIT(4))
 704 /* Save SPE context if active  */
 705 #define DEBUG_STATE_SAVE_SPE    __vcpu_single_flag(iflags, BIT(5))
 706 /* Save TRBE context if active  */
 707 #define DEBUG_STATE_SAVE_TRBE   __vcpu_single_flag(iflags, BIT(6))
 708 /* vcpu running in HYP context */
 709 #define VCPU_HYP_CONTEXT        __vcpu_single_flag(iflags, BIT(7))
 710
 711 /* SVE enabled for host EL0 */
 712 #define HOST_SVE_ENABLED        __vcpu_single_flag(sflags, BIT(0))
 713 /* SME enabled for EL0 */
 714 #define HOST_SME_ENABLED        __vcpu_single_flag(sflags, BIT(1))
 715 /* Physical CPU not in supported_cpus */
 716 #define ON_UNSUPPORTED_CPU      __vcpu_single_flag(sflags, BIT(2))
 717 /* WFIT instruction trapped */
 718 #define IN_WFIT                 __vcpu_single_flag(sflags, BIT(3))
 719 /* vcpu system registers loaded on physical CPU */
 720 #define SYSREGS_ON_CPU          __vcpu_single_flag(sflags, BIT(4))
 721 /* Software step state is Active-pending */
 722 #define DBG_SS_ACTIVE_PENDING   __vcpu_single_flag(sflags, BIT(5))
 723 /* PMUSERENR for the guest EL0 is on physical CPU */
 724 #define PMUSERENR_ON_CPU        __vcpu_single_flag(sflags, BIT(6))
 725
 726
 727 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
 728 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) +      \
 729                              sve_ffr_offset((vcpu)->arch.sve_max_vl))
 730
 731 #define vcpu_sve_max_vq(vcpu)   sve_vq_from_vl((vcpu)->arch.sve_max_vl)
 732
 733 #define vcpu_sve_state_size(vcpu) ({                                    \
 734         size_t __size_ret;                                              \
 735         unsigned int __vcpu_vq;                                         \
 736                                                                         \
 737         if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) {          \
 738                 __size_ret = 0;                                         \
 739         } else {                                                        \
 740                 __vcpu_vq = vcpu_sve_max_vq(vcpu);                      \
 741                 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq);              \
 742         }                                                               \
 743                                                                         \
 744         __size_ret;                                                     \
 745 })
 746
 747 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
 748                                  KVM_GUESTDBG_USE_SW_BP | \
 749                                  KVM_GUESTDBG_USE_HW | \
 750                                  KVM_GUESTDBG_SINGLESTEP)
 751
 752 #define vcpu_has_sve(vcpu) (system_supports_sve() &&                    \
 753                             vcpu_get_flag(vcpu, GUEST_HAS_SVE))
 754
 755 #ifdef CONFIG_ARM64_PTR_AUTH
 756 #define vcpu_has_ptrauth(vcpu)                                          \
 757         ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) ||                \
 758           cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) &&               \
 759           vcpu_get_flag(vcpu, GUEST_HAS_PTRAUTH))
 760 #else
 761 #define vcpu_has_ptrauth(vcpu)          false
 762 #endif
 763
 764 #define vcpu_on_unsupported_cpu(vcpu)                                   \
 765         vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
 766
 767 #define vcpu_set_on_unsupported_cpu(vcpu)                               \
 768         vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
 769
 770 #define vcpu_clear_on_unsupported_cpu(vcpu)                             \
 771         vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
 772
 773 #define vcpu_gp_regs(v)         (&(v)->arch.ctxt.regs)
 774
 775 /*
 776  * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
 777  * memory backed version of a register, and not the one most recently
 778  * accessed by a running VCPU.  For example, for userspace access or
 779  * for system registers that are never context switched, but only
 780  * emulated.
 781  */
 782 #define __ctxt_sys_reg(c,r)     (&(c)->sys_regs[(r)])
 783
 784 #define ctxt_sys_reg(c,r)       (*__ctxt_sys_reg(c,r))
 785
 786 #define __vcpu_sys_reg(v,r)     (ctxt_sys_reg(&(v)->arch.ctxt, (r)))
 787
 788 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
 789 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
 790
 791 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
 792 {
 793         /*
 794          * *** VHE ONLY ***
 795          *
 796          * System registers listed in the switch are not saved on every
 797          * exit from the guest but are only saved on vcpu_put.
 798          *
 799          * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
 800          * should never be listed below, because the guest cannot modify its
 801          * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
 802          * thread when emulating cross-VCPU communication.
 803          */
 804         if (!has_vhe())
 805                 return false;
 806
 807         switch (reg) {
 808         case SCTLR_EL1:         *val = read_sysreg_s(SYS_SCTLR_EL12);   break;
 809         case CPACR_EL1:         *val = read_sysreg_s(SYS_CPACR_EL12);   break;
 810         case TTBR0_EL1:         *val = read_sysreg_s(SYS_TTBR0_EL12);   break;
 811         case TTBR1_EL1:         *val = read_sysreg_s(SYS_TTBR1_EL12);   break;
 812         case TCR_EL1:           *val = read_sysreg_s(SYS_TCR_EL12);     break;
 813         case ESR_EL1:           *val = read_sysreg_s(SYS_ESR_EL12);     break;
 814         case AFSR0_EL1:         *val = read_sysreg_s(SYS_AFSR0_EL12);   break;
 815         case AFSR1_EL1:         *val = read_sysreg_s(SYS_AFSR1_EL12);   break;
 816         case FAR_EL1:           *val = read_sysreg_s(SYS_FAR_EL12);     break;
 817         case MAIR_EL1:          *val = read_sysreg_s(SYS_MAIR_EL12);    break;
 818         case VBAR_EL1:          *val = read_sysreg_s(SYS_VBAR_EL12);    break;
 819         case CONTEXTIDR_EL1:    *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
 820         case TPIDR_EL0:         *val = read_sysreg_s(SYS_TPIDR_EL0);    break;
 821         case TPIDRRO_EL0:       *val = read_sysreg_s(SYS_TPIDRRO_EL0);  break;
 822         case TPIDR_EL1:         *val = read_sysreg_s(SYS_TPIDR_EL1);    break;
 823         case AMAIR_EL1:         *val = read_sysreg_s(SYS_AMAIR_EL12);   break;
 824         case CNTKCTL_EL1:       *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
 825         case ELR_EL1:           *val = read_sysreg_s(SYS_ELR_EL12);     break;
 826         case PAR_EL1:           *val = read_sysreg_par();               break;
 827         case DACR32_EL2:        *val = read_sysreg_s(SYS_DACR32_EL2);   break;
 828         case IFSR32_EL2:        *val = read_sysreg_s(SYS_IFSR32_EL2);   break;
 829         case DBGVCR32_EL2:      *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
 830         default:                return false;
 831         }
 832
 833         return true;
 834 }
 835
 836 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
 837 {
 838         /*
 839          * *** VHE ONLY ***
 840          *
 841          * System registers listed in the switch are not restored on every
 842          * entry to the guest but are only restored on vcpu_load.
 843          *
 844          * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
 845          * should never be listed below, because the MPIDR should only be set
 846          * once, before running the VCPU, and never changed later.
 847          */
 848         if (!has_vhe())
 849                 return false;
 850
 851         switch (reg) {
 852         case SCTLR_EL1:         write_sysreg_s(val, SYS_SCTLR_EL12);    break;
 853         case CPACR_EL1:         write_sysreg_s(val, SYS_CPACR_EL12);    break;
 854         case TTBR0_EL1:         write_sysreg_s(val, SYS_TTBR0_EL12);    break;
 855         case TTBR1_EL1:         write_sysreg_s(val, SYS_TTBR1_EL12);    break;
 856         case TCR_EL1:           write_sysreg_s(val, SYS_TCR_EL12);      break;
 857         case ESR_EL1:           write_sysreg_s(val, SYS_ESR_EL12);      break;
 858         case AFSR0_EL1:         write_sysreg_s(val, SYS_AFSR0_EL12);    break;
 859         case AFSR1_EL1:         write_sysreg_s(val, SYS_AFSR1_EL12);    break;
 860         case FAR_EL1:           write_sysreg_s(val, SYS_FAR_EL12);      break;
 861         case MAIR_EL1:          write_sysreg_s(val, SYS_MAIR_EL12);     break;
 862         case VBAR_EL1:          write_sysreg_s(val, SYS_VBAR_EL12);     break;
 863         case CONTEXTIDR_EL1:    write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
 864         case TPIDR_EL0:         write_sysreg_s(val, SYS_TPIDR_EL0);     break;
 865         case TPIDRRO_EL0:       write_sysreg_s(val, SYS_TPIDRRO_EL0);   break;
 866         case TPIDR_EL1:         write_sysreg_s(val, SYS_TPIDR_EL1);     break;
 867         case AMAIR_EL1:         write_sysreg_s(val, SYS_AMAIR_EL12);    break;
 868         case CNTKCTL_EL1:       write_sysreg_s(val, SYS_CNTKCTL_EL12);  break;
 869         case ELR_EL1:           write_sysreg_s(val, SYS_ELR_EL12);      break;
 870         case PAR_EL1:           write_sysreg_s(val, SYS_PAR_EL1);       break;
 871         case DACR32_EL2:        write_sysreg_s(val, SYS_DACR32_EL2);    break;
 872         case IFSR32_EL2:        write_sysreg_s(val, SYS_IFSR32_EL2);    break;
 873         case DBGVCR32_EL2:      write_sysreg_s(val, SYS_DBGVCR32_EL2);  break;
 874         default:                return false;
 875         }
 876
 877         return true;
 878 }
 879
 880 struct kvm_vm_stat {
 881         struct kvm_vm_stat_generic generic;
 882 };
 883
 884 struct kvm_vcpu_stat {
 885         struct kvm_vcpu_stat_generic generic;
 886         u64 hvc_exit_stat;
 887         u64 wfe_exit_stat;
 888         u64 wfi_exit_stat;
 889         u64 mmio_exit_user;
 890         u64 mmio_exit_kernel;
 891         u64 signal_exits;
 892         u64 exits;
 893 };
 894
 895 void kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
 896 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
 897 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
 898 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 899 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
 900
 901 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
 902 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
 903
 904 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
 905                               struct kvm_vcpu_events *events);
 906
 907 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
 908                               struct kvm_vcpu_events *events);
 909
 910 #define KVM_ARCH_WANT_MMU_NOTIFIER
 911
 912 void kvm_arm_halt_guest(struct kvm *kvm);
 913 void kvm_arm_resume_guest(struct kvm *kvm);
 914
 915 #define vcpu_has_run_once(vcpu) !!rcu_access_pointer((vcpu)->pid)
 916
 917 #ifndef __KVM_NVHE_HYPERVISOR__
 918 #define kvm_call_hyp_nvhe(f, ...)                                               \
 919         ({                                                              \
 920                 struct arm_smccc_res res;                               \
 921                                                                         \
 922                 arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f),               \
 923                                   ##__VA_ARGS__, &res);                 \
 924                 WARN_ON(res.a0 != SMCCC_RET_SUCCESS);                   \
 925                                                                         \
 926                 res.a1;                                                 \
 927         })
 928
 929 /*
 930  * The couple of isb() below are there to guarantee the same behaviour
 931  * on VHE as on !VHE, where the eret to EL1 acts as a context
 932  * synchronization event.
 933  */
 934 #define kvm_call_hyp(f, ...)                                            \
 935         do {                                                            \
 936                 if (has_vhe()) {                                        \
 937                         f(__VA_ARGS__);                                 \
 938                         isb();                                          \
 939                 } else {                                                \
 940                         kvm_call_hyp_nvhe(f, ##__VA_ARGS__);            \
 941                 }                                                       \
 942         } while(0)
 943
 944 #define kvm_call_hyp_ret(f, ...)                                        \
 945         ({                                                              \
 946                 typeof(f(__VA_ARGS__)) ret;                             \
 947                                                                         \
 948                 if (has_vhe()) {                                        \
 949                         ret = f(__VA_ARGS__);                           \
 950                         isb();                                          \
 951                 } else {                                                \
 952                         ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__);      \
 953                 }                                                       \
 954                                                                         \
 955                 ret;                                                    \
 956         })
 957 #else /* __KVM_NVHE_HYPERVISOR__ */
 958 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
 959 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
 960 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
 961 #endif /* __KVM_NVHE_HYPERVISOR__ */
 962
 963 void force_vm_exit(const cpumask_t *mask);
 964
 965 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
 966 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
 967
 968 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
 969 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
 970 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
 971 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
 972 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
 973 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
 974 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
 975
 976 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
 977
 978 int __init kvm_sys_reg_table_init(void);
 979
 980 bool lock_all_vcpus(struct kvm *kvm);
 981 void unlock_all_vcpus(struct kvm *kvm);
 982
 983 /* MMIO helpers */
 984 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
 985 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
 986
 987 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
 988 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
 989
 990 /*
 991  * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
 992  * arrived in guest context.  For arm64, any event that arrives while a vCPU is
 993  * loaded is considered to be "in guest".
 994  */
 995 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
 996 {
 997         return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
 998 }
 999
1000 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
1001 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
1002 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
1003
1004 bool kvm_arm_pvtime_supported(void);
1005 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
1006                             struct kvm_device_attr *attr);
1007 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
1008                             struct kvm_device_attr *attr);
1009 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
1010                             struct kvm_device_attr *attr);
1011
1012 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
1013 int __init kvm_arm_vmid_alloc_init(void);
1014 void __init kvm_arm_vmid_alloc_free(void);
1015 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
1016 void kvm_arm_vmid_clear_active(void);
1017
1018 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
1019 {
1020         vcpu_arch->steal.base = INVALID_GPA;
1021 }
1022
1023 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
1024 {
1025         return (vcpu_arch->steal.base != INVALID_GPA);
1026 }
1027
1028 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
1029
1030 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
1031
1032 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
1033
1034 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
1035 {
1036         /* The host's MPIDR is immutable, so let's set it up at boot time */
1037         ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
1038 }
1039
1040 static inline bool kvm_system_needs_idmapped_vectors(void)
1041 {
1042         return cpus_have_const_cap(ARM64_SPECTRE_V3A);
1043 }
1044
1045 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu);
1046
1047 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
1048 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
1049
1050 void kvm_arm_init_debug(void);
1051 void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu);
1052 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
1053 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
1054 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
1055
1056 #define kvm_vcpu_os_lock_enabled(vcpu)          \
1057         (!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & SYS_OSLSR_OSLK))
1058
1059 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1060                                struct kvm_device_attr *attr);
1061 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1062                                struct kvm_device_attr *attr);
1063 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1064                                struct kvm_device_attr *attr);
1065
1066 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1067                                struct kvm_arm_copy_mte_tags *copy_tags);
1068 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm,
1069                                     struct kvm_arm_counter_offset *offset);
1070
1071 /* Guest/host FPSIMD coordination helpers */
1072 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1073 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1074 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1075 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1076 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1077 void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu);
1078
1079 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1080 {
1081         return (!has_vhe() && attr->exclude_host);
1082 }
1083
1084 /* Flags for host debug state */
1085 void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
1086 void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
1087
1088 #ifdef CONFIG_KVM
1089 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
1090 void kvm_clr_pmu_events(u32 clr);
1091 bool kvm_set_pmuserenr(u64 val);
1092 #else
1093 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
1094 static inline void kvm_clr_pmu_events(u32 clr) {}
1095 static inline bool kvm_set_pmuserenr(u64 val)
1096 {
1097         return false;
1098 }
1099 #endif
1100
1101 void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
1102 void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu);
1103
1104 int __init kvm_set_ipa_limit(void);
1105
1106 #define __KVM_HAVE_ARCH_VM_ALLOC
1107 struct kvm *kvm_arch_alloc_vm(void);
1108
1109 static inline bool kvm_vm_is_protected(struct kvm *kvm)
1110 {
1111         return false;
1112 }
1113
1114 void kvm_init_protected_traps(struct kvm_vcpu *vcpu);
1115
1116 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1117 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1118
1119 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1120
1121 #define kvm_has_mte(kvm)                                        \
1122         (system_supports_mte() &&                               \
1123          test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1124
1125 #define kvm_supports_32bit_el0()                                \
1126         (system_supports_32bit_el0() &&                         \
1127          !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1128
1129 #define kvm_vm_has_ran_once(kvm)                                        \
1130         (test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags))
1131
1132 int kvm_trng_call(struct kvm_vcpu *vcpu);
1133 #ifdef CONFIG_KVM
1134 extern phys_addr_t hyp_mem_base;
1135 extern phys_addr_t hyp_mem_size;
1136 void __init kvm_hyp_reserve(void);
1137 #else
1138 static inline void kvm_hyp_reserve(void) { }
1139 #endif
1140
1141 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1142 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1143
1144 #endif /* __ARM64_KVM_HOST_H__ */