1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/include/kvm_emulate.h
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
11 #ifndef __ARM64_KVM_EMULATE_H__
12 #define __ARM64_KVM_EMULATE_H__
14 #include <linux/kvm_host.h>
16 #include <asm/debug-monitors.h>
18 #include <asm/kvm_arm.h>
19 #include <asm/kvm_hyp.h>
20 #include <asm/ptrace.h>
21 #include <asm/cputype.h>
24 #define CURRENT_EL_SP_EL0_VECTOR 0x0
25 #define CURRENT_EL_SP_ELx_VECTOR 0x200
26 #define LOWER_EL_AArch64_VECTOR 0x400
27 #define LOWER_EL_AArch32_VECTOR 0x600
31 except_type_irq = 0x80,
32 except_type_fiq = 0x100,
33 except_type_serror = 0x180,
36 #define kvm_exception_type_names \
37 { except_type_sync, "SYNC" }, \
38 { except_type_irq, "IRQ" }, \
39 { except_type_fiq, "FIQ" }, \
40 { except_type_serror, "SERROR" }
42 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
43 void kvm_skip_instr32(struct kvm_vcpu *vcpu);
45 void kvm_inject_undefined(struct kvm_vcpu *vcpu);
46 void kvm_inject_vabt(struct kvm_vcpu *vcpu);
47 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
48 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
49 void kvm_inject_size_fault(struct kvm_vcpu *vcpu);
51 void kvm_vcpu_wfi(struct kvm_vcpu *vcpu);
53 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu);
54 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2);
55 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu);
57 #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__)
58 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
60 return !(vcpu->arch.hcr_el2 & HCR_RW);
63 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
65 struct kvm *kvm = vcpu->kvm;
67 WARN_ON_ONCE(!test_bit(KVM_ARCH_FLAG_REG_WIDTH_CONFIGURED,
70 return test_bit(KVM_ARCH_FLAG_EL1_32BIT, &kvm->arch.flags);
74 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
76 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
77 if (is_kernel_in_hyp_mode())
78 vcpu->arch.hcr_el2 |= HCR_E2H;
79 if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) {
80 /* route synchronous external abort exceptions to EL2 */
81 vcpu->arch.hcr_el2 |= HCR_TEA;
82 /* trap error record accesses */
83 vcpu->arch.hcr_el2 |= HCR_TERR;
86 if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {
87 vcpu->arch.hcr_el2 |= HCR_FWB;
90 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C
91 * get set in SCTLR_EL1 such that we can detect when the guest
92 * MMU gets turned on and do the necessary cache maintenance
95 vcpu->arch.hcr_el2 |= HCR_TVM;
98 if (vcpu_el1_is_32bit(vcpu))
99 vcpu->arch.hcr_el2 &= ~HCR_RW;
101 if (kvm_has_mte(vcpu->kvm))
102 vcpu->arch.hcr_el2 |= HCR_ATA;
105 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
107 return (unsigned long *)&vcpu->arch.hcr_el2;
110 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu)
112 vcpu->arch.hcr_el2 &= ~HCR_TWE;
113 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) ||
114 vcpu->kvm->arch.vgic.nassgireq)
115 vcpu->arch.hcr_el2 &= ~HCR_TWI;
117 vcpu->arch.hcr_el2 |= HCR_TWI;
120 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu)
122 vcpu->arch.hcr_el2 |= HCR_TWE;
123 vcpu->arch.hcr_el2 |= HCR_TWI;
126 static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu)
128 vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
131 static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
133 vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
136 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
138 return vcpu->arch.vsesr_el2;
141 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
143 vcpu->arch.vsesr_el2 = vsesr;
146 static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
148 return (unsigned long *)&vcpu_gp_regs(vcpu)->pc;
151 static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
153 return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate;
156 static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
158 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
161 static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
163 if (vcpu_mode_is_32bit(vcpu))
164 return kvm_condition_valid32(vcpu);
169 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
171 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;
175 * vcpu_get_reg and vcpu_set_reg should always be passed a register number
176 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
177 * AArch32 with banked registers.
179 static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
182 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
185 static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
189 vcpu_gp_regs(vcpu)->regs[reg_num] = val;
192 static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt)
194 switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) {
203 static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu)
205 return vcpu_is_el2_ctxt(&vcpu->arch.ctxt);
208 static inline bool __vcpu_el2_e2h_is_set(const struct kvm_cpu_context *ctxt)
210 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_E2H;
213 static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu)
215 return __vcpu_el2_e2h_is_set(&vcpu->arch.ctxt);
218 static inline bool __vcpu_el2_tge_is_set(const struct kvm_cpu_context *ctxt)
220 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_TGE;
223 static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu)
225 return __vcpu_el2_tge_is_set(&vcpu->arch.ctxt);
228 static inline bool __is_hyp_ctxt(const struct kvm_cpu_context *ctxt)
231 * We are in a hypervisor context if the vcpu mode is EL2 or
232 * E2H and TGE bits are set. The latter means we are in the user space
233 * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost'
235 * Note that the HCR_EL2.{E2H,TGE}={0,1} isn't really handled in the
236 * rest of the KVM code, and will result in a misbehaving guest.
238 return vcpu_is_el2_ctxt(ctxt) ||
239 (__vcpu_el2_e2h_is_set(ctxt) && __vcpu_el2_tge_is_set(ctxt)) ||
240 __vcpu_el2_tge_is_set(ctxt);
243 static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu)
245 return __is_hyp_ctxt(&vcpu->arch.ctxt);
249 * The layout of SPSR for an AArch32 state is different when observed from an
250 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
251 * view given an AArch64 view.
253 * In ARM DDI 0487E.a see:
255 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426
256 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
257 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
259 * Which show the following differences:
261 * | Bit | AA64 | AA32 | Notes |
262 * +-----+------+------+-----------------------------|
263 * | 24 | DIT | J | J is RES0 in ARMv8 |
264 * | 21 | SS | DIT | SS doesn't exist in AArch32 |
266 * ... and all other bits are (currently) common.
268 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
270 const unsigned long overlap = BIT(24) | BIT(21);
271 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT);
280 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
284 if (vcpu_mode_is_32bit(vcpu)) {
285 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
286 return mode > PSR_AA32_MODE_USR;
289 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
291 return mode != PSR_MODE_EL0t;
294 static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu)
296 return vcpu->arch.fault.esr_el2;
299 static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
301 u64 esr = kvm_vcpu_get_esr(vcpu);
303 if (esr & ESR_ELx_CV)
304 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
309 static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
311 return vcpu->arch.fault.far_el2;
314 static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
316 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
319 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
321 return vcpu->arch.fault.disr_el1;
324 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
326 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK;
329 static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
331 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV);
334 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu)
336 return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);
339 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
341 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE);
344 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
346 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF);
349 static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
351 return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
354 static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu)
356 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW);
359 /* Always check for S1PTW *before* using this. */
360 static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
362 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR;
365 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
367 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM);
370 static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
372 return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
375 /* This one is not specific to Data Abort */
376 static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
378 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL);
381 static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
383 return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu));
386 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
388 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
391 static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu)
393 return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu);
396 static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
398 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC;
401 static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
403 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_TYPE;
406 static __always_inline u8 kvm_vcpu_trap_get_fault_level(const struct kvm_vcpu *vcpu)
408 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_LEVEL;
411 static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu)
413 switch (kvm_vcpu_trap_get_fault(vcpu)) {
414 case ESR_ELx_FSC_EXTABT:
415 case ESR_ELx_FSC_SEA_TTW0:
416 case ESR_ELx_FSC_SEA_TTW1:
417 case ESR_ELx_FSC_SEA_TTW2:
418 case ESR_ELx_FSC_SEA_TTW3:
419 case ESR_ELx_FSC_SECC:
420 case ESR_ELx_FSC_SECC_TTW0:
421 case ESR_ELx_FSC_SECC_TTW1:
422 case ESR_ELx_FSC_SECC_TTW2:
423 case ESR_ELx_FSC_SECC_TTW3:
430 static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
432 u64 esr = kvm_vcpu_get_esr(vcpu);
433 return ESR_ELx_SYS64_ISS_RT(esr);
436 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
438 if (kvm_vcpu_abt_iss1tw(vcpu)) {
440 * Only a permission fault on a S1PTW should be
441 * considered as a write. Otherwise, page tables baked
442 * in a read-only memslot will result in an exception
443 * being delivered in the guest.
445 * The drawback is that we end-up faulting twice if the
446 * guest is using any of HW AF/DB: a translation fault
447 * to map the page containing the PT (read only at
448 * first), then a permission fault to allow the flags
451 switch (kvm_vcpu_trap_get_fault_type(vcpu)) {
452 case ESR_ELx_FSC_PERM:
459 if (kvm_vcpu_trap_is_iabt(vcpu))
462 return kvm_vcpu_dabt_iswrite(vcpu);
465 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
467 return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
470 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
472 if (vcpu_mode_is_32bit(vcpu)) {
473 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;
475 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
476 sctlr |= SCTLR_ELx_EE;
477 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
481 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
483 if (vcpu_mode_is_32bit(vcpu))
484 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);
486 if (vcpu_mode_priv(vcpu))
487 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE);
489 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E);
492 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
496 if (kvm_vcpu_is_be(vcpu)) {
501 return be16_to_cpu(data & 0xffff);
503 return be32_to_cpu(data & 0xffffffff);
505 return be64_to_cpu(data);
512 return le16_to_cpu(data & 0xffff);
514 return le32_to_cpu(data & 0xffffffff);
516 return le64_to_cpu(data);
520 return data; /* Leave LE untouched */
523 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
527 if (kvm_vcpu_is_be(vcpu)) {
532 return cpu_to_be16(data & 0xffff);
534 return cpu_to_be32(data & 0xffffffff);
536 return cpu_to_be64(data);
543 return cpu_to_le16(data & 0xffff);
545 return cpu_to_le32(data & 0xffffffff);
547 return cpu_to_le64(data);
551 return data; /* Leave LE untouched */
554 static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu)
556 WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION));
557 vcpu_set_flag(vcpu, INCREMENT_PC);
560 #define kvm_pend_exception(v, e) \
562 WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \
563 vcpu_set_flag((v), PENDING_EXCEPTION); \
564 vcpu_set_flag((v), e); \
568 static inline bool vcpu_has_feature(struct kvm_vcpu *vcpu, int feature)
570 return test_bit(feature, vcpu->arch.features);
573 static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu)
578 val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |
579 CPACR_EL1_ZEN_EL1EN);
580 } else if (has_hvhe()) {
581 val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN);
583 val = CPTR_NVHE_EL2_RES1;
585 if (vcpu_has_sve(vcpu) &&
586 (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED))
588 if (cpus_have_final_cap(ARM64_SME))
589 val &= ~CPTR_EL2_TSM;
595 static __always_inline void kvm_reset_cptr_el2(struct kvm_vcpu *vcpu)
597 u64 val = kvm_get_reset_cptr_el2(vcpu);
599 if (has_vhe() || has_hvhe())
600 write_sysreg(val, cpacr_el1);
602 write_sysreg(val, cptr_el2);
604 #endif /* __ARM64_KVM_EMULATE_H__ */