1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
6 #ifndef __ASM_CPUFEATURE_H
7 #define __ASM_CPUFEATURE_H
9 #include <asm/alternative-macros.h>
10 #include <asm/cpucaps.h>
11 #include <asm/cputype.h>
12 #include <asm/hwcap.h>
13 #include <asm/sysreg.h>
15 #define MAX_CPU_FEATURES 128
16 #define cpu_feature(x) KERNEL_HWCAP_ ## x
20 #include <linux/bug.h>
21 #include <linux/jump_label.h>
22 #include <linux/kernel.h>
25 * CPU feature register tracking
27 * The safe value of a CPUID feature field is dependent on the implications
28 * of the values assigned to it by the architecture. Based on the relationship
29 * between the values, the features are classified into 3 types - LOWER_SAFE,
30 * HIGHER_SAFE and EXACT.
32 * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest
33 * for HIGHER_SAFE. It is expected that all CPUs have the same value for
34 * a field when EXACT is specified, failing which, the safe value specified
35 * in the table is chosen.
39 FTR_EXACT, /* Use a predefined safe value */
40 FTR_LOWER_SAFE, /* Smaller value is safe */
41 FTR_HIGHER_SAFE, /* Bigger value is safe */
42 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
45 #define FTR_STRICT true /* SANITY check strict matching required */
46 #define FTR_NONSTRICT false /* SANITY check ignored */
48 #define FTR_SIGNED true /* Value should be treated as signed */
49 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
51 #define FTR_VISIBLE true /* Feature visible to the user space */
52 #define FTR_HIDDEN false /* Feature is hidden from the user */
54 #define FTR_VISIBLE_IF_IS_ENABLED(config) \
55 (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN)
57 struct arm64_ftr_bits {
58 bool sign; /* Value is signed ? */
60 bool strict; /* CPU Sanity check: strict matching required ? */
64 s64 safe_val; /* safe value for FTR_EXACT features */
68 * Describe the early feature override to the core override code:
70 * @val Values that are to be merged into the final
71 * sanitised value of the register. Only the bitfields
72 * set to 1 in @mask are valid
73 * @mask Mask of the features that are overridden by @val
75 * A @mask field set to full-1 indicates that the corresponding field
76 * in @val is a valid override.
78 * A @mask field set to full-0 with the corresponding @val field set
79 * to full-0 denotes that this field has no override
81 * A @mask field set to full-0 with the corresponding @val field set
82 * to full-1 denotes thath this field has an invalid override.
84 struct arm64_ftr_override {
90 * @arm64_ftr_reg - Feature register
91 * @strict_mask Bits which should match across all CPUs for sanity.
92 * @sys_val Safe value across the CPUs (system view)
94 struct arm64_ftr_reg {
100 struct arm64_ftr_override *override;
101 const struct arm64_ftr_bits *ftr_bits;
104 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
109 * We use arm64_cpu_capabilities to represent system features, errata work
110 * arounds (both used internally by kernel and tracked in cpu_hwcaps) and
111 * ELF HWCAPs (which are exposed to user).
113 * To support systems with heterogeneous CPUs, we need to make sure that we
114 * detect the capabilities correctly on the system and take appropriate
115 * measures to ensure there are no incompatibilities.
117 * This comment tries to explain how we treat the capabilities.
118 * Each capability has the following list of attributes :
120 * 1) Scope of Detection : The system detects a given capability by
121 * performing some checks at runtime. This could be, e.g, checking the
122 * value of a field in CPU ID feature register or checking the cpu
123 * model. The capability provides a call back ( @matches() ) to
124 * perform the check. Scope defines how the checks should be performed.
125 * There are three cases:
127 * a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one
128 * matches. This implies, we have to run the check on all the
129 * booting CPUs, until the system decides that state of the
130 * capability is finalised. (See section 2 below)
132 * b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs
133 * matches. This implies, we run the check only once, when the
134 * system decides to finalise the state of the capability. If the
135 * capability relies on a field in one of the CPU ID feature
136 * registers, we use the sanitised value of the register from the
137 * CPU feature infrastructure to make the decision.
139 * c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the
140 * feature. This category is for features that are "finalised"
141 * (or used) by the kernel very early even before the SMP cpus
144 * The process of detection is usually denoted by "update" capability
147 * 2) Finalise the state : The kernel should finalise the state of a
148 * capability at some point during its execution and take necessary
149 * actions if any. Usually, this is done, after all the boot-time
150 * enabled CPUs are brought up by the kernel, so that it can make
151 * better decision based on the available set of CPUs. However, there
152 * are some special cases, where the action is taken during the early
153 * boot by the primary boot CPU. (e.g, running the kernel at EL2 with
154 * Virtualisation Host Extensions). The kernel usually disallows any
155 * changes to the state of a capability once it finalises the capability
156 * and takes any action, as it may be impossible to execute the actions
157 * safely. A CPU brought up after a capability is "finalised" is
158 * referred to as "Late CPU" w.r.t the capability. e.g, all secondary
159 * CPUs are treated "late CPUs" for capabilities determined by the boot
162 * At the moment there are two passes of finalising the capabilities.
163 * a) Boot CPU scope capabilities - Finalised by primary boot CPU via
164 * setup_boot_cpu_capabilities().
165 * b) Everything except (a) - Run via setup_system_capabilities().
167 * 3) Verification: When a CPU is brought online (e.g, by user or by the
168 * kernel), the kernel should make sure that it is safe to use the CPU,
169 * by verifying that the CPU is compliant with the state of the
170 * capabilities finalised already. This happens via :
172 * secondary_start_kernel()-> check_local_cpu_capabilities()
174 * As explained in (2) above, capabilities could be finalised at
175 * different points in the execution. Each newly booted CPU is verified
176 * against the capabilities that have been finalised by the time it
179 * a) SCOPE_BOOT_CPU : All CPUs are verified against the capability
180 * except for the primary boot CPU.
182 * b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the
183 * user after the kernel boot are verified against the capability.
185 * If there is a conflict, the kernel takes an action, based on the
186 * severity (e.g, a CPU could be prevented from booting or cause a
187 * kernel panic). The CPU is allowed to "affect" the state of the
188 * capability, if it has not been finalised already. See section 5
189 * for more details on conflicts.
191 * 4) Action: As mentioned in (2), the kernel can take an action for each
192 * detected capability, on all CPUs on the system. Appropriate actions
193 * include, turning on an architectural feature, modifying the control
194 * registers (e.g, SCTLR, TCR etc.) or patching the kernel via
195 * alternatives. The kernel patching is batched and performed at later
196 * point. The actions are always initiated only after the capability
197 * is finalised. This is usally denoted by "enabling" the capability.
198 * The actions are initiated as follows :
199 * a) Action is triggered on all online CPUs, after the capability is
200 * finalised, invoked within the stop_machine() context from
201 * enable_cpu_capabilitie().
203 * b) Any late CPU, brought up after (1), the action is triggered via:
205 * check_local_cpu_capabilities() -> verify_local_cpu_capabilities()
207 * 5) Conflicts: Based on the state of the capability on a late CPU vs.
208 * the system state, we could have the following combinations :
210 * x-----------------------------x
211 * | Type | System | Late CPU |
212 * |-----------------------------|
214 * |-----------------------------|
216 * x-----------------------------x
218 * Two separate flag bits are defined to indicate whether each kind of
219 * conflict can be allowed:
220 * ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed
221 * ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed
223 * Case (a) is not permitted for a capability that the system requires
224 * all CPUs to have in order for the capability to be enabled. This is
225 * typical for capabilities that represent enhanced functionality.
227 * Case (b) is not permitted for a capability that must be enabled
228 * during boot if any CPU in the system requires it in order to run
229 * safely. This is typical for erratum work arounds that cannot be
230 * enabled after the corresponding capability is finalised.
232 * In some non-typical cases either both (a) and (b), or neither,
233 * should be permitted. This can be described by including neither
234 * or both flags in the capability's type field.
236 * In case of a conflict, the CPU is prevented from booting. If the
237 * ARM64_CPUCAP_PANIC_ON_CONFLICT flag is specified for the capability,
238 * then a kernel panic is triggered.
243 * Decide how the capability is detected.
244 * On any local CPU vs System wide vs the primary boot CPU
246 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0))
247 #define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1))
249 * The capabilitiy is detected on the Boot CPU and is used by kernel
250 * during early boot. i.e, the capability should be "detected" and
251 * "enabled" as early as possibly on all booting CPUs.
253 #define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2))
254 #define ARM64_CPUCAP_SCOPE_MASK \
255 (ARM64_CPUCAP_SCOPE_SYSTEM | \
256 ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
257 ARM64_CPUCAP_SCOPE_BOOT_CPU)
259 #define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM
260 #define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU
261 #define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU
262 #define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK
265 * Is it permitted for a late CPU to have this capability when system
266 * hasn't already enabled it ?
268 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4))
269 /* Is it safe for a late CPU to miss this capability when system has it */
270 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5))
271 /* Panic when a conflict is detected */
272 #define ARM64_CPUCAP_PANIC_ON_CONFLICT ((u16)BIT(6))
275 * CPU errata workarounds that need to be enabled at boot time if one or
276 * more CPUs in the system requires it. When one of these capabilities
277 * has been enabled, it is safe to allow any CPU to boot that doesn't
278 * require the workaround. However, it is not safe if a "late" CPU
279 * requires a workaround and the system hasn't enabled it already.
281 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM \
282 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
284 * CPU feature detected at boot time based on system-wide value of a
285 * feature. It is safe for a late CPU to have this feature even though
286 * the system hasn't enabled it, although the feature will not be used
287 * by Linux in this case. If the system has enabled this feature already,
288 * then every late CPU must have it.
290 #define ARM64_CPUCAP_SYSTEM_FEATURE \
291 (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
293 * CPU feature detected at boot time based on feature of one or more CPUs.
294 * All possible conflicts for a late CPU are ignored.
295 * NOTE: this means that a late CPU with the feature will *not* cause the
296 * capability to be advertised by cpus_have_*cap()!
298 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \
299 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
300 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | \
301 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
304 * CPU feature detected at boot time, on one or more CPUs. A late CPU
305 * is not allowed to have the capability when the system doesn't have it.
306 * It is Ok for a late CPU to miss the feature.
308 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE \
309 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \
310 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
313 * CPU feature used early in the boot based on the boot CPU. All secondary
314 * CPUs must match the state of the capability as detected by the boot CPU. In
315 * case of a conflict, a kernel panic is triggered.
317 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE \
318 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PANIC_ON_CONFLICT)
321 * CPU feature used early in the boot based on the boot CPU. It is safe for a
322 * late CPU to have this feature even though the boot CPU hasn't enabled it,
323 * although the feature will not be used by Linux in this case. If the boot CPU
324 * has enabled this feature already, then every late CPU must have it.
326 #define ARM64_CPUCAP_BOOT_CPU_FEATURE \
327 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
329 struct arm64_cpu_capabilities {
333 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
335 * Take the appropriate actions to configure this capability
336 * for this CPU. If the capability is detected by the kernel
337 * this will be called on all the CPUs in the system,
338 * including the hotplugged CPUs, regardless of whether the
339 * capability is available on that specific CPU. This is
340 * useful for some capabilities (e.g, working around CPU
341 * errata), where all the CPUs must take some action (e.g,
342 * changing system control/configuration). Thus, if an action
343 * is required only if the CPU has the capability, then the
344 * routine must check it before taking any action.
346 void (*cpu_enable)(const struct arm64_cpu_capabilities *cap);
348 struct { /* To be used for erratum handling only */
349 struct midr_range midr_range;
350 const struct arm64_midr_revidr {
351 u32 midr_rv; /* revision/variant */
353 } * const fixed_revs;
356 const struct midr_range *midr_range_list;
357 struct { /* Feature register checking */
369 * An optional list of "matches/cpu_enable" pair for the same
370 * "capability" of the same "type" as described by the parent.
371 * Only matches(), cpu_enable() and fields relevant to these
372 * methods are significant in the list. The cpu_enable is
373 * invoked only if the corresponding entry "matches()".
374 * However, if a cpu_enable() method is associated
375 * with multiple matches(), care should be taken that either
376 * the match criteria are mutually exclusive, or that the
377 * method is robust against being called multiple times.
379 const struct arm64_cpu_capabilities *match_list;
382 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap)
384 return cap->type & ARM64_CPUCAP_SCOPE_MASK;
388 * Generic helper for handling capabilities with multiple (match,enable) pairs
389 * of call backs, sharing the same capability bit.
390 * Iterate over each entry to see if at least one matches.
393 cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry,
396 const struct arm64_cpu_capabilities *caps;
398 for (caps = entry->match_list; caps->matches; caps++)
399 if (caps->matches(caps, scope))
405 static __always_inline bool is_vhe_hyp_code(void)
407 /* Only defined for code run in VHE hyp context */
408 return __is_defined(__KVM_VHE_HYPERVISOR__);
411 static __always_inline bool is_nvhe_hyp_code(void)
413 /* Only defined for code run in NVHE hyp context */
414 return __is_defined(__KVM_NVHE_HYPERVISOR__);
417 static __always_inline bool is_hyp_code(void)
419 return is_vhe_hyp_code() || is_nvhe_hyp_code();
422 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
424 extern DECLARE_BITMAP(boot_capabilities, ARM64_NCAPS);
426 #define for_each_available_cap(cap) \
427 for_each_set_bit(cap, cpu_hwcaps, ARM64_NCAPS)
429 bool this_cpu_has_cap(unsigned int cap);
430 void cpu_set_feature(unsigned int num);
431 bool cpu_have_feature(unsigned int num);
432 unsigned long cpu_get_elf_hwcap(void);
433 unsigned long cpu_get_elf_hwcap2(void);
435 #define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name))
436 #define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name))
438 static __always_inline bool system_capabilities_finalized(void)
440 return alternative_has_feature_likely(ARM64_ALWAYS_SYSTEM);
444 * Test for a capability with a runtime check.
446 * Before the capability is detected, this returns false.
448 static __always_inline bool cpus_have_cap(unsigned int num)
450 if (num >= ARM64_NCAPS)
452 return arch_test_bit(num, cpu_hwcaps);
456 * Test for a capability without a runtime check.
458 * Before capabilities are finalized, this returns false.
459 * After capabilities are finalized, this is patched to avoid a runtime check.
461 * @num must be a compile-time constant.
463 static __always_inline bool __cpus_have_const_cap(int num)
465 if (num >= ARM64_NCAPS)
467 return alternative_has_feature_unlikely(num);
471 * Test for a capability without a runtime check.
473 * Before capabilities are finalized, this will BUG().
474 * After capabilities are finalized, this is patched to avoid a runtime check.
476 * @num must be a compile-time constant.
478 static __always_inline bool cpus_have_final_cap(int num)
480 if (system_capabilities_finalized())
481 return __cpus_have_const_cap(num);
487 * Test for a capability, possibly with a runtime check for non-hyp code.
489 * For hyp code, this behaves the same as cpus_have_final_cap().
492 * Before capabilities are finalized, this behaves as cpus_have_cap().
493 * After capabilities are finalized, this is patched to avoid a runtime check.
495 * @num must be a compile-time constant.
497 static __always_inline bool cpus_have_const_cap(int num)
500 return cpus_have_final_cap(num);
501 else if (system_capabilities_finalized())
502 return __cpus_have_const_cap(num);
504 return cpus_have_cap(num);
507 static inline void cpus_set_cap(unsigned int num)
509 if (num >= ARM64_NCAPS) {
510 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
513 __set_bit(num, cpu_hwcaps);
517 static inline int __attribute_const__
518 cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
520 return (s64)(features << (64 - width - field)) >> (64 - width);
523 static inline int __attribute_const__
524 cpuid_feature_extract_signed_field(u64 features, int field)
526 return cpuid_feature_extract_signed_field_width(features, field, 4);
529 static __always_inline unsigned int __attribute_const__
530 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
532 return (u64)(features << (64 - width - field)) >> (64 - width);
535 static __always_inline unsigned int __attribute_const__
536 cpuid_feature_extract_unsigned_field(u64 features, int field)
538 return cpuid_feature_extract_unsigned_field_width(features, field, 4);
542 * Fields that identify the version of the Performance Monitors Extension do
543 * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825,
544 * "Alternative ID scheme used for the Performance Monitors Extension version".
546 static inline u64 __attribute_const__
547 cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap)
549 u64 val = cpuid_feature_extract_unsigned_field(features, field);
550 u64 mask = GENMASK_ULL(field + 3, field);
552 /* Treat IMPLEMENTATION DEFINED functionality as unimplemented */
553 if (val == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
558 features |= (cap << field) & mask;
564 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
566 return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
569 static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg)
571 return (reg->user_val | (reg->sys_val & reg->user_mask));
574 static inline int __attribute_const__
575 cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
577 if (WARN_ON_ONCE(!width))
580 cpuid_feature_extract_signed_field_width(features, field, width) :
581 cpuid_feature_extract_unsigned_field_width(features, field, width);
584 static inline int __attribute_const__
585 cpuid_feature_extract_field(u64 features, int field, bool sign)
587 return cpuid_feature_extract_field_width(features, field, 4, sign);
590 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
592 return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign);
595 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
597 return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGEND_SHIFT) == 0x1 ||
598 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT) == 0x1;
601 static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)
603 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL1_SHIFT);
605 return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT;
608 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
610 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL0_SHIFT);
612 return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT;
615 static inline bool id_aa64pfr0_sve(u64 pfr0)
617 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SVE_SHIFT);
622 static inline bool id_aa64pfr1_sme(u64 pfr1)
624 u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_SME_SHIFT);
629 static inline bool id_aa64pfr1_mte(u64 pfr1)
631 u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MTE_SHIFT);
633 return val >= ID_AA64PFR1_EL1_MTE_MTE2;
636 void __init setup_cpu_features(void);
637 void check_local_cpu_capabilities(void);
639 u64 read_sanitised_ftr_reg(u32 id);
640 u64 __read_sysreg_by_encoding(u32 sys_id);
642 static inline bool cpu_supports_mixed_endian_el0(void)
644 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
648 static inline bool supports_csv2p3(int scope)
653 if (scope == SCOPE_LOCAL_CPU)
654 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
656 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
658 csv2_val = cpuid_feature_extract_unsigned_field(pfr0,
659 ID_AA64PFR0_EL1_CSV2_SHIFT);
660 return csv2_val == 3;
663 static inline bool supports_clearbhb(int scope)
667 if (scope == SCOPE_LOCAL_CPU)
668 isar2 = read_sysreg_s(SYS_ID_AA64ISAR2_EL1);
670 isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
672 return cpuid_feature_extract_unsigned_field(isar2,
673 ID_AA64ISAR2_EL1_BC_SHIFT);
676 const struct cpumask *system_32bit_el0_cpumask(void);
677 DECLARE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
679 static inline bool system_supports_32bit_el0(void)
681 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
683 return static_branch_unlikely(&arm64_mismatched_32bit_el0) ||
684 id_aa64pfr0_32bit_el0(pfr0);
687 static inline bool system_supports_4kb_granule(void)
692 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
693 val = cpuid_feature_extract_unsigned_field(mmfr0,
694 ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
696 return (val >= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN) &&
697 (val <= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX);
700 static inline bool system_supports_64kb_granule(void)
705 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
706 val = cpuid_feature_extract_unsigned_field(mmfr0,
707 ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
709 return (val >= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN) &&
710 (val <= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX);
713 static inline bool system_supports_16kb_granule(void)
718 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
719 val = cpuid_feature_extract_unsigned_field(mmfr0,
720 ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
722 return (val >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN) &&
723 (val <= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX);
726 static inline bool system_supports_mixed_endian_el0(void)
728 return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1));
731 static inline bool system_supports_mixed_endian(void)
736 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
737 val = cpuid_feature_extract_unsigned_field(mmfr0,
738 ID_AA64MMFR0_EL1_BIGEND_SHIFT);
743 static __always_inline bool system_supports_fpsimd(void)
745 return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);
748 static inline bool system_uses_hw_pan(void)
750 return IS_ENABLED(CONFIG_ARM64_PAN) &&
751 cpus_have_const_cap(ARM64_HAS_PAN);
754 static inline bool system_uses_ttbr0_pan(void)
756 return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
757 !system_uses_hw_pan();
760 static __always_inline bool system_supports_sve(void)
762 return IS_ENABLED(CONFIG_ARM64_SVE) &&
763 cpus_have_const_cap(ARM64_SVE);
766 static __always_inline bool system_supports_sme(void)
768 return IS_ENABLED(CONFIG_ARM64_SME) &&
769 cpus_have_const_cap(ARM64_SME);
772 static __always_inline bool system_supports_fa64(void)
774 return IS_ENABLED(CONFIG_ARM64_SME) &&
775 cpus_have_const_cap(ARM64_SME_FA64);
778 static __always_inline bool system_supports_tpidr2(void)
780 return system_supports_sme();
783 static __always_inline bool system_supports_cnp(void)
785 return IS_ENABLED(CONFIG_ARM64_CNP) &&
786 cpus_have_const_cap(ARM64_HAS_CNP);
789 static inline bool system_supports_address_auth(void)
791 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) &&
792 cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH);
795 static inline bool system_supports_generic_auth(void)
797 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) &&
798 cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH);
801 static inline bool system_has_full_ptr_auth(void)
803 return system_supports_address_auth() && system_supports_generic_auth();
806 static __always_inline bool system_uses_irq_prio_masking(void)
808 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
809 cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING);
812 static inline bool system_supports_mte(void)
814 return IS_ENABLED(CONFIG_ARM64_MTE) &&
815 cpus_have_const_cap(ARM64_MTE);
818 static inline bool system_has_prio_mask_debugging(void)
820 return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) &&
821 system_uses_irq_prio_masking();
824 static inline bool system_supports_bti(void)
826 return IS_ENABLED(CONFIG_ARM64_BTI) && cpus_have_const_cap(ARM64_BTI);
829 static inline bool system_supports_tlb_range(void)
831 return IS_ENABLED(CONFIG_ARM64_TLB_RANGE) &&
832 cpus_have_const_cap(ARM64_HAS_TLB_RANGE);
835 extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
837 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
840 case ID_AA64MMFR0_EL1_PARANGE_32: return 32;
841 case ID_AA64MMFR0_EL1_PARANGE_36: return 36;
842 case ID_AA64MMFR0_EL1_PARANGE_40: return 40;
843 case ID_AA64MMFR0_EL1_PARANGE_42: return 42;
844 case ID_AA64MMFR0_EL1_PARANGE_44: return 44;
845 case ID_AA64MMFR0_EL1_PARANGE_48: return 48;
846 case ID_AA64MMFR0_EL1_PARANGE_52: return 52;
848 * A future PE could use a value unknown to the kernel.
849 * However, by the "D10.1.4 Principles of the ID scheme
850 * for fields in ID registers", ARM DDI 0487C.a, any new
851 * value is guaranteed to be higher than what we know already.
852 * As a safe limit, we return the limit supported by the kernel.
854 default: return CONFIG_ARM64_PA_BITS;
858 /* Check whether hardware update of the Access flag is supported */
859 static inline bool cpu_has_hw_af(void)
863 if (!IS_ENABLED(CONFIG_ARM64_HW_AFDBM))
866 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
867 return cpuid_feature_extract_unsigned_field(mmfr1,
868 ID_AA64MMFR1_EL1_HAFDBS_SHIFT);
871 static inline bool cpu_has_pan(void)
873 u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
874 return cpuid_feature_extract_unsigned_field(mmfr1,
875 ID_AA64MMFR1_EL1_PAN_SHIFT);
878 #ifdef CONFIG_ARM64_AMU_EXTN
879 /* Check whether the cpu supports the Activity Monitors Unit (AMU) */
880 extern bool cpu_has_amu_feat(int cpu);
882 static inline bool cpu_has_amu_feat(int cpu)
888 /* Get a cpu that supports the Activity Monitors Unit (AMU) */
889 extern int get_cpu_with_amu_feat(void);
891 static inline unsigned int get_vmid_bits(u64 mmfr1)
895 vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1,
896 ID_AA64MMFR1_EL1_VMIDBits_SHIFT);
897 if (vmid_bits == ID_AA64MMFR1_EL1_VMIDBits_16)
901 * Return the default here even if any reserved
902 * value is fetched from the system register.
907 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id);
909 extern struct arm64_ftr_override id_aa64mmfr1_override;
910 extern struct arm64_ftr_override id_aa64pfr0_override;
911 extern struct arm64_ftr_override id_aa64pfr1_override;
912 extern struct arm64_ftr_override id_aa64zfr0_override;
913 extern struct arm64_ftr_override id_aa64smfr0_override;
914 extern struct arm64_ftr_override id_aa64isar1_override;
915 extern struct arm64_ftr_override id_aa64isar2_override;
917 u32 get_kvm_ipa_limit(void);
918 void dump_cpu_features(void);
920 #endif /* __ASSEMBLY__ */