1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 ARM Ltd.
8 #include <asm/cputype.h>
10 #define CTR_L1IP_SHIFT 14
11 #define CTR_L1IP_MASK 3
12 #define CTR_DMINLINE_SHIFT 16
13 #define CTR_IMINLINE_SHIFT 0
14 #define CTR_IMINLINE_MASK 0xf
15 #define CTR_ERG_SHIFT 20
16 #define CTR_CWG_SHIFT 24
17 #define CTR_CWG_MASK 15
18 #define CTR_IDC_SHIFT 28
19 #define CTR_DIC_SHIFT 29
21 #define CTR_CACHE_MINLINE_MASK \
22 (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
24 #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
26 #define ICACHE_POLICY_VPIPT 0
27 #define ICACHE_POLICY_VIPT 2
28 #define ICACHE_POLICY_PIPT 3
30 #define L1_CACHE_SHIFT (6)
31 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
34 #define CLIDR_LOUU_SHIFT 27
35 #define CLIDR_LOC_SHIFT 24
36 #define CLIDR_LOUIS_SHIFT 21
38 #define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
39 #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
40 #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
43 * Memory returned by kmalloc() may be used for DMA, so we must make
44 * sure that all such allocations are cache aligned. Otherwise,
45 * unrelated code may cause parts of the buffer to be read into the
46 * cache before the transfer is done, causing old data to be seen by
49 #define ARCH_DMA_MINALIGN (128)
51 #ifdef CONFIG_KASAN_SW_TAGS
52 #define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
57 #include <linux/bitops.h>
59 #define ICACHEF_ALIASING 0
60 #define ICACHEF_VPIPT 1
61 extern unsigned long __icache_flags;
64 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
65 * permitted in the I-cache.
67 static inline int icache_is_aliasing(void)
69 return test_bit(ICACHEF_ALIASING, &__icache_flags);
72 static __always_inline int icache_is_vpipt(void)
74 return test_bit(ICACHEF_VPIPT, &__icache_flags);
77 static inline u32 cache_type_cwg(void)
79 return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
82 #define __read_mostly __section(".data..read_mostly")
84 static inline int cache_line_size_of_cpu(void)
86 u32 cwg = cache_type_cwg();
88 return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
91 int cache_line_size(void);
94 * Read the effective value of CTR_EL0.
96 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
97 * section D10.2.33 "CTR_EL0, Cache Type Register" :
99 * CTR_EL0.IDC reports the data cache clean requirements for
100 * instruction to data coherence.
102 * 0 - dcache clean to PoU is required unless :
103 * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
104 * 1 - dcache clean to PoU is not required for i-to-d coherence.
106 * This routine provides the CTR_EL0 with the IDC field updated to the
109 static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
111 u32 ctr = read_cpuid_cachetype();
113 if (!(ctr & BIT(CTR_IDC_SHIFT))) {
114 u64 clidr = read_sysreg(clidr_el1);
116 if (CLIDR_LOC(clidr) == 0 ||
117 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
118 ctr |= BIT(CTR_IDC_SHIFT);
124 #endif /* __ASSEMBLY__ */