2 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
4 * Copyright (C) 1996-2000 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #error "Only include this from assembly code"
23 #ifndef __ASM_ASSEMBLER_H
24 #define __ASM_ASSEMBLER_H
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
29 #include <asm/pgtable-hwdef.h>
30 #include <asm/ptrace.h>
31 #include <asm/thread_info.h>
34 * Enable and disable interrupts.
45 * Enable and disable debug exceptions.
55 .macro disable_step_tsk, flgs, tmp
56 tbz \flgs, #TIF_SINGLESTEP, 9990f
60 isb // Synchronise with enable_dbg
64 .macro enable_step_tsk, flgs, tmp
65 tbz \flgs, #TIF_SINGLESTEP, 9990f
74 * Enable both debug exceptions and interrupts. This is likely to be
75 * faster than two daifclr operations, since writes to this register
76 * are self-synchronising.
78 .macro enable_dbg_and_irq
83 * SMP data memory barrier
90 * Emit an entry into the exception table
92 .macro _asm_extable, from, to
93 .pushsection __ex_table, "a"
95 .long (\from - .), (\to - .)
99 #define USER(l, x...) \
101 _asm_extable 9999b, l
106 lr .req x30 // link register
117 * Select code when configured for BE.
119 #ifdef CONFIG_CPU_BIG_ENDIAN
120 #define CPU_BE(code...) code
122 #define CPU_BE(code...)
126 * Select code when configured for LE.
128 #ifdef CONFIG_CPU_BIG_ENDIAN
129 #define CPU_LE(code...)
131 #define CPU_LE(code...) code
135 * Define a macro that constructs a 64-bit value by concatenating two
136 * 32-bit registers. Note that on big endian systems the order of the
137 * registers is swapped.
139 #ifndef CONFIG_CPU_BIG_ENDIAN
140 .macro regs_to_64, rd, lbits, hbits
142 .macro regs_to_64, rd, hbits, lbits
144 orr \rd, \lbits, \hbits, lsl #32
148 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
149 * <symbol> is within the range +/- 4 GB of the PC.
152 * @dst: destination register (64 bit wide)
153 * @sym: name of the symbol
154 * @tmp: optional scratch register to be used if <dst> == sp, which
155 * is not allowed in an adrp instruction
157 .macro adr_l, dst, sym, tmp=
160 add \dst, \dst, :lo12:\sym
163 add \dst, \tmp, :lo12:\sym
168 * @dst: destination register (32 or 64 bit wide)
169 * @sym: name of the symbol
170 * @tmp: optional 64-bit scratch register to be used if <dst> is a
171 * 32-bit wide register, in which case it cannot be used to hold
174 .macro ldr_l, dst, sym, tmp=
177 ldr \dst, [\dst, :lo12:\sym]
180 ldr \dst, [\tmp, :lo12:\sym]
185 * @src: source register (32 or 64 bit wide)
186 * @sym: name of the symbol
187 * @tmp: mandatory 64-bit scratch register to calculate the address
188 * while <src> needs to be preserved.
190 .macro str_l, src, sym, tmp
192 str \src, [\tmp, :lo12:\sym]
196 * @sym: The name of the per-cpu variable
197 * @reg: Result of per_cpu(sym, smp_processor_id())
198 * @tmp: scratch register
200 .macro this_cpu_ptr, sym, reg, tmp
207 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
209 .macro vma_vm_mm, rd, rn
210 ldr \rd, [\rn, #VMA_VM_MM]
214 * mmid - get context id from mm pointer (mm->context.id)
217 ldr \rd, [\rn, #MM_CONTEXT_ID]
221 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
222 * from the CTR register.
224 .macro raw_dcache_line_size, reg, tmp
225 mrs \tmp, ctr_el0 // read CTR
226 ubfm \tmp, \tmp, #16, #19 // cache line size encoding
227 mov \reg, #4 // bytes per word
228 lsl \reg, \reg, \tmp // actual cache line size
232 * dcache_line_size - get the safe D-cache line size across all CPUs
234 .macro dcache_line_size, reg, tmp
235 raw_dcache_line_size \reg, \tmp
239 * raw_icache_line_size - get the minimum I-cache line size on this CPU
240 * from the CTR register.
242 .macro raw_icache_line_size, reg, tmp
243 mrs \tmp, ctr_el0 // read CTR
244 and \tmp, \tmp, #0xf // cache line size encoding
245 mov \reg, #4 // bytes per word
246 lsl \reg, \reg, \tmp // actual cache line size
250 * icache_line_size - get the safe I-cache line size across all CPUs
252 .macro icache_line_size, reg, tmp
253 raw_icache_line_size \reg, \tmp
257 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
259 .macro tcr_set_idmap_t0sz, valreg, tmpreg
260 #ifndef CONFIG_ARM64_VA_BITS_48
261 ldr_l \tmpreg, idmap_t0sz
262 bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
267 * Macro to perform a data cache maintenance for the interval
268 * [kaddr, kaddr + size)
270 * op: operation passed to dc instruction
271 * domain: domain used in dsb instruciton
272 * kaddr: starting virtual address of the region
273 * size: size of the region
274 * Corrupts: kaddr, size, tmp1, tmp2
276 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
277 dcache_line_size \tmp1, \tmp2
278 add \size, \kaddr, \size
280 bic \kaddr, \kaddr, \tmp2
282 .if (\op == cvau || \op == cvac)
283 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
291 add \kaddr, \kaddr, \tmp1
298 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
300 .macro reset_pmuserenr_el0, tmpreg
301 mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
302 sbfx \tmpreg, \tmpreg, #8, #4
303 cmp \tmpreg, #1 // Skip if no PMU present
305 msr pmuserenr_el0, xzr // Disable PMU access from EL0
310 * copy_page - copy src to dest using temp registers t1-t8
312 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
313 9998: ldp \t1, \t2, [\src]
314 ldp \t3, \t4, [\src, #16]
315 ldp \t5, \t6, [\src, #32]
316 ldp \t7, \t8, [\src, #48]
318 stnp \t1, \t2, [\dest]
319 stnp \t3, \t4, [\dest, #16]
320 stnp \t5, \t6, [\dest, #32]
321 stnp \t7, \t8, [\dest, #48]
322 add \dest, \dest, #64
323 tst \src, #(PAGE_SIZE - 1)
328 * Annotate a function as position independent, i.e., safe to be called before
329 * the kernel virtual mapping is activated.
331 #define ENDPIPROC(x) \
333 .type __pi_##x, %function; \
335 .size __pi_##x, . - x; \
339 * Emit a 64-bit absolute little endian symbol reference in a way that
340 * ensures that it will be resolved at build time, even when building a
341 * PIE binary. This requires cooperation from the linker script, which
342 * must emit the lo32/hi32 halves individually.
350 * mov_q - move an immediate constant into a 64-bit register using
351 * between 2 and 4 movz/movk instructions (depending on the
352 * magnitude and sign of the operand)
354 .macro mov_q, reg, val
355 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff)
356 movz \reg, :abs_g1_s:\val
358 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff)
359 movz \reg, :abs_g2_s:\val
361 movz \reg, :abs_g3:\val
362 movk \reg, :abs_g2_nc:\val
364 movk \reg, :abs_g1_nc:\val
366 movk \reg, :abs_g0_nc:\val
369 #endif /* __ASM_ASSEMBLER_H */