1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP ZCU100 revC
5 * (C) Copyright 2016 - 2021, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
8 * Nathalie Chan King Choy
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 #include <dt-bindings/phy/phy.h>
22 model = "ZynqMP ZCU100 RevC";
23 compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>;
48 compatible = "gpio-keys";
52 gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
53 linux,code = <KEY_POWER>;
60 compatible = "gpio-leds";
63 gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
69 gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
70 linux,default-trigger = "phy0tx"; /* WLAN tx */
71 default-state = "off";
76 gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
77 linux,default-trigger = "phy0rx"; /* WLAN rx */
78 default-state = "off";
83 gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
84 linux,default-trigger = "bluetooth-power";
87 vbus-det { /* U5 USB5744 VBUS detection via MIO25 */
89 gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
94 wmmcsdio_fixed: fixedregulator-mmcsdio {
95 compatible = "regulator-fixed";
96 regulator-name = "wmmcsdio_fixed";
97 regulator-min-microvolt = <3300000>;
98 regulator-max-microvolt = <3300000>;
103 sdio_pwrseq: sdio-pwrseq {
104 compatible = "mmc-pwrseq-simple";
105 reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
106 post-power-on-delay-ms = <10>;
110 compatible = "iio-hwmon";
111 io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
114 si5335_0: si5335_0 { /* clk0_usb - u23 */
115 compatible = "fixed-clock";
117 clock-frequency = <26000000>;
120 si5335_1: si5335_1 { /* clk1_dp - u23 */
121 compatible = "fixed-clock";
123 clock-frequency = <27000000>;
133 gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
134 "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
135 "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
136 "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
137 "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
138 "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
139 "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
140 "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
141 "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
142 "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
143 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
144 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
145 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
146 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
147 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
148 "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
150 "", "", "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "", "", "",
152 "", "", "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "", "", "",
157 "", "", "", "", "", "", "", "", "", "",
158 "", "", "", "", "", "", "", "", "", "",
164 pinctrl-names = "default", "gpio";
165 pinctrl-0 = <&pinctrl_i2c1_default>;
166 pinctrl-1 = <&pinctrl_i2c1_gpio>;
167 scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
168 sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
169 clock-frequency = <100000>;
170 i2c-mux@75 { /* u11 */
171 compatible = "nxp,pca9548";
172 #address-cells = <1>;
176 #address-cells = <1>;
182 #address-cells = <1>;
188 #address-cells = <1>;
194 #address-cells = <1>;
200 #address-cells = <1>;
204 pmic: pmic@5e { /* Custom TI PMIC u33 */
205 compatible = "ti,tps65086";
207 interrupt-parent = <&gpio>;
208 interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
214 #address-cells = <1>;
218 u35: ina226@40 { /* u35 */
219 compatible = "ti,ina226";
220 #io-channel-cells = <1>;
222 shunt-resistor = <10000>;
223 /* MIO31 is alert which should be routed to PMUFW */
227 #address-cells = <1>;
235 #address-cells = <1>;
240 * 100kHz - this is default freq for us
248 pinctrl_i2c1_default: i2c1-default {
250 groups = "i2c1_1_grp";
255 groups = "i2c1_1_grp";
257 slew-rate = <SLEW_RATE_SLOW>;
258 power-source = <IO_STANDARD_LVCMOS18>;
262 pinctrl_i2c1_gpio: i2c1-gpio {
264 groups = "gpio0_4_grp", "gpio0_5_grp";
269 groups = "gpio0_4_grp", "gpio0_5_grp";
270 slew-rate = <SLEW_RATE_SLOW>;
271 power-source = <IO_STANDARD_LVCMOS18>;
275 pinctrl_sdhci0_default: sdhci0-default {
277 groups = "sdio0_3_grp";
282 groups = "sdio0_3_grp";
283 slew-rate = <SLEW_RATE_SLOW>;
284 power-source = <IO_STANDARD_LVCMOS18>;
289 groups = "sdio0_cd_0_grp";
290 function = "sdio0_cd";
294 groups = "sdio0_cd_0_grp";
297 slew-rate = <SLEW_RATE_SLOW>;
298 power-source = <IO_STANDARD_LVCMOS18>;
302 pinctrl_sdhci1_default: sdhci1-default {
304 groups = "sdio1_2_grp";
309 groups = "sdio1_2_grp";
310 slew-rate = <SLEW_RATE_SLOW>;
311 power-source = <IO_STANDARD_LVCMOS18>;
316 pinctrl_spi0_default: spi0-default {
318 groups = "spi0_3_grp";
323 groups = "spi0_3_grp";
325 slew-rate = <SLEW_RATE_SLOW>;
326 power-source = <IO_STANDARD_LVCMOS18>;
330 groups = "spi0_ss_9_grp";
331 function = "spi0_ss";
335 groups = "spi0_ss_9_grp";
341 pinctrl_spi1_default: spi1-default {
343 groups = "spi1_0_grp";
348 groups = "spi1_0_grp";
350 slew-rate = <SLEW_RATE_SLOW>;
351 power-source = <IO_STANDARD_LVCMOS18>;
355 groups = "spi1_ss_0_grp";
356 function = "spi1_ss";
360 groups = "spi1_ss_0_grp";
366 pinctrl_uart0_default: uart0-default {
368 groups = "uart0_0_grp";
373 groups = "uart0_0_grp";
374 slew-rate = <SLEW_RATE_SLOW>;
375 power-source = <IO_STANDARD_LVCMOS18>;
389 pinctrl_uart1_default: uart1-default {
391 groups = "uart1_0_grp";
396 groups = "uart1_0_grp";
397 slew-rate = <SLEW_RATE_SLOW>;
398 power-source = <IO_STANDARD_LVCMOS18>;
412 pinctrl_usb0_default: usb0-default {
414 groups = "usb0_0_grp";
419 groups = "usb0_0_grp";
420 slew-rate = <SLEW_RATE_SLOW>;
421 power-source = <IO_STANDARD_LVCMOS18>;
425 pins = "MIO52", "MIO53", "MIO55";
430 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
431 "MIO60", "MIO61", "MIO62", "MIO63";
436 pinctrl_usb1_default: usb1-default {
438 groups = "usb1_0_grp";
443 groups = "usb1_0_grp";
444 slew-rate = <SLEW_RATE_SLOW>;
445 power-source = <IO_STANDARD_LVCMOS18>;
449 pins = "MIO64", "MIO65", "MIO67";
454 pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
455 "MIO72", "MIO73", "MIO74", "MIO75";
464 clocks = <&si5335_0>, <&si5335_1>;
465 clock-names = "ref0", "ref1";
472 /* SD0 only supports 3.3V, no level shifter */
477 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_sdhci0_default>;
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_sdhci1_default>;
491 mmc-pwrseq = <&sdio_pwrseq>;
492 vqmmc-supply = <&wmmcsdio_fixed>;
493 #address-cells = <1>;
496 compatible = "ti,wl1831";
498 interrupt-parent = <&gpio>;
499 interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
503 &spi0 { /* Low Speed connector */
507 pinctrl-names = "default";
508 pinctrl-0 = <&pinctrl_spi0_default>;
511 &spi1 { /* High Speed connector */
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_spi1_default>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&pinctrl_uart0_default>;
524 compatible = "ti,wl1831-st";
525 enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&pinctrl_uart1_default>;
535 /* ULPI SMSC USB3320 */
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_usb0_default>;
540 dr_mode = "peripheral";
541 phy-names = "usb3-phy";
542 phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
543 maximum-speed = "super-speed";
546 /* ULPI SMSC USB3320 */
549 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_usb1_default>;
552 phy-names = "usb3-phy";
553 phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
554 maximum-speed = "super-speed";
567 phy-names = "dp-phy0", "dp-phy1";
568 phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
569 <&psgtr 0 PHY_TYPE_DP 1 1>;