arch/arm64/boot/dts/ti/k3-am62-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM625 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_main {
   9         oc_sram: sram@70000000 {
  10                 compatible = "mmio-sram";
  11                 reg = <0x00 0x70000000 0x00 0x10000>;
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges = <0x0 0x00 0x70000000 0x10000>;
  15         };
  16
  17         gic500: interrupt-controller@1800000 {
  18                 compatible = "arm,gic-v3";
  19                 #address-cells = <2>;
  20                 #size-cells = <2>;
  21                 ranges;
  22                 #interrupt-cells = <3>;
  23                 interrupt-controller;
  24                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  25                       <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
  26                       <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
  27                       <0x01 0x00000000 0x00 0x2000>,    /* GICC */
  28                       <0x01 0x00010000 0x00 0x1000>,    /* GICH */
  29                       <0x01 0x00020000 0x00 0x2000>;    /* GICV */
  30                 /*
  31                  * vcpumntirq:
  32                  * virtual CPU interface maintenance interrupt
  33                  */
  34                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  35
  36                 gic_its: msi-controller@1820000 {
  37                         compatible = "arm,gic-v3-its";
  38                         reg = <0x00 0x01820000 0x00 0x10000>;
  39                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  40                         msi-controller;
  41                         #msi-cells = <1>;
  42                 };
  43         };
  44
  45         main_conf: syscon@100000 {
  46                 compatible = "syscon", "simple-mfd";
  47                 reg = <0x00 0x00100000 0x00 0x20000>;
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 ranges = <0x0 0x00 0x00100000 0x20000>;
  51
  52                 phy_gmii_sel: phy@4044 {
  53                         compatible = "ti,am654-phy-gmii-sel";
  54                         reg = <0x4044 0x8>;
  55                         #phy-cells = <1>;
  56                 };
  57         };
  58
  59         dmss: bus@48000000 {
  60                 compatible = "simple-mfd";
  61                 #address-cells = <2>;
  62                 #size-cells = <2>;
  63                 dma-ranges;
  64                 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
  65
  66                 ti,sci-dev-id = <25>;
  67
  68                 secure_proxy_main: mailbox@4d000000 {
  69                         compatible = "ti,am654-secure-proxy";
  70                         #mbox-cells = <1>;
  71                         reg-names = "target_data", "rt", "scfg";
  72                         reg = <0x00 0x4d000000 0x00 0x80000>,
  73                               <0x00 0x4a600000 0x00 0x80000>,
  74                               <0x00 0x4a400000 0x00 0x80000>;
  75                         interrupt-names = "rx_012";
  76                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  77                 };
  78
  79                 inta_main_dmss: interrupt-controller@48000000 {
  80                         compatible = "ti,sci-inta";
  81                         reg = <0x00 0x48000000 0x00 0x100000>;
  82                         #interrupt-cells = <0>;
  83                         interrupt-controller;
  84                         interrupt-parent = <&gic500>;
  85                         msi-controller;
  86                         ti,sci = <&dmsc>;
  87                         ti,sci-dev-id = <28>;
  88                         ti,interrupt-ranges = <4 68 36>;
  89                         ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
  90                 };
  91
  92                 main_bcdma: dma-controller@485c0100 {
  93                         compatible = "ti,am64-dmss-bcdma";
  94                         reg = <0x00 0x485c0100 0x00 0x100>,
  95                               <0x00 0x4c000000 0x00 0x20000>,
  96                               <0x00 0x4a820000 0x00 0x20000>,
  97                               <0x00 0x4aa40000 0x00 0x20000>,
  98                               <0x00 0x4bc00000 0x00 0x100000>;
  99                         reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
 100                         msi-parent = <&inta_main_dmss>;
 101                         #dma-cells = <3>;
 102
 103                         ti,sci = <&dmsc>;
 104                         ti,sci-dev-id = <26>;
 105                         ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
 106                         ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
 107                         ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
 108                 };
 109
 110                 main_pktdma: dma-controller@485c0000 {
 111                         compatible = "ti,am64-dmss-pktdma";
 112                         reg = <0x00 0x485c0000 0x00 0x100>,
 113                               <0x00 0x4a800000 0x00 0x20000>,
 114                               <0x00 0x4aa00000 0x00 0x40000>,
 115                               <0x00 0x4b800000 0x00 0x400000>;
 116                         reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
 117                         msi-parent = <&inta_main_dmss>;
 118                         #dma-cells = <2>;
 119
 120                         ti,sci = <&dmsc>;
 121                         ti,sci-dev-id = <30>;
 122                         ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
 123                                                 <0x24>, /* CPSW_TX_CHAN */
 124                                                 <0x25>, /* SAUL_TX_0_CHAN */
 125                                                 <0x26>; /* SAUL_TX_1_CHAN */
 126                         ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
 127                                                 <0x11>, /* RING_CPSW_TX_CHAN */
 128                                                 <0x12>, /* RING_SAUL_TX_0_CHAN */
 129                                                 <0x13>; /* RING_SAUL_TX_1_CHAN */
 130                         ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
 131                                                 <0x2b>, /* CPSW_RX_CHAN */
 132                                                 <0x2d>, /* SAUL_RX_0_CHAN */
 133                                                 <0x2f>, /* SAUL_RX_1_CHAN */
 134                                                 <0x31>, /* SAUL_RX_2_CHAN */
 135                                                 <0x33>; /* SAUL_RX_3_CHAN */
 136                         ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
 137                                                 <0x2c>, /* FLOW_CPSW_RX_CHAN */
 138                                                 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
 139                                                 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
 140                 };
 141         };
 142
 143         dmsc: system-controller@44043000 {
 144                 compatible = "ti,k2g-sci";
 145                 ti,host-id = <12>;
 146                 mbox-names = "rx", "tx";
 147                 mboxes = <&secure_proxy_main 12>,
 148                          <&secure_proxy_main 13>;
 149                 reg-names = "debug_messages";
 150                 reg = <0x00 0x44043000 0x00 0xfe0>;
 151
 152                 k3_pds: power-controller {
 153                         compatible = "ti,sci-pm-domain";
 154                         #power-domain-cells = <2>;
 155                 };
 156
 157                 k3_clks: clock-controller {
 158                         compatible = "ti,k2g-sci-clk";
 159                         #clock-cells = <2>;
 160                 };
 161
 162                 k3_reset: reset-controller {
 163                         compatible = "ti,sci-reset";
 164                         #reset-cells = <2>;
 165                 };
 166         };
 167
 168         crypto: crypto@40900000 {
 169                 compatible = "ti,am62-sa3ul";
 170                 reg = <0x00 0x40900000 0x00 0x1200>;
 171                 power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>;
 172                 #address-cells = <2>;
 173                 #size-cells = <2>;
 174                 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
 175
 176                 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>,
 177                        <&main_pktdma 0x7507 0>;
 178                 dma-names = "tx", "rx1", "rx2";
 179         };
 180
 181         main_pmx0: pinctrl@f4000 {
 182                 compatible = "pinctrl-single";
 183                 reg = <0x00 0xf4000 0x00 0x2ac>;
 184                 #pinctrl-cells = <1>;
 185                 pinctrl-single,register-width = <32>;
 186                 pinctrl-single,function-mask = <0xffffffff>;
 187         };
 188
 189         main_uart0: serial@2800000 {
 190                 compatible = "ti,am64-uart", "ti,am654-uart";
 191                 reg = <0x00 0x02800000 0x00 0x100>;
 192                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 193                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 194                 clocks = <&k3_clks 146 0>;
 195                 clock-names = "fclk";
 196         };
 197
 198         main_uart1: serial@2810000 {
 199                 compatible = "ti,am64-uart", "ti,am654-uart";
 200                 reg = <0x00 0x02810000 0x00 0x100>;
 201                 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 202                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 203                 clocks = <&k3_clks 152 0>;
 204                 clock-names = "fclk";
 205         };
 206
 207         main_uart2: serial@2820000 {
 208                 compatible = "ti,am64-uart", "ti,am654-uart";
 209                 reg = <0x00 0x02820000 0x00 0x100>;
 210                 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 211                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
 212                 clocks = <&k3_clks 153 0>;
 213                 clock-names = "fclk";
 214         };
 215
 216         main_uart3: serial@2830000 {
 217                 compatible = "ti,am64-uart", "ti,am654-uart";
 218                 reg = <0x00 0x02830000 0x00 0x100>;
 219                 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
 220                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
 221                 clocks = <&k3_clks 154 0>;
 222                 clock-names = "fclk";
 223         };
 224
 225         main_uart4: serial@2840000 {
 226                 compatible = "ti,am64-uart", "ti,am654-uart";
 227                 reg = <0x00 0x02840000 0x00 0x100>;
 228                 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
 229                 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
 230                 clocks = <&k3_clks 155 0>;
 231                 clock-names = "fclk";
 232         };
 233
 234         main_uart5: serial@2850000 {
 235                 compatible = "ti,am64-uart", "ti,am654-uart";
 236                 reg = <0x00 0x02850000 0x00 0x100>;
 237                 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 238                 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
 239                 clocks = <&k3_clks 156 0>;
 240                 clock-names = "fclk";
 241         };
 242
 243         main_uart6: serial@2860000 {
 244                 compatible = "ti,am64-uart", "ti,am654-uart";
 245                 reg = <0x00 0x02860000 0x00 0x100>;
 246                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 247                 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
 248                 clocks = <&k3_clks 158 0>;
 249                 clock-names = "fclk";
 250         };
 251
 252         main_i2c0: i2c@20000000 {
 253                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 254                 reg = <0x00 0x20000000 0x00 0x100>;
 255                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 256                 #address-cells = <1>;
 257                 #size-cells = <0>;
 258                 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 259                 clocks = <&k3_clks 102 2>;
 260                 clock-names = "fck";
 261         };
 262
 263         main_i2c1: i2c@20010000 {
 264                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 265                 reg = <0x00 0x20010000 0x00 0x100>;
 266                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 267                 #address-cells = <1>;
 268                 #size-cells = <0>;
 269                 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
 270                 clocks = <&k3_clks 103 2>;
 271                 clock-names = "fck";
 272         };
 273
 274         main_i2c2: i2c@20020000 {
 275                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 276                 reg = <0x00 0x20020000 0x00 0x100>;
 277                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 278                 #address-cells = <1>;
 279                 #size-cells = <0>;
 280                 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
 281                 clocks = <&k3_clks 104 2>;
 282                 clock-names = "fck";
 283         };
 284
 285         main_i2c3: i2c@20030000 {
 286                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 287                 reg = <0x00 0x20030000 0x00 0x100>;
 288                 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 289                 #address-cells = <1>;
 290                 #size-cells = <0>;
 291                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 292                 clocks = <&k3_clks 105 2>;
 293                 clock-names = "fck";
 294         };
 295
 296         main_spi0: spi@20100000 {
 297                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 298                 reg = <0x00 0x20100000 0x00 0x400>;
 299                 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 300                 #address-cells = <1>;
 301                 #size-cells = <0>;
 302                 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
 303                 clocks = <&k3_clks 172 0>;
 304         };
 305
 306         main_spi1: spi@20110000 {
 307                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 308                 reg = <0x00 0x20110000 0x00 0x400>;
 309                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 310                 #address-cells = <1>;
 311                 #size-cells = <0>;
 312                 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
 313                 clocks = <&k3_clks 173 0>;
 314         };
 315
 316         main_spi2: spi@20120000 {
 317                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 318                 reg = <0x00 0x20120000 0x00 0x400>;
 319                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322                 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
 323                 clocks = <&k3_clks 174 0>;
 324         };
 325
 326         main_gpio_intr: interrupt-controller@a00000 {
 327                 compatible = "ti,sci-intr";
 328                 reg = <0x00 0x00a00000 0x00 0x800>;
 329                 ti,intr-trigger-type = <1>;
 330                 interrupt-controller;
 331                 interrupt-parent = <&gic500>;
 332                 #interrupt-cells = <1>;
 333                 ti,sci = <&dmsc>;
 334                 ti,sci-dev-id = <3>;
 335                 ti,interrupt-ranges = <0 32 16>;
 336         };
 337
 338         main_gpio0: gpio@600000 {
 339                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 340                 reg = <0x0 0x00600000 0x0 0x100>;
 341                 gpio-controller;
 342                 #gpio-cells = <2>;
 343                 interrupt-parent = <&main_gpio_intr>;
 344                 interrupts = <190>, <191>, <192>,
 345                              <193>, <194>, <195>;
 346                 interrupt-controller;
 347                 #interrupt-cells = <2>;
 348                 ti,ngpio = <87>;
 349                 ti,davinci-gpio-unbanked = <0>;
 350                 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
 351                 clocks = <&k3_clks 77 0>;
 352                 clock-names = "gpio";
 353         };
 354
 355         main_gpio1: gpio@601000 {
 356                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 357                 reg = <0x0 0x00601000 0x0 0x100>;
 358                 gpio-controller;
 359                 #gpio-cells = <2>;
 360                 interrupt-parent = <&main_gpio_intr>;
 361                 interrupts = <180>, <181>, <182>,
 362                              <183>, <184>, <185>;
 363                 interrupt-controller;
 364                 #interrupt-cells = <2>;
 365                 ti,ngpio = <88>;
 366                 ti,davinci-gpio-unbanked = <0>;
 367                 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
 368                 clocks = <&k3_clks 78 0>;
 369                 clock-names = "gpio";
 370         };
 371
 372         sdhci0: mmc@fa10000 {
 373                 compatible = "ti,am62-sdhci";
 374                 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
 375                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 376                 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
 377                 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
 378                 clock-names = "clk_ahb", "clk_xin";
 379                 assigned-clocks = <&k3_clks 57 6>;
 380                 assigned-clock-parents = <&k3_clks 57 8>;
 381                 mmc-ddr-1_8v;
 382                 mmc-hs200-1_8v;
 383                 ti,trm-icp = <0x2>;
 384                 bus-width = <8>;
 385                 ti,clkbuf-sel = <0x7>;
 386                 ti,otap-del-sel-legacy = <0x0>;
 387                 ti,otap-del-sel-mmc-hs = <0x0>;
 388                 ti,otap-del-sel-ddr52 = <0x9>;
 389                 ti,otap-del-sel-hs200 = <0x6>;
 390         };
 391
 392         sdhci1: mmc@fa00000 {
 393                 compatible = "ti,am62-sdhci";
 394                 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
 395                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 396                 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
 397                 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
 398                 clock-names = "clk_ahb", "clk_xin";
 399                 ti,trm-icp = <0x2>;
 400                 ti,otap-del-sel-legacy = <0x0>;
 401                 ti,otap-del-sel-sd-hs = <0x0>;
 402                 ti,otap-del-sel-sdr12 = <0xf>;
 403                 ti,otap-del-sel-sdr25 = <0xf>;
 404                 ti,otap-del-sel-sdr50 = <0xc>;
 405                 ti,otap-del-sel-sdr104 = <0x6>;
 406                 ti,otap-del-sel-ddr50 = <0x9>;
 407                 ti,itap-del-sel-legacy = <0x0>;
 408                 ti,itap-del-sel-sd-hs = <0x0>;
 409                 ti,itap-del-sel-sdr12 = <0x0>;
 410                 ti,itap-del-sel-sdr25 = <0x0>;
 411                 ti,clkbuf-sel = <0x7>;
 412                 bus-width = <4>;
 413         };
 414
 415         sdhci2: mmc@fa20000 {
 416                 compatible = "ti,am62-sdhci";
 417                 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
 418                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 419                 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
 420                 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
 421                 clock-names = "clk_ahb", "clk_xin";
 422                 ti,trm-icp = <0x2>;
 423                 ti,otap-del-sel-legacy = <0x0>;
 424                 ti,otap-del-sel-sd-hs = <0x0>;
 425                 ti,otap-del-sel-sdr12 = <0xf>;
 426                 ti,otap-del-sel-sdr25 = <0xf>;
 427                 ti,otap-del-sel-sdr50 = <0xc>;
 428                 ti,otap-del-sel-sdr104 = <0x6>;
 429                 ti,otap-del-sel-ddr50 = <0x9>;
 430                 ti,itap-del-sel-legacy = <0x0>;
 431                 ti,itap-del-sel-sd-hs = <0x0>;
 432                 ti,itap-del-sel-sdr12 = <0x0>;
 433                 ti,itap-del-sel-sdr25 = <0x0>;
 434                 ti,clkbuf-sel = <0x7>;
 435         };
 436
 437         fss: bus@fc00000 {
 438                 compatible = "simple-bus";
 439                 reg = <0x00 0x0fc00000 0x00 0x70000>;
 440                 #address-cells = <2>;
 441                 #size-cells = <2>;
 442                 ranges;
 443
 444                 ospi0: spi@fc40000 {
 445                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 446                         reg = <0x00 0x0fc40000 0x00 0x100>,
 447                               <0x05 0x00000000 0x01 0x00000000>;
 448                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 449                         cdns,fifo-depth = <256>;
 450                         cdns,fifo-width = <4>;
 451                         cdns,trigger-address = <0x0>;
 452                         clocks = <&k3_clks 75 7>;
 453                         assigned-clocks = <&k3_clks 75 7>;
 454                         assigned-clock-parents = <&k3_clks 75 8>;
 455                         assigned-clock-rates = <166666666>;
 456                         power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459                 };
 460         };
 461
 462         cpsw3g: ethernet@8000000 {
 463                 compatible = "ti,am642-cpsw-nuss";
 464                 #address-cells = <2>;
 465                 #size-cells = <2>;
 466                 reg = <0x00 0x08000000 0x00 0x200000>;
 467                 reg-names = "cpsw_nuss";
 468                 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
 469                 clocks = <&k3_clks 13 0>;
 470                 assigned-clocks = <&k3_clks 13 3>;
 471                 assigned-clock-parents = <&k3_clks 13 11>;
 472                 clock-names = "fck";
 473                 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
 474
 475                 dmas = <&main_pktdma 0xc600 15>,
 476                        <&main_pktdma 0xc601 15>,
 477                        <&main_pktdma 0xc602 15>,
 478                        <&main_pktdma 0xc603 15>,
 479                        <&main_pktdma 0xc604 15>,
 480                        <&main_pktdma 0xc605 15>,
 481                        <&main_pktdma 0xc606 15>,
 482                        <&main_pktdma 0xc607 15>,
 483                        <&main_pktdma 0x4600 15>;
 484                 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
 485                             "tx7", "rx";
 486
 487                 ethernet-ports {
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490
 491                         cpsw_port1: port@1 {
 492                                 reg = <1>;
 493                                 ti,mac-only;
 494                                 label = "port1";
 495                                 phys = <&phy_gmii_sel 1>;
 496                                 mac-address = [00 00 00 00 00 00];
 497                                 ti,syscon-efuse = <&wkup_conf 0x200>;
 498                         };
 499
 500                         cpsw_port2: port@2 {
 501                                 reg = <2>;
 502                                 ti,mac-only;
 503                                 label = "port2";
 504                                 phys = <&phy_gmii_sel 2>;
 505                                 mac-address = [00 00 00 00 00 00];
 506                         };
 507                 };
 508
 509                 cpsw3g_mdio: mdio@f00 {
 510                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 511                         reg = <0x00 0xf00 0x00 0x100>;
 512                         #address-cells = <1>;
 513                         #size-cells = <0>;
 514                         clocks = <&k3_clks 13 0>;
 515                         clock-names = "fck";
 516                         bus_freq = <1000000>;
 517                 };
 518
 519                 cpts@3d000 {
 520                         compatible = "ti,j721e-cpts";
 521                         reg = <0x00 0x3d000 0x00 0x400>;
 522                         clocks = <&k3_clks 13 3>;
 523                         clock-names = "cpts";
 524                         interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 525                         interrupt-names = "cpts";
 526                         ti,cpts-ext-ts-inputs = <4>;
 527                         ti,cpts-periodic-outputs = <2>;
 528                 };
 529         };
 530
 531         hwspinlock: spinlock@2a000000 {
 532                 compatible = "ti,am64-hwspinlock";
 533                 reg = <0x00 0x2a000000 0x00 0x1000>;
 534                 #hwlock-cells = <1>;
 535         };
 536
 537         mailbox0_cluster0: mailbox@29000000 {
 538                 compatible = "ti,am64-mailbox";
 539                 reg = <0x00 0x29000000 0x00 0x200>;
 540                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 541                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 542                 #mbox-cells = <1>;
 543                 ti,mbox-num-users = <4>;
 544                 ti,mbox-num-fifos = <16>;
 545         };
 546
 547         ecap0: pwm@23100000 {
 548                 compatible = "ti,am3352-ecap";
 549                 #pwm-cells = <3>;
 550                 reg = <0x00 0x23100000 0x00 0x100>;
 551                 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
 552                 clocks = <&k3_clks 51 0>;
 553                 clock-names = "fck";
 554         };
 555
 556         ecap1: pwm@23110000 {
 557                 compatible = "ti,am3352-ecap";
 558                 #pwm-cells = <3>;
 559                 reg = <0x00 0x23110000 0x00 0x100>;
 560                 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
 561                 clocks = <&k3_clks 52 0>;
 562                 clock-names = "fck";
 563         };
 564
 565         ecap2: pwm@23120000 {
 566                 compatible = "ti,am3352-ecap";
 567                 #pwm-cells = <3>;
 568                 reg = <0x00 0x23120000 0x00 0x100>;
 569                 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
 570                 clocks = <&k3_clks 53 0>;
 571                 clock-names = "fck";
 572         };
 573
 574         main_mcan0: can@20701000 {
 575                 compatible = "bosch,m_can";
 576                 reg = <0x00 0x20701000 0x00 0x200>,
 577                       <0x00 0x20708000 0x00 0x8000>;
 578                 reg-names = "m_can", "message_ram";
 579                 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
 580                 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
 581                 clock-names = "hclk", "cclk";
 582                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 583                              <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 584                 interrupt-names = "int0", "int1";
 585                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 586         };
 587 };