arch/arm64/boot/dts/sprd_sp9838aea_4core.dts

   1 /*
   2  * SPREADTRUM Ltd.clock-cells
   3 sprd_rotation
   4  *
   5  * SharkLT8 5mod refphone DTS
   6  */
   7
   8 /dts-v1/;
   9
  10 /* memory reserved for SMEM */
  11 /memreserve/ 0x87800000 0x5B0000; /* Offset:120M, Size:5M+256K */
  12
  13 /* memory reserved for WARM modem */
  14 /memreserve/ 0x8DC00000 0xD00000; /* Offset:220M, Size:13M*/
  15
  16 /* memory reserved for LTE modem */
  17 /memreserve/ 0x89600000 0x4600000; /* Offset:150M, Size:70M*/
  18
  19 /* memory reserved for fb */
  20 /memreserve/ 0x9ED74000 0xA8C000; /* 1280*720*4*3, 4K alignment*/
  21
  22 /* memory reserved for ION */
  23 /memreserve/ 0x9F800000 0x800000; /* 1280*720*4*2, 1M alignment*/
  24
  25 /* memory reserved for smp */
  26 /memreserve/ 0x9F700000 0x1000; /* size 4K*/
  27
  28 /include/ "sc2723-regulators.dtsi"
  29 /include/ "sprd-sound.dtsi"
  30 /include/ "sprd-battery.dtsi"
  31 /include/ "scx35lt8-clocks.dtsi"
  32
  33 / {
  34         model = "scx35l64";
  35         compatible = "sprd,SharkLT8";
  36         sprd,sc-id = <8830 1 0x20000>;
  37         interrupt-parent = <&gic>;
  38         #address-cells = <2>;
  39         #size-cells = <2>;
  40
  41         chosen {
  42                 bootargs = "earlyprintk=sprd_uart,0x70100000 loglevel=1 console=ttyS1,115200n8";
  43       };
  44
  45         cpus {
  46                 #address-cells = <2>;
  47                 #size-cells = <0>;
  48
  49                 cpu-map {
  50                         cluster0 {
  51                                 core0 {
  52                                         cpu = <&CPU0>;
  53                                 };
  54                                 core1 {
  55                                         cpu = <&CPU1>;
  56                                 };
  57                                 core2 {
  58                                         cpu = <&CPU2>;
  59                                 };
  60                                 core3 {
  61                                         cpu = <&CPU3>;
  62                                 };
  63                         };
  64
  65                         cluster1 {
  66                                 core0 {
  67                                         cpu = <&CPU4>;
  68                                 };
  69                                 core1 {
  70                                         cpu = <&CPU5>;
  71                                 };
  72                                 core2 {
  73                                         cpu = <&CPU6>;
  74                                 };
  75                                 core3 {
  76                                         cpu = <&CPU7>;
  77                                 };
  78                         };
  79                 };
  80
  81                 CPU0: cpu@530000 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a53","arm,armv8";
  84                         reg = <0x0 0x530000>;
  85                         enable-method = "psci";
  86                         cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>;
  87                         clocks = <&clk_little_mcu>;
  88                         cpu0-supply = <&vddarm>;
  89                         operating-points = <
  90                         /* kHz    uV */
  91                         1000000  900000
  92                         800000   900000
  93                         750000   900000
  94                         600000   900000
  95                         533000   900000
  96                         400000   900000
  97                         200000   900000
  98                         >;
  99                 };
 100
 101                 CPU1: cpu@530001 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53","arm,armv8";
 104                         reg = <0x0 0x530001>;
 105                         enable-method = "psci";
 106                         cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>;
 107                 };
 108
 109                 CPU2: cpu@530002 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53","arm,armv8";
 112                         reg = <0x0 0x530002>;
 113                         enable-method = "psci";
 114                         cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>;
 115                 };
 116
 117                 CPU3: cpu@530003 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a53","arm,armv8";
 120                         reg = <0x0 0x530003>;
 121                         enable-method = "psci";
 122                         cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>;
 123                 };
 124
 125                 CPU4: cpu@530100 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a53","arm,armv8";
 128                         reg = <0x0 0x530100>;
 129                         enable-method = "psci";
 130                         cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>;
 131                         clocks = <&clk_big_mcu>;
 132                         cpu0-supply = <&vddbigarm>;
 133                         operating-points = <
 134                         /* kHz    uV */
 135                         1500000   1050000
 136                         1420000   1050000
 137                         1350000   1050000
 138                         1200000   900000
 139                         1100000   900000
 140                         1000000   900000
 141                         960000    900000
 142                         >;
 143                 };
 144
 145                 CPU5: cpu@530101 {
 146                         device_type = "cpu";
 147                         compatible = "arm,cortex-a53","arm,armv8";
 148                         reg = <0x0 0x530101>;
 149                         enable-method = "psci";
 150                         cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>;
 151                 };
 152
 153                 CPU6: cpu@530102 {
 154                         device_type = "cpu";
 155                         compatible = "arm,cortex-a53","arm,armv8";
 156                         reg = <0x0 0x530102>;
 157                         enable-method = "psci";
 158                         cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>;
 159                 };
 160
 161                 CPU7: cpu@530103 {
 162                         device_type = "cpu";
 163                         compatible = "arm,cortex-a53","arm,armv8";
 164                         reg = <0x0 0x530103>;
 165                         enable-method = "psci";
 166                         cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>;
 167                 };
 168
 169                 idle-states{
 170                         entry-method = "arm,psci";
 171                         LIGHT_SLEEP: light_sleep {
 172                                 compatible = "arm,idle-state";
 173                                 exit-latency-us = <100>;
 174                                 min-residency-us = <500>;
 175                                 entry-method-param = <0x00000001>;
 176                         };
 177                         CORE_PD: core_pd {
 178                                 compatible = "arm,idle-state";
 179                                 exit-latency-us = <1070>;
 180                                 min-residency-us = <5000>;
 181                                 entry-method-param = <0x00010002>;
 182                         };
 183                         CLUSTER_PD: cluster_pd {
 184                                 compatible = "arm,idle-state";
 185                                 exit-latency-us = <2000>;
 186                                 min-residency-us = <8000>;
 187                                 entry-method-param = <0x01010003>;
 188                         };
 189                         TOP_PD: top_pd {
 190                                 compatible = "arm,idle-state";
 191                                 exit-latency-us = <2000>;
 192                                 min-residency-us = <5000>;
 193                                 entry-method-param = <0x01010004>;
 194                         };
 195                         DEEP_SLEEP: deep_sleep {
 196                                 compatible = "arm,idle-state";
 197                                 exit-latency-us = <4100>;
 198                                 min-residency-us = <6500>;
 199                                 entry-method-param = <0x01010005>;
 200                         };
 201                 };
 202         };
 203
 204         memory@80000000 {
 205                 device_type = "memory";
 206                 reg = <0 0x80000000 0 0x40000000>;
 207         };
 208
 209         aliases {
 210                 serial0 = &uart0;
 211                 serial1 = &uart1;
 212                 serial2 = &uart2;
 213                 serial3 = &uart3;
 214                 i2c0 = &i2c0;
 215                 i2c1 = &i2c1;
 216                 i2c2 = &i2c2;
 217                 i2c3 = &i2c3;
 218                 i2c4 = &i2c4;
 219                 spi0 = &spi0;
 220                 spi1 = &spi1;
 221                 spi2 = &spi2;
 222                 lcd0 = &fb0;
 223                 hwspinlock0 = &hwspinlock0;
 224                 hwspinlock1 = &hwspinlock1;
 225         };
 226
 227         pmu {
 228                 compatible = "arm,armv8-pmuv3";
 229                 interrupts = <0 92 4>,
 230                         <0 93 4>,
 231                         <0 94 4>,
 232                         <0 95 4>;
 233         };
 234
 235         psci {
 236                 compatible = "arm,psci";
 237                 method = "smc";
 238                 cpu_on  = <0xc4000003>;
 239                 cpu_off = <0x84000002>;
 240                 cpu_suspend = <0xc4000001>;
 241         };
 242
 243         gic: interrupt-controller@12001000 {
 244                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 245                 #interrupt-cells = <3>;
 246                 #address-cells = <0>;
 247                 interrupt-controller;
 248                 reg = <0 0x12001000 0 0x1000>,
 249                       <0 0x12002000 0 0x1000>;
 250         };
 251
 252         intc:interrupt-controller@71400000 {
 253                 compatible = "sprd,intc";
 254                 #interrupt-cells = <0>;
 255                 interrupt-controller;
 256                 reg =   <0 0x71400000 0 0x1000>,
 257                         <0 0x71500000 0 0x1000>,
 258                         <0 0x71600000 0 0x1000>,
 259                         <0 0x71700000 0 0x1000>,
 260                         <0 0x40200000 0 0x1000>;
 261         };
 262
 263         timer {
 264                 compatible = "arm,armv8-timer";
 265                 interrupts = <1 13 0xff01>,
 266                              <1 14 0xff01>,
 267                              <1 11 0xff01>,
 268                              <1 10 0xff01>;
 269                 clock-frequency = <26000000>;
 270         };
 271
 272         sprd_timer {
 273                 compatible  = "sprd,sharkl64-timer";
 274                 reg =   <0 0x40050000 0 0x20>; /*aon GPTIMER0 */
 275                 interrupts = <0 28 0x0>;
 276                 clock-frequency = <32768>;
 277         };
 278
 279         sprd_ap_system_timer {
 280                 reg =   <0 0x40230000 0 0x20>;
 281                 interrupts = <0 31 0x0>;
 282         };
 283
 284         clock: clockdevice {
 285                 compatible = "sprd,scx35l64-clocks";
 286                 #clock-cells = <1>;
 287         };
 288
 289         d_eic_gpio: gpio@40210000 {
 290                 compatible = "sprd,d-eic-gpio";
 291                 reg = <0 0x40210000 0 0x1000>;
 292                 gpio-controller;
 293                 interrupt-controller;
 294                 #interrupt-cells = <2>;
 295                 #gpio-cells = <2>;
 296                 gpiobase = <288>;
 297                 ngpios = <16>;
 298                 interrupts = <0 37 0x0>;
 299         };
 300
 301         d_gpio_gpio: gpio@40280000 {
 302                 compatible = "sprd,d-gpio-gpio";
 303                 reg = <0 0x40280000 0 0x1000>;
 304                 gpio-controller;
 305                 interrupt-controller;
 306                 #interrupt-cells = <2>;
 307                 #gpio-cells = <2>;
 308                 gpiobase = <0>;
 309                 ngpios = <256>;
 310                 interrupts = <0 35 0x0>;
 311         };
 312
 313         uart0: uart@70000000 {
 314                 compatible = "sprd,serial";
 315                 interrupts = <0 2 0xf04>;
 316                 reg = <0 0x70000000 0 0x1000>;
 317                 clock-names = "clk_uart0";
 318                 clocks = <&clock 60>;
 319                 sprdclk = <48000000>;
 320                 sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 321
 322         };
 323
 324         uart1: uart@70100000 {
 325                 compatible = "sprd,serial";
 326                 interrupts = <0 3 0xf04>;
 327                 reg = <0 0x70100000 0 0x1000>;
 328                 clock-names = "clk_uart1";
 329                 clocks = <&clock 61>;
 330                 sprdclk = <26000000>;
 331                 sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 332
 333         };
 334
 335         uart2: uart@70200000 {
 336                 compatible  = "sprd,serial";
 337                 interrupts = <0 4 0xf04>;
 338                 reg = <0 0x70200000 0 0x1000>;
 339                 clock-names = "clk_uart2";
 340                 clocks = <&clock 62>;
 341                 sprdclk = <26000000>;
 342                 sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 343         };
 344
 345         uart3: uart@70300000 {
 346                 compatible  = "sprd,serial";
 347                 interrupts = <0 5 0xf04>;
 348                 reg = <0 0x70300000 0 0x1000>;
 349                 clock-names = "clk_uart3";
 350                 clocks = <&clock 63>;
 351                 sprdclk = <26000000>;
 352                 sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 353         };
 354
 355         hwspinlock0: hwspinlock0@20c00000{
 356                 compatible  = "sprd,sprd-hwspinlock";
 357                 reg = <0 0x20c00000 0 0x1000>;
 358         };
 359
 360         hwspinlock1: hwspinlock1@40060000{
 361                 compatible  = "sprd,sprd-hwspinlock";
 362                 reg = <0 0x40060000 0 0x1000>;
 363                 status = "ok";
 364         };
 365
 366         watchdog {
 367                 compatible = "sprd,watchdog";
 368                 reg = <0 0X40290000 0 0x1000>;
 369         };
 370
 371         pinctrl {
 372                 compatible = "sprd,pinctrl";
 373                 reg = <0 0x402a0000 0 0x1000>;
 374                 pwr_domain = "vdd28",
 375                         "vdd18",
 376                         "vddsim0",
 377                         "vddsim1",
 378                         "vddsim2",
 379                         "vddsdio",
 380                         "vdd18";
 381                         ctrl_desc = <0x10 0 1
 382                         0x10 1 1
 383                         0x10 2 1
 384                         0x10 3 1
 385                         0x10 4 1
 386                         0x10 5 1
 387                         0x10 6 1>;
 388         };
 389
 390         sdios{
 391                 #address-cells = <2>;
 392                 #size-cells = <2>;
 393                 ranges;
 394                 sdio3: sdio@20600000{
 395                         compatible  = "sprd,sdhost-3.0";
 396                         reg = <0 0x20600000 0 0x1000>;
 397                         interrupts = <0 60 0x0>;
 398                         sprd,name = "sdio_emmc";
 399                         /*detect_gpio = <-1>; */
 400                         SD_Pwr_Name = "vddemmccore";
 401                         _1_8V_signal_Name = "vddgen0";
 402                         signal_default_Voltage = <1800000>;
 403                         ocr_avail = <0x00040000>;
 404                         clocks = <&clk_emmc>, <&clk_192m>;
 405                         base_clk = <192000000>;
 406                         caps = <0xC00F8D47>;
 407                         caps2 = <0x202>;
 408                         pm_caps = <0x4>;
 409                         writeDelay = <0x3E>;
 410                         readPosDelay = <0xA>;
 411                         readNegDelay = <0xA>;
 412                 };
 413
 414                 sdio0: sdio@20300000{
 415                         compatible  = "sprd,sdhost-3.0";
 416                         reg = <0 0x20300000 0 0x1000>;
 417                         interrupts = <0 57 0x0>;
 418                         sprd,name = "sdio_sd";
 419                         detect_gpio = <141>;
 420                         SD_Pwr_Name = "vddsdcore";
 421                         _1_8V_signal_Name = "vddsdio";
 422                         signal_default_Voltage = <3000000>;
 423                         ocr_avail = <0x00040000>;
 424                         clocks = <&clk_sdio0>, <&clk_192m>;
 425                         base_clk = <192000000>;
 426                         caps = <0xC0020407>;
 427                         caps2 = <0x200>;
 428                         pm_caps = <0x4>;
 429                         writeDelay = <0x3>;
 430                         readPosDelay = <0x3>;
 431                         readNegDelay = <0x3>;
 432                 };
 433
 434
 435                 sdio1: sdio@20400000{
 436                         compatible  = "sprd,sdhost-3.0";
 437                         reg = <0 0x20400000 0 0x1000>;
 438                         interrupts = <0 58 0x0>;
 439                         sprd,name = "sdio_wifi";
 440                         /* detect_gpio = <-1>; */
 441                         /* SD_Pwr_Name = "vddsdcore"; */
 442                         /* _1_8V_signal_Name = "vddsdio";*/
 443                         /* signal_default_Voltage = <3000000>; */
 444                         ocr_avail = <0x00360080>;
 445                         clocks = <&clk_sdio1>, <&clk_76m8>;
 446                         base_clk = <76000000>;
 447                         caps = <0xC00FA407>;
 448                         caps2 = <0x0>;
 449                         pm_caps = <0x5>;
 450                         writeDelay = <0x03>;
 451                         readPosDelay = <0x03>;
 452                         readNegDelay = <0x03>;
 453                 };
 454         };
 455
 456         adic:adic {
 457                 compatible = "sprd,adi";
 458                 reg = <0 0x40030000 0 0x10000>;
 459         };
 460
 461         adi: adi_bus {
 462                 compatible = "sprd,adi-bus";
 463                 interrupts = <0 38 0x0>;
 464                 reg = <0 0x40038000 0 0x1000>;
 465                 interrupt-controller;
 466                 sprd,irqnums = <11>;
 467                 #interrupt-cells = <2>;
 468                 #address-cells = <1>;
 469                 #size-cells = <1>;
 470                 ranges = <0x100 0 0x40038100 0x80>,
 471                                  <0x440 0 0x40038440 0x40>,
 472                                  <0x800 0 0x40038800 0xff>;
 473
 474                 keyboard_backlight {
 475                         compatible = "sprd,keyboard-backlight";
 476                 };
 477
 478                 sprd_kpled_2723 {
 479                         compatible = "sprd,sprd-kpled-2723";
 480                         brightness_max = <255>;
 481                         brightness_min = <0>;
 482                         run_mode = <1>;
 483                 };
 484
 485                 leds_sprd_bltc_rgb {
 486                         compatible = "sprd,sprd-leds-bltc-rgb";
 487                                    reg = <0x440 0x40>,
 488                                                  <0x800 0xff>;
 489         };
 490
 491                 a_eic_gpio: gpio@100{
 492                         compatible = "sprd,a-eic-gpio";
 493                         reg = <0x100 0x80>; /* adi reg */
 494                         gpio-controller;
 495                         interrupt-controller;
 496                         #interrupt-cells = <2>;
 497                         #gpio-cells = <2>;
 498                         gpiobase = <304>;
 499                         ngpios = <16>;
 500                         interrupt-parent = <&adi>;
 501                         interrupts = <5 0x0>; /* ext irq 5 */
 502                 };
 503                 sprd_eic_keys {
 504                         compatible = "sprd,sprd-eic-keys";
 505                         input-name = "sprd-eic-keys";
 506                         key_power {
 507                                 label = "Power Key";
 508                                 linux,code = <116>;
 509                                 gpios = <&a_eic_gpio 2 0>;
 510                                 debounce-interval = <2>;
 511                                 gpio-key,wakeup;
 512                         };
 513                         key_volumeup {
 514                                 label = "Volumeup Key";
 515                                 linux,code = <115>;
 516                                 gpios = <&a_eic_gpio 10 0>;
 517                                 debounce-interval = <2>;
 518                                 gpio-key,wakeup;
 519                         };
 520                 };
 521
 522                 headset_sprd_sc2723 {
 523                         compatible = "sprd,headset_sprd_sc2723";
 524                         gpio_switch = <0>;
 525                         gpio_detect = <312>;
 526                         gpio_button = <307>;
 527                         irq_trigger_level_detect = <1>;
 528                         irq_trigger_level_button = <1>;
 529                         adc_threshold_3pole_detect = <300>;
 530                         adc_threshold_4pole_detect = <2651>;
 531                         irq_threshold_buttont = <1>;
 532                         voltage_headmicbias = <3000000>;
 533                         nbuttons = <3>;
 534                         headset_buttons_media {
 535                                 adc_min = <0>;
 536                                 adc_max = <430>;
 537                                 code = <226>;
 538                                 type = <0>;
 539                         };
 540
 541                         headset_buttons_up {
 542                                 adc_min = <431>;
 543                                 adc_max = <860>;
 544                                 code = <115>;
 545                                 type = <0>;
 546                         };
 547                         headset_buttons_down {
 548                                 adc_min = <861>;
 549                                 adc_max =<1900>;
 550                                 code = <114>;
 551                                 type = <0>;
 552                         };
 553                 };
 554
 555                 rtc@80{
 556                         compatible = "sprd,rtc";
 557                         reg = <0X80 0x80>;
 558                         interrupt-parent = <&adi>;
 559                         interrupts = <2 0x0>;
 560                 };
 561         };
 562
 563         sprd_pwm_bl {
 564                 compatible = "sprd,sprd_pwm_bl";
 565                 brightness_max = <255>;
 566                 brightness_min = <0>;
 567                 pwm_index = <2>;
 568                 gpio_ctrl_pin = <0>;
 569                 gpio_active_level = <0>;
 570                 reg =<0 0x40260000 0 0xf>;
 571         };
 572
 573         gpio_keys {
 574                 compatible = "gpio-keys";
 575                 input-name = "sprd-gpio-keys";
 576                 key_volumedown {
 577                         label = "Volumedown Key";
 578                         linux,code = <114>;
 579                         gpios = <&d_gpio_gpio 124 1>;
 580                         debounce-interval = <2>;
 581                         gpio-key,wakeup;
 582                 };
 583 /*
 584                 key_volumeup {
 585                         label = "Volumeup Key";
 586                         linux,code = <115>;
 587                         gpios = <&d_gpio_gpio 125 1>;
 588                         debounce-interval = <2>;
 589                         gpio-key,wakeup;
 590                 };
 591 */
 592                 key_camerafocus {
 593                         label = "Camerafocus Key";
 594                         linux,code = <0x210>;
 595                         gpios = <&d_gpio_gpio 121 0>;
 596                         debounce-interval = <2>;
 597                         gpio-key,wakeup;
 598                 };
 599                 key_camera {
 600                         label = "Camera Key";
 601                         linux,code = <212>;
 602                         gpios = <&d_gpio_gpio 122 0>;
 603                         debounce-interval = <2>;
 604                         gpio-key,wakeup;
 605                 };
 606         };
 607
 608         sprd_backlight {
 609                 compatible = "sprd,sprd_backlight";
 610                 start = <3>;
 611                 end = <3>;
 612                 flags = <0x100>;
 613         };
 614
 615         rfkill {
 616                 compatible = "broadcom,rfkill";
 617                 gpios = <&d_gpio_gpio 131 0  /* power */
 618                         &d_gpio_gpio 122 0>;  /* reset */
 619         };
 620         bluesleep {
 621                 compatible = "broadcom,bluesleep";
 622                 bt-wake-gpio = <&d_gpio_gpio 132 0>;
 623                 host-wake-gpio = <&d_gpio_gpio 133 0>;
 624         };
 625
 626         usb: usb@20200000{
 627                 compatible  = "sprd,usb";
 628                 interrupts = <0 55 0x0>;
 629                 ngpios = <1>;
 630                 gpios = <&a_eic_gpio 0 0>;
 631                 reg = <0 0x20200000 0 0x1000>;
 632                 tune_value = <0x0005af33>;
 633                 usb-supply = <&vddusb>;
 634                 #address-cells = <1>;
 635                 #size-cells = <0>;
 636         };
 637         sprd_thermal: thermal@402F0000{
 638                 compatible = "sprd,sprd-thermal";
 639                 id = <0>;
 640                 interrupts = <0 26 0x0>;
 641                 reg = <0 0x402F0000 0 0x1000>;
 642                 trip_points_active = <65 69 95 110>;
 643                 trip_points_lowoff =  <0 57 60 80>;
 644                 trip_points_critical = <100>;
 645                 trip_num = <5>;
 646                 cool_num = <2>;
 647                 cooling-names = "thermal-cpufreq-0","thermal-cpufreq-1";
 648         };
 649         sprd_thermal1:thermal1@402F0000 {
 650                 compatible = "sprd,sprd-thermal";
 651                 id = <1>;
 652                 interrupts = <0 26 0x0>;
 653                 reg = <0 0x402F0000 0 0x1000>;
 654                 trip_points_active = <100>;
 655                 trip_points_lowoff = <90>;
 656                 trip_points_critical = <100>;
 657                 trip_num = <2>;
 658         };
 659         sprd_thermal2: thermal@40038280{
 660                 compatible = "sprd,sprd-thermal";
 661                 id = <2>;
 662                 interrupt-parent = <&adi>;
 663                 interrupts = <9 0x0>;
 664                 reg = <0 0x40038280 0 0x1000>;
 665                 trip_points_active = <110>;
 666                 trip_points_lowoff = <90>;
 667                 trip_points_critical = <110>;
 668                 trip_num = <2>;
 669         };
 670         sprd_board_thermal: board-thermal{
 671                 compatible = "sprd,board-thermal";
 672                 id = <3>;
 673                 trip_points_active = <100>;
 674                 trip_points_lowoff = <90>;
 675                 trip_points_critical = <100>;
 676                 trip_num = <2>;
 677                 temp_inteval=<2>;
 678                 temp-support = <1>;
 679                 temp-adc-ch = <2>;
 680                 temp-adc-scale = <1>;
 681                 temp-adc-sample-cnt = <15>;
 682                 temp-table-mode = <1>;
 683                 temp-tab-size = <16>;
 684                 temp-tab-val = <1122 1094 1049 983 892 779
 685                                 654 528 413 316 238 178
 686                                 133 100 75 57>;
 687                 temp-tab-temp = <965 975 985 995 1005 1015      /* temperature + 1000,750 = 1000 + (-250)*/
 688                                 1025 1035 1045 1055 1065 1075
 689                                 1085 1095 1105 1115>;
 690
 691         };
 692         adc: adc@40038300{
 693                 compatible  = "sprd,sprd-adc";
 694                 reg = <0x40038300 0x1000>;
 695         };
 696         i2c0: i2c@70500000{
 697                 compatible  = "sprd,i2c";
 698                 interrupts = <0 11 0x0>;
 699                 reg = <0 0x70500000 0 0x1000>;
 700                 clock-names = "clk_i2c0";
 701                 clocks = <&clk_i2c0>;
 702                 #address-cells = <1>;
 703                 #size-cells = <0>;
 704                 sensor_main@0x3c {
 705                         compatible = "sprd,sensor_main";
 706                         reg = <0x3c>;
 707                 };
 708                 sensor_sub@0x21 {
 709                         compatible = "sprd,sensor_sub";
 710                         reg = <0x21>;
 711                 };
 712         };
 713         little_cpu_cooling{
 714                 compatible = "sprd,sprd-cpu-cooling";
 715                 id = <0>;
 716                 cluster = <0>;
 717                 max_freq = <1000000 1000000>;
 718                 max_core = <4 1>;
 719                 state_num = <2>;
 720         };
 721         big_cpu_cooling{
 722                 compatible = "sprd,sprd-cpu-cooling";
 723                 id = <1>;
 724                 cluster = <1>;
 725                 max_freq = <1500000 1200000>;
 726                 max_core = <4 0>;
 727                 state_num = <2>;
 728         };
 729
 730         i2c1: i2c@70600000{
 731                 compatible  = "sprd,i2c";
 732                 interrupts = <0 12 0x0>;
 733                 reg = <0 0x70600000 0 0x1000>;
 734                 clock-names = "clk_i2c1";
 735                 clocks = <&clk_i2c1>;
 736                 #address-cells = <1>;
 737                 #size-cells = <0>;
 738                 fairchild_fan53555@60{
 739                         compatible = "fairchild,fairchild_fan53555";
 740                         reg = <0x60>;
 741                         vddbigarm: vddbigarm {
 742                         regulator-name = "vddbigarm";
 743                         regulator-default-microvolt = <1020000>;/*1050000*/
 744                         regulator-step-microvolt = <10000>;/* 10 * 1000 uV */
 745                         regulator-min-microvolt = <600000>;/* 600 * 1000 uV */
 746                         regulator-max-microvolt = <1230000>;/*(600 + 10 * 0x3F) * 1000 uV*/
 747                         };
 748                 };
 749         };
 750
 751         i2c2: i2c@70700000{
 752                 compatible  = "sprd,i2c";
 753                 interrupts = <0 13 0x0>;
 754                 reg = <0 0x70700000 0 0x1000>;
 755                 clock-names = "clk_i2c2";
 756                 clocks = <&clk_i2c2>;
 757                 #address-cells = <1>;
 758                 #size-cells = <0>;
 759
 760                 lis3dh_acc@18{
 761                         compatible = "ST,lis3dh_acc";
 762                         reg = <0x18>;
 763                         poll_interval = <10>;
 764                         min_interval = <10>;
 765                         g_range = <0>;
 766                         axis_map_x = <1>;
 767                         axis_map_y = <0>;
 768                         axis_map_z = <2>;
 769                         negate_x = <0>;
 770                         negate_y = <1>;
 771                         negate_z = <0>;
 772                 };
 773                 ltr_558als@23{
 774                         compatible = "LITEON,ltr_558als";
 775                         reg = <0x23>;
 776                         gpios = <&d_gpio_gpio 140 0>;
 777                 };
 778                 epl259x_pls@49{
 779                         compatible = "ELAN,epl259x_pls";
 780                         reg = <0x49>;
 781                         gpios = <&d_gpio_gpio 140 0>;
 782                 };
 783
 784         };
 785
 786         i2c3: i2c@70800000{
 787                 compatible  = "sprd,i2c";
 788                 interrupts = <0 14 0x0>;
 789                 reg = <0 0x70800000 0 0x1000>;
 790                 clock-names = "clk_i2c3";
 791                 clocks = <&clk_i2c3>;
 792                 #address-cells = <1>;
 793                 #size-cells = <0>;
 794
 795                 focaltech_ts@38{
 796                         compatible = "focaltech,focaltech_ts";
 797                         reg = <0x38>;
 798                         gpios = <&d_gpio_gpio 145 0
 799                                 &d_gpio_gpio 144 0>;
 800                         vdd_name = "vdd18";
 801                         virtualkeys = <580 1350 60 45
 802                                 360 1350 60 45
 803                                 160 1350 60 45>;
 804                         TP_MAX_X = <720>;
 805                         TP_MAX_Y = <1280>;
 806                 };
 807                 msg2138_ts@26{
 808                         compatible = "Mstar,msg2138_ts";
 809                         reg = <0x26>;
 810                         gpios = <&d_gpio_gpio 145 0
 811                                  &d_gpio_gpio 144 0>;
 812                         vdd_name = "vdd28";
 813                         virtualkeys = <256 1068 64 64
 814                                 128 1068 64 64
 815                                 192 1068 64 64>;
 816                         TP_MAX_X = <480>;
 817                         TP_MAX_Y = <800>;
 818                 };
 819         };
 820
 821         i2c4: i2c@70900000{
 822                 compatible  = "sprd,i2c";
 823                 interrupts = <0 15 0x0>;
 824                 reg = <0 0x70900000 0 0x1000>;
 825                 clock-names = "clk_i2c4";
 826                 clocks = <&clk_i2c4>;
 827                 #address-cells = <1>;
 828                 #size-cells = <0>;
 829         };
 830
 831         spi0: spi0@70a00000{
 832                 compatible  = "sprd,sprd-spi";
 833                 interrupts = <0 7 0x0>;
 834                 reg = <0 0x70a00000 0 0x1000>;
 835                 clock-names = "clk_spi0";
 836         };
 837
 838         spi1: spi1@70b00000{
 839                 compatible  = "sprd,sprd-spi";
 840                 interrupts = <0 8 0x0>;
 841                 reg = <0 0x70b00000 0 0x1000>;
 842                 clock-names = "clk_spi1";
 843         };
 844
 845         spi2: spi2@70c00000{
 846                 compatible  = "sprd,sprd-spi";
 847                 interrupts = <0 9 0x0>;
 848                 reg = <0 0x70c00000 0 0x1000>;
 849                 clock-names = "clk_spi2";
 850         };
 851
 852         dma: dma-controller@20100000 {
 853                 compatible = "sprd,sharkl64-dma";
 854                 #dma-cells = <1>;
 855                 #dma-channels = <64>;
 856                 sprd,aon-offset = <32>;
 857                 reg = <0 0x20100000 0 0x4000>,  /* ap reg */
 858                         <0 0x40100000 0 0x4000>;        /* aon reg */
 859                 interrupts = <0 50 0x0>,                /* ap int */
 860                                         <0 70 0x0>;                     /* aon int */
 861         };
 862
 863         sprd-io-base {
 864                 #address-cells = <2>;
 865                 #size-cells = <2>;
 866                 ranges = <0 0 0 0 1 0>;
 867                 ahb {
 868                         compatible = "sprd,ahb";
 869                         reg = <0 0x20e00000 0 0x40000>;
 870                 };
 871                 apbckg {
 872                         compatible = "sprd,apbckg";
 873                         reg = <0 0x21500000 0 0x1000>;
 874                 };
 875                 hwlock0 {
 876                         compatible = "sprd,hwlock0";
 877                         reg = <0 0x20d00000 0 0x1000>;
 878                 };
 879                 pub_apb {
 880                         compatible = "sprd,pub_apb";
 881                         reg = <0 0x30020000 0 0x10000>;
 882                 };
 883                 aon_apb {
 884                         compatible = "sprd,aon_apb";
 885                         reg = <0 0x402e0000 0 0x40000>;
 886                 };
 887                 pmu_apb {
 888                         compatible = "sprd,pmu_apb";
 889                         reg = <0 0x402b0000 0 0x40000>;
 890                 };
 891                 mm_ahb {
 892                         compatible = "sprd,mm_ahb";
 893                         reg = <0 0x60d00000 0 0x10000>;
 894                 };
 895                 mm_clk {
 896                         compatible = "sprd,mm_clk";
 897                         reg = <0 0x60e00000 0 0x1000>;
 898                 };
 899                 codecahb {
 900                         compatible = "sprd,codecahb";
 901                         reg = <0 0x62000000 0 0x1000>;
 902                 };
 903                 ap_ckg {
 904                         compatible = "sprd,ap_ckg";
 905                         reg = <0 0x71200000 0 0x40000>;
 906                 };
 907                 ap_apb {
 908                         compatible = "sprd,ap_apb";
 909                         reg = <0 0x71300000 0 0x40000>;
 910                 };
 911                 gpu_apb {
 912                         compatible = "sprd,gpu_apb";
 913                         reg = <0 0x60100000 0 0x1000>;
 914                 };
 915                 adi {
 916                         compatible = "sprd,adi";
 917                         reg = <0 0x40030000 0 0x10000>;
 918                 };
 919                 adi_slave {
 920                         compatible = "sprd,adi_slave";
 921                         reg = <0 0x40038000 0 0x1000>;
 922                 };
 923
 924                 mailbox {
 925                         compatible = "sprd,mailbox";
 926                         reg = <0 0x400a0000 0 0x10000>;
 927                 };
 928                 uart0 {
 929                         compatible = "sprd,uart0";
 930                         reg = <0 0x70000000 0 0x1000>;
 931                 };
 932                 uart1 {
 933                         compatible = "sprd,uart1";
 934                         reg = <0 0x70100000 0 0x1000>;
 935                 };
 936                 uart2 {
 937                         compatible = "sprd,uart2";
 938                         reg = <0 0x70200000 0 0x1000>;
 939                 };
 940                 uart3 {
 941                         compatible = "sprd,uart3";
 942                         reg = <0 0x70300000 0 0x1000>;
 943                 };
 944                 uart4 {
 945                         compatible = "sprd,uart4";
 946                         reg = <0 0x70400000 0 0x1000>;
 947                 };
 948                 axibm0 {
 949                         compatible  = "sprd,axibm0";
 950                         reg = <0 0x30040000 0 0x20000>;
 951                         interrupts = <0 86 0x0>;
 952                 };
 953                 d_eic_gpio {
 954                         compatible = "sprd,d-eic-gpio";
 955                         reg = <0 0x40210000 0 0x1000>;
 956                 };
 957                 d_gpio_gpio {
 958                         compatible = "sprd,d-gpio-gpio";
 959                         reg = <0 0x40280000 0 0x1000>;
 960                 };
 961                 aon_dma {
 962                         compatible = "sprd,aon_dma";
 963                         reg = <0 0x40100000 0 0x1000>;
 964                         interrupts = <0 50 0x0>;
 965                 };
 966                 pwm {
 967                         compatible  = "sprd,pwm";
 968                         reg = <0 0x40260000 0 0x1000>;
 969                 };
 970                 core {
 971                         compatible = "sprd,core";
 972                         reg = <0 0x12000000 0 0x10000>;
 973                 };
 974                 int {
 975                         compatible = "sprd,int";
 976                         reg = <0 0x40200000 0 0x1000>;
 977                 };
 978                 intc0 {
 979                         compatible = "sprd,intc0";
 980                         reg = <0 0x71400000 0 0x1000>;
 981                 };
 982                 intc1 {
 983                         compatible = "sprd,intc1";
 984                         reg = <0 0x71500000 0 0x1000>;
 985                 };
 986                 intc2 {
 987                         compatible = "sprd,intc2";
 988                         reg = <0 0x71600000 0 0x1000>;
 989                 };
 990                 intc3 {
 991                         compatible = "sprd,intc3";
 992                         reg = <0 0x71700000 0 0x1000>;
 993                 };
 994                 send_mbox {
 995                         compatible = "sprd,send_mbox";
 996                         reg = <0 0x400a0000 0 0x1000>;
 997                 };
 998                 recv_mbox {
 999                         compatible = "sprd,recv_mbox";
1000                         reg = <0 0x400a8000 0 0x1000>;
1001                 };
1002                 uidefuse {
1003                         compatible = "sprd,uidefuse";
1004                         reg = <0 0x40240000 0 0x1000>;
1005                 };
1006                 isp {
1007                         compatible = "sprd,isp";
1008                         reg = <0 0x60a00000 0 0x8000>;
1009                 };
1010                 csi2 {
1011                         compatible = "sprd,csi2";
1012                         reg = <0 0x60c00000 0 0x1000>;
1013                 };
1014                 ipi {
1015                         compatible = "sprd,ipi";
1016                         reg = <0 0x402c0000 0 0x1000>;
1017                 };
1018                 dcam {
1019                         compatible = "sprd,dcam";
1020                         reg = <0 0x60800000 0 0x10000>;
1021                 };
1022                 syscnt {
1023                         compatible = "sprd,syscnt";
1024                         reg = <0 0x40230000 0 0x1000>;
1025                 };
1026                 dma0 {
1027                         compatible = "sprd,dma0";
1028                         reg = <0 0x20100000 0 0x4000>;
1029                 };
1030                 pub {
1031                         compatible = "sprd,pub";
1032                         reg = <0 0x30020000 0 0x10000>;
1033                 };
1034                 pin {
1035                         compatible = "sprd,pin";
1036                         reg = <0 0x402a0000 0 0x1000>;
1037                 };
1038                 aonckg {
1039                         compatible = "sprd,aonckg";
1040                         reg = <0 0x402d0000 0 0x1000>;
1041                 };
1042                 lpddr2 {
1043                         compatible = "sprd,lpddr2";
1044                         reg = <0 0x30000000 0 0x1000>;
1045                 };
1046         };
1047
1048         sprd_dcam {
1049                 compatible = "sprd,sprd_dcam";
1050                 interrupts = <0 45 0>;
1051                 reg = <0 0x60800000 0 0x100000>;
1052                 clock-names = "clk_mm_i","clk_dcam";
1053                 clocks = <&clk_mm>, <&clk_dcam>;
1054         };
1055
1056         sprd_scale {
1057                 compatible = "sprd,sprd_scale";
1058         };
1059
1060         sprd_rotation {
1061                 compatible = "sprd,sprd_rotation";
1062         };
1063
1064         sprd_sensor {
1065                 compatible  = "sprd,sprd_sensor";
1066                 reg = <0 0x60c00000 0 0x100000>;
1067                 gpios = <&d_gpio_gpio 44 0    /*main reset*/
1068                              &d_gpio_gpio 46 0    /*main powerdown*/
1069                              &d_gpio_gpio 45 0    /*sub reset*/
1070                              &d_gpio_gpio 47 0
1071                              &d_gpio_gpio 0 0     /*main core voltage*/
1072                          &d_gpio_gpio 0 0
1073                          &d_gpio_gpio 0 0
1074                          &d_gpio_gpio 0 0>;   /*sub powerdown*/
1075                 clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi";
1076                 clocks = <&clk_mm>,<&clk_sensor>,<&clk_ccir>,<&clk_dcam>,<&clk_dcam_mipi>;
1077         };
1078
1079         sprd_isp {
1080                 compatible  = "sprd,sprd_isp";
1081                 reg = <0 0x60a00000 0 0x100000>;
1082                 clock-names = "clk_mm_i","clk_isp";
1083                 clocks = <&clk_mm>, <&clk_isp>;
1084         };
1085
1086         sprd_dma_copy {
1087                 compatible  = "sprd,sprd_dma_copy";
1088         };
1089
1090         fb0: fb@20800000 {
1091                 compatible = "sprd,sprdfb";
1092                 reg = <0 0x20800000 0 0x1000>,
1093                       <0 0x21800000 0 0x1000>;
1094                 interrupts = <0 46 0x0>,
1095                              <0 48 0x0>,
1096                              <0 49 0x0>;
1097                 clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent";
1098                 clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>;
1099                 clock-src = <256000000 256000000 384000000>;
1100                 dpi_clk_div = <7>;
1101                 sprd,fb_use_reservemem;
1102                 sprd,fb_mem = <0x9ED74000 0xA8C000>;
1103         };
1104
1105         gsp@20a00000 {
1106                 compatible = "sprd,gsp";
1107                 reg = <0 0x20a00000 0 0x1000>;
1108                 interrupts = <0 51 0x0>;
1109                 clock-names = "clk_gsp0", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb";
1110                 clocks = <&clk_gsp0>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>;
1111                 gsp_mmu_ctrl_base = <0x20b08000>;
1112         };
1113
1114         /*sharLT8 gspn initializer */
1115         gspn:gspn@0x20A00000 {
1116                 compatible = "sprd,gspn";
1117                 reg = <0x71500000 0x1000>, // arm interrupt ctl reg
1118                         <0x20E00000 0x1000>, //gspn module enable ctl reg base
1119                         <0x20E00004 0x1000>, //gspn module reset ctl reg base
1120                         <0x20E0304C 0x1000>, //[0] gsp/gspn select reg base, 0:gsp; 1:gspn
1121                         <0x402e00fc 0x1000>; //[0] ap chip id reg addr
1122                 gspn0:gspn@0x20A00000 {
1123                         core_id = <0>;
1124                         gspn_en_rst_bit = <0x00000008>;//bit3
1125                         mmu_en_rst_bit = <0x00000008>;//bit3
1126                         auto_gate_bit = <0x00000100>;//bit8
1127                         force_gate_bit = <0x00000200>;//bit9
1128                         emc_en_bit = <0x00000008>;//bit3
1129                         reg = <0x20A00000 0x1000>, //gspn module ctl reg
1130                                 <0x20B10000 0x1000>, //iommu ctl reg,64MB,page size 4KB
1131                                 <0x21500028 0x1000>, //gspn clock source select ctl reg base
1132                                 <0x20E00010 0x1000>, //gspn clock auto-gate/force-gate ctl reg base
1133                                 <0x20E00000 0x1000>; //gspn emc clock ctl reg base
1134                         interrupts = <0 51 0x0>;
1135                         clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb";
1136                         //clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>;
1137                 };
1138         };
1139
1140         sprd_fm: sprd_fm@40270000{
1141                 compatible  = "sprd,sprd_fm";
1142                 reg = <0 0x40270000 0 0x1000>;
1143         };
1144
1145         sipc: sipc@0x87800000 {
1146                 compatible = "sprd,sipc";
1147                 reg = <0 0x87800000 0 0x5B0000>; /* <SMEM SIZE>*/
1148                 //#interrupt-cells = <2>;
1149                 #address-cells = <1>;
1150                 #size-cells = <1>;
1151                 ranges =<0x09600000 0 0x89600000 0x4600000>,
1152                                 <0x07800000 0 0x87800000 0x5B0000>,
1153                                 <0x0dbff000 0 0x8dbff000 0x1000>;
1154                 sipc_lte@0x09600000 {
1155                         sprd,name = "sipc-lte";
1156                         sprd,dst = <5>;
1157                         /* it's unnecessary to config IPI info upon mailbox arch */
1158                         mailbox,core = <7>;
1159                         reg = <0x09600000 0x4600000> , /* <CP_start_addr size> */
1160                                 <0x07800000 0x5B0000>, /* <SMEM_phy_addr total_size> */
1161                                 <0x0dbff000 0x1000>; /* smsg ring buffer <base size> */
1162                 };
1163         };
1164
1165     sctrl_pmic{
1166                 compatible = "sprd,sctrl";
1167                 sprd,name = "sctrl_pmic";
1168                 sprd,dst = <6>;
1169                 sprd,channel= <1>;
1170                 sprd,ringnr = <1>;
1171                 /* it's unnecessary to config IPI info upon mailbox arch */
1172                 mailbox,core = <1>;
1173                 sprd,ringbase = <0x5000b000>; /*SMSG ring mem base phy address*/
1174                 sprd,size-rxbuf = <0x0400>; /* 2*1024*/
1175                 sprd,size-txbuf = <0x0400>; /* 2*1024 */
1176         };
1177
1178         saudio_lte{
1179                 compatible = "sprd,saudio";
1180                 sprd,saudio-dst-id = <5>;               /* SIPC_ID_LTE */
1181                 sprd,ctrl_channel = <10>;               /* SMSG_CH_VBC */
1182                 sprd,playback_channel = <11>;   /* SMSG_CH_PLAYBACK */
1183                 sprd,capture_channel = <12>;    /* SMSG_CH_CAPTURE */
1184                 sprd,monitor_channel = <13>;    /*SMSG_CH_MONITOR_AUDIO */
1185                 sprd,saudio-names = "saudiolte";
1186         };
1187
1188         saudio_voip{
1189                 compatible = "sprd,saudio";
1190                 sprd,saudio-dst-id = <5>;               /* SIPC_ID_LTE */
1191                 sprd,ctrl_channel = <14>;               /* SMSG_CH_CTRL_VOIP */
1192                 sprd,playback_channel = <15>;   /* SMSG_CH_PLAYBACK_VOIP */
1193                 sprd,capture_channel = <16>;    /* SMSG_CH_CAPTURE_VOIP */
1194                 sprd,monitor_channel = <17>;    /*SMSG_CH_MONITOR_VOIP */
1195                 sprd,saudio-names = "saudiovoip";
1196         };
1197
1198         /* LTE modem virtual devices */
1199         spipe_lte {
1200                 compatible = "sprd,spipe";
1201                 sprd,name = "spipe_lte";
1202                 sprd,dst = <5>;
1203                 sprd,channel = <4>;
1204                 sprd,ringnr = <9>;
1205                 sprd,size-rxbuf = <0x1000>; /* 4*1024 */
1206                 sprd,size-txbuf = <0x1000>; /* 4*1024 */
1207         };
1208
1209         slog_lte {
1210                 compatible = "sprd,spipe";
1211                 sprd,name = "slog_lte";
1212                 sprd,dst = <5>;
1213                 sprd,channel = <5>;
1214                 sprd,ringnr = <1>;
1215                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
1216                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
1217         };
1218
1219         sdiag_lte {
1220                 compatible = "sprd,spipe";
1221                 sprd,name = "sdiag_lte";
1222                 sprd,dst = <5>;
1223                 sprd,channel = <21>;
1224                 sprd,ringnr = <1>;
1225                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
1226                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
1227         };
1228
1229         stty_lte {
1230                 compatible = "sprd,spipe";
1231                 sprd,name = "stty_lte";
1232                 sprd,dst = <5>;
1233                 sprd,channel = <6>;
1234                 sprd,ringnr = <32>;
1235                 sprd,size-rxbuf = <0x0800>; /* 2*1024*/
1236                 sprd,size-txbuf = <0x0800>; /* 2*1024 */
1237         };
1238
1239         seth0_lte {
1240                 compatible = "sprd,seth";
1241                 sprd,name = "seth_lte0";
1242                 sprd,dst = <5>;
1243                 sprd,channel = <7>;
1244                 sprd,blknum = <256>;
1245         };
1246
1247         seth1_lte {
1248                 compatible = "sprd,seth";
1249                 sprd,name = "seth_lte1";
1250                 sprd,dst = <5>;
1251                 sprd,channel = <8>;
1252                 sprd,blknum = <256>;
1253         };
1254
1255         seth2_lte {
1256                 compatible = "sprd,seth";
1257                 sprd,name = "seth_lte2";
1258                 sprd,dst = <5>;
1259                 sprd,channel = <9>;
1260                 sprd,blknum = <256>;
1261         };
1262
1263         seth3_lte {
1264                 compatible = "sprd,seth";
1265                 sprd,name = "seth_lte3";
1266                 sprd,dst = <5>;
1267                 sprd,channel = <18>;
1268                 sprd,blknum = <256>;
1269         };
1270
1271         seth4_lte {
1272                 compatible = "sprd,seth";
1273                 sprd,name = "seth_lte4";
1274                 sprd,dst = <5>;
1275                 sprd,channel = <19>;
1276                 sprd,blknum = <256>;
1277         };
1278
1279         seth5_lte {
1280                 compatible = "sprd,seth";
1281                 sprd,name = "seth_lte5";
1282                 sprd,dst = <5>;
1283                 sprd,channel = <20>;
1284                 sprd,blknum = <256>;
1285         };
1286         scproc_arm7: scproc@0x50800000 {
1287                 compatible = "sprd,scproc";
1288                 sprd,name = "cppmic";
1289                 sprd,ctrl-reg = <0x114 0xff 0xb0 0xff>; /* <shut_down deep_sleep reset get_status> */
1290                 sprd,ctrl-mask = <0x01 0xfffffffe 0x100 0xf0000>; /* masks <> */
1291                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x0>; /* 3rd param equals modem_addr*/
1292                 reg = <0 0x50800000 0 0x8000>, /* <CP_start_addr total_size> = <+128M 26M> */
1293                         <0 0x50800000 0 0x0>, /* <iram1_base size> */
1294                         <0 0x402e0000 0 0x400>, /* <aon_apb_base size> */
1295             <0 0x402b0000 0 0x100>, /* <pmu_base size> */
1296             <0 0x402b0000 0 0x100>, /* <pmu_base size> */
1297                         <0 0x402b0000 0 0x100>; /* <pmu_base size> */
1298                 #address-cells = <1>;
1299                 #size-cells = <1>;
1300                 /* segnr=1 */
1301                 ranges = <0x0 0 0x50800000 0x8000>;
1302                 modem@0x0 {
1303                         cproc,name = "modem";
1304                         reg = <0x0 0x8000>; /* <modem_addr size> */
1305                 };
1306         };
1307
1308         scproc_cp1: scproc@0x89600000 {
1309                 compatible = "sprd,scproc";
1310                 sprd,name = "cptl";
1311                 sprd,ctrl-reg = <0x0c 0xff 0xb0 0x78>; /* <shut_down deep_sleep reset get_status> */
1312                 sprd,ctrl-mask = <0x00300000 0x10000000 0x02 0x1>; /* masks <> */
1313                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x8ae00000>; /* 3rd param equals modem_addr*/
1314                 reg = <0 0x89600000 0 0x5300000>, /* <CP_start_addr total_size> = <+128M 83M> */
1315                         <0 0x50001000 0 0x0c>, /* <iram1_base size> */
1316                         <0 0x402e0000 0 0x100>, /* <aon_apb_base size> */
1317             <0 0x402b0000 0 0x100>, /* <pmu_base size> */
1318             <0 0x402b0000 0 0x100>, /* <pmu_base size> */
1319                         <0 0x402b0000 0 0x100>; /* <pmu_base size> */
1320                 interrupts = <0 84 0x0>; /* cp1_wdg_int */
1321                 #address-cells = <1>;
1322                 #size-cells = <1>;
1323                 /* segnr=4 */
1324                 ranges = <0x1800000 0 0x8ae00000 0x02E00000>,
1325                         <0x0020000 0 0x89620000 0x002E0000>,
1326                         <0x0300000 0 0x89900000 0x1C0000>,
1327                         <0x4900000 0 0x8df00000 0xA00000>;
1328                 modem@0x1800000 {
1329                         cproc,name = "modem";
1330                         reg = <0x1800000 0x02E00000>; /* <modem_addr size> */
1331                 };
1332                 dsp@0x20000 {
1333                         cproc,name = "tgdsp";
1334                         reg = <0x20000 0x002e0000>; /* <dsp_addr size>*/
1335                 };
1336                 dsp@0x300000 {
1337                         cproc,name = "ldsp";
1338                         reg = <0x300000 0x1c0000>; /* <dsp_addr size>*/
1339                 };
1340                 modem@0x4900000 {
1341                         cproc,name = "warm";
1342                         reg = <0x4900000 0xA00000>; /* <modem_addr size>*/
1343                 };
1344         };
1345
1346         itm_wlan{
1347                 compatible = "sprd,itm_wlan";
1348         };
1349
1350         dmac: dmac@20100000 {
1351                 compatible  = "sprd,sprd-dma";
1352                 interrupts = <0 50 0x0>;
1353                 reg = <0 0x20100000 0 0x4000>;
1354         };
1355
1356         gpu: gpu@60000000 {
1357                 compatible = "sprd,mali-midgard";
1358                 reg = <0 0x60000000 0 0x4000>;
1359                 interrupts = <0 39 0x4>,
1360                              <0 39 0x4>,
1361                              <0 39 0x4>;
1362                 interrupt-names = "JOB",
1363                                   "MMU",
1364                                   "GPU";
1365                 clocks = <&clk_gpu_avs>;
1366                 clock-names = "clk_gpu_avs";
1367         };
1368
1369         ion {
1370                 compatible = "sprd,ion-sprd";
1371                 #address-cells = <1>;
1372                 #size-cells = <0>;
1373
1374                 sprd,ion-heap@1 {
1375                         reg = <1>;                      /* SYSTEM */
1376                         reg-names = "ion_heap_system";
1377                         sprd,ion-heap-type = <0>;       /* SYSTEM */
1378                         sprd,ion-heap-mem = <0x0 0x0>;
1379                 };
1380
1381                 sprd,ion-heap@2 {
1382                         reg = <2>;                      /* MM */
1383                         reg-names = "ion_heap_carveout_mm";
1384                         sprd,ion-heap-type = <0>;       /* carveout mm */
1385                         sprd,ion-heap-mem = <0x9864F000 0x7100000>;
1386                 };
1387
1388                 sprd,ion-heap@3 {
1389                         reg = <3>;                      /* OVERLAY */
1390                         reg-names = "ion_heap_carveout_overlay";
1391                         sprd,ion-heap-type = <2>;       /* CARVEOUT */
1392                         sprd,ion-heap-mem = <0x9F800000 0x800000>;      /* 480*854*4*2, 1M alignment */
1393                 };
1394
1395                 sprd,ion-heap@4 {
1396                         reg = <4>;                      /* FB */
1397                         reg-names = "ion_heap_carveout_fb";
1398                         sprd,ion-heap-type = <2>;       /* CARVEOUT */
1399                         sprd,ion-heap-mem = <0x9ED74000 0xA8C000>;
1400                 };
1401         };
1402
1403         sprd_iommu0: sprd_iommu@20b00000 {
1404                 compatible  = "sprd,sprd_iommu";//gsp
1405                 func-name = "sprd_iommu_gsp";
1406                 reg = <0 0x10000000 0 0x2000000>, //iova
1407                         <0 0x20b00000 0 0x8000>,  //pgt
1408                         <0 0x20b08000 0 0x8000>;  //ctrl_reg
1409                 reg_name = "iova","pgt","ctrl_reg";
1410                  clock-names = "clk_gsp_emc","clk_153m6","clk_gsp0";
1411                  clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp0>;
1412                 status = "ok";
1413         };
1414
1415         sprd_iommu1: sprd_iommu@60f00000 {
1416                 compatible  = "sprd,sprd_iommu";//mm
1417                 func-name = "sprd_iommu_mm";
1418                 reg = <0 0x20000000 0 0x8000000>,   //iova
1419                                 <0 0x60f00000 0 0x20000>,     //pgt
1420                                 <0 0x60f20000 0 0x2000>;      //ctrl_reg
1421                 reg_name = "iova","pgt","ctrl_reg";
1422                 clock-names = "clk_mmu","clk_mm_i";
1423                 clocks = <&clk_mmu>,<&clk_mm>;
1424                 status = "ok";
1425         };
1426
1427     sprd_vsp: sprd_vsp@60900000{
1428                 compatible = "sprd,sprd_vsp";
1429                 reg = <0 0x60900000 0 0xc000>;
1430                 interrupts = <0 43 0x0>;
1431                 clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3";
1432                 clocks = <&clk_mm>, <&clk_vsp>, <&clk_307m2>, <&clk_256m>, <&clk_128m>, <&clk_96m>;
1433                 clock-parent-info = <2 4>;
1434                 version = <7>;
1435         };
1436
1437          sprd_vpp@61000000{
1438                  compatible = "sprd,sprd_vpp";
1439                  reg = <0 0x61000000 0 0x4000>;
1440                  interrupts = <0 43 0x0>;
1441                  clock-names = "clk_mm_i","clk_vpp";
1442                  clocks = <&clk_mm>, <&clk_vpp>;
1443          };
1444
1445          sprd_coda7l@62100000{
1446                  compatible = "sprd,sprd_coda7l";
1447                  reg = <0 0x62100000 0 0x4000>;
1448                  interrupts = <0 43 0x0>;
1449                  clock-names = "clk_mm_i","clk_coda7_axi","clk_coda7_cc","clk_coda7_apb";
1450                  clocks = <&clk_mm>, <&clk_coda7_axi>, <&clk_coda7_cc>, <&clk_coda7_apb>;
1451          };
1452
1453         sprd_jpg {
1454                 compatible = "sprd,sprd_jpg";
1455                 reg = <0 0x60b00000 0 0x8000>;
1456                 interrupts = <0 42 0x0>;
1457                 clock-names = "clk_mm_i","clk_jpg";
1458                 clocks = <&clk_mm>, <&clk_jpg>;
1459         };
1460         sprd_bm {
1461                  compatible = "sprd,sprd_bm";
1462                  reg = <0 0x30040000 0 0xA0000
1463                         0 0x20F00000 0 0x300000>;
1464                  interrupts = <0 86 0x0>;
1465                  sprd,bm_status = <1>;
1466                  sprd,bm_count = <10 11>;
1467                  sprd,cpu_chn = <0 1>;
1468                  sprd,disp_chn = <1 1>;
1469                  sprd,gpu_chn = <2 1>;
1470                  sprd,ap_zip_chn = <3 1>;
1471                  sprd,mm_chn = <4 1>;
1472                  sprd,cp0_arm0_1_chn = <5 1>;
1473                  sprd,cp0_dsp_chn = <6 0>;
1474                  sprd,cp1_lte_chn = <7 1>;
1475                  sprd,cp1_dsp_chn = <8 1>;
1476                  sprd,cp1_arm_chn = <9 1>;
1477                  sprd,ap_dap_chn = <0 0>;
1478                  sprd,ap_cpu_chn = <0 1>;
1479                  sprd,ap_dma_r_chn = <0 2>;
1480                  sprd,ap_dma_w_chn = <0 3>;
1481                  sprd,ap_sdio_0_chn = <1 0>;
1482                  sprd,ap_sdio_1_chn = <1 1>;
1483                  sprd,ap_sdio_2_chn = <1 2>;
1484                  sprd,ap_emmc_chn = <1 3>;
1485                  sprd,ap_nandc_chn = <2 0>;
1486                  sprd,ap_otg_chn = <2 1>;
1487                  sprd,ap_hsic_chn = <2 2>;
1488         };
1489         wdt@40290000 {
1490                 compatible = "sprd,sprd-wdt";
1491                 reg = <0 0x40290000 0 0x1000>,
1492                         <0 0x40310000 0 0x1000>;
1493                 interrupts = <0 124 0x0>;
1494         };
1495        sprd-marlin {
1496                compatible = "sprd,marlin";
1497                gpios = <&d_gpio_gpio 97 0 /*marlin gpio0 */
1498                        &d_gpio_gpio 132 0  /*marlin gpio1 */
1499                        &d_gpio_gpio 133 0  /*marlin gpio2 */
1500                        &d_gpio_gpio 94 0  /*marlin gpio3 */
1501                        &d_gpio_gpio 130 0>;  /*marlin reset*/
1502                cp-rfctl-offset = <0x244>;  /*coex func. marlin gpio3*/
1503                vdd-download = "vddcon"; /*vdd 1.6v*/
1504                vdd-pa = "vddwifipa"; /*vdd 3.3v*/
1505                clk-name = "clk_aux0"; /*clk 32k*/
1506                sdhci-name = "sdio_wifi";
1507        };
1508
1509 };
1510
1511 &vbc_r2p0 {
1512         status = "okay";
1513 };
1514
1515 &sprd_codec {
1516         status = "okay";
1517         sprd,audio_power_ver = <4>;
1518 };
1519
1520 &i2s0 {
1521         sprd,config_type = "pcm";
1522         sprd,slave_timeout = <0xF11>;
1523         sprd,_hw_port = <0>;
1524         sprd,fs = <8000>;
1525         sprd,bus_type = <1>;
1526         sprd,rtx_mode = <3>;
1527         sprd,byte_per_chan = <1>;
1528         sprd,slave_mode = <0>;
1529         sprd,lsb = <0>;
1530         sprd,lrck = <0>;
1531         sprd,low_for_left = <1>;
1532         sprd,clk_inv = <0>;
1533         sprd,pcm_short_frame = <1>;
1534         sprd,pcm_slot = <0x1>;
1535         sprd,pcm_cycle = <1>;
1536         sprd,tx_watermark = <12>;
1537         sprd,rx_watermark = <20>;
1538         status = "okay";
1539 };
1540
1541 &i2s1 {
1542         status = "okay";
1543 };
1544
1545 &i2s2 {
1546         status = "okay";
1547 };
1548
1549 &i2s3 {
1550         status = "okay";
1551 };
1552
1553 &i2s_sound {
1554         sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>;
1555 };
1556
1557 &sprd_battery {
1558         gpios = <&a_eic_gpio 0 0        /* chg int */
1559                 &a_eic_gpio 4 0        /* cv state */
1560                 &a_eic_gpio 6 0         /* chg ovi */
1561                 &a_eic_gpio 9 0>;       /* battery detect */
1562
1563         chg-end-vol-h = <4375>;
1564         chg-end-vol-pure = <4350>;
1565         chg-end-vol-l = <4340>;
1566         chg-bat-safety-vol = <4430>;
1567         rechg-vol = <4260>;
1568
1569         fgu-mode = <0>;
1570         alm-soc = <5>;
1571         alm-vol = <3500>;
1572         soft-vbat-uvlo = <3100>;
1573         rint = <200>;
1574         cnom = <2100>;
1575         rsense-real = <118>;
1576         rsense-spec = <200>;
1577         relax-current = <50>;
1578         fgu-cal-ajust = <0>;
1579         ocv-tab-size = <21>;
1580         ocv-tab-vol = <4318 4254 4198 4145 4094 4052 3987 3955 3902 3865 3838 3817 3800 3785 3769 3752 3733 3706 3691 3588 3400>;
1581         ocv-tab-cap = <100  95   90   85   80   75   70   65   60   55   50   45   40   35   30   25   20   15   10   5    0>;
1582 };