arch/arm64/boot/dts/sprd_sp9836aea_fpga.dts

   1 /*
   2  * SPREADTRUM Ltd.
   3  *
   4  * TSharkL DTS
   5  */
   6
   7 /dts-v1/;
   8
   9 /memreserve/ 0x80000000 0x00010000;
  10 /memreserve/ 0x8a800000 0x600000;
  11
  12 /* memory reserved for ION(carveout mm)*/
  13 /memreserve/ 0x98800000 0x7100000;
  14
  15 /* memory reserved for ION(overlay)*/
  16 /memreserve/ 0x9f900000 0x700000; /* 7MK */
  17
  18 /include/ "sc2723-regulators.dtsi"
  19 /include/ "sprd-battery.dtsi"
  20 /* **** FPGA needn't clk **** *\
  21 include "scx35l64-clocks.dtsi"
  22 \* ************************** */
  23
  24 / {
  25         model = "scx35l64";
  26         compatible = "sprd,TsharkL";
  27         sprd,sc-id = <8830 1 0x20000>;
  28         interrupt-parent = <&gic>;
  29         #address-cells = <2>;
  30         #size-cells = <2>;
  31
  32         chosen {
  33                 bootargs = "earlyprintk=sprd_uart,0x70000000";
  34       };
  35
  36         cpus {
  37                 #address-cells = <2>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,armv8";
  43                         reg = <0x0 0x0>;
  44                         enable-method = "spin-table";
  45                         cpu-release-addr = <0x0 0x8000fff8>;
  46                 };
  47                 cpu@1 {
  48                         device_type = "cpu";
  49                         compatible = "arm,armv8";
  50                         reg = <0x0 0x1>;
  51                         enable-method = "spin-table";
  52                         cpu-release-addr = <0x0 0x8000fff8>;
  53                 };
  54                 cpu@2 {
  55                         device_type = "cpu";
  56                         compatible = "arm,armv8";
  57                         reg = <0x0 0x2>;
  58                         enable-method = "spin-table";
  59                         cpu-release-addr = <0x0 0x8000fff8>;
  60                 };
  61                 cpu@3 {
  62                         device_type = "cpu";
  63                         compatible = "arm,armv8";
  64                         reg = <0x0 0x3>;
  65                         enable-method = "spin-table";
  66                         cpu-release-addr = <0x0 0x8000fff8>;
  67                 };
  68         };
  69
  70         memory@80000000 {
  71                 device_type = "memory";
  72                 reg = <0 0x80000000 0 0x20000000>;
  73         };
  74
  75         aliases {
  76                 serial0 = &uart0;
  77                 serial1 = &uart1;
  78                 i2c0 = &i2c0;
  79                 i2c1 = &i2c1;
  80                 i2c2 = &i2c2;
  81                 i2c3 = &i2c3;
  82                 i2c4 = &i2c4;
  83                 spi0 = &spi0;
  84                 spi1 = &spi1;
  85                 spi2 = &spi2;
  86                 lcd0 = &fb0;
  87                 hwspinlock0 = &hwspinlock0;
  88                 hwspinlock1 = &hwspinlock1;
  89         };
  90
  91         gic: interrupt-controller@12001000 {
  92                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  93                 #interrupt-cells = <3>;
  94                 #address-cells = <0>;
  95                 interrupt-controller;
  96                 reg = <0 0x12001000 0 0x1000>,
  97                       <0 0x12002000 0 0x1000>;
  98         };
  99
 100         intc:interrupt-controller@71400000 {
 101                 compatible = "sprd,intc";
 102                 #interrupt-cells = <0>;
 103                 interrupt-controller;
 104                 reg =   <0 0x71400000 0 0x1000>,
 105                         <0 0x71500000 0 0x1000>,
 106                         <0 0x71600000 0 0x1000>,
 107                         <0 0x71700000 0 0x1000>;
 108         };
 109
 110         timer {
 111                 compatible = "arm,armv8-timer";
 112                 interrupts = <1 13 0xff01>,
 113                              <1 14 0xff01>,
 114                              <1 11 0xff01>,
 115                              <1 10 0xff01>;
 116                 clock-frequency = <26000000>;
 117         };
 118
 119         sprd_timer {
 120                 compatible  = "sprd,sharkl64-timer";
 121                 reg =   <0 0x40050000 0 0x20>; /*aon GPTIMER0 */
 122                 interrupts = <0 28 0x0>;
 123                 clock-frequency = <32768>;
 124         };
 125
 126         sprd_ap_system_timer {
 127                 reg =   <0 0x40230000 0 0x20>;
 128                 interrupts = <0 31 0x0>;
 129         };
 130
 131         uart0: uart@70000000 {
 132                 compatible = "sprd,serial";
 133                 reg = <0 0x70000000 0 0x100>;
 134                 interrupts = <0 2 0xf04>;
 135         };
 136
 137         uart1: uart@70100000 {
 138                 compatible = "sprd,serial";
 139                 reg = <0 0x70100000 0 0x100>;
 140                 interrupts = <0 3 0xf04>;
 141         };
 142         sprd_backlight {
 143                 compatible = "sprd,sprd_backlight";
 144                 start = <3>;
 145                 end = <3>;
 146                 flags = <0x100>;
 147         };
 148         sprd_pwm_bl {
 149                 compatible = "sprd,sprd_pwm_bl";
 150                 reg =<0 0x40260000 0 0xf>;
 151         };
 152         hwspinlock0: hwspinlock0@20c00000{
 153                 compatible  = "sprd,sprd-hwspinlock";
 154                 reg = <0 0x20c00000 0 0x1000>;
 155         };
 156         hwspinlock1: hwspinlock1@40060000{
 157                 compatible  = "sprd,sprd-hwspinlock";
 158                 reg = <0 0x40060000 0 0x1000>;
 159                 status = "ok";
 160         };
 161         watchdog {
 162                 compatible = "sprd,watchdog";
 163                 reg = <0 0X40290000 0 0x1000>;
 164         };
 165
 166         d_eic_gpio: gpio@40210000 {
 167                 compatible = "sprd,d-eic-gpio";
 168                 reg = <0 0x40210000 0 0x1000>;
 169                 gpio-controller;
 170                 interrupt-controller;
 171                 #interrupt-cells = <2>;
 172                 #gpio-cells = <2>;
 173                 gpiobase = <288>;
 174                 ngpios = <16>;
 175                 interrupts = <0 37 0x0>;
 176         };
 177
 178         d_gpio_gpio: gpio@40280000 {
 179                 compatible = "sprd,d-gpio-gpio";
 180                 reg = <0 0x40280000 0 0x1000>;
 181                 gpio-controller;
 182                 interrupt-controller;
 183                 #interrupt-cells = <2>;
 184                 #gpio-cells = <2>;
 185                 gpiobase = <0>;
 186                 ngpios = <256>;
 187                 interrupts = <0 35 0x0>;
 188         };
 189
 190         sdhci3: sdhci@20600000 {
 191                 compatible  = "sprd,sdhci-shark";
 192                 interrupts = <0 60 0x0>;
 193                 reg = <0 0x20600000 0 0x1000>;
 194                 id = <3>;
 195                 bus-width = <8>;
 196                 max-frequency = <384000000>;
 197                 keep-power-in-suspend = <1>;
 198                 non-removable = <1>;
 199                 caps = <0x80000000>;
 200                 caps2 = <0x202>;
 201                 quirks = <0x21009001>;  //SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_CLOCK_BEFORE_RESET
 202                 quirks2 = <0x8>;  //SDHCI_QUIRK2_PRESET_VALUE_BROKEN
 203                 host-caps-mask = <0x03000000>;
 204                // vdd-vmmc = "vddemmccore";
 205                // vdd-vqmmc = "vddemmcio";
 206                 vdd-vmmc = "vddemmccore";
 207                 vdd-vqmmc = "vddgen1";
 208                 clock-names = "clk_emmc";
 209                 clocks = <&clk_emmc>, <&clk_384m>;
 210                 enb-bit = <0x800>;
 211                 rst-bit = <0x4000>;
 212                 write-delay = <0x04>;
 213                 read-pos-delay = <0x04>;
 214                 read-neg-delay = <0x04>;
 215                 keep-power = <0>;
 216                 runtime = <1>;
 217         };
 218
 219         sdhci0: sdhci@20300000 {
 220                 compatible  = "sprd,sdhci-shark";
 221                 interrupts = <0 57 0x0>;
 222                 reg = <0 0x20300000 0 0x1000>;
 223                 id = <0>;
 224                 bus-width = <4>;
 225                 max-frequency = <384000000>;
 226                 keep-power-in-suspend = <1>;
 227                 caps = <0x80000000>;
 228                 caps2 = <0x202>;
 229                 quirks = <0x21009001>; //SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_CLOCK_BEFORE_RESET
 230                 quirks2 = <0x8>; //SDHCI_QUIRK2_PRESET_VALUE_BROKEN
 231                 host-caps-mask = <0x05000000>;
 232                 vdd-vmmc = "vddsdcore";
 233                 vdd-vqmmc = "vddsdio";
 234                 vqmmc-voltage-level = <3000000>;
 235                 cd-gpios = <71>;
 236                 clock-names = "clk_sdio0";
 237                 clocks = <&clk_sdio0>, <&clk_384m>;
 238                 enb-bit = <0x100>;
 239                 rst-bit = <0x800>;
 240                 keep-power = <0>;
 241                 runtime = <1>;
 242         };
 243         sdhci1: sdhci@20400000 {
 244                 compatible  = "sprd,sdhci-shark";
 245                 interrupts = <0 58 0x0>;
 246                 reg = <0 0x20400000 0 0x1000>;
 247                 id = <1>;
 248                 bus-width = <4>;
 249                 max-frequency = <96000000>;
 250                 keep-power-in-suspend = <1>;
 251                 cap-power-off-card = <1>;
 252                 caps = <0x80000000>;
 253                 quirks = <0x21009001>; //SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_CLOCK_BEFORE_RESET
 254                 quirks2 = <0x8>;  //SDHCI_QUIRK2_PRESET_VALUE_BROKEN
 255                 clock-names = "clk_sdio1";
 256                 clocks = <&clk_sdio1>, <&clk_96m>;
 257                 enb-bit = <0x200>;
 258                 rst-bit = <0x1000>;
 259                 keep-power = <0>;
 260                 runtime = <1>;
 261         };
 262
 263
 264         adi: adi_bus {
 265                 compatible = "sprd,adi-bus";
 266                 interrupts = <0 38 0x0>;
 267                 reg = <0 0x40038000 0 0x1000>;
 268                 interrupt-controller;
 269                 sprd,irqnums = <11>;
 270                 #interrupt-cells = <2>;
 271                 #address-cells = <1>;
 272                 #size-cells = <1>;
 273                 ranges = <0x100 0 0x40038100 0x80>;
 274
 275                 keyboard_backlight {
 276                         compatible = "sprd,keyboard-backlight";
 277                 };
 278                 a_eic_gpio: gpio@100{
 279                         compatible = "sprd,a-eic-gpio";
 280                         reg = <0x100 0x80>; /* adi reg */
 281                         gpio-controller;
 282                         interrupt-controller;
 283                         #interrupt-cells = <2>;
 284                         #gpio-cells = <2>;
 285                         gpiobase = <304>;
 286                         ngpios = <16>;
 287                         interrupt-parent = <&adi>;
 288                         interrupts = <5 0x0>; /* ext irq 5 */
 289                 };
 290                 sprd_eic_keys {
 291                         compatible = "sprd,sprd-eic-keys";
 292                         key_power {
 293                                 label = "Power Key";
 294                                 linux,code = <116>;
 295                                 gpios = <&a_eic_gpio 2 0>;
 296                                 debounce-interval = <2>;
 297                                 gpio-key,wakeup;
 298                         };
 299                 };
 300         };
 301         gpio_keys {
 302                 compatible = "gpio-keys";
 303                 input-name = "sprd-gpio-keys";
 304                 key_volumedown {
 305                         label = "Volumedown Key";
 306                         linux,code = <114>;
 307                         gpios = <&d_gpio_gpio 124 1>;
 308                         debounce-interval = <2>;
 309                         gpio-key,wakeup;
 310                 };
 311                 key_volumeup {
 312                         label = "Volumeup Key";
 313                         linux,code = <115>;
 314                         gpios = <&d_gpio_gpio 125 1>;
 315                         debounce-interval = <2>;
 316                         gpio-key,wakeup;
 317                 };
 318         };
 319
 320          usb: usb@20200000{
 321                  compatible  = "sprd,usb";
 322                  interrupts = <0 55 0x0>;
 323                  ngpios = <1>;
 324                  gpios = <&a_eic_gpio 0 0>;
 325                  reg = <0 0x20200000 0 0x1000>;
 326                  tune_value = <0x44073e33>;
 327                  usb-supply = <&vddusb>;
 328                  #address-cells = <1>;
 329                  #size-cells = <0>;
 330          };
 331         sprd_thermal: sprd_thermal@402F0000{
 332                 compatible = "sprd,sprd-thermal";
 333                 id = <0>;
 334                 interrupts = <0 26 0x0>;
 335                 reg = <0 0x402F0000 0 0x1000>;
 336                 trip_points_active = <105>;
 337                 trip_points_critical = <114>;
 338                 trip_num = <5>;
 339         };
 340         i2c0: i2c@70500000{
 341                 compatible  = "sprd,i2c";
 342                 interrupts = <0 11 0x0>;
 343                 reg = <0 0x70500000 0 0x1000>;
 344                 #clock-names = "clk_i2c0";
 345                 #address-cells = <1>;
 346                 #size-cells = <0>;
 347                 sensor_main@0x3c {
 348                         compatible = "sprd,sensor_main";
 349                         reg = <0x3c>;
 350                 };
 351                 sensor_sub@0x21 {
 352                         compatible = "sprd,sensor_sub";
 353                         reg = <0x21>;
 354                 };
 355         };
 356         sprd-io-base {
 357                 #address-cells = <2>;
 358                 #size-cells = <2>;
 359                 ranges = <0 0 0 0 1 0>;
 360                 ahb {
 361                         compatible = "sprd,ahb";
 362                         reg = <0 0x20e00000 0 0x40000>;
 363                 };
 364                 apbckg {
 365                         compatible = "sprd,apbckg";
 366                         reg = <0 0x21500000 0 0x1000>;
 367                 };
 368                 hwlock0 {
 369                         compatible = "sprd,hwlock0";
 370                         reg = <0 0x20d00000 0 0x1000>;
 371                 };
 372                 pub_apb {
 373                         compatible = "sprd,pub_apb";
 374                         reg = <0 0x30020000 0 0x10000>;
 375                 };
 376                 aon_apb {
 377                         compatible = "sprd,aon_apb";
 378                         reg = <0 0x402e0000 0 0x40000>;
 379                 };
 380                 pmu_apb {
 381                         compatible = "sprd,pmu_apb";
 382                         reg = <0 0x402b0000 0 0x40000>;
 383                 };
 384                 mm_ahb {
 385                         compatible = "sprd,mm_ahb";
 386                         reg = <0 0x60d00000 0 0x10000>;
 387                 };
 388                 mm_clk {
 389                         compatible = "sprd,mm_clk";
 390                         reg = <0 0x60e00000 0 0x1000>;
 391                 };
 392                 ap_ckg {
 393                         compatible = "sprd,ap_ckg";
 394                         reg = <0 0x71200000 0 0x40000>;
 395                 };
 396                 ap_apb {
 397                         compatible = "sprd,ap_apb";
 398                         reg = <0 0x71300000 0 0x40000>;
 399                 };
 400                 gpu_apb {
 401                         compatible = "sprd,gpu_apb";
 402                         reg = <0 0x60100000 0 0x1000>;
 403                 };
 404                 adi {
 405                         compatible = "sprd,adi";
 406                         reg = <0 0x40030000 0 0x10000>;
 407                 };
 408                 adi_slave {
 409                         compatible = "sprd,adi_slave";
 410                         reg = <0 0x40038000 0 0x1000>;
 411                 };
 412                 adc {
 413                         compatible = "sprd,adc";
 414                         reg = <0 0x40038300 0 0x1000>;
 415                 };
 416                 dma {
 417                         compatible = "sprd,dma";
 418                         reg = <0 0x20100000 0 0x4000>;
 419                         interrupts = <0 50 0x0>;
 420                 };
 421                 mailbox {
 422                         compatible = "sprd,mailbox";
 423                         reg = <0 0x400a0000 0 0x10000>;
 424                 };
 425                 rtc {
 426                         compatible = "sprd,rtc";
 427                         reg = <0 0x40038080 0 0x80>;
 428                         interrupts = <0 2 0x0>;
 429                 };
 430                 axibm0 {
 431                         compatible  = "sprd,axibm0";
 432                         reg = <0 0x30040000 0 0x20000>;
 433                         interrupts = <0 86 0x0>;
 434                 };
 435          i2c0: i2c@70500000{
 436                  compatible  = "sprd,i2c";
 437                  interrupts = <0 11 0x0>;
 438                  reg = <0 0x70500000 0 0x1000>;
 439          //address-cells = <1>;
 440                  //size-cells = <0>;
 441                  //clock-names = "clk_i2c0";
 442          sensor_main@0x3c {
 443                         compatible = "sprd,sensor_main";
 444                         reg = <0x3c>;
 445                  };
 446                  sensor_sub@0x21 {
 447                         compatible = "sprd,sensor_sub";
 448                         reg = <0x21>;
 449                  };
 450          };
 451          i2c1: i2c@70600000{
 452                  compatible  = "sprd,i2c";
 453                  interrupts = <0 12 0x0>;
 454                  reg = <0 0x70600000 0 0x1000>;
 455                  //clock-names = "clk_i2c1";
 456          };
 457          i2c2: i2c@70700000{
 458                  compatible  = "sprd,i2c";
 459                  interrupts = <0 13 0x0>;
 460                  reg = <0 0x70700000 0 0x1000>;
 461                  //clock-names = "clk_i2c2";
 462          };
 463          i2c3: i2c@70800000{
 464                  compatible  = "sprd,i2c";
 465                  interrupts = <0 14 0x0>;
 466                  reg = <0 0x70800000 0 0x1000>;
 467                  //clock-names = "clk_i2c3";
 468          };
 469          i2c4: i2c@70900000{
 470                  compatible  = "sprd,i2c";
 471                  interrupts = <0 15 0x0>;
 472                  reg = <0 0x70900000 0 0x1000>;
 473                  //clock-names = "clk_i2c4";
 474          };
 475
 476                 spi0: spi0@70a00000{
 477              compatible  = "sprd,sprd-spi";
 478              interrupts = <0 7 0x0>;
 479              reg = <0 0x70a00000 0 0x1000>;
 480              //clock-names = "clk_spi0";
 481         };
 482         spi1: spi1@70b00000{
 483              compatible  = "sprd,sprd-spi";
 484              interrupts = <0 8 0x0>;
 485              reg = <0 0x70b00000 0 0x1000>;
 486              //clock-names = "clk_spi1";
 487         };
 488         spi2: spi2@70c00000{
 489              compatible  = "sprd,sprd-spi";
 490              interrupts = <0 9 0x0>;
 491              reg = <0 0x70c00000 0 0x1000>;
 492              //clock-names = "clk_spi2";
 493         };
 494               d_eic_gpio {
 495                       compatible = "sprd,d-eic-gpio";
 496                       reg = <0 0x40210000 0 0x1000>;
 497               };
 498               d_gpio_gpio {
 499                       compatible = "sprd,d-gpio-gpio";
 500                       reg = <0 0x40280000 0 0x1000>;
 501               };
 502               aon_dma {
 503                       compatible = "sprd,aon_dma";
 504                       reg = <0 0x40100000 0 0x1000>;
 505                       interrupts = <0 50 0x0>;
 506               };
 507               pwm {
 508                       compatible  = "sprd,pwm";
 509                       reg = <0 0x40260000 0 0x1000>;
 510               };
 511         };
 512
 513         sprd_dcam {
 514                 compatible = "sprd,sprd_dcam";
 515                 reg = <0 0x60800000 0 0x100000>;
 516                 interrupts = <0 45 0>;
 517         };
 518         sprd_scale {
 519                 compatible = "sprd,sprd_scale";
 520         };
 521         sprd_rotation {
 522                 compatible = "sprd,sprd_rotation";
 523         };
 524         sprd_sensor {
 525                 compatible  = "sprd,sprd_sensor";
 526                 reg = <0 0x60c00000 0 0x100000>;
 527                 gpios = <&d_gpio_gpio 45 0   /*main reset*/
 528                         &d_gpio_gpio 47 0    /*main powerdown*/
 529                         &d_gpio_gpio 44 0    /*sub reset*/
 530                         &d_gpio_gpio 46 0>;  /*sub powerdown*/
 531         };
 532         sprd_isp {
 533                 compatible  = "sprd,sprd_isp";
 534                 reg = <0 0x60a00000 0 0x100000>;
 535         };
 536         sprd_dma_copy {
 537                 compatible  = "sprd,sprd_dma_copy";
 538         };
 539
 540         fb0: fb@20800000 {
 541                 compatible = "sprd,sprdfb";
 542                 reg = <0 0x20800000 0 0x1000>,
 543                       <0 0x21800000 0 0x1000>;
 544                 interrupts = <0 46 0x0>,
 545                              <0 48 0x0>,
 546                              <0 49 0x0>;
 547 /*
 548                 clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent";
 549                 //clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>;
 550                 clock-src = <256000000 256000000 384000000>;
 551                 dpi_clk_div = <7>;
 552 */
 553                 sprd,fb_use_reservemem;
 554                 sprd,fb_mem = <0x8a800000 0x600000>;
 555
 556         };
 557
 558         gsp@20a00000 {
 559                 compatible = "sprd,gsp";
 560                 reg = <0 0x20a00000 0 0x1000>;
 561                 interrupts = <0 51 0x0>;
 562 /*
 563                 clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb";
 564                 clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>;
 565 */
 566                 gsp_mmu_ctrl_base = <0x20b08000>;
 567         };
 568
 569
 570          gpu {
 571                  compatible  = "sprd,mali-utgard";
 572                  mali_pp_core_number = <4>;
 573                  interrupt-names =     "mali_gp_irq",
 574                                        "mali_gp_mmu_irq",
 575                                        "mali_pp0_irq",
 576                                        "mali_pp0_mmu_irq",
 577                                        "mali_pp1_irq",
 578                                        "mali_pp1_mmu_irq";
 579                  reg-names       =     "mali_l2",
 580                                        "mali_gp",
 581                                        "mali_gp_mmu",
 582                                        "mali_pp0",
 583                                        "mali_pp0_mmu",
 584                                        "mali_pp1",
 585                                        "mali_pp1_mmu",
 586                                        "mali_pmu";
 587                  interrupts =  <0 39 0x0>,  //  MALI_GP_IRQ,
 588                        <0 39 0x0>,  //  MALI_GP_MMU_IRQ,
 589                        <0 39 0x0>,  //  MALI_PP0_IRQ,
 590                        <0 39 0x0>,  //  MALI_PP0_MMU_IRQ,
 591                        <0 39 0x0>,  //  MALI_PP1_IRQ,
 592                        <0 39 0x0>;  //  MALI_PP1_MMU_IRQ,
 593                  reg = <0 0x60001000 0 0x200>,//  MALI_L2,MALI_GPU_RESOURCE_L2(base_addr + 0x1000)
 594                        <0 0x60000000 0 0x100>,//  MALI_GP,
 595                        <0 0x60003000 0 0x100>,//  MALI_GP_MMU,
 596                        <0 0x60008000 0 0x1100>,//  MALI_PP0,
 597                        <0 0x60004000 0 0x100>,//  MALI_PP0_MMU,
 598                        <0 0x6000A000 0 0x1100>,//  MALI_PP1,
 599                        <0 0x60005000 0 0x100>;//  MALI_PP1_MMU,
 600    /*                    <0x60002000 0x100>;  //MALI_PMU,
 601                  clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_208m","clk_256m","clk_312m","clk_384m","clk_460m8";
 602                  clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_208m>,<&clk_256m>,<&clk_312m>,<&clk_384m>,<&clk_460m8>;
 603 */
 604          };
 605
 606          ion {
 607                  compatible = "sprd,ion-sprd";
 608                  #address-cells = <1>;
 609                  #size-cells = <0>;
 610
 611                  sprd,ion-heap@1 {
 612                        reg = <1>;                      /* SYSTEM */
 613                        reg-names = "ion_heap_system";
 614                        sprd,ion-heap-type = <0>;       /* SYSTEM */
 615                        sprd,ion-heap-mem = <0x0 0x0>;
 616                  };
 617
 618                  sprd,ion-heap@2 {
 619                        reg = <2>;                      /* MM */
 620                        reg-names = "ion_heap_carveout_mm";
 621                        sprd,ion-heap-type = <2>;       /* carveout mm */
 622                        sprd,ion-heap-mem = <0x98800000 0x7100000>;
 623                  };
 624
 625                  sprd,ion-heap@3 {
 626                        reg = <3>;                      /* OVERLAY */
 627                        reg-names = "ion_heap_carveout_overlay";
 628                        sprd,ion-heap-type = <2>;       /* CARVEOUT */
 629                        sprd,ion-heap-mem = <0x9f900000 0x700000>;      /* 7M */
 630                  };
 631          };
 632
 633          sprd_iommu0: sprd_iommu@20b00000 {
 634                  compatible  = "sprd,sprd_iommu";//gsp
 635                  func-name = "sprd_iommu_gsp";
 636                  reg = <0 0x10000000 0 0x2000000>, //iova
 637                        <0 0x20b00000 0 0x8000>,  //pgt
 638                        <0 0x20b08000 0 0x8000>;  //ctrl_reg
 639                  reg_name = "iova","pgt","ctrl_reg";
 640                  clock-names = "clk_gsp_emc","clk_153m6","clk_gsp";
 641                  //clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp>;
 642                  status = "ok";
 643          };
 644
 645          sprd_iommu1: sprd_iommu@60f00000 {
 646                  compatible  = "sprd,sprd_iommu";//mm
 647                  func-name = "sprd_iommu_mm";
 648                  reg = <0 0x20000000 0 0x8000000>,   //iova
 649                        <0 0x60f00000 0 0x20000>,     //pgt
 650                        <0 0x60f20000 0 0x2000>;      //ctrl_reg
 651                  reg_name = "iova","pgt","ctrl_reg";
 652                  clock-names = "clk_mmu","clk_mm_i";
 653                  //clocks = <&clk_mmu>,<&clk_mm>;
 654                  status = "ok";
 655
 656          };
 657
 658     sprd_vsp: sprd_vsp@60900000{
 659                  compatible = "sprd,sprd_vsp";
 660                  reg = <0 0x60900000 0 0xc000>;
 661                  interrupts = <0 43 0x0>;
 662                  clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3";
 663                  //clocks = <&clk_mm>, <&clk_vsp>, <&clk_307m2>, <&clk_256m>, <&clk_128m>, <&clk_96m>;
 664                  clock-parent-info = <2 4>;
 665                  version = <6>;
 666         };
 667         sprd_jpg {
 668                  compatible  = "sprd,sprd_jpg";
 669                  reg = <0 0x60B00000 0 0x8000>;
 670                  interrupts = <0 42 0x0>;
 671                  //clock-names = "clk_mm_i","clk_jpg";
 672                  //clocks = <&clk_mm>, <&clk_jpg>;
 673          };
 674
 675 };