arch/arm64/boot/dts/rockchip/rk356x.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
   4  */
   5
   6 #include <dt-bindings/clock/rk3568-cru.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/phy/phy.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3568-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 gpio0 = &gpio0;
  22                 gpio1 = &gpio1;
  23                 gpio2 = &gpio2;
  24                 gpio3 = &gpio3;
  25                 gpio4 = &gpio4;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 i2c4 = &i2c4;
  31                 i2c5 = &i2c5;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37                 serial5 = &uart5;
  38                 serial6 = &uart6;
  39                 serial7 = &uart7;
  40                 serial8 = &uart8;
  41                 serial9 = &uart9;
  42                 spi0 = &spi0;
  43                 spi1 = &spi1;
  44                 spi2 = &spi2;
  45                 spi3 = &spi3;
  46         };
  47
  48         cpus {
  49                 #address-cells = <2>;
  50                 #size-cells = <0>;
  51
  52                 cpu0: cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a55";
  55                         reg = <0x0 0x0>;
  56                         clocks = <&scmi_clk 0>;
  57                         #cooling-cells = <2>;
  58                         enable-method = "psci";
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                 };
  61
  62                 cpu1: cpu@100 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a55";
  65                         reg = <0x0 0x100>;
  66                         #cooling-cells = <2>;
  67                         enable-method = "psci";
  68                         operating-points-v2 = <&cpu0_opp_table>;
  69                 };
  70
  71                 cpu2: cpu@200 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a55";
  74                         reg = <0x0 0x200>;
  75                         #cooling-cells = <2>;
  76                         enable-method = "psci";
  77                         operating-points-v2 = <&cpu0_opp_table>;
  78                 };
  79
  80                 cpu3: cpu@300 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a55";
  83                         reg = <0x0 0x300>;
  84                         #cooling-cells = <2>;
  85                         enable-method = "psci";
  86                         operating-points-v2 = <&cpu0_opp_table>;
  87                 };
  88         };
  89
  90         cpu0_opp_table: opp-table-0 {
  91                 compatible = "operating-points-v2";
  92                 opp-shared;
  93
  94                 opp-408000000 {
  95                         opp-hz = /bits/ 64 <408000000>;
  96                         opp-microvolt = <900000 900000 1150000>;
  97                         clock-latency-ns = <40000>;
  98                 };
  99
 100                 opp-600000000 {
 101                         opp-hz = /bits/ 64 <600000000>;
 102                         opp-microvolt = <900000 900000 1150000>;
 103                 };
 104
 105                 opp-816000000 {
 106                         opp-hz = /bits/ 64 <816000000>;
 107                         opp-microvolt = <900000 900000 1150000>;
 108                         opp-suspend;
 109                 };
 110
 111                 opp-1104000000 {
 112                         opp-hz = /bits/ 64 <1104000000>;
 113                         opp-microvolt = <900000 900000 1150000>;
 114                 };
 115
 116                 opp-1416000000 {
 117                         opp-hz = /bits/ 64 <1416000000>;
 118                         opp-microvolt = <900000 900000 1150000>;
 119                 };
 120
 121                 opp-1608000000 {
 122                         opp-hz = /bits/ 64 <1608000000>;
 123                         opp-microvolt = <975000 975000 1150000>;
 124                 };
 125
 126                 opp-1800000000 {
 127                         opp-hz = /bits/ 64 <1800000000>;
 128                         opp-microvolt = <1050000 1050000 1150000>;
 129                 };
 130         };
 131
 132         display_subsystem: display-subsystem {
 133                 compatible = "rockchip,display-subsystem";
 134                 ports = <&vop_out>;
 135         };
 136
 137         firmware {
 138                 scmi: scmi {
 139                         compatible = "arm,scmi-smc";
 140                         arm,smc-id = <0x82000010>;
 141                         shmem = <&scmi_shmem>;
 142                         #address-cells = <1>;
 143                         #size-cells = <0>;
 144
 145                         scmi_clk: protocol@14 {
 146                                 reg = <0x14>;
 147                                 #clock-cells = <1>;
 148                         };
 149                 };
 150         };
 151
 152         gpu_opp_table: opp-table-1 {
 153                 compatible = "operating-points-v2";
 154
 155                 opp-200000000 {
 156                         opp-hz = /bits/ 64 <200000000>;
 157                         opp-microvolt = <825000>;
 158                 };
 159
 160                 opp-300000000 {
 161                         opp-hz = /bits/ 64 <300000000>;
 162                         opp-microvolt = <825000>;
 163                 };
 164
 165                 opp-400000000 {
 166                         opp-hz = /bits/ 64 <400000000>;
 167                         opp-microvolt = <825000>;
 168                 };
 169
 170                 opp-600000000 {
 171                         opp-hz = /bits/ 64 <600000000>;
 172                         opp-microvolt = <825000>;
 173                 };
 174
 175                 opp-700000000 {
 176                         opp-hz = /bits/ 64 <700000000>;
 177                         opp-microvolt = <900000>;
 178                 };
 179
 180                 opp-800000000 {
 181                         opp-hz = /bits/ 64 <800000000>;
 182                         opp-microvolt = <1000000>;
 183                 };
 184         };
 185
 186         hdmi_sound: hdmi-sound {
 187                 compatible = "simple-audio-card";
 188                 simple-audio-card,name = "HDMI";
 189                 simple-audio-card,format = "i2s";
 190                 simple-audio-card,mclk-fs = <256>;
 191                 status = "disabled";
 192
 193                 simple-audio-card,codec {
 194                         sound-dai = <&hdmi>;
 195                 };
 196
 197                 simple-audio-card,cpu {
 198                         sound-dai = <&i2s0_8ch>;
 199                 };
 200         };
 201
 202         pmu {
 203                 compatible = "arm,cortex-a55-pmu";
 204                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
 208                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 209         };
 210
 211         psci {
 212                 compatible = "arm,psci-1.0";
 213                 method = "smc";
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv8-timer";
 218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 222                 arm,no-tick-in-suspend;
 223         };
 224
 225         xin24m: xin24m {
 226                 compatible = "fixed-clock";
 227                 clock-frequency = <24000000>;
 228                 clock-output-names = "xin24m";
 229                 #clock-cells = <0>;
 230         };
 231
 232         xin32k: xin32k {
 233                 compatible = "fixed-clock";
 234                 clock-frequency = <32768>;
 235                 clock-output-names = "xin32k";
 236                 pinctrl-0 = <&clk32k_out0>;
 237                 pinctrl-names = "default";
 238                 #clock-cells = <0>;
 239         };
 240
 241         sram@10f000 {
 242                 compatible = "mmio-sram";
 243                 reg = <0x0 0x0010f000 0x0 0x100>;
 244                 #address-cells = <1>;
 245                 #size-cells = <1>;
 246                 ranges = <0 0x0 0x0010f000 0x100>;
 247
 248                 scmi_shmem: sram@0 {
 249                         compatible = "arm,scmi-shmem";
 250                         reg = <0x0 0x100>;
 251                 };
 252         };
 253
 254         sata1: sata@fc400000 {
 255                 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
 256                 reg = <0 0xfc400000 0 0x1000>;
 257                 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
 258                          <&cru CLK_SATA1_RXOOB>;
 259                 clock-names = "sata", "pmalive", "rxoob";
 260                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 261                 phys = <&combphy1 PHY_TYPE_SATA>;
 262                 phy-names = "sata-phy";
 263                 ports-implemented = <0x1>;
 264                 power-domains = <&power RK3568_PD_PIPE>;
 265                 status = "disabled";
 266         };
 267
 268         sata2: sata@fc800000 {
 269                 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
 270                 reg = <0 0xfc800000 0 0x1000>;
 271                 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
 272                          <&cru CLK_SATA2_RXOOB>;
 273                 clock-names = "sata", "pmalive", "rxoob";
 274                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 275                 phys = <&combphy2 PHY_TYPE_SATA>;
 276                 phy-names = "sata-phy";
 277                 ports-implemented = <0x1>;
 278                 power-domains = <&power RK3568_PD_PIPE>;
 279                 status = "disabled";
 280         };
 281
 282         usb_host0_xhci: usb@fcc00000 {
 283                 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
 284                 reg = <0x0 0xfcc00000 0x0 0x400000>;
 285                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 286                 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
 287                          <&cru ACLK_USB3OTG0>;
 288                 clock-names = "ref_clk", "suspend_clk",
 289                               "bus_clk";
 290                 dr_mode = "otg";
 291                 phy_type = "utmi_wide";
 292                 power-domains = <&power RK3568_PD_PIPE>;
 293                 resets = <&cru SRST_USB3OTG0>;
 294                 snps,dis_u2_susphy_quirk;
 295                 status = "disabled";
 296         };
 297
 298         usb_host1_xhci: usb@fd000000 {
 299                 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
 300                 reg = <0x0 0xfd000000 0x0 0x400000>;
 301                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 302                 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
 303                          <&cru ACLK_USB3OTG1>;
 304                 clock-names = "ref_clk", "suspend_clk",
 305                               "bus_clk";
 306                 dr_mode = "host";
 307                 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
 308                 phy-names = "usb2-phy", "usb3-phy";
 309                 phy_type = "utmi_wide";
 310                 power-domains = <&power RK3568_PD_PIPE>;
 311                 resets = <&cru SRST_USB3OTG1>;
 312                 snps,dis_u2_susphy_quirk;
 313                 status = "disabled";
 314         };
 315
 316         gic: interrupt-controller@fd400000 {
 317                 compatible = "arm,gic-v3";
 318                 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
 319                       <0x0 0xfd460000 0 0x80000>; /* GICR */
 320                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 321                 interrupt-controller;
 322                 #interrupt-cells = <3>;
 323                 mbi-alias = <0x0 0xfd410000>;
 324                 mbi-ranges = <296 24>;
 325                 msi-controller;
 326         };
 327
 328         usb_host0_ehci: usb@fd800000 {
 329                 compatible = "generic-ehci";
 330                 reg = <0x0 0xfd800000 0x0 0x40000>;
 331                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
 333                          <&cru PCLK_USB>;
 334                 phys = <&usb2phy1_otg>;
 335                 phy-names = "usb";
 336                 status = "disabled";
 337         };
 338
 339         usb_host0_ohci: usb@fd840000 {
 340                 compatible = "generic-ohci";
 341                 reg = <0x0 0xfd840000 0x0 0x40000>;
 342                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
 344                          <&cru PCLK_USB>;
 345                 phys = <&usb2phy1_otg>;
 346                 phy-names = "usb";
 347                 status = "disabled";
 348         };
 349
 350         usb_host1_ehci: usb@fd880000 {
 351                 compatible = "generic-ehci";
 352                 reg = <0x0 0xfd880000 0x0 0x40000>;
 353                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
 355                          <&cru PCLK_USB>;
 356                 phys = <&usb2phy1_host>;
 357                 phy-names = "usb";
 358                 status = "disabled";
 359         };
 360
 361         usb_host1_ohci: usb@fd8c0000 {
 362                 compatible = "generic-ohci";
 363                 reg = <0x0 0xfd8c0000 0x0 0x40000>;
 364                 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 365                 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
 366                          <&cru PCLK_USB>;
 367                 phys = <&usb2phy1_host>;
 368                 phy-names = "usb";
 369                 status = "disabled";
 370         };
 371
 372         pmugrf: syscon@fdc20000 {
 373                 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
 374                 reg = <0x0 0xfdc20000 0x0 0x10000>;
 375
 376                 pmu_io_domains: io-domains {
 377                         compatible = "rockchip,rk3568-pmu-io-voltage-domain";
 378                         status = "disabled";
 379                 };
 380         };
 381
 382         pipegrf: syscon@fdc50000 {
 383                 reg = <0x0 0xfdc50000 0x0 0x1000>;
 384         };
 385
 386         grf: syscon@fdc60000 {
 387                 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
 388                 reg = <0x0 0xfdc60000 0x0 0x10000>;
 389         };
 390
 391         pipe_phy_grf1: syscon@fdc80000 {
 392                 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
 393                 reg = <0x0 0xfdc80000 0x0 0x1000>;
 394         };
 395
 396         pipe_phy_grf2: syscon@fdc90000 {
 397                 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
 398                 reg = <0x0 0xfdc90000 0x0 0x1000>;
 399         };
 400
 401         usb2phy0_grf: syscon@fdca0000 {
 402                 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 403                 reg = <0x0 0xfdca0000 0x0 0x8000>;
 404         };
 405
 406         usb2phy1_grf: syscon@fdca8000 {
 407                 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
 408                 reg = <0x0 0xfdca8000 0x0 0x8000>;
 409         };
 410
 411         pmucru: clock-controller@fdd00000 {
 412                 compatible = "rockchip,rk3568-pmucru";
 413                 reg = <0x0 0xfdd00000 0x0 0x1000>;
 414                 #clock-cells = <1>;
 415                 #reset-cells = <1>;
 416         };
 417
 418         cru: clock-controller@fdd20000 {
 419                 compatible = "rockchip,rk3568-cru";
 420                 reg = <0x0 0xfdd20000 0x0 0x1000>;
 421                 clocks = <&xin24m>;
 422                 clock-names = "xin24m";
 423                 #clock-cells = <1>;
 424                 #reset-cells = <1>;
 425                 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
 426                 assigned-clock-rates = <32768>, <1200000000>, <200000000>;
 427                 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
 428                 rockchip,grf = <&grf>;
 429         };
 430
 431         i2c0: i2c@fdd40000 {
 432                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 433                 reg = <0x0 0xfdd40000 0x0 0x1000>;
 434                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
 436                 clock-names = "i2c", "pclk";
 437                 pinctrl-0 = <&i2c0_xfer>;
 438                 pinctrl-names = "default";
 439                 #address-cells = <1>;
 440                 #size-cells = <0>;
 441                 status = "disabled";
 442         };
 443
 444         uart0: serial@fdd50000 {
 445                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 446                 reg = <0x0 0xfdd50000 0x0 0x100>;
 447                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 448                 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
 449                 clock-names = "baudclk", "apb_pclk";
 450                 dmas = <&dmac0 0>, <&dmac0 1>;
 451                 pinctrl-0 = <&uart0_xfer>;
 452                 pinctrl-names = "default";
 453                 reg-io-width = <4>;
 454                 reg-shift = <2>;
 455                 status = "disabled";
 456         };
 457
 458         pwm0: pwm@fdd70000 {
 459                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 460                 reg = <0x0 0xfdd70000 0x0 0x10>;
 461                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 462                 clock-names = "pwm", "pclk";
 463                 pinctrl-0 = <&pwm0m0_pins>;
 464                 pinctrl-names = "default";
 465                 #pwm-cells = <3>;
 466                 status = "disabled";
 467         };
 468
 469         pwm1: pwm@fdd70010 {
 470                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 471                 reg = <0x0 0xfdd70010 0x0 0x10>;
 472                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 473                 clock-names = "pwm", "pclk";
 474                 pinctrl-0 = <&pwm1m0_pins>;
 475                 pinctrl-names = "default";
 476                 #pwm-cells = <3>;
 477                 status = "disabled";
 478         };
 479
 480         pwm2: pwm@fdd70020 {
 481                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 482                 reg = <0x0 0xfdd70020 0x0 0x10>;
 483                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 484                 clock-names = "pwm", "pclk";
 485                 pinctrl-0 = <&pwm2m0_pins>;
 486                 pinctrl-names = "default";
 487                 #pwm-cells = <3>;
 488                 status = "disabled";
 489         };
 490
 491         pwm3: pwm@fdd70030 {
 492                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 493                 reg = <0x0 0xfdd70030 0x0 0x10>;
 494                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
 495                 clock-names = "pwm", "pclk";
 496                 pinctrl-0 = <&pwm3_pins>;
 497                 pinctrl-names = "default";
 498                 #pwm-cells = <3>;
 499                 status = "disabled";
 500         };
 501
 502         pmu: power-management@fdd90000 {
 503                 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
 504                 reg = <0x0 0xfdd90000 0x0 0x1000>;
 505
 506                 power: power-controller {
 507                         compatible = "rockchip,rk3568-power-controller";
 508                         #power-domain-cells = <1>;
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511
 512                         /* These power domains are grouped by VD_GPU */
 513                         power-domain@RK3568_PD_GPU {
 514                                 reg = <RK3568_PD_GPU>;
 515                                 clocks = <&cru ACLK_GPU_PRE>,
 516                                          <&cru PCLK_GPU_PRE>;
 517                                 pm_qos = <&qos_gpu>;
 518                                 #power-domain-cells = <0>;
 519                         };
 520
 521                         /* These power domains are grouped by VD_LOGIC */
 522                         power-domain@RK3568_PD_VI {
 523                                 reg = <RK3568_PD_VI>;
 524                                 clocks = <&cru HCLK_VI>,
 525                                          <&cru PCLK_VI>;
 526                                 pm_qos = <&qos_isp>,
 527                                          <&qos_vicap0>,
 528                                          <&qos_vicap1>;
 529                                 #power-domain-cells = <0>;
 530                         };
 531
 532                         power-domain@RK3568_PD_VO {
 533                                 reg = <RK3568_PD_VO>;
 534                                 clocks = <&cru HCLK_VO>,
 535                                          <&cru PCLK_VO>,
 536                                          <&cru ACLK_VOP_PRE>;
 537                                 pm_qos = <&qos_hdcp>,
 538                                          <&qos_vop_m0>,
 539                                          <&qos_vop_m1>;
 540                                 #power-domain-cells = <0>;
 541                         };
 542
 543                         power-domain@RK3568_PD_RGA {
 544                                 reg = <RK3568_PD_RGA>;
 545                                 clocks = <&cru HCLK_RGA_PRE>,
 546                                          <&cru PCLK_RGA_PRE>;
 547                                 pm_qos = <&qos_ebc>,
 548                                          <&qos_iep>,
 549                                          <&qos_jpeg_dec>,
 550                                          <&qos_jpeg_enc>,
 551                                          <&qos_rga_rd>,
 552                                          <&qos_rga_wr>;
 553                                 #power-domain-cells = <0>;
 554                         };
 555
 556                         power-domain@RK3568_PD_VPU {
 557                                 reg = <RK3568_PD_VPU>;
 558                                 clocks = <&cru HCLK_VPU_PRE>;
 559                                 pm_qos = <&qos_vpu>;
 560                                 #power-domain-cells = <0>;
 561                         };
 562
 563                         power-domain@RK3568_PD_RKVDEC {
 564                                 clocks = <&cru HCLK_RKVDEC_PRE>;
 565                                 reg = <RK3568_PD_RKVDEC>;
 566                                 pm_qos = <&qos_rkvdec>;
 567                                 #power-domain-cells = <0>;
 568                         };
 569
 570                         power-domain@RK3568_PD_RKVENC {
 571                                 reg = <RK3568_PD_RKVENC>;
 572                                 clocks = <&cru HCLK_RKVENC_PRE>;
 573                                 pm_qos = <&qos_rkvenc_rd_m0>,
 574                                          <&qos_rkvenc_rd_m1>,
 575                                          <&qos_rkvenc_wr_m0>;
 576                                 #power-domain-cells = <0>;
 577                         };
 578                 };
 579         };
 580
 581         gpu: gpu@fde60000 {
 582                 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
 583                 reg = <0x0 0xfde60000 0x0 0x4000>;
 584                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 585                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 586                              <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 587                 interrupt-names = "job", "mmu", "gpu";
 588                 clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
 589                 clock-names = "gpu", "bus";
 590                 #cooling-cells = <2>;
 591                 operating-points-v2 = <&gpu_opp_table>;
 592                 power-domains = <&power RK3568_PD_GPU>;
 593                 status = "disabled";
 594         };
 595
 596         vpu: video-codec@fdea0400 {
 597                 compatible = "rockchip,rk3568-vpu";
 598                 reg = <0x0 0xfdea0000 0x0 0x800>;
 599                 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 600                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 601                 clock-names = "aclk", "hclk";
 602                 iommus = <&vdpu_mmu>;
 603                 power-domains = <&power RK3568_PD_VPU>;
 604         };
 605
 606         vdpu_mmu: iommu@fdea0800 {
 607                 compatible = "rockchip,rk3568-iommu";
 608                 reg = <0x0 0xfdea0800 0x0 0x40>;
 609                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 610                 clock-names = "aclk", "iface";
 611                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 612                 power-domains = <&power RK3568_PD_VPU>;
 613                 #iommu-cells = <0>;
 614         };
 615
 616         rga: rga@fdeb0000 {
 617                 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
 618                 reg = <0x0 0xfdeb0000 0x0 0x180>;
 619                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 620                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
 621                 clock-names = "aclk", "hclk", "sclk";
 622                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
 623                 reset-names = "core", "axi", "ahb";
 624                 power-domains = <&power RK3568_PD_RGA>;
 625         };
 626
 627         vepu: video-codec@fdee0000 {
 628                 compatible = "rockchip,rk3568-vepu";
 629                 reg = <0x0 0xfdee0000 0x0 0x800>;
 630                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 631                 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
 632                 clock-names = "aclk", "hclk";
 633                 iommus = <&vepu_mmu>;
 634                 power-domains = <&power RK3568_PD_RGA>;
 635         };
 636
 637         vepu_mmu: iommu@fdee0800 {
 638                 compatible = "rockchip,rk3568-iommu";
 639                 reg = <0x0 0xfdee0800 0x0 0x40>;
 640                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 641                 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
 642                 clock-names = "aclk", "iface";
 643                 power-domains = <&power RK3568_PD_RGA>;
 644                 #iommu-cells = <0>;
 645         };
 646
 647         sdmmc2: mmc@fe000000 {
 648                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
 649                 reg = <0x0 0xfe000000 0x0 0x4000>;
 650                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 651                 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
 652                          <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
 653                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 654                 fifo-depth = <0x100>;
 655                 max-frequency = <150000000>;
 656                 resets = <&cru SRST_SDMMC2>;
 657                 reset-names = "reset";
 658                 status = "disabled";
 659         };
 660
 661         gmac1: ethernet@fe010000 {
 662                 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
 663                 reg = <0x0 0xfe010000 0x0 0x10000>;
 664                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 665                              <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 666                 interrupt-names = "macirq", "eth_wake_irq";
 667                 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
 668                          <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
 669                          <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
 670                          <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
 671                 clock-names = "stmmaceth", "mac_clk_rx",
 672                               "mac_clk_tx", "clk_mac_refout",
 673                               "aclk_mac", "pclk_mac",
 674                               "clk_mac_speed", "ptp_ref";
 675                 resets = <&cru SRST_A_GMAC1>;
 676                 reset-names = "stmmaceth";
 677                 rockchip,grf = <&grf>;
 678                 snps,axi-config = <&gmac1_stmmac_axi_setup>;
 679                 snps,mixed-burst;
 680                 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
 681                 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
 682                 snps,tso;
 683                 status = "disabled";
 684
 685                 mdio1: mdio {
 686                         compatible = "snps,dwmac-mdio";
 687                         #address-cells = <0x1>;
 688                         #size-cells = <0x0>;
 689                 };
 690
 691                 gmac1_stmmac_axi_setup: stmmac-axi-config {
 692                         snps,blen = <0 0 0 0 16 8 4>;
 693                         snps,rd_osr_lmt = <8>;
 694                         snps,wr_osr_lmt = <4>;
 695                 };
 696
 697                 gmac1_mtl_rx_setup: rx-queues-config {
 698                         snps,rx-queues-to-use = <1>;
 699                         queue0 {};
 700                 };
 701
 702                 gmac1_mtl_tx_setup: tx-queues-config {
 703                         snps,tx-queues-to-use = <1>;
 704                         queue0 {};
 705                 };
 706         };
 707
 708         vop: vop@fe040000 {
 709                 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
 710                 reg-names = "vop", "gamma-lut";
 711                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 712                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
 713                          <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
 714                 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
 715                 iommus = <&vop_mmu>;
 716                 power-domains = <&power RK3568_PD_VO>;
 717                 rockchip,grf = <&grf>;
 718                 status = "disabled";
 719
 720                 vop_out: ports {
 721                         #address-cells = <1>;
 722                         #size-cells = <0>;
 723
 724                         vp0: port@0 {
 725                                 reg = <0>;
 726                                 #address-cells = <1>;
 727                                 #size-cells = <0>;
 728                         };
 729
 730                         vp1: port@1 {
 731                                 reg = <1>;
 732                                 #address-cells = <1>;
 733                                 #size-cells = <0>;
 734                         };
 735
 736                         vp2: port@2 {
 737                                 reg = <2>;
 738                                 #address-cells = <1>;
 739                                 #size-cells = <0>;
 740                         };
 741                 };
 742         };
 743
 744         vop_mmu: iommu@fe043e00 {
 745                 compatible = "rockchip,rk3568-iommu";
 746                 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
 747                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 748                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 749                 clock-names = "aclk", "iface";
 750                 #iommu-cells = <0>;
 751                 status = "disabled";
 752         };
 753
 754         dsi0: dsi@fe060000 {
 755                 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
 756                 reg = <0x00 0xfe060000 0x00 0x10000>;
 757                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 758                 clock-names = "pclk";
 759                 clocks = <&cru PCLK_DSITX_0>;
 760                 phy-names = "dphy";
 761                 phys = <&dsi_dphy0>;
 762                 power-domains = <&power RK3568_PD_VO>;
 763                 reset-names = "apb";
 764                 resets = <&cru SRST_P_DSITX_0>;
 765                 rockchip,grf = <&grf>;
 766                 status = "disabled";
 767
 768                 ports {
 769                         #address-cells = <1>;
 770                         #size-cells = <0>;
 771
 772                         dsi0_in: port@0 {
 773                                 reg = <0>;
 774                         };
 775
 776                         dsi0_out: port@1 {
 777                                 reg = <1>;
 778                         };
 779                 };
 780         };
 781
 782         dsi1: dsi@fe070000 {
 783                 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
 784                 reg = <0x0 0xfe070000 0x0 0x10000>;
 785                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 786                 clock-names = "pclk";
 787                 clocks = <&cru PCLK_DSITX_1>;
 788                 phy-names = "dphy";
 789                 phys = <&dsi_dphy1>;
 790                 power-domains = <&power RK3568_PD_VO>;
 791                 reset-names = "apb";
 792                 resets = <&cru SRST_P_DSITX_1>;
 793                 rockchip,grf = <&grf>;
 794                 status = "disabled";
 795
 796                 ports {
 797                         #address-cells = <1>;
 798                         #size-cells = <0>;
 799
 800                         dsi1_in: port@0 {
 801                                 reg = <0>;
 802                         };
 803
 804                         dsi1_out: port@1 {
 805                                 reg = <1>;
 806                         };
 807                 };
 808         };
 809
 810         hdmi: hdmi@fe0a0000 {
 811                 compatible = "rockchip,rk3568-dw-hdmi";
 812                 reg = <0x0 0xfe0a0000 0x0 0x20000>;
 813                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 814                 clocks = <&cru PCLK_HDMI_HOST>,
 815                          <&cru CLK_HDMI_SFR>,
 816                          <&cru CLK_HDMI_CEC>,
 817                          <&pmucru CLK_HDMI_REF>,
 818                          <&cru HCLK_VO>;
 819                 clock-names = "iahb", "isfr", "cec", "ref";
 820                 pinctrl-names = "default";
 821                 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
 822                 power-domains = <&power RK3568_PD_VO>;
 823                 reg-io-width = <4>;
 824                 rockchip,grf = <&grf>;
 825                 #sound-dai-cells = <0>;
 826                 status = "disabled";
 827
 828                 ports {
 829                         #address-cells = <1>;
 830                         #size-cells = <0>;
 831
 832                         hdmi_in: port@0 {
 833                                 reg = <0>;
 834                         };
 835
 836                         hdmi_out: port@1 {
 837                                 reg = <1>;
 838                         };
 839                 };
 840         };
 841
 842         qos_gpu: qos@fe128000 {
 843                 compatible = "rockchip,rk3568-qos", "syscon";
 844                 reg = <0x0 0xfe128000 0x0 0x20>;
 845         };
 846
 847         qos_rkvenc_rd_m0: qos@fe138080 {
 848                 compatible = "rockchip,rk3568-qos", "syscon";
 849                 reg = <0x0 0xfe138080 0x0 0x20>;
 850         };
 851
 852         qos_rkvenc_rd_m1: qos@fe138100 {
 853                 compatible = "rockchip,rk3568-qos", "syscon";
 854                 reg = <0x0 0xfe138100 0x0 0x20>;
 855         };
 856
 857         qos_rkvenc_wr_m0: qos@fe138180 {
 858                 compatible = "rockchip,rk3568-qos", "syscon";
 859                 reg = <0x0 0xfe138180 0x0 0x20>;
 860         };
 861
 862         qos_isp: qos@fe148000 {
 863                 compatible = "rockchip,rk3568-qos", "syscon";
 864                 reg = <0x0 0xfe148000 0x0 0x20>;
 865         };
 866
 867         qos_vicap0: qos@fe148080 {
 868                 compatible = "rockchip,rk3568-qos", "syscon";
 869                 reg = <0x0 0xfe148080 0x0 0x20>;
 870         };
 871
 872         qos_vicap1: qos@fe148100 {
 873                 compatible = "rockchip,rk3568-qos", "syscon";
 874                 reg = <0x0 0xfe148100 0x0 0x20>;
 875         };
 876
 877         qos_vpu: qos@fe150000 {
 878                 compatible = "rockchip,rk3568-qos", "syscon";
 879                 reg = <0x0 0xfe150000 0x0 0x20>;
 880         };
 881
 882         qos_ebc: qos@fe158000 {
 883                 compatible = "rockchip,rk3568-qos", "syscon";
 884                 reg = <0x0 0xfe158000 0x0 0x20>;
 885         };
 886
 887         qos_iep: qos@fe158100 {
 888                 compatible = "rockchip,rk3568-qos", "syscon";
 889                 reg = <0x0 0xfe158100 0x0 0x20>;
 890         };
 891
 892         qos_jpeg_dec: qos@fe158180 {
 893                 compatible = "rockchip,rk3568-qos", "syscon";
 894                 reg = <0x0 0xfe158180 0x0 0x20>;
 895         };
 896
 897         qos_jpeg_enc: qos@fe158200 {
 898                 compatible = "rockchip,rk3568-qos", "syscon";
 899                 reg = <0x0 0xfe158200 0x0 0x20>;
 900         };
 901
 902         qos_rga_rd: qos@fe158280 {
 903                 compatible = "rockchip,rk3568-qos", "syscon";
 904                 reg = <0x0 0xfe158280 0x0 0x20>;
 905         };
 906
 907         qos_rga_wr: qos@fe158300 {
 908                 compatible = "rockchip,rk3568-qos", "syscon";
 909                 reg = <0x0 0xfe158300 0x0 0x20>;
 910         };
 911
 912         qos_npu: qos@fe180000 {
 913                 compatible = "rockchip,rk3568-qos", "syscon";
 914                 reg = <0x0 0xfe180000 0x0 0x20>;
 915         };
 916
 917         qos_pcie2x1: qos@fe190000 {
 918                 compatible = "rockchip,rk3568-qos", "syscon";
 919                 reg = <0x0 0xfe190000 0x0 0x20>;
 920         };
 921
 922         qos_sata1: qos@fe190280 {
 923                 compatible = "rockchip,rk3568-qos", "syscon";
 924                 reg = <0x0 0xfe190280 0x0 0x20>;
 925         };
 926
 927         qos_sata2: qos@fe190300 {
 928                 compatible = "rockchip,rk3568-qos", "syscon";
 929                 reg = <0x0 0xfe190300 0x0 0x20>;
 930         };
 931
 932         qos_usb3_0: qos@fe190380 {
 933                 compatible = "rockchip,rk3568-qos", "syscon";
 934                 reg = <0x0 0xfe190380 0x0 0x20>;
 935         };
 936
 937         qos_usb3_1: qos@fe190400 {
 938                 compatible = "rockchip,rk3568-qos", "syscon";
 939                 reg = <0x0 0xfe190400 0x0 0x20>;
 940         };
 941
 942         qos_rkvdec: qos@fe198000 {
 943                 compatible = "rockchip,rk3568-qos", "syscon";
 944                 reg = <0x0 0xfe198000 0x0 0x20>;
 945         };
 946
 947         qos_hdcp: qos@fe1a8000 {
 948                 compatible = "rockchip,rk3568-qos", "syscon";
 949                 reg = <0x0 0xfe1a8000 0x0 0x20>;
 950         };
 951
 952         qos_vop_m0: qos@fe1a8080 {
 953                 compatible = "rockchip,rk3568-qos", "syscon";
 954                 reg = <0x0 0xfe1a8080 0x0 0x20>;
 955         };
 956
 957         qos_vop_m1: qos@fe1a8100 {
 958                 compatible = "rockchip,rk3568-qos", "syscon";
 959                 reg = <0x0 0xfe1a8100 0x0 0x20>;
 960         };
 961
 962         pcie2x1: pcie@fe260000 {
 963                 compatible = "rockchip,rk3568-pcie";
 964                 reg = <0x3 0xc0000000 0x0 0x00400000>,
 965                       <0x0 0xfe260000 0x0 0x00010000>,
 966                       <0x0 0xf4000000 0x0 0x00100000>;
 967                 reg-names = "dbi", "apb", "config";
 968                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 969                              <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 970                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 971                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 972                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 973                 interrupt-names = "sys", "pmc", "msi", "legacy", "err";
 974                 bus-range = <0x0 0xf>;
 975                 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
 976                          <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
 977                          <&cru CLK_PCIE20_AUX_NDFT>;
 978                 clock-names = "aclk_mst", "aclk_slv",
 979                               "aclk_dbi", "pclk", "aux";
 980                 device_type = "pci";
 981                 #interrupt-cells = <1>;
 982                 interrupt-map-mask = <0 0 0 7>;
 983                 interrupt-map = <0 0 0 1 &pcie_intc 0>,
 984                                 <0 0 0 2 &pcie_intc 1>,
 985                                 <0 0 0 3 &pcie_intc 2>,
 986                                 <0 0 0 4 &pcie_intc 3>;
 987                 linux,pci-domain = <0>;
 988                 num-ib-windows = <6>;
 989                 num-ob-windows = <2>;
 990                 max-link-speed = <2>;
 991                 msi-map = <0x0 &gic 0x0 0x1000>;
 992                 num-lanes = <1>;
 993                 phys = <&combphy2 PHY_TYPE_PCIE>;
 994                 phy-names = "pcie-phy";
 995                 power-domains = <&power RK3568_PD_PIPE>;
 996                 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
 997                          <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
 998                          <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
 999                 resets = <&cru SRST_PCIE20_POWERUP>;
1000                 reset-names = "pipe";
1001                 #address-cells = <3>;
1002                 #size-cells = <2>;
1003                 status = "disabled";
1004
1005                 pcie_intc: legacy-interrupt-controller {
1006                         #address-cells = <0>;
1007                         #interrupt-cells = <1>;
1008                         interrupt-controller;
1009                         interrupt-parent = <&gic>;
1010                         interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
1011                 };
1012         };
1013
1014         sdmmc0: mmc@fe2b0000 {
1015                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1016                 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1017                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1018                 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
1019                          <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1020                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1021                 fifo-depth = <0x100>;
1022                 max-frequency = <150000000>;
1023                 resets = <&cru SRST_SDMMC0>;
1024                 reset-names = "reset";
1025                 status = "disabled";
1026         };
1027
1028         sdmmc1: mmc@fe2c0000 {
1029                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1030                 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1031                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1032                 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
1033                          <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1034                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1035                 fifo-depth = <0x100>;
1036                 max-frequency = <150000000>;
1037                 resets = <&cru SRST_SDMMC1>;
1038                 reset-names = "reset";
1039                 status = "disabled";
1040         };
1041
1042         sfc: spi@fe300000 {
1043                 compatible = "rockchip,sfc";
1044                 reg = <0x0 0xfe300000 0x0 0x4000>;
1045                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1046                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1047                 clock-names = "clk_sfc", "hclk_sfc";
1048                 pinctrl-0 = <&fspi_pins>;
1049                 pinctrl-names = "default";
1050                 status = "disabled";
1051         };
1052
1053         sdhci: mmc@fe310000 {
1054                 compatible = "rockchip,rk3568-dwcmshc";
1055                 reg = <0x0 0xfe310000 0x0 0x10000>;
1056                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1057                 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1058                 assigned-clock-rates = <200000000>, <24000000>;
1059                 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1060                          <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1061                          <&cru TCLK_EMMC>;
1062                 clock-names = "core", "bus", "axi", "block", "timer";
1063                 status = "disabled";
1064         };
1065
1066         i2s0_8ch: i2s@fe400000 {
1067                 compatible = "rockchip,rk3568-i2s-tdm";
1068                 reg = <0x0 0xfe400000 0x0 0x1000>;
1069                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1070                 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1071                 assigned-clock-rates = <1188000000>, <1188000000>;
1072                 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1073                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1074                 dmas = <&dmac1 0>;
1075                 dma-names = "tx";
1076                 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1077                 reset-names = "tx-m", "rx-m";
1078                 rockchip,grf = <&grf>;
1079                 #sound-dai-cells = <0>;
1080                 status = "disabled";
1081         };
1082
1083         i2s1_8ch: i2s@fe410000 {
1084                 compatible = "rockchip,rk3568-i2s-tdm";
1085                 reg = <0x0 0xfe410000 0x0 0x1000>;
1086                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1087                 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1088                 assigned-clock-rates = <1188000000>, <1188000000>;
1089                 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
1090                          <&cru HCLK_I2S1_8CH>;
1091                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1092                 dmas = <&dmac1 3>, <&dmac1 2>;
1093                 dma-names = "rx", "tx";
1094                 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1095                 reset-names = "tx-m", "rx-m";
1096                 rockchip,grf = <&grf>;
1097                 pinctrl-names = "default";
1098                 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1099                              &i2s1m0_lrcktx &i2s1m0_lrckrx
1100                              &i2s1m0_sdi0   &i2s1m0_sdi1
1101                              &i2s1m0_sdi2   &i2s1m0_sdi3
1102                              &i2s1m0_sdo0   &i2s1m0_sdo1
1103                              &i2s1m0_sdo2   &i2s1m0_sdo3>;
1104                 #sound-dai-cells = <0>;
1105                 status = "disabled";
1106         };
1107
1108         i2s2_2ch: i2s@fe420000 {
1109                 compatible = "rockchip,rk3568-i2s-tdm";
1110                 reg = <0x0 0xfe420000 0x0 0x1000>;
1111                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1112                 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1113                 assigned-clock-rates = <1188000000>;
1114                 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1115                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1116                 dmas = <&dmac1 4>, <&dmac1 5>;
1117                 dma-names = "tx", "rx";
1118                 resets = <&cru SRST_M_I2S2_2CH>;
1119                 reset-names = "m";
1120                 rockchip,grf = <&grf>;
1121                 pinctrl-names = "default";
1122                 pinctrl-0 = <&i2s2m0_sclktx
1123                                 &i2s2m0_lrcktx
1124                                 &i2s2m0_sdi
1125                                 &i2s2m0_sdo>;
1126                 #sound-dai-cells = <0>;
1127                 status = "disabled";
1128         };
1129
1130         i2s3_2ch: i2s@fe430000 {
1131                 compatible = "rockchip,rk3568-i2s-tdm";
1132                 reg = <0x0 0xfe430000 0x0 0x1000>;
1133                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1134                 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
1135                          <&cru HCLK_I2S3_2CH>;
1136                 clock-names = "mclk_tx", "mclk_rx", "hclk";
1137                 dmas = <&dmac1 6>, <&dmac1 7>;
1138                 dma-names = "tx", "rx";
1139                 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
1140                 reset-names = "tx-m", "rx-m";
1141                 rockchip,grf = <&grf>;
1142                 #sound-dai-cells = <0>;
1143                 status = "disabled";
1144         };
1145
1146         pdm: pdm@fe440000 {
1147                 compatible = "rockchip,rk3568-pdm";
1148                 reg = <0x0 0xfe440000 0x0 0x1000>;
1149                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1150                 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1151                 clock-names = "pdm_clk", "pdm_hclk";
1152                 dmas = <&dmac1 9>;
1153                 dma-names = "rx";
1154                 pinctrl-0 = <&pdmm0_clk
1155                              &pdmm0_clk1
1156                              &pdmm0_sdi0
1157                              &pdmm0_sdi1
1158                              &pdmm0_sdi2
1159                              &pdmm0_sdi3>;
1160                 pinctrl-names = "default";
1161                 resets = <&cru SRST_M_PDM>;
1162                 reset-names = "pdm-m";
1163                 #sound-dai-cells = <0>;
1164                 status = "disabled";
1165         };
1166
1167         spdif: spdif@fe460000 {
1168                 compatible = "rockchip,rk3568-spdif";
1169                 reg = <0x0 0xfe460000 0x0 0x1000>;
1170                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1171                 clock-names = "mclk", "hclk";
1172                 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
1173                 dmas = <&dmac1 1>;
1174                 dma-names = "tx";
1175                 pinctrl-names = "default";
1176                 pinctrl-0 = <&spdifm0_tx>;
1177                 #sound-dai-cells = <0>;
1178                 status = "disabled";
1179         };
1180
1181         dmac0: dma-controller@fe530000 {
1182                 compatible = "arm,pl330", "arm,primecell";
1183                 reg = <0x0 0xfe530000 0x0 0x4000>;
1184                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1185                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1186                 arm,pl330-periph-burst;
1187                 clocks = <&cru ACLK_BUS>;
1188                 clock-names = "apb_pclk";
1189                 #dma-cells = <1>;
1190         };
1191
1192         dmac1: dma-controller@fe550000 {
1193                 compatible = "arm,pl330", "arm,primecell";
1194                 reg = <0x0 0xfe550000 0x0 0x4000>;
1195                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1196                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1197                 arm,pl330-periph-burst;
1198                 clocks = <&cru ACLK_BUS>;
1199                 clock-names = "apb_pclk";
1200                 #dma-cells = <1>;
1201         };
1202
1203         i2c1: i2c@fe5a0000 {
1204                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1205                 reg = <0x0 0xfe5a0000 0x0 0x1000>;
1206                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1207                 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1208                 clock-names = "i2c", "pclk";
1209                 pinctrl-0 = <&i2c1_xfer>;
1210                 pinctrl-names = "default";
1211                 #address-cells = <1>;
1212                 #size-cells = <0>;
1213                 status = "disabled";
1214         };
1215
1216         i2c2: i2c@fe5b0000 {
1217                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1218                 reg = <0x0 0xfe5b0000 0x0 0x1000>;
1219                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1220                 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1221                 clock-names = "i2c", "pclk";
1222                 pinctrl-0 = <&i2c2m0_xfer>;
1223                 pinctrl-names = "default";
1224                 #address-cells = <1>;
1225                 #size-cells = <0>;
1226                 status = "disabled";
1227         };
1228
1229         i2c3: i2c@fe5c0000 {
1230                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1231                 reg = <0x0 0xfe5c0000 0x0 0x1000>;
1232                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1233                 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1234                 clock-names = "i2c", "pclk";
1235                 pinctrl-0 = <&i2c3m0_xfer>;
1236                 pinctrl-names = "default";
1237                 #address-cells = <1>;
1238                 #size-cells = <0>;
1239                 status = "disabled";
1240         };
1241
1242         i2c4: i2c@fe5d0000 {
1243                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1244                 reg = <0x0 0xfe5d0000 0x0 0x1000>;
1245                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1246                 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1247                 clock-names = "i2c", "pclk";
1248                 pinctrl-0 = <&i2c4m0_xfer>;
1249                 pinctrl-names = "default";
1250                 #address-cells = <1>;
1251                 #size-cells = <0>;
1252                 status = "disabled";
1253         };
1254
1255         i2c5: i2c@fe5e0000 {
1256                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1257                 reg = <0x0 0xfe5e0000 0x0 0x1000>;
1258                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1259                 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1260                 clock-names = "i2c", "pclk";
1261                 pinctrl-0 = <&i2c5m0_xfer>;
1262                 pinctrl-names = "default";
1263                 #address-cells = <1>;
1264                 #size-cells = <0>;
1265                 status = "disabled";
1266         };
1267
1268         wdt: watchdog@fe600000 {
1269                 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1270                 reg = <0x0 0xfe600000 0x0 0x100>;
1271                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1272                 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1273                 clock-names = "tclk", "pclk";
1274         };
1275
1276         spi0: spi@fe610000 {
1277                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1278                 reg = <0x0 0xfe610000 0x0 0x1000>;
1279                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1280                 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1281                 clock-names = "spiclk", "apb_pclk";
1282                 dmas = <&dmac0 20>, <&dmac0 21>;
1283                 dma-names = "tx", "rx";
1284                 pinctrl-names = "default";
1285                 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1286                 #address-cells = <1>;
1287                 #size-cells = <0>;
1288                 status = "disabled";
1289         };
1290
1291         spi1: spi@fe620000 {
1292                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1293                 reg = <0x0 0xfe620000 0x0 0x1000>;
1294                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1295                 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1296                 clock-names = "spiclk", "apb_pclk";
1297                 dmas = <&dmac0 22>, <&dmac0 23>;
1298                 dma-names = "tx", "rx";
1299                 pinctrl-names = "default";
1300                 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1301                 #address-cells = <1>;
1302                 #size-cells = <0>;
1303                 status = "disabled";
1304         };
1305
1306         spi2: spi@fe630000 {
1307                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1308                 reg = <0x0 0xfe630000 0x0 0x1000>;
1309                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1310                 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1311                 clock-names = "spiclk", "apb_pclk";
1312                 dmas = <&dmac0 24>, <&dmac0 25>;
1313                 dma-names = "tx", "rx";
1314                 pinctrl-names = "default";
1315                 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1316                 #address-cells = <1>;
1317                 #size-cells = <0>;
1318                 status = "disabled";
1319         };
1320
1321         spi3: spi@fe640000 {
1322                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1323                 reg = <0x0 0xfe640000 0x0 0x1000>;
1324                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1325                 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1326                 clock-names = "spiclk", "apb_pclk";
1327                 dmas = <&dmac0 26>, <&dmac0 27>;
1328                 dma-names = "tx", "rx";
1329                 pinctrl-names = "default";
1330                 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1331                 #address-cells = <1>;
1332                 #size-cells = <0>;
1333                 status = "disabled";
1334         };
1335
1336         uart1: serial@fe650000 {
1337                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1338                 reg = <0x0 0xfe650000 0x0 0x100>;
1339                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1340                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1341                 clock-names = "baudclk", "apb_pclk";
1342                 dmas = <&dmac0 2>, <&dmac0 3>;
1343                 pinctrl-0 = <&uart1m0_xfer>;
1344                 pinctrl-names = "default";
1345                 reg-io-width = <4>;
1346                 reg-shift = <2>;
1347                 status = "disabled";
1348         };
1349
1350         uart2: serial@fe660000 {
1351                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1352                 reg = <0x0 0xfe660000 0x0 0x100>;
1353                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1354                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1355                 clock-names = "baudclk", "apb_pclk";
1356                 dmas = <&dmac0 4>, <&dmac0 5>;
1357                 pinctrl-0 = <&uart2m0_xfer>;
1358                 pinctrl-names = "default";
1359                 reg-io-width = <4>;
1360                 reg-shift = <2>;
1361                 status = "disabled";
1362         };
1363
1364         uart3: serial@fe670000 {
1365                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1366                 reg = <0x0 0xfe670000 0x0 0x100>;
1367                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1368                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1369                 clock-names = "baudclk", "apb_pclk";
1370                 dmas = <&dmac0 6>, <&dmac0 7>;
1371                 pinctrl-0 = <&uart3m0_xfer>;
1372                 pinctrl-names = "default";
1373                 reg-io-width = <4>;
1374                 reg-shift = <2>;
1375                 status = "disabled";
1376         };
1377
1378         uart4: serial@fe680000 {
1379                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1380                 reg = <0x0 0xfe680000 0x0 0x100>;
1381                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1382                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1383                 clock-names = "baudclk", "apb_pclk";
1384                 dmas = <&dmac0 8>, <&dmac0 9>;
1385                 pinctrl-0 = <&uart4m0_xfer>;
1386                 pinctrl-names = "default";
1387                 reg-io-width = <4>;
1388                 reg-shift = <2>;
1389                 status = "disabled";
1390         };
1391
1392         uart5: serial@fe690000 {
1393                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1394                 reg = <0x0 0xfe690000 0x0 0x100>;
1395                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1396                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1397                 clock-names = "baudclk", "apb_pclk";
1398                 dmas = <&dmac0 10>, <&dmac0 11>;
1399                 pinctrl-0 = <&uart5m0_xfer>;
1400                 pinctrl-names = "default";
1401                 reg-io-width = <4>;
1402                 reg-shift = <2>;
1403                 status = "disabled";
1404         };
1405
1406         uart6: serial@fe6a0000 {
1407                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1408                 reg = <0x0 0xfe6a0000 0x0 0x100>;
1409                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1410                 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1411                 clock-names = "baudclk", "apb_pclk";
1412                 dmas = <&dmac0 12>, <&dmac0 13>;
1413                 pinctrl-0 = <&uart6m0_xfer>;
1414                 pinctrl-names = "default";
1415                 reg-io-width = <4>;
1416                 reg-shift = <2>;
1417                 status = "disabled";
1418         };
1419
1420         uart7: serial@fe6b0000 {
1421                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1422                 reg = <0x0 0xfe6b0000 0x0 0x100>;
1423                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1424                 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1425                 clock-names = "baudclk", "apb_pclk";
1426                 dmas = <&dmac0 14>, <&dmac0 15>;
1427                 pinctrl-0 = <&uart7m0_xfer>;
1428                 pinctrl-names = "default";
1429                 reg-io-width = <4>;
1430                 reg-shift = <2>;
1431                 status = "disabled";
1432         };
1433
1434         uart8: serial@fe6c0000 {
1435                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1436                 reg = <0x0 0xfe6c0000 0x0 0x100>;
1437                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1438                 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1439                 clock-names = "baudclk", "apb_pclk";
1440                 dmas = <&dmac0 16>, <&dmac0 17>;
1441                 pinctrl-0 = <&uart8m0_xfer>;
1442                 pinctrl-names = "default";
1443                 reg-io-width = <4>;
1444                 reg-shift = <2>;
1445                 status = "disabled";
1446         };
1447
1448         uart9: serial@fe6d0000 {
1449                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1450                 reg = <0x0 0xfe6d0000 0x0 0x100>;
1451                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1452                 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1453                 clock-names = "baudclk", "apb_pclk";
1454                 dmas = <&dmac0 18>, <&dmac0 19>;
1455                 pinctrl-0 = <&uart9m0_xfer>;
1456                 pinctrl-names = "default";
1457                 reg-io-width = <4>;
1458                 reg-shift = <2>;
1459                 status = "disabled";
1460         };
1461
1462         thermal_zones: thermal-zones {
1463                 cpu_thermal: cpu-thermal {
1464                         polling-delay-passive = <100>;
1465                         polling-delay = <1000>;
1466
1467                         thermal-sensors = <&tsadc 0>;
1468
1469                         trips {
1470                                 cpu_alert0: cpu_alert0 {
1471                                         temperature = <70000>;
1472                                         hysteresis = <2000>;
1473                                         type = "passive";
1474                                 };
1475                                 cpu_alert1: cpu_alert1 {
1476                                         temperature = <75000>;
1477                                         hysteresis = <2000>;
1478                                         type = "passive";
1479                                 };
1480                                 cpu_crit: cpu_crit {
1481                                         temperature = <95000>;
1482                                         hysteresis = <2000>;
1483                                         type = "critical";
1484                                 };
1485                         };
1486
1487                         cooling-maps {
1488                                 map0 {
1489                                         trip = <&cpu_alert0>;
1490                                         cooling-device =
1491                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1492                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1493                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1494                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1495                                 };
1496                         };
1497                 };
1498
1499                 gpu_thermal: gpu-thermal {
1500                         polling-delay-passive = <20>; /* milliseconds */
1501                         polling-delay = <1000>; /* milliseconds */
1502
1503                         thermal-sensors = <&tsadc 1>;
1504
1505                         trips {
1506                                 gpu_threshold: gpu-threshold {
1507                                         temperature = <70000>;
1508                                         hysteresis = <2000>;
1509                                         type = "passive";
1510                                 };
1511                                 gpu_target: gpu-target {
1512                                         temperature = <75000>;
1513                                         hysteresis = <2000>;
1514                                         type = "passive";
1515                                 };
1516                                 gpu_crit: gpu-crit {
1517                                         temperature = <95000>;
1518                                         hysteresis = <2000>;
1519                                         type = "critical";
1520                                 };
1521                         };
1522
1523                         cooling-maps {
1524                                 map0 {
1525                                         trip = <&gpu_target>;
1526                                         cooling-device =
1527                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1528                                 };
1529                         };
1530                 };
1531         };
1532
1533         tsadc: tsadc@fe710000 {
1534                 compatible = "rockchip,rk3568-tsadc";
1535                 reg = <0x0 0xfe710000 0x0 0x100>;
1536                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1537                 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1538                 assigned-clock-rates = <17000000>, <700000>;
1539                 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
1540                 clock-names = "tsadc", "apb_pclk";
1541                 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
1542                          <&cru SRST_TSADCPHY>;
1543                 rockchip,grf = <&grf>;
1544                 rockchip,hw-tshut-temp = <95000>;
1545                 pinctrl-names = "init", "default", "sleep";
1546                 pinctrl-0 = <&tsadc_pin>;
1547                 pinctrl-1 = <&tsadc_shutorg>;
1548                 pinctrl-2 = <&tsadc_pin>;
1549                 #thermal-sensor-cells = <1>;
1550                 status = "disabled";
1551         };
1552
1553         saradc: saradc@fe720000 {
1554                 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1555                 reg = <0x0 0xfe720000 0x0 0x100>;
1556                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1557                 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1558                 clock-names = "saradc", "apb_pclk";
1559                 resets = <&cru SRST_P_SARADC>;
1560                 reset-names = "saradc-apb";
1561                 #io-channel-cells = <1>;
1562                 status = "disabled";
1563         };
1564
1565         pwm4: pwm@fe6e0000 {
1566                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1567                 reg = <0x0 0xfe6e0000 0x0 0x10>;
1568                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1569                 clock-names = "pwm", "pclk";
1570                 pinctrl-0 = <&pwm4_pins>;
1571                 pinctrl-names = "default";
1572                 #pwm-cells = <3>;
1573                 status = "disabled";
1574         };
1575
1576         pwm5: pwm@fe6e0010 {
1577                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1578                 reg = <0x0 0xfe6e0010 0x0 0x10>;
1579                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1580                 clock-names = "pwm", "pclk";
1581                 pinctrl-0 = <&pwm5_pins>;
1582                 pinctrl-names = "default";
1583                 #pwm-cells = <3>;
1584                 status = "disabled";
1585         };
1586
1587         pwm6: pwm@fe6e0020 {
1588                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1589                 reg = <0x0 0xfe6e0020 0x0 0x10>;
1590                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1591                 clock-names = "pwm", "pclk";
1592                 pinctrl-0 = <&pwm6_pins>;
1593                 pinctrl-names = "default";
1594                 #pwm-cells = <3>;
1595                 status = "disabled";
1596         };
1597
1598         pwm7: pwm@fe6e0030 {
1599                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1600                 reg = <0x0 0xfe6e0030 0x0 0x10>;
1601                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1602                 clock-names = "pwm", "pclk";
1603                 pinctrl-0 = <&pwm7_pins>;
1604                 pinctrl-names = "default";
1605                 #pwm-cells = <3>;
1606                 status = "disabled";
1607         };
1608
1609         pwm8: pwm@fe6f0000 {
1610                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1611                 reg = <0x0 0xfe6f0000 0x0 0x10>;
1612                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1613                 clock-names = "pwm", "pclk";
1614                 pinctrl-0 = <&pwm8m0_pins>;
1615                 pinctrl-names = "default";
1616                 #pwm-cells = <3>;
1617                 status = "disabled";
1618         };
1619
1620         pwm9: pwm@fe6f0010 {
1621                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1622                 reg = <0x0 0xfe6f0010 0x0 0x10>;
1623                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1624                 clock-names = "pwm", "pclk";
1625                 pinctrl-0 = <&pwm9m0_pins>;
1626                 pinctrl-names = "default";
1627                 #pwm-cells = <3>;
1628                 status = "disabled";
1629         };
1630
1631         pwm10: pwm@fe6f0020 {
1632                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1633                 reg = <0x0 0xfe6f0020 0x0 0x10>;
1634                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1635                 clock-names = "pwm", "pclk";
1636                 pinctrl-0 = <&pwm10m0_pins>;
1637                 pinctrl-names = "default";
1638                 #pwm-cells = <3>;
1639                 status = "disabled";
1640         };
1641
1642         pwm11: pwm@fe6f0030 {
1643                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1644                 reg = <0x0 0xfe6f0030 0x0 0x10>;
1645                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1646                 clock-names = "pwm", "pclk";
1647                 pinctrl-0 = <&pwm11m0_pins>;
1648                 pinctrl-names = "default";
1649                 #pwm-cells = <3>;
1650                 status = "disabled";
1651         };
1652
1653         pwm12: pwm@fe700000 {
1654                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1655                 reg = <0x0 0xfe700000 0x0 0x10>;
1656                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1657                 clock-names = "pwm", "pclk";
1658                 pinctrl-0 = <&pwm12m0_pins>;
1659                 pinctrl-names = "default";
1660                 #pwm-cells = <3>;
1661                 status = "disabled";
1662         };
1663
1664         pwm13: pwm@fe700010 {
1665                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1666                 reg = <0x0 0xfe700010 0x0 0x10>;
1667                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1668                 clock-names = "pwm", "pclk";
1669                 pinctrl-0 = <&pwm13m0_pins>;
1670                 pinctrl-names = "default";
1671                 #pwm-cells = <3>;
1672                 status = "disabled";
1673         };
1674
1675         pwm14: pwm@fe700020 {
1676                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1677                 reg = <0x0 0xfe700020 0x0 0x10>;
1678                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1679                 clock-names = "pwm", "pclk";
1680                 pinctrl-0 = <&pwm14m0_pins>;
1681                 pinctrl-names = "default";
1682                 #pwm-cells = <3>;
1683                 status = "disabled";
1684         };
1685
1686         pwm15: pwm@fe700030 {
1687                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1688                 reg = <0x0 0xfe700030 0x0 0x10>;
1689                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1690                 clock-names = "pwm", "pclk";
1691                 pinctrl-0 = <&pwm15m0_pins>;
1692                 pinctrl-names = "default";
1693                 #pwm-cells = <3>;
1694                 status = "disabled";
1695         };
1696
1697         combphy1: phy@fe830000 {
1698                 compatible = "rockchip,rk3568-naneng-combphy";
1699                 reg = <0x0 0xfe830000 0x0 0x100>;
1700                 clocks = <&pmucru CLK_PCIEPHY1_REF>,
1701                          <&cru PCLK_PIPEPHY1>,
1702                          <&cru PCLK_PIPE>;
1703                 clock-names = "ref", "apb", "pipe";
1704                 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1705                 assigned-clock-rates = <100000000>;
1706                 resets = <&cru SRST_PIPEPHY1>;
1707                 rockchip,pipe-grf = <&pipegrf>;
1708                 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1709                 #phy-cells = <1>;
1710                 status = "disabled";
1711         };
1712
1713         combphy2: phy@fe840000 {
1714                 compatible = "rockchip,rk3568-naneng-combphy";
1715                 reg = <0x0 0xfe840000 0x0 0x100>;
1716                 clocks = <&pmucru CLK_PCIEPHY2_REF>,
1717                          <&cru PCLK_PIPEPHY2>,
1718                          <&cru PCLK_PIPE>;
1719                 clock-names = "ref", "apb", "pipe";
1720                 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1721                 assigned-clock-rates = <100000000>;
1722                 resets = <&cru SRST_PIPEPHY2>;
1723                 rockchip,pipe-grf = <&pipegrf>;
1724                 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1725                 #phy-cells = <1>;
1726                 status = "disabled";
1727         };
1728
1729         csi_dphy: phy@fe870000 {
1730                 compatible = "rockchip,rk3568-csi-dphy";
1731                 reg = <0x0 0xfe870000 0x0 0x10000>;
1732                 clocks = <&cru PCLK_MIPICSIPHY>;
1733                 clock-names = "pclk";
1734                 #phy-cells = <0>;
1735                 resets = <&cru SRST_P_MIPICSIPHY>;
1736                 reset-names = "apb";
1737                 rockchip,grf = <&grf>;
1738                 status = "disabled";
1739         };
1740
1741         dsi_dphy0: mipi-dphy@fe850000 {
1742                 compatible = "rockchip,rk3568-dsi-dphy";
1743                 reg = <0x0 0xfe850000 0x0 0x10000>;
1744                 clock-names = "ref", "pclk";
1745                 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
1746                 #phy-cells = <0>;
1747                 power-domains = <&power RK3568_PD_VO>;
1748                 reset-names = "apb";
1749                 resets = <&cru SRST_P_MIPIDSIPHY0>;
1750                 status = "disabled";
1751         };
1752
1753         dsi_dphy1: mipi-dphy@fe860000 {
1754                 compatible = "rockchip,rk3568-dsi-dphy";
1755                 reg = <0x0 0xfe860000 0x0 0x10000>;
1756                 clock-names = "ref", "pclk";
1757                 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
1758                 #phy-cells = <0>;
1759                 power-domains = <&power RK3568_PD_VO>;
1760                 reset-names = "apb";
1761                 resets = <&cru SRST_P_MIPIDSIPHY1>;
1762                 status = "disabled";
1763         };
1764
1765         usb2phy0: usb2phy@fe8a0000 {
1766                 compatible = "rockchip,rk3568-usb2phy";
1767                 reg = <0x0 0xfe8a0000 0x0 0x10000>;
1768                 clocks = <&pmucru CLK_USBPHY0_REF>;
1769                 clock-names = "phyclk";
1770                 clock-output-names = "clk_usbphy0_480m";
1771                 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1772                 rockchip,usbgrf = <&usb2phy0_grf>;
1773                 #clock-cells = <0>;
1774                 status = "disabled";
1775
1776                 usb2phy0_host: host-port {
1777                         #phy-cells = <0>;
1778                         status = "disabled";
1779                 };
1780
1781                 usb2phy0_otg: otg-port {
1782                         #phy-cells = <0>;
1783                         status = "disabled";
1784                 };
1785         };
1786
1787         usb2phy1: usb2phy@fe8b0000 {
1788                 compatible = "rockchip,rk3568-usb2phy";
1789                 reg = <0x0 0xfe8b0000 0x0 0x10000>;
1790                 clocks = <&pmucru CLK_USBPHY1_REF>;
1791                 clock-names = "phyclk";
1792                 clock-output-names = "clk_usbphy1_480m";
1793                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1794                 rockchip,usbgrf = <&usb2phy1_grf>;
1795                 #clock-cells = <0>;
1796                 status = "disabled";
1797
1798                 usb2phy1_host: host-port {
1799                         #phy-cells = <0>;
1800                         status = "disabled";
1801                 };
1802
1803                 usb2phy1_otg: otg-port {
1804                         #phy-cells = <0>;
1805                         status = "disabled";
1806                 };
1807         };
1808
1809         pinctrl: pinctrl {
1810                 compatible = "rockchip,rk3568-pinctrl";
1811                 rockchip,grf = <&grf>;
1812                 rockchip,pmu = <&pmugrf>;
1813                 #address-cells = <2>;
1814                 #size-cells = <2>;
1815                 ranges;
1816
1817                 gpio0: gpio@fdd60000 {
1818                         compatible = "rockchip,gpio-bank";
1819                         reg = <0x0 0xfdd60000 0x0 0x100>;
1820                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1821                         clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
1822                         gpio-controller;
1823                         gpio-ranges = <&pinctrl 0 0 32>;
1824                         #gpio-cells = <2>;
1825                         interrupt-controller;
1826                         #interrupt-cells = <2>;
1827                 };
1828
1829                 gpio1: gpio@fe740000 {
1830                         compatible = "rockchip,gpio-bank";
1831                         reg = <0x0 0xfe740000 0x0 0x100>;
1832                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1833                         clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1834                         gpio-controller;
1835                         gpio-ranges = <&pinctrl 0 32 32>;
1836                         #gpio-cells = <2>;
1837                         interrupt-controller;
1838                         #interrupt-cells = <2>;
1839                 };
1840
1841                 gpio2: gpio@fe750000 {
1842                         compatible = "rockchip,gpio-bank";
1843                         reg = <0x0 0xfe750000 0x0 0x100>;
1844                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1845                         clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1846                         gpio-controller;
1847                         gpio-ranges = <&pinctrl 0 64 32>;
1848                         #gpio-cells = <2>;
1849                         interrupt-controller;
1850                         #interrupt-cells = <2>;
1851                 };
1852
1853                 gpio3: gpio@fe760000 {
1854                         compatible = "rockchip,gpio-bank";
1855                         reg = <0x0 0xfe760000 0x0 0x100>;
1856                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1857                         clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1858                         gpio-controller;
1859                         gpio-ranges = <&pinctrl 0 96 32>;
1860                         #gpio-cells = <2>;
1861                         interrupt-controller;
1862                         #interrupt-cells = <2>;
1863                 };
1864
1865                 gpio4: gpio@fe770000 {
1866                         compatible = "rockchip,gpio-bank";
1867                         reg = <0x0 0xfe770000 0x0 0x100>;
1868                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1869                         clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
1870                         gpio-controller;
1871                         gpio-ranges = <&pinctrl 0 128 32>;
1872                         #gpio-cells = <2>;
1873                         interrupt-controller;
1874                         #interrupt-cells = <2>;
1875                 };
1876         };
1877 };
1878
1879 #include "rk3568-pinctrl.dtsi"