1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
5 * Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
13 #include "rk3568.dtsi"
16 model = "EmbedFire LubanCat 2";
17 compatible = "embedfire,lubancat-2", "rockchip,rk3568";
27 stdout-path = "serial2:1500000n8";
31 compatible = "gpio-leds";
35 linux,default-trigger = "heartbeat";
37 gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
38 pinctrl-names = "default";
39 pinctrl-0 = <&user_led_pin>;
44 compatible = "hdmi-connector";
48 hdmi_con_in: endpoint {
49 remote-endpoint = <&hdmi_out_con>;
54 dc_5v: dc-5v-regulator {
55 compatible = "regulator-fixed";
56 regulator-name = "dc_5v";
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
63 vcc3v3_sys: vcc3v3-sys-regulator {
64 compatible = "regulator-fixed";
65 regulator-name = "vcc3v3_sys";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 vin-supply = <&vcc5v0_sys>;
73 vcc5v0_sys: vcc5v0-sys-regulator {
74 compatible = "regulator-fixed";
75 regulator-name = "vcc5v0_sys";
78 regulator-min-microvolt = <5000000>;
79 regulator-max-microvolt = <5000000>;
80 vin-supply = <&dc_5v>;
83 vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator {
84 compatible = "regulator-fixed";
85 regulator-name = "m2_pcie_3v3";
87 regulator-min-microvolt = <3300000>;
88 regulator-max-microvolt = <3300000>;
89 gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
90 pinctrl-0 = <&vcc3v3_m2_pcie_en>;
91 pinctrl-names = "default";
92 startup-delay-us = <200000>;
93 vin-supply = <&vcc5v0_sys>;
96 vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator {
97 compatible = "regulator-fixed";
98 regulator-name = "minipcie_3v3";
100 regulator-min-microvolt = <3300000>;
101 regulator-max-microvolt = <3300000>;
102 gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
103 pinctrl-0 = <&vcc3v3_mini_pcie_en>;
104 pinctrl-names = "default";
105 startup-delay-us = <5000>;
106 vin-supply = <&vcc5v0_sys>;
109 vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
110 compatible = "regulator-fixed";
111 regulator-name = "vcc5v0_usb20_host";
113 gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
114 pinctrl-0 = <&vcc5v0_usb20_host_en>;
115 pinctrl-names = "default";
118 vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
119 compatible = "regulator-fixed";
120 regulator-name = "vcc5v0_usb30_host";
122 gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
123 pinctrl-0 = <&vcc5v0_usb30_host_en>;
124 pinctrl-names = "default";
127 vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator {
128 compatible = "regulator-fixed";
129 regulator-name = "vcc5v0_otg_vbus";
131 regulator-min-microvolt = <5000000>;
132 regulator-max-microvolt = <5000000>;
133 gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
134 pinctrl-0 = <&vcc5v0_otg_vbus_en>;
135 pinctrl-names = "default";
152 cpu-supply = <&vdd_cpu>;
156 cpu-supply = <&vdd_cpu>;
160 cpu-supply = <&vdd_cpu>;
164 cpu-supply = <&vdd_cpu>;
168 mali-supply = <&vdd_gpu>;
173 avdd-0v9-supply = <&vdda0v9_image>;
174 avdd-1v8-supply = <&vcca1v8_image>;
179 hdmi_in_vp0: endpoint {
180 remote-endpoint = <&vp0_out_hdmi>;
185 hdmi_out_con: endpoint {
186 remote-endpoint = <&hdmi_con_in>;
197 vdd_cpu: regulator@1c {
198 compatible = "tcs,tcs4525";
200 fcs,suspend-voltage-selector = <1>;
201 regulator-name = "vdd_cpu";
204 regulator-min-microvolt = <800000>;
205 regulator-max-microvolt = <1150000>;
206 regulator-ramp-delay = <2300>;
207 vin-supply = <&vcc5v0_sys>;
209 regulator-state-mem {
210 regulator-off-in-suspend;
215 compatible = "rockchip,rk809";
217 interrupt-parent = <&gpio0>;
218 interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
219 assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
220 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
222 clock-names = "mclk";
223 clocks = <&cru I2S1_MCLKOUT_TX>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pmic_int>;
226 rockchip,system-power-controller;
227 #sound-dai-cells = <0>;
228 vcc1-supply = <&vcc3v3_sys>;
229 vcc2-supply = <&vcc3v3_sys>;
230 vcc3-supply = <&vcc3v3_sys>;
231 vcc4-supply = <&vcc3v3_sys>;
232 vcc5-supply = <&vcc3v3_sys>;
233 vcc6-supply = <&vcc3v3_sys>;
234 vcc7-supply = <&vcc3v3_sys>;
235 vcc8-supply = <&vcc3v3_sys>;
236 vcc9-supply = <&vcc3v3_sys>;
240 vdd_logic: DCDC_REG1 {
241 regulator-name = "vdd_logic";
244 regulator-min-microvolt = <500000>;
245 regulator-max-microvolt = <1350000>;
246 regulator-init-microvolt = <900000>;
247 regulator-ramp-delay = <6001>;
248 regulator-initial-mode = <0x2>;
250 regulator-state-mem {
251 regulator-off-in-suspend;
256 regulator-name = "vdd_gpu";
259 regulator-min-microvolt = <500000>;
260 regulator-max-microvolt = <1350000>;
261 regulator-init-microvolt = <900000>;
262 regulator-ramp-delay = <6001>;
263 regulator-initial-mode = <0x2>;
265 regulator-state-mem {
266 regulator-off-in-suspend;
271 regulator-name = "vcc_ddr";
274 regulator-initial-mode = <0x2>;
276 regulator-state-mem {
277 regulator-on-in-suspend;
282 regulator-name = "vdd_npu";
285 regulator-min-microvolt = <500000>;
286 regulator-max-microvolt = <1350000>;
287 regulator-init-microvolt = <900000>;
288 regulator-ramp-delay = <6001>;
289 regulator-initial-mode = <0x2>;
291 regulator-state-mem {
292 regulator-off-in-suspend;
297 regulator-name = "vcc_1v8";
300 regulator-min-microvolt = <1800000>;
301 regulator-max-microvolt = <1800000>;
303 regulator-state-mem {
304 regulator-off-in-suspend;
308 vdda0v9_image: LDO_REG1 {
309 regulator-name = "vdda0v9_image";
312 regulator-min-microvolt = <900000>;
313 regulator-max-microvolt = <900000>;
315 regulator-state-mem {
316 regulator-off-in-suspend;
321 regulator-name = "vdda_0v9";
324 regulator-min-microvolt = <900000>;
325 regulator-max-microvolt = <900000>;
327 regulator-state-mem {
328 regulator-off-in-suspend;
332 vdda0v9_pmu: LDO_REG3 {
333 regulator-name = "vdda0v9_pmu";
336 regulator-min-microvolt = <900000>;
337 regulator-max-microvolt = <900000>;
339 regulator-state-mem {
340 regulator-on-in-suspend;
341 regulator-suspend-microvolt = <900000>;
345 vccio_acodec: LDO_REG4 {
346 regulator-name = "vccio_acodec";
349 regulator-min-microvolt = <3300000>;
350 regulator-max-microvolt = <3300000>;
352 regulator-state-mem {
353 regulator-off-in-suspend;
358 regulator-name = "vccio_sd";
361 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <3300000>;
364 regulator-state-mem {
365 regulator-off-in-suspend;
369 vcc3v3_pmu: LDO_REG6 {
370 regulator-name = "vcc3v3_pmu";
373 regulator-min-microvolt = <3300000>;
374 regulator-max-microvolt = <3300000>;
376 regulator-state-mem {
377 regulator-on-in-suspend;
378 regulator-suspend-microvolt = <3300000>;
383 regulator-name = "vcca_1v8";
386 regulator-min-microvolt = <1800000>;
387 regulator-max-microvolt = <1800000>;
389 regulator-state-mem {
390 regulator-off-in-suspend;
394 vcca1v8_pmu: LDO_REG8 {
395 regulator-name = "vcca1v8_pmu";
398 regulator-min-microvolt = <1800000>;
399 regulator-max-microvolt = <1800000>;
401 regulator-state-mem {
402 regulator-on-in-suspend;
403 regulator-suspend-microvolt = <1800000>;
407 vcca1v8_image: LDO_REG9 {
408 regulator-name = "vcca1v8_image";
411 regulator-min-microvolt = <1800000>;
412 regulator-max-microvolt = <1800000>;
414 regulator-state-mem {
415 regulator-off-in-suspend;
419 vcc_3v3: SWITCH_REG1 {
420 regulator-name = "vcc_3v3";
424 regulator-state-mem {
425 regulator-off-in-suspend;
429 vcc3v3_sd: SWITCH_REG2 {
430 regulator-name = "vcc3v3_sd";
434 regulator-state-mem {
435 regulator-off-in-suspend;
443 rockchip,trcm-sync-tx-only;
449 clock_in_out = "output";
451 snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
452 snps,reset-active-low;
453 /* Reset time is 20ms, 100ms for rtl8211f */
454 snps,reset-delays-us = <0 20000 100000>;
456 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
457 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&gmac0_miim
469 phy-handle = <&rgmii_phy0>;
475 compatible = "ethernet-phy-ieee802.3-c22";
482 clock_in_out = "output";
484 snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
485 snps,reset-active-low;
486 /* Reset time is 20ms, 100ms for rtl8211f */
487 snps,reset-delays-us = <0 20000 100000>;
489 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
490 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&gmac1m1_miim
502 phy-handle = <&rgmii_phy1>;
508 compatible = "ethernet-phy-ieee802.3-c22";
514 mbi-ranges = <94 31>, <229 31>, <289 31>;
522 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
523 vpcie3v3-supply = <&vcc3v3_m2_pcie>;
528 reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
529 disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
530 vpcie3v3-supply = <&vcc3v3_mini_pcie>;
535 pmuio2-supply = <&vcc3v3_pmu>;
536 vccio1-supply = <&vccio_acodec>;
537 vccio3-supply = <&vccio_sd>;
538 vccio4-supply = <&vcc_1v8>;
539 vccio5-supply = <&vcc_3v3>;
540 vccio6-supply = <&vcc_1v8>;
541 vccio7-supply = <&vcc_3v3>;
562 pinctrl-0 = <&spi3m1_pins>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&uart3m1_xfer>;
577 vref-supply = <&vcca_1v8>;
582 rockchip,hw-tshut-mode = <1>;
583 rockchip,hw-tshut-polarity = <0>;
588 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
589 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
591 max-frequency = <200000000>;
594 pinctrl-names = "default";
595 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
601 max-frequency = <150000000>;
609 vmmc-supply = <&vcc3v3_sd>;
610 vqmmc-supply = <&vccio_sd>;
611 pinctrl-names = "default";
612 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
616 /* USB OTG/USB Host_1 USB 2.0 Comb */
622 phy-supply = <&vcc5v0_usb30_host>;
627 phy-supply = <&vcc5v0_otg_vbus>;
639 /* USB Host_2/USB Host_3 USB 2.0 Comb */
649 phy-supply = <&vcc5v0_usb20_host>;
661 /* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */
663 phys = <&usb2phy0_otg>;
664 phy-names = "usb2-phy";
665 extcon = <&usb2phy0>;
666 maximum-speed = "high-speed";
681 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
682 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
691 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
692 reg = <ROCKCHIP_VOP2_EP_HDMI0>;
693 remote-endpoint = <&hdmi_in_vp0>;
699 user_led_pin: user-status-led-pin {
700 rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
705 vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
706 rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
709 vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
710 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
713 vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en {
714 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
719 vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en {
720 rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
723 vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en {
724 rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
730 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;