arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3399-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3399-power.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "rockchip,rk3399";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 i2c6 = &i2c6;
  30                 i2c7 = &i2c7;
  31                 i2c8 = &i2c8;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37         };
  38
  39         cpus {
  40                 #address-cells = <2>;
  41                 #size-cells = <0>;
  42
  43                 cpu-map {
  44                         cluster0 {
  45                                 core0 {
  46                                         cpu = <&cpu_l0>;
  47                                 };
  48                                 core1 {
  49                                         cpu = <&cpu_l1>;
  50                                 };
  51                                 core2 {
  52                                         cpu = <&cpu_l2>;
  53                                 };
  54                                 core3 {
  55                                         cpu = <&cpu_l3>;
  56                                 };
  57                         };
  58
  59                         cluster1 {
  60                                 core0 {
  61                                         cpu = <&cpu_b0>;
  62                                 };
  63                                 core1 {
  64                                         cpu = <&cpu_b1>;
  65                                 };
  66                         };
  67                 };
  68
  69                 cpu_l0: cpu@0 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53";
  72                         reg = <0x0 0x0>;
  73                         enable-method = "psci";
  74                         capacity-dmips-mhz = <485>;
  75                         clocks = <&cru ARMCLKL>;
  76                         #cooling-cells = <2>; /* min followed by max */
  77                         dynamic-power-coefficient = <100>;
  78                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  79                 };
  80
  81                 cpu_l1: cpu@1 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a53";
  84                         reg = <0x0 0x1>;
  85                         enable-method = "psci";
  86                         capacity-dmips-mhz = <485>;
  87                         clocks = <&cru ARMCLKL>;
  88                         #cooling-cells = <2>; /* min followed by max */
  89                         dynamic-power-coefficient = <100>;
  90                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  91                 };
  92
  93                 cpu_l2: cpu@2 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53";
  96                         reg = <0x0 0x2>;
  97                         enable-method = "psci";
  98                         capacity-dmips-mhz = <485>;
  99                         clocks = <&cru ARMCLKL>;
 100                         #cooling-cells = <2>; /* min followed by max */
 101                         dynamic-power-coefficient = <100>;
 102                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 103                 };
 104
 105                 cpu_l3: cpu@3 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53";
 108                         reg = <0x0 0x3>;
 109                         enable-method = "psci";
 110                         capacity-dmips-mhz = <485>;
 111                         clocks = <&cru ARMCLKL>;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         dynamic-power-coefficient = <100>;
 114                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 115                 };
 116
 117                 cpu_b0: cpu@100 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a72";
 120                         reg = <0x0 0x100>;
 121                         enable-method = "psci";
 122                         capacity-dmips-mhz = <1024>;
 123                         clocks = <&cru ARMCLKB>;
 124                         #cooling-cells = <2>; /* min followed by max */
 125                         dynamic-power-coefficient = <436>;
 126                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 127
 128                         thermal-idle {
 129                                 #cooling-cells = <2>;
 130                                 duration-us = <10000>;
 131                                 exit-latency-us = <500>;
 132                         };
 133                 };
 134
 135                 cpu_b1: cpu@101 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a72";
 138                         reg = <0x0 0x101>;
 139                         enable-method = "psci";
 140                         capacity-dmips-mhz = <1024>;
 141                         clocks = <&cru ARMCLKB>;
 142                         #cooling-cells = <2>; /* min followed by max */
 143                         dynamic-power-coefficient = <436>;
 144                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 145
 146                         thermal-idle {
 147                                 #cooling-cells = <2>;
 148                                 duration-us = <10000>;
 149                                 exit-latency-us = <500>;
 150                         };
 151                 };
 152
 153                 idle-states {
 154                         entry-method = "psci";
 155
 156                         CPU_SLEEP: cpu-sleep {
 157                                 compatible = "arm,idle-state";
 158                                 local-timer-stop;
 159                                 arm,psci-suspend-param = <0x0010000>;
 160                                 entry-latency-us = <120>;
 161                                 exit-latency-us = <250>;
 162                                 min-residency-us = <900>;
 163                         };
 164
 165                         CLUSTER_SLEEP: cluster-sleep {
 166                                 compatible = "arm,idle-state";
 167                                 local-timer-stop;
 168                                 arm,psci-suspend-param = <0x1010000>;
 169                                 entry-latency-us = <400>;
 170                                 exit-latency-us = <500>;
 171                                 min-residency-us = <2000>;
 172                         };
 173                 };
 174         };
 175
 176         display-subsystem {
 177                 compatible = "rockchip,display-subsystem";
 178                 ports = <&vopl_out>, <&vopb_out>;
 179         };
 180
 181         dmc: memory-controller {
 182                 compatible = "rockchip,rk3399-dmc";
 183                 rockchip,pmu = <&pmugrf>;
 184                 devfreq-events = <&dfi>;
 185                 clocks = <&cru SCLK_DDRC>;
 186                 clock-names = "dmc_clk";
 187                 status = "disabled";
 188         };
 189
 190         pmu_a53 {
 191                 compatible = "arm,cortex-a53-pmu";
 192                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 193         };
 194
 195         pmu_a72 {
 196                 compatible = "arm,cortex-a72-pmu";
 197                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 198         };
 199
 200         psci {
 201                 compatible = "arm,psci-1.0";
 202                 method = "smc";
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv8-timer";
 207                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 208                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 209                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 210                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 211                 arm,no-tick-in-suspend;
 212         };
 213
 214         xin24m: xin24m {
 215                 compatible = "fixed-clock";
 216                 clock-frequency = <24000000>;
 217                 clock-output-names = "xin24m";
 218                 #clock-cells = <0>;
 219         };
 220
 221         pcie0: pcie@f8000000 {
 222                 compatible = "rockchip,rk3399-pcie";
 223                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 224                       <0x0 0xfd000000 0x0 0x1000000>;
 225                 reg-names = "axi-base", "apb-base";
 226                 device_type = "pci";
 227                 #address-cells = <3>;
 228                 #size-cells = <2>;
 229                 #interrupt-cells = <1>;
 230                 aspm-no-l0s;
 231                 bus-range = <0x0 0x1f>;
 232                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 233                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 234                 clock-names = "aclk", "aclk-perf",
 235                               "hclk", "pm";
 236                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 237                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 238                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 239                 interrupt-names = "sys", "legacy", "client";
 240                 interrupt-map-mask = <0 0 0 7>;
 241                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 242                                 <0 0 0 2 &pcie0_intc 1>,
 243                                 <0 0 0 3 &pcie0_intc 2>,
 244                                 <0 0 0 4 &pcie0_intc 3>;
 245                 max-link-speed = <1>;
 246                 msi-map = <0x0 &its 0x0 0x1000>;
 247                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
 248                        <&pcie_phy 2>, <&pcie_phy 3>;
 249                 phy-names = "pcie-phy-0", "pcie-phy-1",
 250                             "pcie-phy-2", "pcie-phy-3";
 251                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
 252                          <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
 253                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 254                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 255                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 256                          <&cru SRST_A_PCIE>;
 257                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 258                               "pm", "pclk", "aclk";
 259                 status = "disabled";
 260
 261                 pcie0_intc: interrupt-controller {
 262                         interrupt-controller;
 263                         #address-cells = <0>;
 264                         #interrupt-cells = <1>;
 265                 };
 266         };
 267
 268         gmac: ethernet@fe300000 {
 269                 compatible = "rockchip,rk3399-gmac";
 270                 reg = <0x0 0xfe300000 0x0 0x10000>;
 271                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 272                 interrupt-names = "macirq";
 273                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 274                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 275                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 276                          <&cru PCLK_GMAC>;
 277                 clock-names = "stmmaceth", "mac_clk_rx",
 278                               "mac_clk_tx", "clk_mac_ref",
 279                               "clk_mac_refout", "aclk_mac",
 280                               "pclk_mac";
 281                 power-domains = <&power RK3399_PD_GMAC>;
 282                 resets = <&cru SRST_A_GMAC>;
 283                 reset-names = "stmmaceth";
 284                 rockchip,grf = <&grf>;
 285                 snps,txpbl = <0x4>;
 286                 status = "disabled";
 287         };
 288
 289         sdio0: mmc@fe310000 {
 290                 compatible = "rockchip,rk3399-dw-mshc",
 291                              "rockchip,rk3288-dw-mshc";
 292                 reg = <0x0 0xfe310000 0x0 0x4000>;
 293                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 294                 max-frequency = <150000000>;
 295                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 296                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 297                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 298                 fifo-depth = <0x100>;
 299                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 300                 resets = <&cru SRST_SDIO0>;
 301                 reset-names = "reset";
 302                 status = "disabled";
 303         };
 304
 305         sdmmc: mmc@fe320000 {
 306                 compatible = "rockchip,rk3399-dw-mshc",
 307                              "rockchip,rk3288-dw-mshc";
 308                 reg = <0x0 0xfe320000 0x0 0x4000>;
 309                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 310                 max-frequency = <150000000>;
 311                 assigned-clocks = <&cru HCLK_SD>;
 312                 assigned-clock-rates = <200000000>;
 313                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 314                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 315                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 316                 fifo-depth = <0x100>;
 317                 power-domains = <&power RK3399_PD_SD>;
 318                 resets = <&cru SRST_SDMMC>;
 319                 reset-names = "reset";
 320                 status = "disabled";
 321         };
 322
 323         sdhci: mmc@fe330000 {
 324                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 325                 reg = <0x0 0xfe330000 0x0 0x10000>;
 326                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 327                 arasan,soc-ctl-syscon = <&grf>;
 328                 assigned-clocks = <&cru SCLK_EMMC>;
 329                 assigned-clock-rates = <200000000>;
 330                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 331                 clock-names = "clk_xin", "clk_ahb";
 332                 clock-output-names = "emmc_cardclock";
 333                 #clock-cells = <0>;
 334                 phys = <&emmc_phy>;
 335                 phy-names = "phy_arasan";
 336                 power-domains = <&power RK3399_PD_EMMC>;
 337                 disable-cqe-dcmd;
 338                 status = "disabled";
 339         };
 340
 341         usb_host0_ehci: usb@fe380000 {
 342                 compatible = "generic-ehci";
 343                 reg = <0x0 0xfe380000 0x0 0x20000>;
 344                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 345                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 346                          <&u2phy0>;
 347                 phys = <&u2phy0_host>;
 348                 phy-names = "usb";
 349                 status = "disabled";
 350         };
 351
 352         usb_host0_ohci: usb@fe3a0000 {
 353                 compatible = "generic-ohci";
 354                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 355                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 356                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 357                          <&u2phy0>;
 358                 phys = <&u2phy0_host>;
 359                 phy-names = "usb";
 360                 status = "disabled";
 361         };
 362
 363         usb_host1_ehci: usb@fe3c0000 {
 364                 compatible = "generic-ehci";
 365                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 366                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 367                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 368                          <&u2phy1>;
 369                 phys = <&u2phy1_host>;
 370                 phy-names = "usb";
 371                 status = "disabled";
 372         };
 373
 374         usb_host1_ohci: usb@fe3e0000 {
 375                 compatible = "generic-ohci";
 376                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 377                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 378                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 379                          <&u2phy1>;
 380                 phys = <&u2phy1_host>;
 381                 phy-names = "usb";
 382                 status = "disabled";
 383         };
 384
 385         debug@fe430000 {
 386                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 387                 reg = <0 0xfe430000 0 0x1000>;
 388                 clocks = <&cru PCLK_COREDBG_L>;
 389                 clock-names = "apb_pclk";
 390                 cpu = <&cpu_l0>;
 391         };
 392
 393         debug@fe432000 {
 394                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 395                 reg = <0 0xfe432000 0 0x1000>;
 396                 clocks = <&cru PCLK_COREDBG_L>;
 397                 clock-names = "apb_pclk";
 398                 cpu = <&cpu_l1>;
 399         };
 400
 401         debug@fe434000 {
 402                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 403                 reg = <0 0xfe434000 0 0x1000>;
 404                 clocks = <&cru PCLK_COREDBG_L>;
 405                 clock-names = "apb_pclk";
 406                 cpu = <&cpu_l2>;
 407         };
 408
 409         debug@fe436000 {
 410                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 411                 reg = <0 0xfe436000 0 0x1000>;
 412                 clocks = <&cru PCLK_COREDBG_L>;
 413                 clock-names = "apb_pclk";
 414                 cpu = <&cpu_l3>;
 415         };
 416
 417         debug@fe610000 {
 418                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 419                 reg = <0 0xfe610000 0 0x1000>;
 420                 clocks = <&cru PCLK_COREDBG_B>;
 421                 clock-names = "apb_pclk";
 422                 cpu = <&cpu_b0>;
 423         };
 424
 425         debug@fe710000 {
 426                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 427                 reg = <0 0xfe710000 0 0x1000>;
 428                 clocks = <&cru PCLK_COREDBG_B>;
 429                 clock-names = "apb_pclk";
 430                 cpu = <&cpu_b1>;
 431         };
 432
 433         usbdrd3_0: usb@fe800000 {
 434                 compatible = "rockchip,rk3399-dwc3";
 435                 #address-cells = <2>;
 436                 #size-cells = <2>;
 437                 ranges;
 438                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 439                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 440                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 441                 clock-names = "ref_clk", "suspend_clk",
 442                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 443                               "aclk_usb3", "grf_clk";
 444                 resets = <&cru SRST_A_USB3_OTG0>;
 445                 reset-names = "usb3-otg";
 446                 status = "disabled";
 447
 448                 usbdrd_dwc3_0: usb@fe800000 {
 449                         compatible = "snps,dwc3";
 450                         reg = <0x0 0xfe800000 0x0 0x100000>;
 451                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 452                         clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
 453                                  <&cru SCLK_USB3OTG0_SUSPEND>;
 454                         clock-names = "ref", "bus_early", "suspend";
 455                         dr_mode = "otg";
 456                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 457                         phy-names = "usb2-phy", "usb3-phy";
 458                         phy_type = "utmi_wide";
 459                         snps,dis_enblslpm_quirk;
 460                         snps,dis-u2-freeclk-exists-quirk;
 461                         snps,dis_u2_susphy_quirk;
 462                         snps,dis-del-phy-power-chg-quirk;
 463                         snps,dis-tx-ipgap-linecheck-quirk;
 464                         power-domains = <&power RK3399_PD_USB3>;
 465                         status = "disabled";
 466                 };
 467         };
 468
 469         usbdrd3_1: usb@fe900000 {
 470                 compatible = "rockchip,rk3399-dwc3";
 471                 #address-cells = <2>;
 472                 #size-cells = <2>;
 473                 ranges;
 474                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 475                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 476                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 477                 clock-names = "ref_clk", "suspend_clk",
 478                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 479                               "aclk_usb3", "grf_clk";
 480                 resets = <&cru SRST_A_USB3_OTG1>;
 481                 reset-names = "usb3-otg";
 482                 status = "disabled";
 483
 484                 usbdrd_dwc3_1: usb@fe900000 {
 485                         compatible = "snps,dwc3";
 486                         reg = <0x0 0xfe900000 0x0 0x100000>;
 487                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 488                         clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
 489                                  <&cru SCLK_USB3OTG1_SUSPEND>;
 490                         clock-names = "ref", "bus_early", "suspend";
 491                         dr_mode = "otg";
 492                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 493                         phy-names = "usb2-phy", "usb3-phy";
 494                         phy_type = "utmi_wide";
 495                         snps,dis_enblslpm_quirk;
 496                         snps,dis-u2-freeclk-exists-quirk;
 497                         snps,dis_u2_susphy_quirk;
 498                         snps,dis-del-phy-power-chg-quirk;
 499                         snps,dis-tx-ipgap-linecheck-quirk;
 500                         power-domains = <&power RK3399_PD_USB3>;
 501                         status = "disabled";
 502                 };
 503         };
 504
 505         cdn_dp: dp@fec00000 {
 506                 compatible = "rockchip,rk3399-cdn-dp";
 507                 reg = <0x0 0xfec00000 0x0 0x100000>;
 508                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 509                 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
 510                 assigned-clock-rates = <100000000>, <200000000>;
 511                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 512                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 513                 clock-names = "core-clk", "pclk", "spdif", "grf";
 514                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 515                 power-domains = <&power RK3399_PD_HDCP>;
 516                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 517                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 518                 reset-names = "spdif", "dptx", "apb", "core";
 519                 rockchip,grf = <&grf>;
 520                 #sound-dai-cells = <1>;
 521                 status = "disabled";
 522
 523                 ports {
 524                         dp_in: port {
 525                                 #address-cells = <1>;
 526                                 #size-cells = <0>;
 527
 528                                 dp_in_vopb: endpoint@0 {
 529                                         reg = <0>;
 530                                         remote-endpoint = <&vopb_out_dp>;
 531                                 };
 532
 533                                 dp_in_vopl: endpoint@1 {
 534                                         reg = <1>;
 535                                         remote-endpoint = <&vopl_out_dp>;
 536                                 };
 537                         };
 538                 };
 539         };
 540
 541         gic: interrupt-controller@fee00000 {
 542                 compatible = "arm,gic-v3";
 543                 #interrupt-cells = <4>;
 544                 #address-cells = <2>;
 545                 #size-cells = <2>;
 546                 ranges;
 547                 interrupt-controller;
 548
 549                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 550                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 551                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 552                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 553                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 554                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 555                 its: interrupt-controller@fee20000 {
 556                         compatible = "arm,gic-v3-its";
 557                         msi-controller;
 558                         #msi-cells = <1>;
 559                         reg = <0x0 0xfee20000 0x0 0x20000>;
 560                 };
 561
 562                 ppi-partitions {
 563                         ppi_cluster0: interrupt-partition-0 {
 564                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 565                         };
 566
 567                         ppi_cluster1: interrupt-partition-1 {
 568                                 affinity = <&cpu_b0 &cpu_b1>;
 569                         };
 570                 };
 571         };
 572
 573         saradc: saradc@ff100000 {
 574                 compatible = "rockchip,rk3399-saradc";
 575                 reg = <0x0 0xff100000 0x0 0x100>;
 576                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 577                 #io-channel-cells = <1>;
 578                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 579                 clock-names = "saradc", "apb_pclk";
 580                 resets = <&cru SRST_P_SARADC>;
 581                 reset-names = "saradc-apb";
 582                 status = "disabled";
 583         };
 584
 585         i2c1: i2c@ff110000 {
 586                 compatible = "rockchip,rk3399-i2c";
 587                 reg = <0x0 0xff110000 0x0 0x1000>;
 588                 assigned-clocks = <&cru SCLK_I2C1>;
 589                 assigned-clock-rates = <200000000>;
 590                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 591                 clock-names = "i2c", "pclk";
 592                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 593                 pinctrl-names = "default";
 594                 pinctrl-0 = <&i2c1_xfer>;
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 status = "disabled";
 598         };
 599
 600         i2c2: i2c@ff120000 {
 601                 compatible = "rockchip,rk3399-i2c";
 602                 reg = <0x0 0xff120000 0x0 0x1000>;
 603                 assigned-clocks = <&cru SCLK_I2C2>;
 604                 assigned-clock-rates = <200000000>;
 605                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 606                 clock-names = "i2c", "pclk";
 607                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 608                 pinctrl-names = "default";
 609                 pinctrl-0 = <&i2c2_xfer>;
 610                 #address-cells = <1>;
 611                 #size-cells = <0>;
 612                 status = "disabled";
 613         };
 614
 615         i2c3: i2c@ff130000 {
 616                 compatible = "rockchip,rk3399-i2c";
 617                 reg = <0x0 0xff130000 0x0 0x1000>;
 618                 assigned-clocks = <&cru SCLK_I2C3>;
 619                 assigned-clock-rates = <200000000>;
 620                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 621                 clock-names = "i2c", "pclk";
 622                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 623                 pinctrl-names = "default";
 624                 pinctrl-0 = <&i2c3_xfer>;
 625                 #address-cells = <1>;
 626                 #size-cells = <0>;
 627                 status = "disabled";
 628         };
 629
 630         i2c5: i2c@ff140000 {
 631                 compatible = "rockchip,rk3399-i2c";
 632                 reg = <0x0 0xff140000 0x0 0x1000>;
 633                 assigned-clocks = <&cru SCLK_I2C5>;
 634                 assigned-clock-rates = <200000000>;
 635                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 636                 clock-names = "i2c", "pclk";
 637                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 638                 pinctrl-names = "default";
 639                 pinctrl-0 = <&i2c5_xfer>;
 640                 #address-cells = <1>;
 641                 #size-cells = <0>;
 642                 status = "disabled";
 643         };
 644
 645         i2c6: i2c@ff150000 {
 646                 compatible = "rockchip,rk3399-i2c";
 647                 reg = <0x0 0xff150000 0x0 0x1000>;
 648                 assigned-clocks = <&cru SCLK_I2C6>;
 649                 assigned-clock-rates = <200000000>;
 650                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 651                 clock-names = "i2c", "pclk";
 652                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 653                 pinctrl-names = "default";
 654                 pinctrl-0 = <&i2c6_xfer>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 status = "disabled";
 658         };
 659
 660         i2c7: i2c@ff160000 {
 661                 compatible = "rockchip,rk3399-i2c";
 662                 reg = <0x0 0xff160000 0x0 0x1000>;
 663                 assigned-clocks = <&cru SCLK_I2C7>;
 664                 assigned-clock-rates = <200000000>;
 665                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 666                 clock-names = "i2c", "pclk";
 667                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 668                 pinctrl-names = "default";
 669                 pinctrl-0 = <&i2c7_xfer>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 status = "disabled";
 673         };
 674
 675         uart0: serial@ff180000 {
 676                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 677                 reg = <0x0 0xff180000 0x0 0x100>;
 678                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 679                 clock-names = "baudclk", "apb_pclk";
 680                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 681                 reg-shift = <2>;
 682                 reg-io-width = <4>;
 683                 pinctrl-names = "default";
 684                 pinctrl-0 = <&uart0_xfer>;
 685                 status = "disabled";
 686         };
 687
 688         uart1: serial@ff190000 {
 689                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 690                 reg = <0x0 0xff190000 0x0 0x100>;
 691                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 692                 clock-names = "baudclk", "apb_pclk";
 693                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 694                 reg-shift = <2>;
 695                 reg-io-width = <4>;
 696                 pinctrl-names = "default";
 697                 pinctrl-0 = <&uart1_xfer>;
 698                 status = "disabled";
 699         };
 700
 701         uart2: serial@ff1a0000 {
 702                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 703                 reg = <0x0 0xff1a0000 0x0 0x100>;
 704                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 705                 clock-names = "baudclk", "apb_pclk";
 706                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 707                 reg-shift = <2>;
 708                 reg-io-width = <4>;
 709                 pinctrl-names = "default";
 710                 pinctrl-0 = <&uart2c_xfer>;
 711                 status = "disabled";
 712         };
 713
 714         uart3: serial@ff1b0000 {
 715                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 716                 reg = <0x0 0xff1b0000 0x0 0x100>;
 717                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 718                 clock-names = "baudclk", "apb_pclk";
 719                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 720                 reg-shift = <2>;
 721                 reg-io-width = <4>;
 722                 pinctrl-names = "default";
 723                 pinctrl-0 = <&uart3_xfer>;
 724                 status = "disabled";
 725         };
 726
 727         spi0: spi@ff1c0000 {
 728                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 729                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 730                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 731                 clock-names = "spiclk", "apb_pclk";
 732                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 733                 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
 734                 dma-names = "tx", "rx";
 735                 pinctrl-names = "default";
 736                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 737                 #address-cells = <1>;
 738                 #size-cells = <0>;
 739                 status = "disabled";
 740         };
 741
 742         spi1: spi@ff1d0000 {
 743                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 744                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 745                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 746                 clock-names = "spiclk", "apb_pclk";
 747                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 748                 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
 749                 dma-names = "tx", "rx";
 750                 pinctrl-names = "default";
 751                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 752                 #address-cells = <1>;
 753                 #size-cells = <0>;
 754                 status = "disabled";
 755         };
 756
 757         spi2: spi@ff1e0000 {
 758                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 759                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 760                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 761                 clock-names = "spiclk", "apb_pclk";
 762                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 763                 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
 764                 dma-names = "tx", "rx";
 765                 pinctrl-names = "default";
 766                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 767                 #address-cells = <1>;
 768                 #size-cells = <0>;
 769                 status = "disabled";
 770         };
 771
 772         spi4: spi@ff1f0000 {
 773                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 774                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 775                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 776                 clock-names = "spiclk", "apb_pclk";
 777                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 778                 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
 779                 dma-names = "tx", "rx";
 780                 pinctrl-names = "default";
 781                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 782                 #address-cells = <1>;
 783                 #size-cells = <0>;
 784                 status = "disabled";
 785         };
 786
 787         spi5: spi@ff200000 {
 788                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 789                 reg = <0x0 0xff200000 0x0 0x1000>;
 790                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 791                 clock-names = "spiclk", "apb_pclk";
 792                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 793                 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
 794                 dma-names = "tx", "rx";
 795                 pinctrl-names = "default";
 796                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 797                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 798                 #address-cells = <1>;
 799                 #size-cells = <0>;
 800                 status = "disabled";
 801         };
 802
 803         thermal_zones: thermal-zones {
 804                 cpu_thermal: cpu-thermal {
 805                         polling-delay-passive = <100>;
 806                         polling-delay = <1000>;
 807
 808                         thermal-sensors = <&tsadc 0>;
 809
 810                         trips {
 811                                 cpu_alert0: cpu_alert0 {
 812                                         temperature = <70000>;
 813                                         hysteresis = <2000>;
 814                                         type = "passive";
 815                                 };
 816                                 cpu_alert1: cpu_alert1 {
 817                                         temperature = <75000>;
 818                                         hysteresis = <2000>;
 819                                         type = "passive";
 820                                 };
 821                                 cpu_crit: cpu_crit {
 822                                         temperature = <95000>;
 823                                         hysteresis = <2000>;
 824                                         type = "critical";
 825                                 };
 826                         };
 827
 828                         cooling-maps {
 829                                 map0 {
 830                                         trip = <&cpu_alert0>;
 831                                         cooling-device =
 832                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 833                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 834                                 };
 835                                 map1 {
 836                                         trip = <&cpu_alert1>;
 837                                         cooling-device =
 838                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 839                                                 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 840                                                 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 841                                                 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 842                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 843                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 844                                 };
 845                         };
 846                 };
 847
 848                 gpu_thermal: gpu-thermal {
 849                         polling-delay-passive = <100>;
 850                         polling-delay = <1000>;
 851
 852                         thermal-sensors = <&tsadc 1>;
 853
 854                         trips {
 855                                 gpu_alert0: gpu_alert0 {
 856                                         temperature = <75000>;
 857                                         hysteresis = <2000>;
 858                                         type = "passive";
 859                                 };
 860                                 gpu_crit: gpu_crit {
 861                                         temperature = <95000>;
 862                                         hysteresis = <2000>;
 863                                         type = "critical";
 864                                 };
 865                         };
 866
 867                         cooling-maps {
 868                                 map0 {
 869                                         trip = <&gpu_alert0>;
 870                                         cooling-device =
 871                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 872                                 };
 873                         };
 874                 };
 875         };
 876
 877         tsadc: tsadc@ff260000 {
 878                 compatible = "rockchip,rk3399-tsadc";
 879                 reg = <0x0 0xff260000 0x0 0x100>;
 880                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 881                 assigned-clocks = <&cru SCLK_TSADC>;
 882                 assigned-clock-rates = <750000>;
 883                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 884                 clock-names = "tsadc", "apb_pclk";
 885                 resets = <&cru SRST_TSADC>;
 886                 reset-names = "tsadc-apb";
 887                 rockchip,grf = <&grf>;
 888                 rockchip,hw-tshut-temp = <95000>;
 889                 pinctrl-names = "init", "default", "sleep";
 890                 pinctrl-0 = <&otp_pin>;
 891                 pinctrl-1 = <&otp_out>;
 892                 pinctrl-2 = <&otp_pin>;
 893                 #thermal-sensor-cells = <1>;
 894                 status = "disabled";
 895         };
 896
 897         qos_emmc: qos@ffa58000 {
 898                 compatible = "rockchip,rk3399-qos", "syscon";
 899                 reg = <0x0 0xffa58000 0x0 0x20>;
 900         };
 901
 902         qos_gmac: qos@ffa5c000 {
 903                 compatible = "rockchip,rk3399-qos", "syscon";
 904                 reg = <0x0 0xffa5c000 0x0 0x20>;
 905         };
 906
 907         qos_pcie: qos@ffa60080 {
 908                 compatible = "rockchip,rk3399-qos", "syscon";
 909                 reg = <0x0 0xffa60080 0x0 0x20>;
 910         };
 911
 912         qos_usb_host0: qos@ffa60100 {
 913                 compatible = "rockchip,rk3399-qos", "syscon";
 914                 reg = <0x0 0xffa60100 0x0 0x20>;
 915         };
 916
 917         qos_usb_host1: qos@ffa60180 {
 918                 compatible = "rockchip,rk3399-qos", "syscon";
 919                 reg = <0x0 0xffa60180 0x0 0x20>;
 920         };
 921
 922         qos_usb_otg0: qos@ffa70000 {
 923                 compatible = "rockchip,rk3399-qos", "syscon";
 924                 reg = <0x0 0xffa70000 0x0 0x20>;
 925         };
 926
 927         qos_usb_otg1: qos@ffa70080 {
 928                 compatible = "rockchip,rk3399-qos", "syscon";
 929                 reg = <0x0 0xffa70080 0x0 0x20>;
 930         };
 931
 932         qos_sd: qos@ffa74000 {
 933                 compatible = "rockchip,rk3399-qos", "syscon";
 934                 reg = <0x0 0xffa74000 0x0 0x20>;
 935         };
 936
 937         qos_sdioaudio: qos@ffa76000 {
 938                 compatible = "rockchip,rk3399-qos", "syscon";
 939                 reg = <0x0 0xffa76000 0x0 0x20>;
 940         };
 941
 942         qos_hdcp: qos@ffa90000 {
 943                 compatible = "rockchip,rk3399-qos", "syscon";
 944                 reg = <0x0 0xffa90000 0x0 0x20>;
 945         };
 946
 947         qos_iep: qos@ffa98000 {
 948                 compatible = "rockchip,rk3399-qos", "syscon";
 949                 reg = <0x0 0xffa98000 0x0 0x20>;
 950         };
 951
 952         qos_isp0_m0: qos@ffaa0000 {
 953                 compatible = "rockchip,rk3399-qos", "syscon";
 954                 reg = <0x0 0xffaa0000 0x0 0x20>;
 955         };
 956
 957         qos_isp0_m1: qos@ffaa0080 {
 958                 compatible = "rockchip,rk3399-qos", "syscon";
 959                 reg = <0x0 0xffaa0080 0x0 0x20>;
 960         };
 961
 962         qos_isp1_m0: qos@ffaa8000 {
 963                 compatible = "rockchip,rk3399-qos", "syscon";
 964                 reg = <0x0 0xffaa8000 0x0 0x20>;
 965         };
 966
 967         qos_isp1_m1: qos@ffaa8080 {
 968                 compatible = "rockchip,rk3399-qos", "syscon";
 969                 reg = <0x0 0xffaa8080 0x0 0x20>;
 970         };
 971
 972         qos_rga_r: qos@ffab0000 {
 973                 compatible = "rockchip,rk3399-qos", "syscon";
 974                 reg = <0x0 0xffab0000 0x0 0x20>;
 975         };
 976
 977         qos_rga_w: qos@ffab0080 {
 978                 compatible = "rockchip,rk3399-qos", "syscon";
 979                 reg = <0x0 0xffab0080 0x0 0x20>;
 980         };
 981
 982         qos_video_m0: qos@ffab8000 {
 983                 compatible = "rockchip,rk3399-qos", "syscon";
 984                 reg = <0x0 0xffab8000 0x0 0x20>;
 985         };
 986
 987         qos_video_m1_r: qos@ffac0000 {
 988                 compatible = "rockchip,rk3399-qos", "syscon";
 989                 reg = <0x0 0xffac0000 0x0 0x20>;
 990         };
 991
 992         qos_video_m1_w: qos@ffac0080 {
 993                 compatible = "rockchip,rk3399-qos", "syscon";
 994                 reg = <0x0 0xffac0080 0x0 0x20>;
 995         };
 996
 997         qos_vop_big_r: qos@ffac8000 {
 998                 compatible = "rockchip,rk3399-qos", "syscon";
 999                 reg = <0x0 0xffac8000 0x0 0x20>;
1000         };
1001
1002         qos_vop_big_w: qos@ffac8080 {
1003                 compatible = "rockchip,rk3399-qos", "syscon";
1004                 reg = <0x0 0xffac8080 0x0 0x20>;
1005         };
1006
1007         qos_vop_little: qos@ffad0000 {
1008                 compatible = "rockchip,rk3399-qos", "syscon";
1009                 reg = <0x0 0xffad0000 0x0 0x20>;
1010         };
1011
1012         qos_perihp: qos@ffad8080 {
1013                 compatible = "rockchip,rk3399-qos", "syscon";
1014                 reg = <0x0 0xffad8080 0x0 0x20>;
1015         };
1016
1017         qos_gpu: qos@ffae0000 {
1018                 compatible = "rockchip,rk3399-qos", "syscon";
1019                 reg = <0x0 0xffae0000 0x0 0x20>;
1020         };
1021
1022         pmu: power-management@ff310000 {
1023                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
1024                 reg = <0x0 0xff310000 0x0 0x1000>;
1025
1026                 /*
1027                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
1028                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
1029                  * Some of the power domains are grouped together for every
1030                  * voltage domain.
1031                  * The detail contents as below.
1032                  */
1033                 power: power-controller {
1034                         compatible = "rockchip,rk3399-power-controller";
1035                         #power-domain-cells = <1>;
1036                         #address-cells = <1>;
1037                         #size-cells = <0>;
1038
1039                         /* These power domains are grouped by VD_CENTER */
1040                         power-domain@RK3399_PD_IEP {
1041                                 reg = <RK3399_PD_IEP>;
1042                                 clocks = <&cru ACLK_IEP>,
1043                                          <&cru HCLK_IEP>;
1044                                 pm_qos = <&qos_iep>;
1045                                 #power-domain-cells = <0>;
1046                         };
1047                         power-domain@RK3399_PD_RGA {
1048                                 reg = <RK3399_PD_RGA>;
1049                                 clocks = <&cru ACLK_RGA>,
1050                                          <&cru HCLK_RGA>;
1051                                 pm_qos = <&qos_rga_r>,
1052                                          <&qos_rga_w>;
1053                                 #power-domain-cells = <0>;
1054                         };
1055                         power-domain@RK3399_PD_VCODEC {
1056                                 reg = <RK3399_PD_VCODEC>;
1057                                 clocks = <&cru ACLK_VCODEC>,
1058                                          <&cru HCLK_VCODEC>;
1059                                 pm_qos = <&qos_video_m0>;
1060                                 #power-domain-cells = <0>;
1061                         };
1062                         power-domain@RK3399_PD_VDU {
1063                                 reg = <RK3399_PD_VDU>;
1064                                 clocks = <&cru ACLK_VDU>,
1065                                          <&cru HCLK_VDU>;
1066                                 pm_qos = <&qos_video_m1_r>,
1067                                          <&qos_video_m1_w>;
1068                                 #power-domain-cells = <0>;
1069                         };
1070
1071                         /* These power domains are grouped by VD_GPU */
1072                         power-domain@RK3399_PD_GPU {
1073                                 reg = <RK3399_PD_GPU>;
1074                                 clocks = <&cru ACLK_GPU>;
1075                                 pm_qos = <&qos_gpu>;
1076                                 #power-domain-cells = <0>;
1077                         };
1078
1079                         /* These power domains are grouped by VD_LOGIC */
1080                         power-domain@RK3399_PD_EDP {
1081                                 reg = <RK3399_PD_EDP>;
1082                                 clocks = <&cru PCLK_EDP_CTRL>;
1083                                 #power-domain-cells = <0>;
1084                         };
1085                         power-domain@RK3399_PD_EMMC {
1086                                 reg = <RK3399_PD_EMMC>;
1087                                 clocks = <&cru ACLK_EMMC>;
1088                                 pm_qos = <&qos_emmc>;
1089                                 #power-domain-cells = <0>;
1090                         };
1091                         power-domain@RK3399_PD_GMAC {
1092                                 reg = <RK3399_PD_GMAC>;
1093                                 clocks = <&cru ACLK_GMAC>,
1094                                          <&cru PCLK_GMAC>;
1095                                 pm_qos = <&qos_gmac>;
1096                                 #power-domain-cells = <0>;
1097                         };
1098                         power-domain@RK3399_PD_SD {
1099                                 reg = <RK3399_PD_SD>;
1100                                 clocks = <&cru HCLK_SDMMC>,
1101                                          <&cru SCLK_SDMMC>;
1102                                 pm_qos = <&qos_sd>;
1103                                 #power-domain-cells = <0>;
1104                         };
1105                         power-domain@RK3399_PD_SDIOAUDIO {
1106                                 reg = <RK3399_PD_SDIOAUDIO>;
1107                                 clocks = <&cru HCLK_SDIO>;
1108                                 pm_qos = <&qos_sdioaudio>;
1109                                 #power-domain-cells = <0>;
1110                         };
1111                         power-domain@RK3399_PD_TCPD0 {
1112                                 reg = <RK3399_PD_TCPD0>;
1113                                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1114                                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1115                                 #power-domain-cells = <0>;
1116                         };
1117                         power-domain@RK3399_PD_TCPD1 {
1118                                 reg = <RK3399_PD_TCPD1>;
1119                                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1120                                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1121                                 #power-domain-cells = <0>;
1122                         };
1123                         power-domain@RK3399_PD_USB3 {
1124                                 reg = <RK3399_PD_USB3>;
1125                                 clocks = <&cru ACLK_USB3>;
1126                                 pm_qos = <&qos_usb_otg0>,
1127                                          <&qos_usb_otg1>;
1128                                 #power-domain-cells = <0>;
1129                         };
1130                         power-domain@RK3399_PD_VIO {
1131                                 reg = <RK3399_PD_VIO>;
1132                                 #power-domain-cells = <1>;
1133                                 #address-cells = <1>;
1134                                 #size-cells = <0>;
1135
1136                                 power-domain@RK3399_PD_HDCP {
1137                                         reg = <RK3399_PD_HDCP>;
1138                                         clocks = <&cru ACLK_HDCP>,
1139                                                  <&cru HCLK_HDCP>,
1140                                                  <&cru PCLK_HDCP>;
1141                                         pm_qos = <&qos_hdcp>;
1142                                         #power-domain-cells = <0>;
1143                                 };
1144                                 power-domain@RK3399_PD_ISP0 {
1145                                         reg = <RK3399_PD_ISP0>;
1146                                         clocks = <&cru ACLK_ISP0>,
1147                                                  <&cru HCLK_ISP0>;
1148                                         pm_qos = <&qos_isp0_m0>,
1149                                                  <&qos_isp0_m1>;
1150                                         #power-domain-cells = <0>;
1151                                 };
1152                                 power-domain@RK3399_PD_ISP1 {
1153                                         reg = <RK3399_PD_ISP1>;
1154                                         clocks = <&cru ACLK_ISP1>,
1155                                                  <&cru HCLK_ISP1>;
1156                                         pm_qos = <&qos_isp1_m0>,
1157                                                  <&qos_isp1_m1>;
1158                                         #power-domain-cells = <0>;
1159                                 };
1160                                 power-domain@RK3399_PD_VO {
1161                                         reg = <RK3399_PD_VO>;
1162                                         #power-domain-cells = <1>;
1163                                         #address-cells = <1>;
1164                                         #size-cells = <0>;
1165
1166                                         power-domain@RK3399_PD_VOPB {
1167                                                 reg = <RK3399_PD_VOPB>;
1168                                                 clocks = <&cru ACLK_VOP0>,
1169                                                          <&cru HCLK_VOP0>;
1170                                                 pm_qos = <&qos_vop_big_r>,
1171                                                          <&qos_vop_big_w>;
1172                                                 #power-domain-cells = <0>;
1173                                         };
1174                                         power-domain@RK3399_PD_VOPL {
1175                                                 reg = <RK3399_PD_VOPL>;
1176                                                 clocks = <&cru ACLK_VOP1>,
1177                                                          <&cru HCLK_VOP1>;
1178                                                 pm_qos = <&qos_vop_little>;
1179                                                 #power-domain-cells = <0>;
1180                                         };
1181                                 };
1182                         };
1183                 };
1184         };
1185
1186         pmugrf: syscon@ff320000 {
1187                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1188                 reg = <0x0 0xff320000 0x0 0x1000>;
1189
1190                 pmu_io_domains: io-domains {
1191                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1192                         status = "disabled";
1193                 };
1194         };
1195
1196         spi3: spi@ff350000 {
1197                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1198                 reg = <0x0 0xff350000 0x0 0x1000>;
1199                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1200                 clock-names = "spiclk", "apb_pclk";
1201                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1202                 pinctrl-names = "default";
1203                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1204                 #address-cells = <1>;
1205                 #size-cells = <0>;
1206                 status = "disabled";
1207         };
1208
1209         uart4: serial@ff370000 {
1210                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1211                 reg = <0x0 0xff370000 0x0 0x100>;
1212                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1213                 clock-names = "baudclk", "apb_pclk";
1214                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1215                 reg-shift = <2>;
1216                 reg-io-width = <4>;
1217                 pinctrl-names = "default";
1218                 pinctrl-0 = <&uart4_xfer>;
1219                 status = "disabled";
1220         };
1221
1222         i2c0: i2c@ff3c0000 {
1223                 compatible = "rockchip,rk3399-i2c";
1224                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1225                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1226                 assigned-clock-rates = <200000000>;
1227                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1228                 clock-names = "i2c", "pclk";
1229                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1230                 pinctrl-names = "default";
1231                 pinctrl-0 = <&i2c0_xfer>;
1232                 #address-cells = <1>;
1233                 #size-cells = <0>;
1234                 status = "disabled";
1235         };
1236
1237         i2c4: i2c@ff3d0000 {
1238                 compatible = "rockchip,rk3399-i2c";
1239                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1240                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1241                 assigned-clock-rates = <200000000>;
1242                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1243                 clock-names = "i2c", "pclk";
1244                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1245                 pinctrl-names = "default";
1246                 pinctrl-0 = <&i2c4_xfer>;
1247                 #address-cells = <1>;
1248                 #size-cells = <0>;
1249                 status = "disabled";
1250         };
1251
1252         i2c8: i2c@ff3e0000 {
1253                 compatible = "rockchip,rk3399-i2c";
1254                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1255                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1256                 assigned-clock-rates = <200000000>;
1257                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1258                 clock-names = "i2c", "pclk";
1259                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1260                 pinctrl-names = "default";
1261                 pinctrl-0 = <&i2c8_xfer>;
1262                 #address-cells = <1>;
1263                 #size-cells = <0>;
1264                 status = "disabled";
1265         };
1266
1267         pwm0: pwm@ff420000 {
1268                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1269                 reg = <0x0 0xff420000 0x0 0x10>;
1270                 #pwm-cells = <3>;
1271                 pinctrl-names = "default";
1272                 pinctrl-0 = <&pwm0_pin>;
1273                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1274                 status = "disabled";
1275         };
1276
1277         pwm1: pwm@ff420010 {
1278                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1279                 reg = <0x0 0xff420010 0x0 0x10>;
1280                 #pwm-cells = <3>;
1281                 pinctrl-names = "default";
1282                 pinctrl-0 = <&pwm1_pin>;
1283                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1284                 status = "disabled";
1285         };
1286
1287         pwm2: pwm@ff420020 {
1288                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1289                 reg = <0x0 0xff420020 0x0 0x10>;
1290                 #pwm-cells = <3>;
1291                 pinctrl-names = "default";
1292                 pinctrl-0 = <&pwm2_pin>;
1293                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1294                 status = "disabled";
1295         };
1296
1297         pwm3: pwm@ff420030 {
1298                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1299                 reg = <0x0 0xff420030 0x0 0x10>;
1300                 #pwm-cells = <3>;
1301                 pinctrl-names = "default";
1302                 pinctrl-0 = <&pwm3a_pin>;
1303                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1304                 status = "disabled";
1305         };
1306
1307         dfi: dfi@ff630000 {
1308                 reg = <0x00 0xff630000 0x00 0x4000>;
1309                 compatible = "rockchip,rk3399-dfi";
1310                 rockchip,pmu = <&pmugrf>;
1311                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1312                 clocks = <&cru PCLK_DDR_MON>;
1313                 clock-names = "pclk_ddr_mon";
1314                 status = "disabled";
1315         };
1316
1317         vpu: video-codec@ff650000 {
1318                 compatible = "rockchip,rk3399-vpu";
1319                 reg = <0x0 0xff650000 0x0 0x800>;
1320                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1321                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1322                 interrupt-names = "vepu", "vdpu";
1323                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1324                 clock-names = "aclk", "hclk";
1325                 iommus = <&vpu_mmu>;
1326                 power-domains = <&power RK3399_PD_VCODEC>;
1327         };
1328
1329         vpu_mmu: iommu@ff650800 {
1330                 compatible = "rockchip,iommu";
1331                 reg = <0x0 0xff650800 0x0 0x40>;
1332                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1333                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1334                 clock-names = "aclk", "iface";
1335                 #iommu-cells = <0>;
1336                 power-domains = <&power RK3399_PD_VCODEC>;
1337         };
1338
1339         vdec: video-codec@ff660000 {
1340                 compatible = "rockchip,rk3399-vdec";
1341                 reg = <0x0 0xff660000 0x0 0x400>;
1342                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1343                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1344                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1345                 clock-names = "axi", "ahb", "cabac", "core";
1346                 iommus = <&vdec_mmu>;
1347                 power-domains = <&power RK3399_PD_VDU>;
1348         };
1349
1350         vdec_mmu: iommu@ff660480 {
1351                 compatible = "rockchip,iommu";
1352                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1353                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1354                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1355                 clock-names = "aclk", "iface";
1356                 power-domains = <&power RK3399_PD_VDU>;
1357                 #iommu-cells = <0>;
1358         };
1359
1360         iep_mmu: iommu@ff670800 {
1361                 compatible = "rockchip,iommu";
1362                 reg = <0x0 0xff670800 0x0 0x40>;
1363                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1364                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1365                 clock-names = "aclk", "iface";
1366                 #iommu-cells = <0>;
1367                 status = "disabled";
1368         };
1369
1370         rga: rga@ff680000 {
1371                 compatible = "rockchip,rk3399-rga";
1372                 reg = <0x0 0xff680000 0x0 0x10000>;
1373                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1374                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1375                 clock-names = "aclk", "hclk", "sclk";
1376                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1377                 reset-names = "core", "axi", "ahb";
1378                 power-domains = <&power RK3399_PD_RGA>;
1379         };
1380
1381         efuse0: efuse@ff690000 {
1382                 compatible = "rockchip,rk3399-efuse";
1383                 reg = <0x0 0xff690000 0x0 0x80>;
1384                 #address-cells = <1>;
1385                 #size-cells = <1>;
1386                 clocks = <&cru PCLK_EFUSE1024NS>;
1387                 clock-names = "pclk_efuse";
1388
1389                 /* Data cells */
1390                 cpu_id: cpu-id@7 {
1391                         reg = <0x07 0x10>;
1392                 };
1393                 cpub_leakage: cpu-leakage@17 {
1394                         reg = <0x17 0x1>;
1395                 };
1396                 gpu_leakage: gpu-leakage@18 {
1397                         reg = <0x18 0x1>;
1398                 };
1399                 center_leakage: center-leakage@19 {
1400                         reg = <0x19 0x1>;
1401                 };
1402                 cpul_leakage: cpu-leakage@1a {
1403                         reg = <0x1a 0x1>;
1404                 };
1405                 logic_leakage: logic-leakage@1b {
1406                         reg = <0x1b 0x1>;
1407                 };
1408                 wafer_info: wafer-info@1c {
1409                         reg = <0x1c 0x1>;
1410                 };
1411         };
1412
1413         dmac_bus: dma-controller@ff6d0000 {
1414                 compatible = "arm,pl330", "arm,primecell";
1415                 reg = <0x0 0xff6d0000 0x0 0x4000>;
1416                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
1417                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
1418                 #dma-cells = <1>;
1419                 arm,pl330-periph-burst;
1420                 clocks = <&cru ACLK_DMAC0_PERILP>;
1421                 clock-names = "apb_pclk";
1422         };
1423
1424         dmac_peri: dma-controller@ff6e0000 {
1425                 compatible = "arm,pl330", "arm,primecell";
1426                 reg = <0x0 0xff6e0000 0x0 0x4000>;
1427                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
1428                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
1429                 #dma-cells = <1>;
1430                 arm,pl330-periph-burst;
1431                 clocks = <&cru ACLK_DMAC1_PERILP>;
1432                 clock-names = "apb_pclk";
1433         };
1434
1435         pmucru: clock-controller@ff750000 {
1436                 compatible = "rockchip,rk3399-pmucru";
1437                 reg = <0x0 0xff750000 0x0 0x1000>;
1438                 clocks = <&xin24m>;
1439                 clock-names = "xin24m";
1440                 rockchip,grf = <&pmugrf>;
1441                 #clock-cells = <1>;
1442                 #reset-cells = <1>;
1443                 assigned-clocks = <&pmucru PLL_PPLL>;
1444                 assigned-clock-rates = <676000000>;
1445         };
1446
1447         cru: clock-controller@ff760000 {
1448                 compatible = "rockchip,rk3399-cru";
1449                 reg = <0x0 0xff760000 0x0 0x1000>;
1450                 clocks = <&xin24m>;
1451                 clock-names = "xin24m";
1452                 rockchip,grf = <&grf>;
1453                 #clock-cells = <1>;
1454                 #reset-cells = <1>;
1455                 assigned-clocks =
1456                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1457                         <&cru PLL_NPLL>,
1458                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1459                         <&cru PCLK_PERIHP>,
1460                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1461                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1462                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1463                         <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1464                         <&cru ACLK_GIC_PRE>,
1465                         <&cru PCLK_DDR>,
1466                         <&cru ACLK_VDU>;
1467                 assigned-clock-rates =
1468                          <594000000>,  <800000000>,
1469                         <1000000000>,
1470                          <150000000>,   <75000000>,
1471                           <37500000>,
1472                          <100000000>,  <100000000>,
1473                           <50000000>, <600000000>,
1474                          <100000000>,   <50000000>,
1475                          <400000000>, <400000000>,
1476                          <200000000>,
1477                          <200000000>,
1478                          <400000000>;
1479         };
1480
1481         grf: syscon@ff770000 {
1482                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1483                 reg = <0x0 0xff770000 0x0 0x10000>;
1484                 #address-cells = <1>;
1485                 #size-cells = <1>;
1486
1487                 io_domains: io-domains {
1488                         compatible = "rockchip,rk3399-io-voltage-domain";
1489                         status = "disabled";
1490                 };
1491
1492                 mipi_dphy_rx0: mipi-dphy-rx0 {
1493                         compatible = "rockchip,rk3399-mipi-dphy-rx0";
1494                         clocks = <&cru SCLK_MIPIDPHY_REF>,
1495                                  <&cru SCLK_DPHY_RX0_CFG>,
1496                                  <&cru PCLK_VIO_GRF>;
1497                         clock-names = "dphy-ref", "dphy-cfg", "grf";
1498                         power-domains = <&power RK3399_PD_VIO>;
1499                         #phy-cells = <0>;
1500                         status = "disabled";
1501                 };
1502
1503                 u2phy0: usb2phy@e450 {
1504                         compatible = "rockchip,rk3399-usb2phy";
1505                         reg = <0xe450 0x10>;
1506                         clocks = <&cru SCLK_USB2PHY0_REF>;
1507                         clock-names = "phyclk";
1508                         #clock-cells = <0>;
1509                         clock-output-names = "clk_usbphy0_480m";
1510                         status = "disabled";
1511
1512                         u2phy0_host: host-port {
1513                                 #phy-cells = <0>;
1514                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1515                                 interrupt-names = "linestate";
1516                                 status = "disabled";
1517                         };
1518
1519                         u2phy0_otg: otg-port {
1520                                 #phy-cells = <0>;
1521                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1522                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1523                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1524                                 interrupt-names = "otg-bvalid", "otg-id",
1525                                                   "linestate";
1526                                 status = "disabled";
1527                         };
1528                 };
1529
1530                 u2phy1: usb2phy@e460 {
1531                         compatible = "rockchip,rk3399-usb2phy";
1532                         reg = <0xe460 0x10>;
1533                         clocks = <&cru SCLK_USB2PHY1_REF>;
1534                         clock-names = "phyclk";
1535                         #clock-cells = <0>;
1536                         clock-output-names = "clk_usbphy1_480m";
1537                         status = "disabled";
1538
1539                         u2phy1_host: host-port {
1540                                 #phy-cells = <0>;
1541                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1542                                 interrupt-names = "linestate";
1543                                 status = "disabled";
1544                         };
1545
1546                         u2phy1_otg: otg-port {
1547                                 #phy-cells = <0>;
1548                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1549                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1550                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1551                                 interrupt-names = "otg-bvalid", "otg-id",
1552                                                   "linestate";
1553                                 status = "disabled";
1554                         };
1555                 };
1556
1557                 emmc_phy: phy@f780 {
1558                         compatible = "rockchip,rk3399-emmc-phy";
1559                         reg = <0xf780 0x24>;
1560                         clocks = <&sdhci>;
1561                         clock-names = "emmcclk";
1562                         drive-impedance-ohm = <50>;
1563                         #phy-cells = <0>;
1564                         status = "disabled";
1565                 };
1566
1567                 pcie_phy: pcie-phy {
1568                         compatible = "rockchip,rk3399-pcie-phy";
1569                         clocks = <&cru SCLK_PCIEPHY_REF>;
1570                         clock-names = "refclk";
1571                         #phy-cells = <1>;
1572                         resets = <&cru SRST_PCIEPHY>;
1573                         reset-names = "phy";
1574                         status = "disabled";
1575                 };
1576         };
1577
1578         tcphy0: phy@ff7c0000 {
1579                 compatible = "rockchip,rk3399-typec-phy";
1580                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1581                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1582                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1583                 clock-names = "tcpdcore", "tcpdphy-ref";
1584                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1585                 assigned-clock-rates = <50000000>;
1586                 power-domains = <&power RK3399_PD_TCPD0>;
1587                 resets = <&cru SRST_UPHY0>,
1588                          <&cru SRST_UPHY0_PIPE_L00>,
1589                          <&cru SRST_P_UPHY0_TCPHY>;
1590                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1591                 rockchip,grf = <&grf>;
1592                 status = "disabled";
1593
1594                 tcphy0_dp: dp-port {
1595                         #phy-cells = <0>;
1596                 };
1597
1598                 tcphy0_usb3: usb3-port {
1599                         #phy-cells = <0>;
1600                 };
1601         };
1602
1603         tcphy1: phy@ff800000 {
1604                 compatible = "rockchip,rk3399-typec-phy";
1605                 reg = <0x0 0xff800000 0x0 0x40000>;
1606                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1607                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1608                 clock-names = "tcpdcore", "tcpdphy-ref";
1609                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1610                 assigned-clock-rates = <50000000>;
1611                 power-domains = <&power RK3399_PD_TCPD1>;
1612                 resets = <&cru SRST_UPHY1>,
1613                          <&cru SRST_UPHY1_PIPE_L00>,
1614                          <&cru SRST_P_UPHY1_TCPHY>;
1615                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1616                 rockchip,grf = <&grf>;
1617                 status = "disabled";
1618
1619                 tcphy1_dp: dp-port {
1620                         #phy-cells = <0>;
1621                 };
1622
1623                 tcphy1_usb3: usb3-port {
1624                         #phy-cells = <0>;
1625                 };
1626         };
1627
1628         watchdog@ff848000 {
1629                 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
1630                 reg = <0x0 0xff848000 0x0 0x100>;
1631                 clocks = <&cru PCLK_WDT>;
1632                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1633         };
1634
1635         rktimer: rktimer@ff850000 {
1636                 compatible = "rockchip,rk3399-timer";
1637                 reg = <0x0 0xff850000 0x0 0x1000>;
1638                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1639                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1640                 clock-names = "pclk", "timer";
1641         };
1642
1643         spdif: spdif@ff870000 {
1644                 compatible = "rockchip,rk3399-spdif";
1645                 reg = <0x0 0xff870000 0x0 0x1000>;
1646                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1647                 dmas = <&dmac_bus 7>;
1648                 dma-names = "tx";
1649                 clock-names = "mclk", "hclk";
1650                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1651                 pinctrl-names = "default";
1652                 pinctrl-0 = <&spdif_bus>;
1653                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1654                 #sound-dai-cells = <0>;
1655                 status = "disabled";
1656         };
1657
1658         i2s0: i2s@ff880000 {
1659                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1660                 reg = <0x0 0xff880000 0x0 0x1000>;
1661                 rockchip,grf = <&grf>;
1662                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1663                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1664                 dma-names = "tx", "rx";
1665                 clock-names = "i2s_clk", "i2s_hclk";
1666                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1667                 pinctrl-names = "bclk_on", "bclk_off";
1668                 pinctrl-0 = <&i2s0_8ch_bus>;
1669                 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
1670                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1671                 #sound-dai-cells = <0>;
1672                 status = "disabled";
1673         };
1674
1675         i2s1: i2s@ff890000 {
1676                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1677                 reg = <0x0 0xff890000 0x0 0x1000>;
1678                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1679                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1680                 dma-names = "tx", "rx";
1681                 clock-names = "i2s_clk", "i2s_hclk";
1682                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1683                 pinctrl-names = "default";
1684                 pinctrl-0 = <&i2s1_2ch_bus>;
1685                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1686                 #sound-dai-cells = <0>;
1687                 status = "disabled";
1688         };
1689
1690         i2s2: i2s@ff8a0000 {
1691                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1692                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1693                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1694                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1695                 dma-names = "tx", "rx";
1696                 clock-names = "i2s_clk", "i2s_hclk";
1697                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1698                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1699                 #sound-dai-cells = <0>;
1700                 status = "disabled";
1701         };
1702
1703         vopl: vop@ff8f0000 {
1704                 compatible = "rockchip,rk3399-vop-lit";
1705                 reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>;
1706                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1707                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1708                 assigned-clock-rates = <400000000>, <100000000>;
1709                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1710                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1711                 iommus = <&vopl_mmu>;
1712                 power-domains = <&power RK3399_PD_VOPL>;
1713                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1714                 reset-names = "axi", "ahb", "dclk";
1715                 status = "disabled";
1716
1717                 vopl_out: port {
1718                         #address-cells = <1>;
1719                         #size-cells = <0>;
1720
1721                         vopl_out_mipi: endpoint@0 {
1722                                 reg = <0>;
1723                                 remote-endpoint = <&mipi_in_vopl>;
1724                         };
1725
1726                         vopl_out_edp: endpoint@1 {
1727                                 reg = <1>;
1728                                 remote-endpoint = <&edp_in_vopl>;
1729                         };
1730
1731                         vopl_out_hdmi: endpoint@2 {
1732                                 reg = <2>;
1733                                 remote-endpoint = <&hdmi_in_vopl>;
1734                         };
1735
1736                         vopl_out_mipi1: endpoint@3 {
1737                                 reg = <3>;
1738                                 remote-endpoint = <&mipi1_in_vopl>;
1739                         };
1740
1741                         vopl_out_dp: endpoint@4 {
1742                                 reg = <4>;
1743                                 remote-endpoint = <&dp_in_vopl>;
1744                         };
1745                 };
1746         };
1747
1748         vopl_mmu: iommu@ff8f3f00 {
1749                 compatible = "rockchip,iommu";
1750                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1751                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1752                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1753                 clock-names = "aclk", "iface";
1754                 power-domains = <&power RK3399_PD_VOPL>;
1755                 #iommu-cells = <0>;
1756                 status = "disabled";
1757         };
1758
1759         vopb: vop@ff900000 {
1760                 compatible = "rockchip,rk3399-vop-big";
1761                 reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>;
1762                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1763                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1764                 assigned-clock-rates = <400000000>, <100000000>;
1765                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1766                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1767                 iommus = <&vopb_mmu>;
1768                 power-domains = <&power RK3399_PD_VOPB>;
1769                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1770                 reset-names = "axi", "ahb", "dclk";
1771                 status = "disabled";
1772
1773                 vopb_out: port {
1774                         #address-cells = <1>;
1775                         #size-cells = <0>;
1776
1777                         vopb_out_edp: endpoint@0 {
1778                                 reg = <0>;
1779                                 remote-endpoint = <&edp_in_vopb>;
1780                         };
1781
1782                         vopb_out_mipi: endpoint@1 {
1783                                 reg = <1>;
1784                                 remote-endpoint = <&mipi_in_vopb>;
1785                         };
1786
1787                         vopb_out_hdmi: endpoint@2 {
1788                                 reg = <2>;
1789                                 remote-endpoint = <&hdmi_in_vopb>;
1790                         };
1791
1792                         vopb_out_mipi1: endpoint@3 {
1793                                 reg = <3>;
1794                                 remote-endpoint = <&mipi1_in_vopb>;
1795                         };
1796
1797                         vopb_out_dp: endpoint@4 {
1798                                 reg = <4>;
1799                                 remote-endpoint = <&dp_in_vopb>;
1800                         };
1801                 };
1802         };
1803
1804         vopb_mmu: iommu@ff903f00 {
1805                 compatible = "rockchip,iommu";
1806                 reg = <0x0 0xff903f00 0x0 0x100>;
1807                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1808                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1809                 clock-names = "aclk", "iface";
1810                 power-domains = <&power RK3399_PD_VOPB>;
1811                 #iommu-cells = <0>;
1812                 status = "disabled";
1813         };
1814
1815         isp0: isp0@ff910000 {
1816                 compatible = "rockchip,rk3399-cif-isp";
1817                 reg = <0x0 0xff910000 0x0 0x4000>;
1818                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1819                 clocks = <&cru SCLK_ISP0>,
1820                          <&cru ACLK_ISP0_WRAPPER>,
1821                          <&cru HCLK_ISP0_WRAPPER>;
1822                 clock-names = "isp", "aclk", "hclk";
1823                 iommus = <&isp0_mmu>;
1824                 phys = <&mipi_dphy_rx0>;
1825                 phy-names = "dphy";
1826                 power-domains = <&power RK3399_PD_ISP0>;
1827                 status = "disabled";
1828
1829                 ports {
1830                         #address-cells = <1>;
1831                         #size-cells = <0>;
1832
1833                         port@0 {
1834                                 reg = <0>;
1835                                 #address-cells = <1>;
1836                                 #size-cells = <0>;
1837                         };
1838                 };
1839         };
1840
1841         isp0_mmu: iommu@ff914000 {
1842                 compatible = "rockchip,iommu";
1843                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1844                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1845                 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1846                 clock-names = "aclk", "iface";
1847                 #iommu-cells = <0>;
1848                 power-domains = <&power RK3399_PD_ISP0>;
1849                 rockchip,disable-mmu-reset;
1850         };
1851
1852         isp1: isp1@ff920000 {
1853                 compatible = "rockchip,rk3399-cif-isp";
1854                 reg = <0x0 0xff920000 0x0 0x4000>;
1855                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1856                 clocks = <&cru SCLK_ISP1>,
1857                          <&cru ACLK_ISP1_WRAPPER>,
1858                          <&cru HCLK_ISP1_WRAPPER>;
1859                 clock-names = "isp", "aclk", "hclk";
1860                 iommus = <&isp1_mmu>;
1861                 phys = <&mipi_dsi1>;
1862                 phy-names = "dphy";
1863                 power-domains = <&power RK3399_PD_ISP1>;
1864                 status = "disabled";
1865
1866                 ports {
1867                         #address-cells = <1>;
1868                         #size-cells = <0>;
1869
1870                         port@0 {
1871                                 reg = <0>;
1872                                 #address-cells = <1>;
1873                                 #size-cells = <0>;
1874                         };
1875                 };
1876         };
1877
1878         isp1_mmu: iommu@ff924000 {
1879                 compatible = "rockchip,iommu";
1880                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1881                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1882                 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1883                 clock-names = "aclk", "iface";
1884                 #iommu-cells = <0>;
1885                 power-domains = <&power RK3399_PD_ISP1>;
1886                 rockchip,disable-mmu-reset;
1887         };
1888
1889         hdmi_sound: hdmi-sound {
1890                 compatible = "simple-audio-card";
1891                 simple-audio-card,format = "i2s";
1892                 simple-audio-card,mclk-fs = <256>;
1893                 simple-audio-card,name = "hdmi-sound";
1894                 status = "disabled";
1895
1896                 simple-audio-card,cpu {
1897                         sound-dai = <&i2s2>;
1898                 };
1899                 simple-audio-card,codec {
1900                         sound-dai = <&hdmi>;
1901                 };
1902         };
1903
1904         hdmi: hdmi@ff940000 {
1905                 compatible = "rockchip,rk3399-dw-hdmi";
1906                 reg = <0x0 0xff940000 0x0 0x20000>;
1907                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1908                 clocks = <&cru PCLK_HDMI_CTRL>,
1909                          <&cru SCLK_HDMI_SFR>,
1910                          <&cru SCLK_HDMI_CEC>,
1911                          <&cru PCLK_VIO_GRF>,
1912                          <&cru PLL_VPLL>;
1913                 clock-names = "iahb", "isfr", "cec", "grf", "ref";
1914                 power-domains = <&power RK3399_PD_HDCP>;
1915                 reg-io-width = <4>;
1916                 rockchip,grf = <&grf>;
1917                 #sound-dai-cells = <0>;
1918                 status = "disabled";
1919
1920                 ports {
1921                         hdmi_in: port {
1922                                 #address-cells = <1>;
1923                                 #size-cells = <0>;
1924
1925                                 hdmi_in_vopb: endpoint@0 {
1926                                         reg = <0>;
1927                                         remote-endpoint = <&vopb_out_hdmi>;
1928                                 };
1929                                 hdmi_in_vopl: endpoint@1 {
1930                                         reg = <1>;
1931                                         remote-endpoint = <&vopl_out_hdmi>;
1932                                 };
1933                         };
1934                 };
1935         };
1936
1937         mipi_dsi: mipi@ff960000 {
1938                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1939                 reg = <0x0 0xff960000 0x0 0x8000>;
1940                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1941                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1942                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1943                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1944                 power-domains = <&power RK3399_PD_VIO>;
1945                 resets = <&cru SRST_P_MIPI_DSI0>;
1946                 reset-names = "apb";
1947                 rockchip,grf = <&grf>;
1948                 #address-cells = <1>;
1949                 #size-cells = <0>;
1950                 status = "disabled";
1951
1952                 ports {
1953                         #address-cells = <1>;
1954                         #size-cells = <0>;
1955
1956                         mipi_in: port@0 {
1957                                 reg = <0>;
1958                                 #address-cells = <1>;
1959                                 #size-cells = <0>;
1960
1961                                 mipi_in_vopb: endpoint@0 {
1962                                         reg = <0>;
1963                                         remote-endpoint = <&vopb_out_mipi>;
1964                                 };
1965                                 mipi_in_vopl: endpoint@1 {
1966                                         reg = <1>;
1967                                         remote-endpoint = <&vopl_out_mipi>;
1968                                 };
1969                         };
1970                 };
1971         };
1972
1973         mipi_dsi1: mipi@ff968000 {
1974                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1975                 reg = <0x0 0xff968000 0x0 0x8000>;
1976                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1977                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1978                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1979                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1980                 power-domains = <&power RK3399_PD_VIO>;
1981                 resets = <&cru SRST_P_MIPI_DSI1>;
1982                 reset-names = "apb";
1983                 rockchip,grf = <&grf>;
1984                 #address-cells = <1>;
1985                 #size-cells = <0>;
1986                 #phy-cells = <0>;
1987                 status = "disabled";
1988
1989                 ports {
1990                         #address-cells = <1>;
1991                         #size-cells = <0>;
1992
1993                         mipi1_in: port@0 {
1994                                 reg = <0>;
1995                                 #address-cells = <1>;
1996                                 #size-cells = <0>;
1997
1998                                 mipi1_in_vopb: endpoint@0 {
1999                                         reg = <0>;
2000                                         remote-endpoint = <&vopb_out_mipi1>;
2001                                 };
2002
2003                                 mipi1_in_vopl: endpoint@1 {
2004                                         reg = <1>;
2005                                         remote-endpoint = <&vopl_out_mipi1>;
2006                                 };
2007                         };
2008                 };
2009         };
2010
2011         edp: edp@ff970000 {
2012                 compatible = "rockchip,rk3399-edp";
2013                 reg = <0x0 0xff970000 0x0 0x8000>;
2014                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
2015                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
2016                 clock-names = "dp", "pclk", "grf";
2017                 pinctrl-names = "default";
2018                 pinctrl-0 = <&edp_hpd>;
2019                 power-domains = <&power RK3399_PD_EDP>;
2020                 resets = <&cru SRST_P_EDP_CTRL>;
2021                 reset-names = "dp";
2022                 rockchip,grf = <&grf>;
2023                 status = "disabled";
2024
2025                 ports {
2026                         #address-cells = <1>;
2027                         #size-cells = <0>;
2028                         edp_in: port@0 {
2029                                 reg = <0>;
2030                                 #address-cells = <1>;
2031                                 #size-cells = <0>;
2032
2033                                 edp_in_vopb: endpoint@0 {
2034                                         reg = <0>;
2035                                         remote-endpoint = <&vopb_out_edp>;
2036                                 };
2037
2038                                 edp_in_vopl: endpoint@1 {
2039                                         reg = <1>;
2040                                         remote-endpoint = <&vopl_out_edp>;
2041                                 };
2042                         };
2043                 };
2044         };
2045
2046         gpu: gpu@ff9a0000 {
2047                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
2048                 reg = <0x0 0xff9a0000 0x0 0x10000>;
2049                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
2050                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
2051                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
2052                 interrupt-names = "job", "mmu", "gpu";
2053                 clocks = <&cru ACLK_GPU>;
2054                 #cooling-cells = <2>;
2055                 power-domains = <&power RK3399_PD_GPU>;
2056                 status = "disabled";
2057         };
2058
2059         pinctrl: pinctrl {
2060                 compatible = "rockchip,rk3399-pinctrl";
2061                 rockchip,grf = <&grf>;
2062                 rockchip,pmu = <&pmugrf>;
2063                 #address-cells = <2>;
2064                 #size-cells = <2>;
2065                 ranges;
2066
2067                 gpio0: gpio@ff720000 {
2068                         compatible = "rockchip,gpio-bank";
2069                         reg = <0x0 0xff720000 0x0 0x100>;
2070                         clocks = <&pmucru PCLK_GPIO0_PMU>;
2071                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
2072
2073                         gpio-controller;
2074                         #gpio-cells = <0x2>;
2075
2076                         interrupt-controller;
2077                         #interrupt-cells = <0x2>;
2078                 };
2079
2080                 gpio1: gpio@ff730000 {
2081                         compatible = "rockchip,gpio-bank";
2082                         reg = <0x0 0xff730000 0x0 0x100>;
2083                         clocks = <&pmucru PCLK_GPIO1_PMU>;
2084                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
2085
2086                         gpio-controller;
2087                         #gpio-cells = <0x2>;
2088
2089                         interrupt-controller;
2090                         #interrupt-cells = <0x2>;
2091                 };
2092
2093                 gpio2: gpio@ff780000 {
2094                         compatible = "rockchip,gpio-bank";
2095                         reg = <0x0 0xff780000 0x0 0x100>;
2096                         clocks = <&cru PCLK_GPIO2>;
2097                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2098
2099                         gpio-controller;
2100                         #gpio-cells = <0x2>;
2101
2102                         interrupt-controller;
2103                         #interrupt-cells = <0x2>;
2104                 };
2105
2106                 gpio3: gpio@ff788000 {
2107                         compatible = "rockchip,gpio-bank";
2108                         reg = <0x0 0xff788000 0x0 0x100>;
2109                         clocks = <&cru PCLK_GPIO3>;
2110                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2111
2112                         gpio-controller;
2113                         #gpio-cells = <0x2>;
2114
2115                         interrupt-controller;
2116                         #interrupt-cells = <0x2>;
2117                 };
2118
2119                 gpio4: gpio@ff790000 {
2120                         compatible = "rockchip,gpio-bank";
2121                         reg = <0x0 0xff790000 0x0 0x100>;
2122                         clocks = <&cru PCLK_GPIO4>;
2123                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2124
2125                         gpio-controller;
2126                         #gpio-cells = <0x2>;
2127
2128                         interrupt-controller;
2129                         #interrupt-cells = <0x2>;
2130                 };
2131
2132                 pcfg_pull_up: pcfg-pull-up {
2133                         bias-pull-up;
2134                 };
2135
2136                 pcfg_pull_down: pcfg-pull-down {
2137                         bias-pull-down;
2138                 };
2139
2140                 pcfg_pull_none: pcfg-pull-none {
2141                         bias-disable;
2142                 };
2143
2144                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2145                         bias-disable;
2146                         drive-strength = <12>;
2147                 };
2148
2149                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2150                         bias-disable;
2151                         drive-strength = <13>;
2152                 };
2153
2154                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2155                         bias-disable;
2156                         drive-strength = <18>;
2157                 };
2158
2159                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2160                         bias-disable;
2161                         drive-strength = <20>;
2162                 };
2163
2164                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2165                         bias-pull-up;
2166                         drive-strength = <2>;
2167                 };
2168
2169                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2170                         bias-pull-up;
2171                         drive-strength = <8>;
2172                 };
2173
2174                 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2175                         bias-pull-up;
2176                         drive-strength = <18>;
2177                 };
2178
2179                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2180                         bias-pull-up;
2181                         drive-strength = <20>;
2182                 };
2183
2184                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2185                         bias-pull-down;
2186                         drive-strength = <4>;
2187                 };
2188
2189                 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2190                         bias-pull-down;
2191                         drive-strength = <8>;
2192                 };
2193
2194                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2195                         bias-pull-down;
2196                         drive-strength = <12>;
2197                 };
2198
2199                 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2200                         bias-pull-down;
2201                         drive-strength = <18>;
2202                 };
2203
2204                 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2205                         bias-pull-down;
2206                         drive-strength = <20>;
2207                 };
2208
2209                 pcfg_output_high: pcfg-output-high {
2210                         output-high;
2211                 };
2212
2213                 pcfg_output_low: pcfg-output-low {
2214                         output-low;
2215                 };
2216
2217                 pcfg_input_enable: pcfg-input-enable {
2218                         input-enable;
2219                 };
2220
2221                 pcfg_input_pull_up: pcfg-input-pull-up {
2222                         input-enable;
2223                         bias-pull-up;
2224                         drive-strength = <2>;
2225                 };
2226
2227                 pcfg_input_pull_down: pcfg-input-pull-down {
2228                         input-enable;
2229                         bias-pull-down;
2230                         drive-strength = <2>;
2231                 };
2232
2233                 clock {
2234                         clk_32k: clk-32k {
2235                                 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
2236                         };
2237                 };
2238
2239                 cif {
2240                         cif_clkin: cif-clkin {
2241                                 rockchip,pins =
2242                                         <2 RK_PB2 3 &pcfg_pull_none>;
2243                         };
2244
2245                         cif_clkouta: cif-clkouta {
2246                                 rockchip,pins =
2247                                         <2 RK_PB3 3 &pcfg_pull_none>;
2248                         };
2249                 };
2250
2251                 edp {
2252                         edp_hpd: edp-hpd {
2253                                 rockchip,pins =
2254                                         <4 RK_PC7 2 &pcfg_pull_none>;
2255                         };
2256                 };
2257
2258                 gmac {
2259                         rgmii_pins: rgmii-pins {
2260                                 rockchip,pins =
2261                                         /* mac_txclk */
2262                                         <3 RK_PC1 1 &pcfg_pull_none_13ma>,
2263                                         /* mac_rxclk */
2264                                         <3 RK_PB6 1 &pcfg_pull_none>,
2265                                         /* mac_mdio */
2266                                         <3 RK_PB5 1 &pcfg_pull_none>,
2267                                         /* mac_txen */
2268                                         <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2269                                         /* mac_clk */
2270                                         <3 RK_PB3 1 &pcfg_pull_none>,
2271                                         /* mac_rxdv */
2272                                         <3 RK_PB1 1 &pcfg_pull_none>,
2273                                         /* mac_mdc */
2274                                         <3 RK_PB0 1 &pcfg_pull_none>,
2275                                         /* mac_rxd1 */
2276                                         <3 RK_PA7 1 &pcfg_pull_none>,
2277                                         /* mac_rxd0 */
2278                                         <3 RK_PA6 1 &pcfg_pull_none>,
2279                                         /* mac_txd1 */
2280                                         <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2281                                         /* mac_txd0 */
2282                                         <3 RK_PA4 1 &pcfg_pull_none_13ma>,
2283                                         /* mac_rxd3 */
2284                                         <3 RK_PA3 1 &pcfg_pull_none>,
2285                                         /* mac_rxd2 */
2286                                         <3 RK_PA2 1 &pcfg_pull_none>,
2287                                         /* mac_txd3 */
2288                                         <3 RK_PA1 1 &pcfg_pull_none_13ma>,
2289                                         /* mac_txd2 */
2290                                         <3 RK_PA0 1 &pcfg_pull_none_13ma>;
2291                         };
2292
2293                         rmii_pins: rmii-pins {
2294                                 rockchip,pins =
2295                                         /* mac_mdio */
2296                                         <3 RK_PB5 1 &pcfg_pull_none>,
2297                                         /* mac_txen */
2298                                         <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2299                                         /* mac_clk */
2300                                         <3 RK_PB3 1 &pcfg_pull_none>,
2301                                         /* mac_rxer */
2302                                         <3 RK_PB2 1 &pcfg_pull_none>,
2303                                         /* mac_rxdv */
2304                                         <3 RK_PB1 1 &pcfg_pull_none>,
2305                                         /* mac_mdc */
2306                                         <3 RK_PB0 1 &pcfg_pull_none>,
2307                                         /* mac_rxd1 */
2308                                         <3 RK_PA7 1 &pcfg_pull_none>,
2309                                         /* mac_rxd0 */
2310                                         <3 RK_PA6 1 &pcfg_pull_none>,
2311                                         /* mac_txd1 */
2312                                         <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2313                                         /* mac_txd0 */
2314                                         <3 RK_PA4 1 &pcfg_pull_none_13ma>;
2315                         };
2316                 };
2317
2318                 i2c0 {
2319                         i2c0_xfer: i2c0-xfer {
2320                                 rockchip,pins =
2321                                         <1 RK_PB7 2 &pcfg_pull_none>,
2322                                         <1 RK_PC0 2 &pcfg_pull_none>;
2323                         };
2324                 };
2325
2326                 i2c1 {
2327                         i2c1_xfer: i2c1-xfer {
2328                                 rockchip,pins =
2329                                         <4 RK_PA2 1 &pcfg_pull_none>,
2330                                         <4 RK_PA1 1 &pcfg_pull_none>;
2331                         };
2332                 };
2333
2334                 i2c2 {
2335                         i2c2_xfer: i2c2-xfer {
2336                                 rockchip,pins =
2337                                         <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2338                                         <2 RK_PA0 2 &pcfg_pull_none_12ma>;
2339                         };
2340                 };
2341
2342                 i2c3 {
2343                         i2c3_xfer: i2c3-xfer {
2344                                 rockchip,pins =
2345                                         <4 RK_PC1 1 &pcfg_pull_none>,
2346                                         <4 RK_PC0 1 &pcfg_pull_none>;
2347                         };
2348                 };
2349
2350                 i2c4 {
2351                         i2c4_xfer: i2c4-xfer {
2352                                 rockchip,pins =
2353                                         <1 RK_PB4 1 &pcfg_pull_none>,
2354                                         <1 RK_PB3 1 &pcfg_pull_none>;
2355                         };
2356                 };
2357
2358                 i2c5 {
2359                         i2c5_xfer: i2c5-xfer {
2360                                 rockchip,pins =
2361                                         <3 RK_PB3 2 &pcfg_pull_none>,
2362                                         <3 RK_PB2 2 &pcfg_pull_none>;
2363                         };
2364                 };
2365
2366                 i2c6 {
2367                         i2c6_xfer: i2c6-xfer {
2368                                 rockchip,pins =
2369                                         <2 RK_PB2 2 &pcfg_pull_none>,
2370                                         <2 RK_PB1 2 &pcfg_pull_none>;
2371                         };
2372                 };
2373
2374                 i2c7 {
2375                         i2c7_xfer: i2c7-xfer {
2376                                 rockchip,pins =
2377                                         <2 RK_PB0 2 &pcfg_pull_none>,
2378                                         <2 RK_PA7 2 &pcfg_pull_none>;
2379                         };
2380                 };
2381
2382                 i2c8 {
2383                         i2c8_xfer: i2c8-xfer {
2384                                 rockchip,pins =
2385                                         <1 RK_PC5 1 &pcfg_pull_none>,
2386                                         <1 RK_PC4 1 &pcfg_pull_none>;
2387                         };
2388                 };
2389
2390                 i2s0 {
2391                         i2s0_2ch_bus: i2s0-2ch-bus {
2392                                 rockchip,pins =
2393                                         <3 RK_PD0 1 &pcfg_pull_none>,
2394                                         <3 RK_PD1 1 &pcfg_pull_none>,
2395                                         <3 RK_PD2 1 &pcfg_pull_none>,
2396                                         <3 RK_PD3 1 &pcfg_pull_none>,
2397                                         <3 RK_PD7 1 &pcfg_pull_none>,
2398                                         <4 RK_PA0 1 &pcfg_pull_none>;
2399                         };
2400
2401                         i2s0_8ch_bus: i2s0-8ch-bus {
2402                                 rockchip,pins =
2403                                         <3 RK_PD0 1 &pcfg_pull_none>,
2404                                         <3 RK_PD1 1 &pcfg_pull_none>,
2405                                         <3 RK_PD2 1 &pcfg_pull_none>,
2406                                         <3 RK_PD3 1 &pcfg_pull_none>,
2407                                         <3 RK_PD4 1 &pcfg_pull_none>,
2408                                         <3 RK_PD5 1 &pcfg_pull_none>,
2409                                         <3 RK_PD6 1 &pcfg_pull_none>,
2410                                         <3 RK_PD7 1 &pcfg_pull_none>,
2411                                         <4 RK_PA0 1 &pcfg_pull_none>;
2412                         };
2413
2414                         i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
2415                                 rockchip,pins =
2416                                         <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>,
2417                                         <3 RK_PD1 1 &pcfg_pull_none>,
2418                                         <3 RK_PD2 1 &pcfg_pull_none>,
2419                                         <3 RK_PD3 1 &pcfg_pull_none>,
2420                                         <3 RK_PD4 1 &pcfg_pull_none>,
2421                                         <3 RK_PD5 1 &pcfg_pull_none>,
2422                                         <3 RK_PD6 1 &pcfg_pull_none>,
2423                                         <3 RK_PD7 1 &pcfg_pull_none>,
2424                                         <4 RK_PA0 1 &pcfg_pull_none>;
2425                         };
2426                 };
2427
2428                 i2s1 {
2429                         i2s1_2ch_bus: i2s1-2ch-bus {
2430                                 rockchip,pins =
2431                                         <4 RK_PA3 1 &pcfg_pull_none>,
2432                                         <4 RK_PA4 1 &pcfg_pull_none>,
2433                                         <4 RK_PA5 1 &pcfg_pull_none>,
2434                                         <4 RK_PA6 1 &pcfg_pull_none>,
2435                                         <4 RK_PA7 1 &pcfg_pull_none>;
2436                         };
2437
2438                         i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
2439                                 rockchip,pins =
2440                                         <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>,
2441                                         <4 RK_PA4 1 &pcfg_pull_none>,
2442                                         <4 RK_PA5 1 &pcfg_pull_none>,
2443                                         <4 RK_PA6 1 &pcfg_pull_none>,
2444                                         <4 RK_PA7 1 &pcfg_pull_none>;
2445                         };
2446                 };
2447
2448                 sdio0 {
2449                         sdio0_bus1: sdio0-bus1 {
2450                                 rockchip,pins =
2451                                         <2 RK_PC4 1 &pcfg_pull_up>;
2452                         };
2453
2454                         sdio0_bus4: sdio0-bus4 {
2455                                 rockchip,pins =
2456                                         <2 RK_PC4 1 &pcfg_pull_up>,
2457                                         <2 RK_PC5 1 &pcfg_pull_up>,
2458                                         <2 RK_PC6 1 &pcfg_pull_up>,
2459                                         <2 RK_PC7 1 &pcfg_pull_up>;
2460                         };
2461
2462                         sdio0_cmd: sdio0-cmd {
2463                                 rockchip,pins =
2464                                         <2 RK_PD0 1 &pcfg_pull_up>;
2465                         };
2466
2467                         sdio0_clk: sdio0-clk {
2468                                 rockchip,pins =
2469                                         <2 RK_PD1 1 &pcfg_pull_none>;
2470                         };
2471
2472                         sdio0_cd: sdio0-cd {
2473                                 rockchip,pins =
2474                                         <2 RK_PD2 1 &pcfg_pull_up>;
2475                         };
2476
2477                         sdio0_pwr: sdio0-pwr {
2478                                 rockchip,pins =
2479                                         <2 RK_PD3 1 &pcfg_pull_up>;
2480                         };
2481
2482                         sdio0_bkpwr: sdio0-bkpwr {
2483                                 rockchip,pins =
2484                                         <2 RK_PD4 1 &pcfg_pull_up>;
2485                         };
2486
2487                         sdio0_wp: sdio0-wp {
2488                                 rockchip,pins =
2489                                         <0 RK_PA3 1 &pcfg_pull_up>;
2490                         };
2491
2492                         sdio0_int: sdio0-int {
2493                                 rockchip,pins =
2494                                         <0 RK_PA4 1 &pcfg_pull_up>;
2495                         };
2496                 };
2497
2498                 sdmmc {
2499                         sdmmc_bus1: sdmmc-bus1 {
2500                                 rockchip,pins =
2501                                         <4 RK_PB0 1 &pcfg_pull_up>;
2502                         };
2503
2504                         sdmmc_bus4: sdmmc-bus4 {
2505                                 rockchip,pins =
2506                                         <4 RK_PB0 1 &pcfg_pull_up>,
2507                                         <4 RK_PB1 1 &pcfg_pull_up>,
2508                                         <4 RK_PB2 1 &pcfg_pull_up>,
2509                                         <4 RK_PB3 1 &pcfg_pull_up>;
2510                         };
2511
2512                         sdmmc_clk: sdmmc-clk {
2513                                 rockchip,pins =
2514                                         <4 RK_PB4 1 &pcfg_pull_none>;
2515                         };
2516
2517                         sdmmc_cmd: sdmmc-cmd {
2518                                 rockchip,pins =
2519                                         <4 RK_PB5 1 &pcfg_pull_up>;
2520                         };
2521
2522                         sdmmc_cd: sdmmc-cd {
2523                                 rockchip,pins =
2524                                         <0 RK_PA7 1 &pcfg_pull_up>;
2525                         };
2526
2527                         sdmmc_wp: sdmmc-wp {
2528                                 rockchip,pins =
2529                                         <0 RK_PB0 1 &pcfg_pull_up>;
2530                         };
2531                 };
2532
2533                 suspend {
2534                         ap_pwroff: ap-pwroff {
2535                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
2536                         };
2537
2538                         ddrio_pwroff: ddrio-pwroff {
2539                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
2540                         };
2541                 };
2542
2543                 spdif {
2544                         spdif_bus: spdif-bus {
2545                                 rockchip,pins =
2546                                         <4 RK_PC5 1 &pcfg_pull_none>;
2547                         };
2548
2549                         spdif_bus_1: spdif-bus-1 {
2550                                 rockchip,pins =
2551                                         <3 RK_PC0 3 &pcfg_pull_none>;
2552                         };
2553                 };
2554
2555                 spi0 {
2556                         spi0_clk: spi0-clk {
2557                                 rockchip,pins =
2558                                         <3 RK_PA6 2 &pcfg_pull_up>;
2559                         };
2560                         spi0_cs0: spi0-cs0 {
2561                                 rockchip,pins =
2562                                         <3 RK_PA7 2 &pcfg_pull_up>;
2563                         };
2564                         spi0_cs1: spi0-cs1 {
2565                                 rockchip,pins =
2566                                         <3 RK_PB0 2 &pcfg_pull_up>;
2567                         };
2568                         spi0_tx: spi0-tx {
2569                                 rockchip,pins =
2570                                         <3 RK_PA5 2 &pcfg_pull_up>;
2571                         };
2572                         spi0_rx: spi0-rx {
2573                                 rockchip,pins =
2574                                         <3 RK_PA4 2 &pcfg_pull_up>;
2575                         };
2576                 };
2577
2578                 spi1 {
2579                         spi1_clk: spi1-clk {
2580                                 rockchip,pins =
2581                                         <1 RK_PB1 2 &pcfg_pull_up>;
2582                         };
2583                         spi1_cs0: spi1-cs0 {
2584                                 rockchip,pins =
2585                                         <1 RK_PB2 2 &pcfg_pull_up>;
2586                         };
2587                         spi1_rx: spi1-rx {
2588                                 rockchip,pins =
2589                                         <1 RK_PA7 2 &pcfg_pull_up>;
2590                         };
2591                         spi1_tx: spi1-tx {
2592                                 rockchip,pins =
2593                                         <1 RK_PB0 2 &pcfg_pull_up>;
2594                         };
2595                 };
2596
2597                 spi2 {
2598                         spi2_clk: spi2-clk {
2599                                 rockchip,pins =
2600                                         <2 RK_PB3 1 &pcfg_pull_up>;
2601                         };
2602                         spi2_cs0: spi2-cs0 {
2603                                 rockchip,pins =
2604                                         <2 RK_PB4 1 &pcfg_pull_up>;
2605                         };
2606                         spi2_rx: spi2-rx {
2607                                 rockchip,pins =
2608                                         <2 RK_PB1 1 &pcfg_pull_up>;
2609                         };
2610                         spi2_tx: spi2-tx {
2611                                 rockchip,pins =
2612                                         <2 RK_PB2 1 &pcfg_pull_up>;
2613                         };
2614                 };
2615
2616                 spi3 {
2617                         spi3_clk: spi3-clk {
2618                                 rockchip,pins =
2619                                         <1 RK_PC1 1 &pcfg_pull_up>;
2620                         };
2621                         spi3_cs0: spi3-cs0 {
2622                                 rockchip,pins =
2623                                         <1 RK_PC2 1 &pcfg_pull_up>;
2624                         };
2625                         spi3_rx: spi3-rx {
2626                                 rockchip,pins =
2627                                         <1 RK_PB7 1 &pcfg_pull_up>;
2628                         };
2629                         spi3_tx: spi3-tx {
2630                                 rockchip,pins =
2631                                         <1 RK_PC0 1 &pcfg_pull_up>;
2632                         };
2633                 };
2634
2635                 spi4 {
2636                         spi4_clk: spi4-clk {
2637                                 rockchip,pins =
2638                                         <3 RK_PA2 2 &pcfg_pull_up>;
2639                         };
2640                         spi4_cs0: spi4-cs0 {
2641                                 rockchip,pins =
2642                                         <3 RK_PA3 2 &pcfg_pull_up>;
2643                         };
2644                         spi4_rx: spi4-rx {
2645                                 rockchip,pins =
2646                                         <3 RK_PA0 2 &pcfg_pull_up>;
2647                         };
2648                         spi4_tx: spi4-tx {
2649                                 rockchip,pins =
2650                                         <3 RK_PA1 2 &pcfg_pull_up>;
2651                         };
2652                 };
2653
2654                 spi5 {
2655                         spi5_clk: spi5-clk {
2656                                 rockchip,pins =
2657                                         <2 RK_PC6 2 &pcfg_pull_up>;
2658                         };
2659                         spi5_cs0: spi5-cs0 {
2660                                 rockchip,pins =
2661                                         <2 RK_PC7 2 &pcfg_pull_up>;
2662                         };
2663                         spi5_rx: spi5-rx {
2664                                 rockchip,pins =
2665                                         <2 RK_PC4 2 &pcfg_pull_up>;
2666                         };
2667                         spi5_tx: spi5-tx {
2668                                 rockchip,pins =
2669                                         <2 RK_PC5 2 &pcfg_pull_up>;
2670                         };
2671                 };
2672
2673                 testclk {
2674                         test_clkout0: test-clkout0 {
2675                                 rockchip,pins =
2676                                         <0 RK_PA0 1 &pcfg_pull_none>;
2677                         };
2678
2679                         test_clkout1: test-clkout1 {
2680                                 rockchip,pins =
2681                                         <2 RK_PD1 2 &pcfg_pull_none>;
2682                         };
2683
2684                         test_clkout2: test-clkout2 {
2685                                 rockchip,pins =
2686                                         <0 RK_PB0 3 &pcfg_pull_none>;
2687                         };
2688                 };
2689
2690                 tsadc {
2691                         otp_pin: otp-pin {
2692                                 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2693                         };
2694
2695                         otp_out: otp-out {
2696                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
2697                         };
2698                 };
2699
2700                 uart0 {
2701                         uart0_xfer: uart0-xfer {
2702                                 rockchip,pins =
2703                                         <2 RK_PC0 1 &pcfg_pull_up>,
2704                                         <2 RK_PC1 1 &pcfg_pull_none>;
2705                         };
2706
2707                         uart0_cts: uart0-cts {
2708                                 rockchip,pins =
2709                                         <2 RK_PC2 1 &pcfg_pull_none>;
2710                         };
2711
2712                         uart0_rts: uart0-rts {
2713                                 rockchip,pins =
2714                                         <2 RK_PC3 1 &pcfg_pull_none>;
2715                         };
2716                 };
2717
2718                 uart1 {
2719                         uart1_xfer: uart1-xfer {
2720                                 rockchip,pins =
2721                                         <3 RK_PB4 2 &pcfg_pull_up>,
2722                                         <3 RK_PB5 2 &pcfg_pull_none>;
2723                         };
2724                 };
2725
2726                 uart2a {
2727                         uart2a_xfer: uart2a-xfer {
2728                                 rockchip,pins =
2729                                         <4 RK_PB0 2 &pcfg_pull_up>,
2730                                         <4 RK_PB1 2 &pcfg_pull_none>;
2731                         };
2732                 };
2733
2734                 uart2b {
2735                         uart2b_xfer: uart2b-xfer {
2736                                 rockchip,pins =
2737                                         <4 RK_PC0 2 &pcfg_pull_up>,
2738                                         <4 RK_PC1 2 &pcfg_pull_none>;
2739                         };
2740                 };
2741
2742                 uart2c {
2743                         uart2c_xfer: uart2c-xfer {
2744                                 rockchip,pins =
2745                                         <4 RK_PC3 1 &pcfg_pull_up>,
2746                                         <4 RK_PC4 1 &pcfg_pull_none>;
2747                         };
2748                 };
2749
2750                 uart3 {
2751                         uart3_xfer: uart3-xfer {
2752                                 rockchip,pins =
2753                                         <3 RK_PB6 2 &pcfg_pull_up>,
2754                                         <3 RK_PB7 2 &pcfg_pull_none>;
2755                         };
2756
2757                         uart3_cts: uart3-cts {
2758                                 rockchip,pins =
2759                                         <3 RK_PC0 2 &pcfg_pull_none>;
2760                         };
2761
2762                         uart3_rts: uart3-rts {
2763                                 rockchip,pins =
2764                                         <3 RK_PC1 2 &pcfg_pull_none>;
2765                         };
2766                 };
2767
2768                 uart4 {
2769                         uart4_xfer: uart4-xfer {
2770                                 rockchip,pins =
2771                                         <1 RK_PA7 1 &pcfg_pull_up>,
2772                                         <1 RK_PB0 1 &pcfg_pull_none>;
2773                         };
2774                 };
2775
2776                 uarthdcp {
2777                         uarthdcp_xfer: uarthdcp-xfer {
2778                                 rockchip,pins =
2779                                         <4 RK_PC5 2 &pcfg_pull_up>,
2780                                         <4 RK_PC6 2 &pcfg_pull_none>;
2781                         };
2782                 };
2783
2784                 pwm0 {
2785                         pwm0_pin: pwm0-pin {
2786                                 rockchip,pins =
2787                                         <4 RK_PC2 1 &pcfg_pull_none>;
2788                         };
2789
2790                         pwm0_pin_pull_down: pwm0-pin-pull-down {
2791                                 rockchip,pins =
2792                                         <4 RK_PC2 1 &pcfg_pull_down>;
2793                         };
2794
2795                         vop0_pwm_pin: vop0-pwm-pin {
2796                                 rockchip,pins =
2797                                         <4 RK_PC2 2 &pcfg_pull_none>;
2798                         };
2799
2800                         vop1_pwm_pin: vop1-pwm-pin {
2801                                 rockchip,pins =
2802                                         <4 RK_PC2 3 &pcfg_pull_none>;
2803                         };
2804                 };
2805
2806                 pwm1 {
2807                         pwm1_pin: pwm1-pin {
2808                                 rockchip,pins =
2809                                         <4 RK_PC6 1 &pcfg_pull_none>;
2810                         };
2811
2812                         pwm1_pin_pull_down: pwm1-pin-pull-down {
2813                                 rockchip,pins =
2814                                         <4 RK_PC6 1 &pcfg_pull_down>;
2815                         };
2816                 };
2817
2818                 pwm2 {
2819                         pwm2_pin: pwm2-pin {
2820                                 rockchip,pins =
2821                                         <1 RK_PC3 1 &pcfg_pull_none>;
2822                         };
2823
2824                         pwm2_pin_pull_down: pwm2-pin-pull-down {
2825                                 rockchip,pins =
2826                                         <1 RK_PC3 1 &pcfg_pull_down>;
2827                         };
2828                 };
2829
2830                 pwm3a {
2831                         pwm3a_pin: pwm3a-pin {
2832                                 rockchip,pins =
2833                                         <0 RK_PA6 1 &pcfg_pull_none>;
2834                         };
2835                 };
2836
2837                 pwm3b {
2838                         pwm3b_pin: pwm3b-pin {
2839                                 rockchip,pins =
2840                                         <1 RK_PB6 1 &pcfg_pull_none>;
2841                         };
2842                 };
2843
2844                 hdmi {
2845                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2846                                 rockchip,pins =
2847                                         <4 RK_PC1 3 &pcfg_pull_none>,
2848                                         <4 RK_PC0 3 &pcfg_pull_none>;
2849                         };
2850
2851                         hdmi_cec: hdmi-cec {
2852                                 rockchip,pins =
2853                                         <4 RK_PC7 1 &pcfg_pull_none>;
2854                         };
2855                 };
2856
2857                 pcie {
2858                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2859                                 rockchip,pins =
2860                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2861                         };
2862
2863                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2864                                 rockchip,pins =
2865                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2866                         };
2867                 };
2868
2869         };
2870 };