arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Gru-scarlet board device tree source
   4  *
   5  * Copyright 2018 Google, Inc
   6  */
   7
   8 #include "rk3399-gru.dtsi"
   9
  10 /{
  11         /* Power tree */
  12
  13         /* ppvar_sys children, sorted by name */
  14         pp1250_s3: pp1250-s3 {
  15                 compatible = "regulator-fixed";
  16                 regulator-name = "pp1250_s3";
  17
  18                 /* EC turns on w/ pp1250_s3_en; always on for AP */
  19                 regulator-always-on;
  20                 regulator-boot-on;
  21                 regulator-min-microvolt = <1250000>;
  22                 regulator-max-microvolt = <1250000>;
  23
  24                 vin-supply = <&ppvar_sys>;
  25         };
  26
  27         pp1250_cam: pp1250-dvdd {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "pp1250_dvdd";
  30                 pinctrl-names = "default";
  31                 pinctrl-0 = <&pp1250_cam_en>;
  32
  33                 enable-active-high;
  34                 gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>;
  35
  36                 /* 740us delay from gpio output high to pp1250 stable,
  37                  * rounding up to 1ms for safety.
  38                  */
  39                 startup-delay-us = <1000>;
  40                 vin-supply = <&pp1250_s3>;
  41         };
  42
  43         pp900_s0: pp900-s0 {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "pp900_s0";
  46
  47                 /* EC turns on w/ pp900_s0_en; always on for AP */
  48                 regulator-always-on;
  49                 regulator-boot-on;
  50                 regulator-min-microvolt = <900000>;
  51                 regulator-max-microvolt = <900000>;
  52
  53                 vin-supply = <&ppvar_sys>;
  54         };
  55
  56         ppvarn_lcd: ppvarn-lcd {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "ppvarn_lcd";
  59                 pinctrl-names = "default";
  60                 pinctrl-0 = <&ppvarn_lcd_en>;
  61
  62                 enable-active-high;
  63                 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
  64                 vin-supply = <&ppvar_sys>;
  65         };
  66
  67         ppvarp_lcd: ppvarp-lcd {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "ppvarp_lcd";
  70                 pinctrl-names = "default";
  71                 pinctrl-0 = <&ppvarp_lcd_en>;
  72
  73                 enable-active-high;
  74                 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
  75                 vin-supply = <&ppvar_sys>;
  76         };
  77
  78         /* pp1800 children, sorted by name */
  79         pp900_s3: pp900-s3 {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "pp900_s3";
  82
  83                 /* EC turns on w/ pp900_s3_en; always on for AP */
  84                 regulator-always-on;
  85                 regulator-boot-on;
  86                 regulator-min-microvolt = <900000>;
  87                 regulator-max-microvolt = <900000>;
  88
  89                 vin-supply = <&pp1800>;
  90         };
  91
  92         /* EC turns on pp1800_s3_en */
  93         pp1800_s3: pp1800 {
  94         };
  95
  96         /* pp3300 children, sorted by name */
  97         pp2800_cam: pp2800-avdd {
  98                 compatible = "regulator-fixed";
  99                 regulator-name = "pp2800_avdd";
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&pp2800_cam_en>;
 102
 103                 enable-active-high;
 104                 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
 105                 startup-delay-us = <100>;
 106                 vin-supply = <&pp3300>;
 107         };
 108
 109         /* EC turns on pp3300_s0_en */
 110         pp3300_s0: pp3300 {
 111         };
 112
 113         /* EC turns on pp3300_s3_en */
 114         pp3300_s3: pp3300 {
 115         };
 116
 117         /*
 118          * See b/66922012
 119          *
 120          * This is a hack to make sure the Bluetooth part of the QCA6174A
 121          * is reset at boot by toggling BT_EN. At boot BT_EN is first set
 122          * to low when the bt_3v3 regulator is registered (in disabled
 123          * state). The fake regulator is configured as a supply of the
 124          * wlan_3v3 regulator below. When wlan_3v3 is enabled early in
 125          * the boot process it also enables its supply regulator bt_3v3,
 126          * which changes BT_EN to high.
 127          */
 128         bt_3v3: bt-3v3 {
 129                 compatible = "regulator-fixed";
 130                 regulator-name = "bt_3v3";
 131                 pinctrl-names = "default";
 132                 pinctrl-0 = <&bt_en_1v8_l>;
 133
 134                 enable-active-high;
 135                 gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
 136                 vin-supply = <&pp3300_s3>;
 137         };
 138
 139         wlan_3v3: wlan-3v3 {
 140                 compatible = "regulator-fixed";
 141                 regulator-name = "wlan_3v3";
 142                 pinctrl-names = "default";
 143                 pinctrl-0 = <&wlan_pd_1v8_l>;
 144
 145                 /*
 146                  * The WL_EN pin is driven low when the regulator is
 147                  * registered, and transitions to high when the PCIe bus
 148                  * is powered up.
 149                  */
 150                 enable-active-high;
 151                 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
 152
 153                 /*
 154                  * Require minimum 10ms from power-on (e.g., PD#) to init PCIe.
 155                  * TODO (b/64444991): how long to assert PD#?
 156                  */
 157                 regulator-enable-ramp-delay = <10000>;
 158                 /* See bt_3v3 hack above */
 159                 vin-supply = <&bt_3v3>;
 160         };
 161
 162         backlight: backlight {
 163                 compatible = "pwm-backlight";
 164                 enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
 165                 pinctrl-names = "default";
 166                 pinctrl-0 = <&bl_en>;
 167                 pwms = <&pwm1 0 1000000 0>;
 168                 pwm-delay-us = <10000>;
 169         };
 170
 171         dmic: dmic {
 172                 compatible = "dmic-codec";
 173                 dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
 174                 pinctrl-names = "default";
 175                 pinctrl-0 = <&dmic_en>;
 176                 wakeup-delay-ms = <250>;
 177         };
 178
 179         gpio_keys: gpio-keys {
 180                 compatible = "gpio-keys";
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&pen_eject_odl>;
 183
 184                 pen-insert {
 185                         label = "Pen Insert";
 186                         /* Insert = low, eject = high */
 187                         gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 188                         linux,code = <SW_PEN_INSERTED>;
 189                         linux,input-type = <EV_SW>;
 190                         wakeup-source;
 191                 };
 192         };
 193 };
 194
 195 /* pp900_s0 aliases */
 196 pp900_ddrpll_ap: &pp900_s0 {
 197 };
 198 pp900_pcie: &pp900_s0 {
 199 };
 200 pp900_usb: &pp900_s0 {
 201 };
 202
 203 /* pp900_s3 aliases */
 204 pp900_emmcpll: &pp900_s3 {
 205 };
 206
 207 /* EC turns on; alias for pp1800_s0 */
 208 pp1800_pcie: &pp1800_s0 {
 209 };
 210
 211 /* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */
 212 &ppvar_bigcpu {
 213         ctrl-voltage-range = <800074 1299226>;
 214         regulator-min-microvolt = <800074>;
 215         regulator-max-microvolt = <1299226>;
 216 };
 217
 218 &ppvar_bigcpu_pwm {
 219         /* On scarlet ppvar big cpu use pwm3 */
 220         pwms = <&pwm3 0 3337 0>;
 221         regulator-min-microvolt = <800074>;
 222         regulator-max-microvolt = <1299226>;
 223 };
 224
 225 &ppvar_litcpu {
 226         ctrl-voltage-range = <802122 1199620>;
 227         regulator-min-microvolt = <802122>;
 228         regulator-max-microvolt = <1199620>;
 229 };
 230
 231 &ppvar_litcpu_pwm {
 232         regulator-min-microvolt = <802122>;
 233         regulator-max-microvolt = <1199620>;
 234 };
 235
 236 &ppvar_gpu {
 237         ctrl-voltage-range = <799600 1099600>;
 238         regulator-min-microvolt = <799600>;
 239         regulator-max-microvolt = <1099600>;
 240 };
 241
 242 &ppvar_gpu_pwm {
 243         regulator-min-microvolt = <799600>;
 244         regulator-max-microvolt = <1099600>;
 245 };
 246
 247 &ppvar_sd_card_io {
 248         states = <1800000 0x0>, <3300000 0x1>;
 249         regulator-max-microvolt = <3300000>;
 250 };
 251
 252 &pp3000_sd_slot {
 253         vin-supply = <&pp3300>;
 254 };
 255
 256 ap_i2c_dig: &i2c2 {
 257         status = "okay";
 258
 259         clock-frequency = <400000>;
 260
 261         /* These are relatively safe rise/fall times. */
 262         i2c-scl-falling-time-ns = <50>;
 263         i2c-scl-rising-time-ns = <300>;
 264
 265         digitizer: digitizer@9 {
 266                 compatible = "hid-over-i2c";
 267                 reg = <0x9>;
 268                 interrupt-parent = <&gpio1>;
 269                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 270                 hid-descr-addr = <0x1>;
 271                 pinctrl-names = "default";
 272                 pinctrl-0 = <&pen_int_odl &pen_reset_l>;
 273         };
 274 };
 275
 276 &ap_i2c_ts {
 277         touchscreen: touchscreen@10 {
 278                 compatible = "elan,ekth3500";
 279                 reg = <0x10>;
 280                 interrupt-parent = <&gpio1>;
 281                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 282                 pinctrl-names = "default";
 283                 pinctrl-0 = <&touch_int_l &touch_reset_l>;
 284                 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
 285         };
 286 };
 287
 288 camera: &i2c7 {
 289         status = "okay";
 290
 291         clock-frequency = <400000>;
 292
 293         /* These are relatively safe rise/fall times; TODO: measure */
 294         i2c-scl-falling-time-ns = <50>;
 295         i2c-scl-rising-time-ns = <300>;
 296
 297         /* 24M mclk is shared between world and user cameras */
 298         pinctrl-0 = <&i2c7_xfer &test_clkout1>;
 299
 300         /* Rear-facing camera */
 301         wcam: camera@36 {
 302                 compatible = "ovti,ov5695";
 303                 reg = <0x36>;
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&wcam_rst>;
 306
 307                 clocks = <&cru SCLK_TESTCLKOUT1>;
 308                 clock-names = "xvclk";
 309
 310                 avdd-supply = <&pp2800_cam>;
 311                 dvdd-supply = <&pp1250_cam>;
 312                 dovdd-supply = <&pp1800_s0>;
 313                 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
 314
 315                 port {
 316                         wcam_out: endpoint {
 317                                 remote-endpoint = <&mipi_in_wcam>;
 318                                 data-lanes = <1 2>;
 319                         };
 320                 };
 321         };
 322
 323         /* Front-facing camera */
 324         ucam: camera@3c {
 325                 compatible = "ovti,ov2685";
 326                 reg = <0x3c>;
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&ucam_rst>;
 329
 330                 clocks = <&cru SCLK_TESTCLKOUT1>;
 331                 clock-names = "xvclk";
 332
 333                 avdd-supply = <&pp2800_cam>;
 334                 dovdd-supply = <&pp1800_s0>;
 335                 dvdd-supply = <&pp1800_s0>;
 336                 reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
 337
 338                 port {
 339                         ucam_out: endpoint {
 340                                 remote-endpoint = <&mipi_in_ucam>;
 341                                 data-lanes = <1>;
 342                         };
 343                 };
 344         };
 345 };
 346
 347 &cdn_dp {
 348         extcon = <&usbc_extcon0>;
 349         phys = <&tcphy0_dp>;
 350 };
 351
 352 &cpu_alert0 {
 353         temperature = <66000>;
 354 };
 355
 356 &cpu_alert1 {
 357         temperature = <71000>;
 358 };
 359
 360 &cros_ec {
 361         interrupt-parent = <&gpio1>;
 362         interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 363 };
 364
 365 &cru {
 366         assigned-clocks =
 367                 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 368                 <&cru PLL_NPLL>,
 369                 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 370                 <&cru PCLK_PERIHP>,
 371                 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 372                 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
 373                 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
 374                 <&cru ACLK_VIO>,
 375                 <&cru ACLK_GIC_PRE>,
 376                 <&cru PCLK_DDR>,
 377                 <&cru ACLK_HDCP>;
 378         assigned-clock-rates =
 379                 <600000000>, <1600000000>,
 380                 <1000000000>,
 381                 <150000000>, <75000000>,
 382                 <37500000>,
 383                 <100000000>, <100000000>,
 384                 <50000000>, <800000000>,
 385                 <100000000>, <50000000>,
 386                 <400000000>,
 387                 <200000000>,
 388                 <200000000>,
 389                 <400000000>;
 390 };
 391
 392 &gpio0 {
 393         gpio-line-names = /* GPIO0 A 0-7 */
 394                           "CLK_32K_AP",
 395                           "EC_IN_RW_OD",
 396                           "SPK_PA_EN",
 397                           "WLAN_PERST_1V8_L",
 398                           "WLAN_PD_1V8_L",
 399                           "WLAN_RF_KILL_1V8_L",
 400                           "BIGCPU_DVS_PWM",
 401                           "SD_CD_L_JTAG_EN",
 402
 403                           /* GPIO0 B 0-5 */
 404                           "BT_EN_BT_RF_KILL_1V8_L",
 405                           "PMUIO2_33_18_L_PP3300_S0_EN",
 406                           "TOUCH_RESET_L",
 407                           "AP_EC_WARM_RESET_REQ",
 408                           "PEN_RESET_L",
 409                           /*
 410                            * AP_FLASH_WP_L is crossystem ABI. Schematics call
 411                            * it AP_FLASH_WP_R_ODL.
 412                            */
 413                           "AP_FLASH_WP_L";
 414 };
 415
 416 &gpio1 {
 417         gpio-line-names = /* GPIO1 A 0-7 */
 418                           "PEN_INT_ODL",
 419                           "PEN_EJECT_ODL",
 420                           "BT_HOST_WAKE_1V8_L",
 421                           "WLAN_HOST_WAKE_1V8_L",
 422                           "TOUCH_INT_ODL",
 423                           "AP_EC_S3_S0_L",
 424                           "AP_EC_OVERTEMP",
 425                           "AP_SPI_FLASH_MISO",
 426
 427                           /* GPIO1 B 0-7 */
 428                           "AP_SPI_FLASH_MOSI_R",
 429                           "AP_SPI_FLASH_CLK_R",
 430                           "AP_SPI_FLASH_CS_L_R",
 431                           "SD_CARD_DET_ODL",
 432                           "",
 433                           "AP_EXPANSION_IO1",
 434                           "AP_EXPANSION_IO2",
 435                           "AP_I2C_DISP_SDA",
 436
 437                           /* GPIO1 C 0-7 */
 438                           "AP_I2C_DISP_SCL",
 439                           "H1_INT_ODL",
 440                           "EC_AP_INT_ODL",
 441                           "LITCPU_DVS_PWM",
 442                           "AP_I2C_AUDIO_SDA",
 443                           "AP_I2C_AUDIO_SCL",
 444                           "AP_EXPANSION_IO3",
 445                           "HEADSET_INT_ODL",
 446
 447                           /* GPIO1 D0 */
 448                           "AP_EXPANSION_IO4";
 449 };
 450
 451 &gpio2 {
 452         gpio-line-names = /* GPIO2 A 0-7 */
 453                           "AP_I2C_PEN_SDA",
 454                           "AP_I2C_PEN_SCL",
 455                           "SD_IO_PWR_EN",
 456                           "UCAM_RST_L",
 457                           "PP1250_CAM_EN",
 458                           "WCAM_RST_L",
 459                           "AP_EXPANSION_IO5",
 460                           "AP_I2C_CAM_SDA",
 461
 462                           /* GPIO2 B 0-7 */
 463                           "AP_I2C_CAM_SCL",
 464                           "AP_H1_SPI_MISO",
 465                           "AP_H1_SPI_MOSI",
 466                           "AP_H1_SPI_CLK",
 467                           "AP_H1_SPI_CS_L",
 468                           "",
 469                           "",
 470                           "",
 471
 472                           /* GPIO2 C 0-7 */
 473                           "UART_EXPANSION_TX_AP_RX",
 474                           "UART_AP_TX_EXPANSION_RX",
 475                           "UART_EXPANSION_RTS_AP_CTS",
 476                           "UART_AP_RTS_EXPANSION_CTS",
 477                           "AP_SPI_EC_MISO",
 478                           "AP_SPI_EC_MOSI",
 479                           "AP_SPI_EC_CLK",
 480                           "AP_SPI_EC_CS_L",
 481
 482                           /* GPIO2 D 0-4 */
 483                           "PP2800_CAM_EN",
 484                           "CLK_24M_CAM",
 485                           "WLAN_PCIE_CLKREQ_1V8_L",
 486                           "",
 487                           "SD_PWR_3000_1800_L";
 488 };
 489
 490 &gpio3 {
 491         gpio-line-names = /* GPIO3 A 0-7 */
 492                           "",
 493                           "",
 494                           "",
 495                           "",
 496                           "",
 497                           "",
 498                           "",
 499                           "",
 500
 501                           /* GPIO3 B 0-7 */
 502                           "",
 503                           "",
 504                           "",
 505                           "",
 506                           "",
 507                           "",
 508                           "",
 509                           "",
 510
 511                           /* GPIO3 C 0-7 */
 512                           "",
 513                           "",
 514                           "",
 515                           "",
 516                           "",
 517                           "",
 518                           "",
 519                           "",
 520
 521                           /* GPIO3 D 0-7 */
 522                           "I2S0_SCLK",
 523                           "I2S0_LRCK_RX",
 524                           "I2S0_LRCK_TX",
 525                           "I2S0_SDI_0",
 526                           "STRAP_LCDBIAS_L",
 527                           "STRAP_FEATURE_1",
 528                           "STRAP_FEATURE_2",
 529                           "I2S0_SDO_0";
 530 };
 531
 532 &gpio4 {
 533         gpio-line-names = /* GPIO4 A 0-7 */
 534                           "I2S_MCLK",
 535                           "AP_I2C_EXPANSION_SDA",
 536                           "AP_I2C_EXPANSION_SCL",
 537                           "DMIC_EN",
 538                           "",
 539                           "",
 540                           "",
 541                           "",
 542
 543                           /* GPIO4 B 0-7 */
 544                           "",
 545                           "",
 546                           "",
 547                           "",
 548                           "",
 549                           "",
 550                           "",
 551                           "",
 552
 553                           /* GPIO4 C 0-7 */
 554                           "AP_I2C_TS_SDA",
 555                           "AP_I2C_TS_SCL",
 556                           "GPU_DVS_PWM",
 557                           "UART_DBG_TX_AP_RX",
 558                           "UART_AP_TX_DBG_RX",
 559                           "BL_EN",
 560                           "BL_PWM",
 561                           "",
 562
 563                           /* GPIO4 D 0-5 */
 564                           "",
 565                           "DISPLAY_RST_L",
 566                           "",
 567                           "PPVARP_LCD_EN",
 568                           "PPVARN_LCD_EN",
 569                           "SD_SLOT_PWR_EN";
 570 };
 571
 572 &i2c_tunnel {
 573         google,remote-bus = <0>;
 574 };
 575
 576 &io_domains {
 577         bt656-supply = <&pp1800_s0>;            /* APIO2_VDD;  2a 2b */
 578         audio-supply = <&pp1800_s0>;            /* APIO5_VDD;  3d 4a */
 579         gpio1830-supply = <&pp1800_s0>;         /* APIO4_VDD;  4c 4d */
 580 };
 581
 582 &isp0 {
 583         status = "okay";
 584
 585         ports {
 586                 port@0 {
 587                         mipi_in_wcam: endpoint@0 {
 588                                 reg = <0>;
 589                                 remote-endpoint = <&wcam_out>;
 590                                 data-lanes = <1 2>;
 591                         };
 592
 593                         mipi_in_ucam: endpoint@1 {
 594                                 reg = <1>;
 595                                 remote-endpoint = <&ucam_out>;
 596                                 data-lanes = <1>;
 597                         };
 598                 };
 599         };
 600 };
 601
 602 &isp0_mmu {
 603         status = "okay";
 604 };
 605
 606 &max98357a {
 607         sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
 608 };
 609
 610 &mipi_dphy_rx0 {
 611         status = "okay";
 612 };
 613
 614 &mipi_dsi {
 615         status = "okay";
 616         clock-master;
 617
 618         ports {
 619                 mipi_out: port@1 {
 620                         reg = <1>;
 621
 622                         mipi_out_panel: endpoint {
 623                                 remote-endpoint = <&mipi_in_panel>;
 624                         };
 625                 };
 626         };
 627
 628         mipi_panel: panel@0 {
 629                 /* 2 different panels are used, compatibles are in dts files */
 630                 reg = <0>;
 631                 backlight = <&backlight>;
 632                 enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 633                 pinctrl-names = "default";
 634                 pinctrl-0 = <&display_rst_l>;
 635
 636                 ports {
 637                         #address-cells = <1>;
 638                         #size-cells = <0>;
 639
 640                         port@0 {
 641                                 reg = <0>;
 642
 643                                 mipi_in_panel: endpoint {
 644                                         remote-endpoint = <&mipi_out_panel>;
 645                                 };
 646                         };
 647
 648                         port@1 {
 649                                 reg = <1>;
 650
 651                                 mipi1_in_panel: endpoint@1 {
 652                                         remote-endpoint = <&mipi1_out_panel>;
 653                                 };
 654                         };
 655                 };
 656         };
 657 };
 658
 659 &mipi_dsi1 {
 660         status = "okay";
 661
 662         ports {
 663                 mipi1_out: port@1 {
 664                         reg = <1>;
 665
 666                         mipi1_out_panel: endpoint {
 667                                 remote-endpoint = <&mipi1_in_panel>;
 668                         };
 669                 };
 670         };
 671 };
 672
 673 &pcie0 {
 674         ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
 675
 676         /* PERST# asserted in S3 */
 677         pcie-reset-suspend = <1>;
 678
 679         vpcie3v3-supply = <&wlan_3v3>;
 680         vpcie1v8-supply = <&pp1800_pcie>;
 681 };
 682
 683 &sdmmc {
 684         cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 685 };
 686
 687 &sound {
 688         rockchip,codec = <&max98357a &dmic &codec &cdn_dp>;
 689 };
 690
 691 &spi2 {
 692         status = "okay";
 693
 694         cr50@0 {
 695                 compatible = "google,cr50";
 696                 reg = <0>;
 697                 interrupt-parent = <&gpio1>;
 698                 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 699                 pinctrl-names = "default";
 700                 pinctrl-0 = <&h1_int_od_l>;
 701                 spi-max-frequency = <800000>;
 702         };
 703 };
 704
 705 &usb_host0_ohci {
 706         #address-cells = <1>;
 707         #size-cells = <0>;
 708
 709         qca_bt: bluetooth@1 {
 710                 compatible = "usbcf3,e300", "usb4ca,301a";
 711                 reg = <1>;
 712                 pinctrl-names = "default";
 713                 pinctrl-0 = <&bt_host_wake_l>;
 714                 interrupt-parent = <&gpio1>;
 715                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 716                 interrupt-names = "wakeup";
 717         };
 718 };
 719
 720 /* PINCTRL OVERRIDES */
 721 &ec_ap_int_l {
 722         rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
 723 };
 724
 725 &ap_fw_wp {
 726         rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
 727 };
 728
 729 &bl_en {
 730         rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 731 };
 732
 733 &bt_host_wake_l {
 734         rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 735 };
 736
 737 &ec_ap_int_l {
 738         rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
 739 };
 740
 741 &headset_int_l {
 742         rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
 743 };
 744
 745 &i2s0_8ch_bus {
 746         rockchip,pins =
 747                 <3 RK_PD0 1 &pcfg_pull_none_6ma>,
 748                 <3 RK_PD1 1 &pcfg_pull_none_6ma>,
 749                 <3 RK_PD2 1 &pcfg_pull_none_6ma>,
 750                 <3 RK_PD3 1 &pcfg_pull_none_6ma>,
 751                 <3 RK_PD7 1 &pcfg_pull_none_6ma>,
 752                 <4 RK_PA0 1 &pcfg_pull_none_6ma>;
 753 };
 754
 755 /* there is no external pull up, so need to set this pin pull up */
 756 &sdmmc_cd_pin {
 757         rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
 758 };
 759
 760 &sd_pwr_1800_sel {
 761         rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
 762 };
 763
 764 &sdmode_en {
 765         rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
 766 };
 767
 768 &touch_reset_l {
 769         rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
 770 };
 771
 772 &touch_int_l {
 773         rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
 774 };
 775
 776 &pinctrl {
 777         pinctrl-0 = <
 778                 &ap_pwroff      /* AP will auto-assert this when in S3 */
 779                 &clk_32k        /* This pin is always 32k on gru boards */
 780                 &wlan_rf_kill_1v8_l
 781         >;
 782
 783         pcfg_pull_none_6ma: pcfg-pull-none-6ma {
 784                 bias-disable;
 785                 drive-strength = <6>;
 786         };
 787
 788         camera {
 789                 pp1250_cam_en: pp1250-dvdd {
 790                         rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
 791                 };
 792
 793                 pp2800_cam_en: pp2800-avdd {
 794                         rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
 795                 };
 796
 797                 ucam_rst: ucam_rst {
 798                         rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 799                 };
 800
 801                 wcam_rst: wcam_rst {
 802                         rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
 803                 };
 804         };
 805
 806         digitizer {
 807                 pen_int_odl: pen-int-odl {
 808                         rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
 809                 };
 810
 811                 pen_reset_l: pen-reset-l {
 812                         rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
 813                 };
 814         };
 815
 816         discrete-regulators {
 817                 display_rst_l: display-rst-l {
 818                         rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>;
 819                 };
 820
 821                 ppvarp_lcd_en: ppvarp-lcd-en {
 822                         rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
 823                 };
 824
 825                 ppvarn_lcd_en: ppvarn-lcd-en {
 826                         rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
 827                 };
 828         };
 829
 830         dmic {
 831                 dmic_en: dmic-en {
 832                         rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 833                 };
 834         };
 835
 836         pen {
 837                 pen_eject_odl: pen-eject-odl {
 838                         rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
 839                 };
 840         };
 841
 842         tpm {
 843                 h1_int_od_l: h1-int-od-l {
 844                         rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
 845                 };
 846         };
 847 };
 848
 849 &wifi {
 850         bt_en_1v8_l: bt-en-1v8-l {
 851                 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
 852         };
 853
 854         wlan_pd_1v8_l: wlan-pd-1v8-l {
 855                 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
 856         };
 857
 858         /* Default pull-up, but just to be clear */
 859         wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l {
 860                 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
 861         };
 862
 863         wifi_perst_l: wifi-perst-l {
 864                 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 865         };
 866
 867         wlan_host_wake_l: wlan-host-wake-l {
 868                 rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
 869         };
 870 };