arch/arm64/boot/dts/renesas/r8a779f0.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 or MIT)
   2 /*
   3  * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/r8a779f0-sysc.h>
  11
  12 / {
  13         compatible = "renesas,r8a779f0";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 a55_0: cpu@0 {
  22                         compatible = "arm,cortex-a55";
  23                         reg = <0>;
  24                         device_type = "cpu";
  25                         power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
  26                 };
  27         };
  28
  29         extal_clk: extal {
  30                 compatible = "fixed-clock";
  31                 #clock-cells = <0>;
  32                 /* This value must be overridden by the board */
  33                 clock-frequency = <0>;
  34         };
  35
  36         extalr_clk: extalr {
  37                 compatible = "fixed-clock";
  38                 #clock-cells = <0>;
  39                 /* This value must be overridden by the board */
  40                 clock-frequency = <0>;
  41         };
  42
  43         pmu_a55 {
  44                 compatible = "arm,cortex-a55-pmu";
  45                 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
  46         };
  47
  48         /* External SCIF clock - to be overridden by boards that provide it */
  49         scif_clk: scif {
  50                 compatible = "fixed-clock";
  51                 #clock-cells = <0>;
  52                 clock-frequency = <0>;
  53         };
  54
  55         soc: soc {
  56                 compatible = "simple-bus";
  57                 interrupt-parent = <&gic>;
  58                 #address-cells = <2>;
  59                 #size-cells = <2>;
  60                 ranges;
  61
  62                 rwdt: watchdog@e6020000 {
  63                         compatible = "renesas,r8a779f0-wdt",
  64                                      "renesas,rcar-gen4-wdt";
  65                         reg = <0 0xe6020000 0 0x0c>;
  66                         clocks = <&cpg CPG_MOD 907>;
  67                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
  68                         resets = <&cpg 907>;
  69                         status = "disabled";
  70                 };
  71
  72                 pfc: pinctrl@e6050000 {
  73                         compatible = "renesas,pfc-r8a779f0";
  74                         reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
  75                               <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
  76                 };
  77
  78                 cpg: clock-controller@e6150000 {
  79                         compatible = "renesas,r8a779f0-cpg-mssr";
  80                         reg = <0 0xe6150000 0 0x4000>;
  81                         clocks = <&extal_clk>, <&extalr_clk>;
  82                         clock-names = "extal", "extalr";
  83                         #clock-cells = <2>;
  84                         #power-domain-cells = <0>;
  85                         #reset-cells = <1>;
  86                 };
  87
  88                 rst: reset-controller@e6160000 {
  89                         compatible = "renesas,r8a779f0-rst";
  90                         reg = <0 0xe6160000 0 0x4000>;
  91                 };
  92
  93                 sysc: system-controller@e6180000 {
  94                         compatible = "renesas,r8a779f0-sysc";
  95                         reg = <0 0xe6180000 0 0x4000>;
  96                         #power-domain-cells = <1>;
  97                 };
  98
  99                 scif3: serial@e6c50000 {
 100                         compatible = "renesas,scif-r8a779f0",
 101                                      "renesas,rcar-gen4-scif", "renesas,scif";
 102                         reg = <0 0xe6c50000 0 64>;
 103                         interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 104                         clocks = <&cpg CPG_MOD 704>,
 105                                  <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
 106                                  <&scif_clk>;
 107                         clock-names = "fck", "brg_int", "scif_clk";
 108                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 109                         resets = <&cpg 704>;
 110                         status = "disabled";
 111                 };
 112
 113                 dmac0: dma-controller@e7350000 {
 114                         compatible = "renesas,dmac-r8a779f0",
 115                                      "renesas,rcar-gen4-dmac";
 116                         reg = <0 0xe7350000 0 0x1000>,
 117                               <0 0xe7300000 0 0x10000>;
 118                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 119                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 120                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 121                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 122                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 123                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 124                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 125                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 126                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 127                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 128                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 129                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 130                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 131                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 132                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 133                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 134                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 135                         interrupt-names = "error",
 136                                           "ch0", "ch1", "ch2", "ch3", "ch4",
 137                                           "ch5", "ch6", "ch7", "ch8", "ch9",
 138                                           "ch10", "ch11", "ch12", "ch13",
 139                                           "ch14", "ch15";
 140                         clocks = <&cpg CPG_MOD 709>;
 141                         clock-names = "fck";
 142                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 143                         resets = <&cpg 709>;
 144                         #dma-cells = <1>;
 145                         dma-channels = <16>;
 146                 };
 147
 148                 dmac1: dma-controller@e7351000 {
 149                         compatible = "renesas,dmac-r8a779f0",
 150                                      "renesas,rcar-gen4-dmac";
 151                         reg = <0 0xe7351000 0 0x1000>,
 152                               <0 0xe7310000 0 0x10000>;
 153                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 154                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 155                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 156                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 157                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 159                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 160                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 161                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 162                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 163                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 164                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 165                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 166                                      <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 167                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 168                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 169                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 170                         interrupt-names = "error",
 171                                           "ch0", "ch1", "ch2", "ch3", "ch4",
 172                                           "ch5", "ch6", "ch7", "ch8", "ch9",
 173                                           "ch10", "ch11", "ch12", "ch13",
 174                                           "ch14", "ch15";
 175                         clocks = <&cpg CPG_MOD 710>;
 176                         clock-names = "fck";
 177                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 178                         resets = <&cpg 710>;
 179                         #dma-cells = <1>;
 180                         dma-channels = <16>;
 181                 };
 182
 183                 gic: interrupt-controller@f1000000 {
 184                         compatible = "arm,gic-v3";
 185                         #interrupt-cells = <3>;
 186                         #address-cells = <0>;
 187                         interrupt-controller;
 188                         reg = <0x0 0xf1000000 0 0x20000>,
 189                               <0x0 0xf1060000 0 0x110000>;
 190                         interrupts = <GIC_PPI 9
 191                                       (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 192                 };
 193
 194                 prr: chipid@fff00044 {
 195                         compatible = "renesas,prr";
 196                         reg = <0 0xfff00044 0 4>;
 197                 };
 198         };
 199
 200         timer {
 201                 compatible = "arm,armv8-timer";
 202                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 203                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 204                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 205                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 206         };
 207 };