arch/arm64/boot/dts/renesas/r8a77980.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the r8a77980 SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  * Copyright (C) 2018 Cogent Embedded, Inc.
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  12
  13 / {
  14         compatible = "renesas,r8a77980";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 a53_0: cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a53", "arm,armv8";
  25                         reg = <0>;
  26                         clocks = <&cpg CPG_CORE 0>;
  27                         power-domains = <&sysc 5>;
  28                         next-level-cache = <&L2_CA53>;
  29                         enable-method = "psci";
  30                 };
  31
  32                 L2_CA53: cache-controller {
  33                         compatible = "cache";
  34                         power-domains = <&sysc 21>;
  35                         cache-unified;
  36                         cache-level = <2>;
  37                 };
  38         };
  39
  40         extal_clk: extal {
  41                 compatible = "fixed-clock";
  42                 #clock-cells = <0>;
  43                 /* This value must be overridden by the board */
  44                 clock-frequency = <0>;
  45         };
  46
  47         extalr_clk: extalr {
  48                 compatible = "fixed-clock";
  49                 #clock-cells = <0>;
  50                 /* This value must be overridden by the board */
  51                 clock-frequency = <0>;
  52         };
  53
  54         psci {
  55                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  56                 method = "smc";
  57         };
  58
  59         /* External SCIF clock - to be overridden by boards that provide it */
  60         scif_clk: scif {
  61                 compatible = "fixed-clock";
  62                 #clock-cells = <0>;
  63                 clock-frequency = <0>;
  64         };
  65
  66         soc {
  67                 compatible = "simple-bus";
  68                 interrupt-parent = <&gic>;
  69
  70                 #address-cells = <2>;
  71                 #size-cells = <2>;
  72                 ranges;
  73
  74                 cpg: clock-controller@e6150000 {
  75                         compatible = "renesas,r8a77980-cpg-mssr";
  76                         reg = <0 0xe6150000 0 0x1000>;
  77                         clocks = <&extal_clk>, <&extalr_clk>;
  78                         clock-names = "extal", "extalr";
  79                         #clock-cells = <2>;
  80                         #power-domain-cells = <0>;
  81                         #reset-cells = <1>;
  82                 };
  83
  84                 rst: reset-controller@e6160000 {
  85                         compatible = "renesas,r8a77980-rst";
  86                         reg = <0 0xe6160000 0 0x200>;
  87                 };
  88
  89                 sysc: system-controller@e6180000 {
  90                         compatible = "renesas,r8a77980-sysc";
  91                         reg = <0 0xe6180000 0 0x440>;
  92                         #power-domain-cells = <1>;
  93                 };
  94
  95                 hscif0: serial@e6540000 {
  96                         compatible = "renesas,hscif-r8a77980",
  97                                      "renesas,rcar-gen3-hscif",
  98                                      "renesas,hscif";
  99                         reg = <0 0xe6540000 0 0x60>;
 100                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 101                         clocks = <&cpg CPG_MOD 520>,
 102                                  <&cpg CPG_CORE 19>,
 103                                  <&scif_clk>;
 104                         clock-names = "fck", "brg_int", "scif_clk";
 105                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 106                                <&dmac2 0x31>, <&dmac2 0x30>;
 107                         dma-names = "tx", "rx", "tx", "rx";
 108                         power-domains = <&sysc 32>;
 109                         resets = <&cpg 520>;
 110                         status = "disabled";
 111                 };
 112
 113                 hscif1: serial@e6550000 {
 114                         compatible = "renesas,hscif-r8a77980",
 115                                      "renesas,rcar-gen3-hscif",
 116                                      "renesas,hscif";
 117                         reg = <0 0xe6550000 0 0x60>;
 118                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 119                         clocks = <&cpg CPG_MOD 519>,
 120                                  <&cpg CPG_CORE 19>,
 121                                  <&scif_clk>;
 122                         clock-names = "fck", "brg_int", "scif_clk";
 123                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 124                                <&dmac2 0x33>, <&dmac2 0x32>;
 125                         dma-names = "tx", "rx", "tx", "rx";
 126                         power-domains = <&sysc 32>;
 127                         resets = <&cpg 519>;
 128                         status = "disabled";
 129                 };
 130
 131                 hscif2: serial@e6560000 {
 132                         compatible = "renesas,hscif-r8a77980",
 133                                      "renesas,rcar-gen3-hscif",
 134                                      "renesas,hscif";
 135                         reg = <0 0xe6560000 0 0x60>;
 136                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 137                         clocks = <&cpg CPG_MOD 518>,
 138                                  <&cpg CPG_CORE 19>,
 139                                  <&scif_clk>;
 140                         clock-names = "fck", "brg_int", "scif_clk";
 141                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 142                                <&dmac2 0x35>, <&dmac2 0x34>;
 143                         dma-names = "tx", "rx", "tx", "rx";
 144                         power-domains = <&sysc 32>;
 145                         resets = <&cpg 518>;
 146                         status = "disabled";
 147                 };
 148
 149                 hscif3: serial@e66a0000 {
 150                         compatible = "renesas,hscif-r8a77980",
 151                                      "renesas,rcar-gen3-hscif",
 152                                      "renesas,hscif";
 153                         reg = <0 0xe66a0000 0 0x60>;
 154                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 155                         clocks = <&cpg CPG_MOD 517>,
 156                                  <&cpg CPG_CORE 19>,
 157                                  <&scif_clk>;
 158                         clock-names = "fck", "brg_int", "scif_clk";
 159                         dmas = <&dmac1 0x37>, <&dmac1 0x36>,
 160                                <&dmac2 0x37>, <&dmac2 0x36>;
 161                         dma-names = "tx", "rx", "tx", "rx";
 162                         power-domains = <&sysc 32>;
 163                         resets = <&cpg 517>;
 164                         status = "disabled";
 165                 };
 166
 167                 avb: ethernet@e6800000 {
 168                         compatible = "renesas,etheravb-r8a77980",
 169                                      "renesas,etheravb-rcar-gen3";
 170                         reg = <0 0xe6800000 0 0x800>;
 171                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 172                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 173                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 174                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 175                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 176                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 177                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 178                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 180                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 181                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 183                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 184                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 185                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 188                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 189                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 190                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 192                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 193                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 194                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 196                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 197                                           "ch4", "ch5", "ch6", "ch7",
 198                                           "ch8", "ch9", "ch10", "ch11",
 199                                           "ch12", "ch13", "ch14", "ch15",
 200                                           "ch16", "ch17", "ch18", "ch19",
 201                                           "ch20", "ch21", "ch22", "ch23",
 202                                           "ch24";
 203                         clocks = <&cpg CPG_MOD 812>;
 204                         power-domains = <&sysc 32>;
 205                         resets = <&cpg 812>;
 206                         phy-mode = "rgmii";
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                 };
 210
 211                 scif0: serial@e6e60000 {
 212                         compatible = "renesas,scif-r8a77980",
 213                                      "renesas,rcar-gen3-scif",
 214                                      "renesas,scif";
 215                         reg = <0 0xe6e60000 0 0x40>;
 216                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 217                         clocks = <&cpg CPG_MOD 207>,
 218                                  <&cpg CPG_CORE 19>,
 219                                  <&scif_clk>;
 220                         clock-names = "fck", "brg_int", "scif_clk";
 221                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 222                                <&dmac2 0x51>, <&dmac2 0x50>;
 223                         dma-names = "tx", "rx", "tx", "rx";
 224                         power-domains = <&sysc 32>;
 225                         resets = <&cpg 207>;
 226                         status = "disabled";
 227                 };
 228
 229                 scif1: serial@e6e68000 {
 230                         compatible = "renesas,scif-r8a77980",
 231                                      "renesas,rcar-gen3-scif",
 232                                      "renesas,scif";
 233                         reg = <0 0xe6e68000 0 0x40>;
 234                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 235                         clocks = <&cpg CPG_MOD 206>,
 236                                  <&cpg CPG_CORE 19>,
 237                                  <&scif_clk>;
 238                         clock-names = "fck", "brg_int", "scif_clk";
 239                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 240                                <&dmac2 0x53>, <&dmac2 0x52>;
 241                         dma-names = "tx", "rx", "tx", "rx";
 242                         power-domains = <&sysc 32>;
 243                         resets = <&cpg 206>;
 244                         status = "disabled";
 245                 };
 246
 247                 scif3: serial@e6c50000 {
 248                         compatible = "renesas,scif-r8a77980",
 249                                      "renesas,rcar-gen3-scif",
 250                                      "renesas,scif";
 251                         reg = <0 0xe6c50000 0 0x40>;
 252                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&cpg CPG_MOD 204>,
 254                                  <&cpg CPG_CORE 19>,
 255                                  <&scif_clk>;
 256                         clock-names = "fck", "brg_int", "scif_clk";
 257                         dmas = <&dmac1 0x57>, <&dmac1 0x56>,
 258                                <&dmac2 0x57>, <&dmac2 0x56>;
 259                         dma-names = "tx", "rx", "tx", "rx";
 260                         power-domains = <&sysc 32>;
 261                         resets = <&cpg 204>;
 262                         status = "disabled";
 263                 };
 264
 265                 scif4: serial@e6c40000 {
 266                         compatible = "renesas,scif-r8a77980",
 267                                      "renesas,rcar-gen3-scif",
 268                                      "renesas,scif";
 269                         reg = <0 0xe6c40000 0 0x40>;
 270                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 271                         clocks = <&cpg CPG_MOD 203>,
 272                                  <&cpg CPG_CORE 19>,
 273                                  <&scif_clk>;
 274                         clock-names = "fck", "brg_int", "scif_clk";
 275                         dmas = <&dmac1 0x59>, <&dmac1 0x58>,
 276                                <&dmac2 0x59>, <&dmac2 0x58>;
 277                         dma-names = "tx", "rx", "tx", "rx";
 278                         power-domains = <&sysc 32>;
 279                         resets = <&cpg 203>;
 280                         status = "disabled";
 281                 };
 282
 283                 dmac1: dma-controller@e7300000 {
 284                         compatible = "renesas,dmac-r8a77980",
 285                                      "renesas,rcar-dmac";
 286                         reg = <0 0xe7300000 0 0x10000>;
 287                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 288                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 289                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 290                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 291                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 292                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 293                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 294                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 295                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 296                                       GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH
 297                                       GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH
 298                                       GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH
 299                                       GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH
 300                                       GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH
 301                                       GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH
 302                                       GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
 303                                       GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
 304                         interrupt-names = "error",
 305                                           "ch0", "ch1", "ch2", "ch3",
 306                                           "ch4", "ch5", "ch6", "ch7",
 307                                           "ch8", "ch9", "ch10", "ch11",
 308                                           "ch12", "ch13", "ch14", "ch15";
 309                         clocks = <&cpg CPG_MOD 218>;
 310                         clock-names = "fck";
 311                         power-domains = <&sysc 32>;
 312                         resets = <&cpg 218>;
 313                         #dma-cells = <1>;
 314                         dma-channels = <16>;
 315                 };
 316
 317                 dmac2: dma-controller@e7310000 {
 318                         compatible = "renesas,dmac-r8a77980",
 319                                      "renesas,rcar-dmac";
 320                         reg = <0 0xe7310000 0 0x10000>;
 321                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
 322                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 323                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 324                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 325                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 326                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 327                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 328                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 329                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH
 330                                       GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH
 331                                       GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH
 332                                       GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH
 333                                       GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH
 334                                       GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH
 335                                       GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH
 336                                       GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
 337                                       GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
 338                         interrupt-names = "error",
 339                                           "ch0", "ch1", "ch2", "ch3",
 340                                           "ch4", "ch5", "ch6", "ch7",
 341                                           "ch8", "ch9", "ch10", "ch11",
 342                                           "ch12", "ch13", "ch14", "ch15";
 343                         clocks = <&cpg CPG_MOD 217>;
 344                         clock-names = "fck";
 345                         power-domains = <&sysc 32>;
 346                         resets = <&cpg 217>;
 347                         #dma-cells = <1>;
 348                         dma-channels = <16>;
 349                 };
 350
 351                 gic: interrupt-controller@f1010000 {
 352                         compatible = "arm,gic-400";
 353                         #interrupt-cells = <3>;
 354                         #address-cells = <0>;
 355                         interrupt-controller;
 356                         reg = <0x0 0xf1010000 0 0x1000>,
 357                               <0x0 0xf1020000 0 0x20000>,
 358                               <0x0 0xf1040000 0 0x20000>,
 359                               <0x0 0xf1060000 0 0x20000>;
 360                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
 361                                       IRQ_TYPE_LEVEL_HIGH)>;
 362                         clocks = <&cpg CPG_MOD 408>;
 363                         clock-names = "clk";
 364                         power-domains = <&sysc 32>;
 365                         resets = <&cpg 408>;
 366                 };
 367
 368                 prr: chipid@fff00044 {
 369                         compatible = "renesas,prr";
 370                         reg = <0 0xfff00044 0 4>;
 371                 };
 372         };
 373
 374         timer {
 375                 compatible = "arm,armv8-timer";
 376                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
 377                                        IRQ_TYPE_LEVEL_LOW)>,
 378                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
 379                                        IRQ_TYPE_LEVEL_LOW)>,
 380                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
 381                                        IRQ_TYPE_LEVEL_LOW)>,
 382                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
 383                                        IRQ_TYPE_LEVEL_LOW)>;
 384         };
 385 };