Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[platform/kernel/linux-rpi.git] / arch / arm64 / boot / dts / renesas / r8a7795-es1.dtsi
1 /*
2  * Device Tree Source for the r8a7795 ES1.x SoC
3  *
4  * Copyright (C) 2015 Renesas Electronics Corp.
5  *
6  * This file is licensed under the terms of the GNU General Public License
7  * version 2.  This program is licensed "as is" without any warranty of any
8  * kind, whether express or implied.
9  */
10
11 #include "r8a7795.dtsi"
12
13 &soc {
14         xhci1: usb@ee0400000 {
15                 compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
16                 reg = <0 0xee040000 0 0xc00>;
17                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
18                 clocks = <&cpg CPG_MOD 327>;
19                 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
20                 resets = <&cpg 327>;
21                 status = "disabled";
22         };
23
24         fcpf2: fcp@fe952000 {
25                 compatible = "renesas,fcpf";
26                 reg = <0 0xfe952000 0 0x200>;
27                 clocks = <&cpg CPG_MOD 613>;
28                 power-domains = <&sysc R8A7795_PD_A3VP>;
29                 resets = <&cpg 613>;
30         };
31
32         vspi2: vsp@fe9c0000 {
33                 compatible = "renesas,vsp2";
34                 reg = <0 0xfe9c0000 0 0x8000>;
35                 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
36                 clocks = <&cpg CPG_MOD 629>;
37                 power-domains = <&sysc R8A7795_PD_A3VP>;
38                 resets = <&cpg 629>;
39
40                 renesas,fcp = <&fcpvi2>;
41         };
42
43         fcpvi2: fcp@fe9cf000 {
44                 compatible = "renesas,fcpv";
45                 reg = <0 0xfe9cf000 0 0x200>;
46                 clocks = <&cpg CPG_MOD 609>;
47                 power-domains = <&sysc R8A7795_PD_A3VP>;
48                 resets = <&cpg 609>;
49         };
50
51         vspd3: vsp@fea38000 {
52                 compatible = "renesas,vsp2";
53                 reg = <0 0xfea38000 0 0x4000>;
54                 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
55                 clocks = <&cpg CPG_MOD 620>;
56                 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
57                 resets = <&cpg 620>;
58
59                 renesas,fcp = <&fcpvd3>;
60         };
61
62         fcpvd3: fcp@fea3f000 {
63                 compatible = "renesas,fcpv";
64                 reg = <0 0xfea3f000 0 0x200>;
65                 clocks = <&cpg CPG_MOD 600>;
66                 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
67                 resets = <&cpg 600>;
68         };
69
70         fdp1@fe948000 {
71                 compatible = "renesas,fdp1";
72                 reg = <0 0xfe948000 0 0x2400>;
73                 interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
74                 clocks = <&cpg CPG_MOD 117>;
75                 power-domains = <&sysc R8A7795_PD_A3VP>;
76                 resets = <&cpg 117>;
77                 renesas,fcp = <&fcpf2>;
78         };
79 };
80
81 &du {
82         compatible = "renesas,du-r8a7795";
83         vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
84 };