arch/arm64/boot/dts/renesas/r8a774c0.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the RZ/G2E (R8A774C0) SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/r8a774c0-sysc.h>
  11
  12 / {
  13         compatible = "renesas,r8a774c0";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         /*
  18          * The external audio clocks are configured as 0 Hz fixed frequency
  19          * clocks by default.
  20          * Boards that provide audio clocks should override them.
  21          */
  22         audio_clk_a: audio_clk_a {
  23                 compatible = "fixed-clock";
  24                 #clock-cells = <0>;
  25                 clock-frequency = <0>;
  26         };
  27
  28         audio_clk_b: audio_clk_b {
  29                 compatible = "fixed-clock";
  30                 #clock-cells = <0>;
  31                 clock-frequency = <0>;
  32         };
  33
  34         audio_clk_c: audio_clk_c {
  35                 compatible = "fixed-clock";
  36                 #clock-cells = <0>;
  37                 clock-frequency = <0>;
  38         };
  39
  40         /* External CAN clock - to be overridden by boards that provide it */
  41         can_clk: can {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <0>;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 /* 1 core only at this point */
  52                 a53_0: cpu@0 {
  53                         compatible = "arm,cortex-a53", "arm,armv8";
  54                         reg = <0>;
  55                         device_type = "cpu";
  56                         power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
  57                         next-level-cache = <&L2_CA53>;
  58                         enable-method = "psci";
  59                 };
  60
  61                 L2_CA53: cache-controller-0 {
  62                         compatible = "cache";
  63                         power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
  64                         cache-unified;
  65                         cache-level = <2>;
  66                 };
  67         };
  68
  69         extal_clk: extal {
  70                 compatible = "fixed-clock";
  71                 #clock-cells = <0>;
  72                 /* This value must be overridden by the board */
  73                 clock-frequency = <0>;
  74         };
  75
  76         /* External PCIe clock - can be overridden by the board */
  77         pcie_bus_clk: pcie_bus {
  78                 compatible = "fixed-clock";
  79                 #clock-cells = <0>;
  80                 clock-frequency = <0>;
  81         };
  82
  83         pmu_a53 {
  84                 compatible = "arm,cortex-a53-pmu";
  85                 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  86                 interrupt-affinity = <&a53_0>;
  87         };
  88
  89         psci {
  90                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  91                 method = "smc";
  92         };
  93
  94         /* External SCIF clock - to be overridden by boards that provide it */
  95         scif_clk: scif {
  96                 compatible = "fixed-clock";
  97                 #clock-cells = <0>;
  98                 clock-frequency = <0>;
  99         };
 100
 101         soc: soc {
 102                 compatible = "simple-bus";
 103                 interrupt-parent = <&gic>;
 104                 #address-cells = <2>;
 105                 #size-cells = <2>;
 106                 ranges;
 107
 108                 cpg: clock-controller@e6150000 {
 109                         compatible = "renesas,r8a774c0-cpg-mssr";
 110                         reg = <0 0xe6150000 0 0x1000>;
 111                         clocks = <&extal_clk>;
 112                         clock-names = "extal";
 113                         #clock-cells = <2>;
 114                         #power-domain-cells = <0>;
 115                         #reset-cells = <1>;
 116                 };
 117
 118                 rst: reset-controller@e6160000 {
 119                         compatible = "renesas,r8a774c0-rst";
 120                         reg = <0 0xe6160000 0 0x0200>;
 121                 };
 122
 123                 sysc: system-controller@e6180000 {
 124                         compatible = "renesas,r8a774c0-sysc";
 125                         reg = <0 0xe6180000 0 0x0400>;
 126                         #power-domain-cells = <1>;
 127                 };
 128
 129                 scif2: serial@e6e88000 {
 130                         compatible = "renesas,scif-r8a774c0",
 131                                      "renesas,rcar-gen3-scif", "renesas,scif";
 132                         reg = <0 0xe6e88000 0 64>;
 133                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 134                         clocks = <&cpg CPG_MOD 310>,
 135                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 136                                  <&scif_clk>;
 137                         clock-names = "fck", "brg_int", "scif_clk";
 138                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 139                         resets = <&cpg 310>;
 140                         status = "disabled";
 141                 };
 142
 143                 gic: interrupt-controller@f1010000 {
 144                         compatible = "arm,gic-400";
 145                         #interrupt-cells = <3>;
 146                         #address-cells = <0>;
 147                         interrupt-controller;
 148                         reg = <0x0 0xf1010000 0 0x1000>,
 149                               <0x0 0xf1020000 0 0x20000>,
 150                               <0x0 0xf1040000 0 0x20000>,
 151                               <0x0 0xf1060000 0 0x20000>;
 152                         interrupts = <GIC_PPI 9
 153                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 154                         clocks = <&cpg CPG_MOD 408>;
 155                         clock-names = "clk";
 156                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 157                         resets = <&cpg 408>;
 158                 };
 159
 160                 prr: chipid@fff00044 {
 161                         compatible = "renesas,prr";
 162                         reg = <0 0xfff00044 0 4>;
 163                 };
 164         };
 165
 166         timer {
 167                 compatible = "arm,armv8-timer";
 168                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 169                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 170                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 171                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 172         };
 173
 174         /* External USB clocks - can be overridden by the board */
 175         usb3s0_clk: usb3s0 {
 176                 compatible = "fixed-clock";
 177                 #clock-cells = <0>;
 178                 clock-frequency = <0>;
 179         };
 180
 181         usb_extal_clk: usb_extal {
 182                 compatible = "fixed-clock";
 183                 #clock-cells = <0>;
 184                 clock-frequency = <0>;
 185         };
 186 };