arch/arm64/boot/dts/renesas/r8a774c0.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the RZ/G2E (R8A774C0) SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/r8a774c0-sysc.h>
  11
  12 / {
  13         compatible = "renesas,r8a774c0";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         /*
  18          * The external audio clocks are configured as 0 Hz fixed frequency
  19          * clocks by default.
  20          * Boards that provide audio clocks should override them.
  21          */
  22         audio_clk_a: audio_clk_a {
  23                 compatible = "fixed-clock";
  24                 #clock-cells = <0>;
  25                 clock-frequency = <0>;
  26         };
  27
  28         audio_clk_b: audio_clk_b {
  29                 compatible = "fixed-clock";
  30                 #clock-cells = <0>;
  31                 clock-frequency = <0>;
  32         };
  33
  34         audio_clk_c: audio_clk_c {
  35                 compatible = "fixed-clock";
  36                 #clock-cells = <0>;
  37                 clock-frequency = <0>;
  38         };
  39
  40         /* External CAN clock - to be overridden by boards that provide it */
  41         can_clk: can {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <0>;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 a53_0: cpu@0 {
  52                         compatible = "arm,cortex-a53", "arm,armv8";
  53                         reg = <0>;
  54                         device_type = "cpu";
  55                         power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
  56                         next-level-cache = <&L2_CA53>;
  57                         enable-method = "psci";
  58                 };
  59
  60                 a53_1: cpu@1 {
  61                         compatible = "arm,cortex-a53", "arm,armv8";
  62                         reg = <1>;
  63                         device_type = "cpu";
  64                         power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
  65                         next-level-cache = <&L2_CA53>;
  66                         enable-method = "psci";
  67                 };
  68
  69                 L2_CA53: cache-controller-0 {
  70                         compatible = "cache";
  71                         power-domains = <&sysc R8A774C0_PD_CA53_SCU>;
  72                         cache-unified;
  73                         cache-level = <2>;
  74                 };
  75         };
  76
  77         extal_clk: extal {
  78                 compatible = "fixed-clock";
  79                 #clock-cells = <0>;
  80                 /* This value must be overridden by the board */
  81                 clock-frequency = <0>;
  82         };
  83
  84         /* External PCIe clock - can be overridden by the board */
  85         pcie_bus_clk: pcie_bus {
  86                 compatible = "fixed-clock";
  87                 #clock-cells = <0>;
  88                 clock-frequency = <0>;
  89         };
  90
  91         pmu_a53 {
  92                 compatible = "arm,cortex-a53-pmu";
  93                 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
  94                                       <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  95                 interrupt-affinity = <&a53_0>, <&a53_1>;
  96         };
  97
  98         psci {
  99                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 100                 method = "smc";
 101         };
 102
 103         /* External SCIF clock - to be overridden by boards that provide it */
 104         scif_clk: scif {
 105                 compatible = "fixed-clock";
 106                 #clock-cells = <0>;
 107                 clock-frequency = <0>;
 108         };
 109
 110         soc: soc {
 111                 compatible = "simple-bus";
 112                 interrupt-parent = <&gic>;
 113                 #address-cells = <2>;
 114                 #size-cells = <2>;
 115                 ranges;
 116
 117                 rwdt: watchdog@e6020000 {
 118                         compatible = "renesas,r8a774c0-wdt",
 119                                      "renesas,rcar-gen3-wdt";
 120                         reg = <0 0xe6020000 0 0x0c>;
 121                         clocks = <&cpg CPG_MOD 402>;
 122                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 123                         resets = <&cpg 402>;
 124                         status = "disabled";
 125                 };
 126
 127                 gpio0: gpio@e6050000 {
 128                         compatible = "renesas,gpio-r8a774c0",
 129                                      "renesas,rcar-gen3-gpio";
 130                         reg = <0 0xe6050000 0 0x50>;
 131                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 132                         #gpio-cells = <2>;
 133                         gpio-controller;
 134                         gpio-ranges = <&pfc 0 0 18>;
 135                         #interrupt-cells = <2>;
 136                         interrupt-controller;
 137                         clocks = <&cpg CPG_MOD 912>;
 138                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 139                         resets = <&cpg 912>;
 140                 };
 141
 142                 gpio1: gpio@e6051000 {
 143                         compatible = "renesas,gpio-r8a774c0",
 144                                      "renesas,rcar-gen3-gpio";
 145                         reg = <0 0xe6051000 0 0x50>;
 146                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 147                         #gpio-cells = <2>;
 148                         gpio-controller;
 149                         gpio-ranges = <&pfc 0 32 23>;
 150                         #interrupt-cells = <2>;
 151                         interrupt-controller;
 152                         clocks = <&cpg CPG_MOD 911>;
 153                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 154                         resets = <&cpg 911>;
 155                 };
 156
 157                 gpio2: gpio@e6052000 {
 158                         compatible = "renesas,gpio-r8a774c0",
 159                                      "renesas,rcar-gen3-gpio";
 160                         reg = <0 0xe6052000 0 0x50>;
 161                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 162                         #gpio-cells = <2>;
 163                         gpio-controller;
 164                         gpio-ranges = <&pfc 0 64 26>;
 165                         #interrupt-cells = <2>;
 166                         interrupt-controller;
 167                         clocks = <&cpg CPG_MOD 910>;
 168                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 169                         resets = <&cpg 910>;
 170                 };
 171
 172                 gpio3: gpio@e6053000 {
 173                         compatible = "renesas,gpio-r8a774c0",
 174                                      "renesas,rcar-gen3-gpio";
 175                         reg = <0 0xe6053000 0 0x50>;
 176                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 177                         #gpio-cells = <2>;
 178                         gpio-controller;
 179                         gpio-ranges = <&pfc 0 96 16>;
 180                         #interrupt-cells = <2>;
 181                         interrupt-controller;
 182                         clocks = <&cpg CPG_MOD 909>;
 183                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 184                         resets = <&cpg 909>;
 185                 };
 186
 187                 gpio4: gpio@e6054000 {
 188                         compatible = "renesas,gpio-r8a774c0",
 189                                      "renesas,rcar-gen3-gpio";
 190                         reg = <0 0xe6054000 0 0x50>;
 191                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 192                         #gpio-cells = <2>;
 193                         gpio-controller;
 194                         gpio-ranges = <&pfc 0 128 11>;
 195                         #interrupt-cells = <2>;
 196                         interrupt-controller;
 197                         clocks = <&cpg CPG_MOD 908>;
 198                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 199                         resets = <&cpg 908>;
 200                 };
 201
 202                 gpio5: gpio@e6055000 {
 203                         compatible = "renesas,gpio-r8a774c0",
 204                                      "renesas,rcar-gen3-gpio";
 205                         reg = <0 0xe6055000 0 0x50>;
 206                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 207                         #gpio-cells = <2>;
 208                         gpio-controller;
 209                         gpio-ranges = <&pfc 0 160 20>;
 210                         #interrupt-cells = <2>;
 211                         interrupt-controller;
 212                         clocks = <&cpg CPG_MOD 907>;
 213                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 214                         resets = <&cpg 907>;
 215                 };
 216
 217                 gpio6: gpio@e6055400 {
 218                         compatible = "renesas,gpio-r8a774c0",
 219                                      "renesas,rcar-gen3-gpio";
 220                         reg = <0 0xe6055400 0 0x50>;
 221                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 222                         #gpio-cells = <2>;
 223                         gpio-controller;
 224                         gpio-ranges = <&pfc 0 192 18>;
 225                         #interrupt-cells = <2>;
 226                         interrupt-controller;
 227                         clocks = <&cpg CPG_MOD 906>;
 228                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 229                         resets = <&cpg 906>;
 230                 };
 231
 232                 pfc: pin-controller@e6060000 {
 233                         compatible = "renesas,pfc-r8a774c0";
 234                         reg = <0 0xe6060000 0 0x508>;
 235                 };
 236
 237                 cpg: clock-controller@e6150000 {
 238                         compatible = "renesas,r8a774c0-cpg-mssr";
 239                         reg = <0 0xe6150000 0 0x1000>;
 240                         clocks = <&extal_clk>;
 241                         clock-names = "extal";
 242                         #clock-cells = <2>;
 243                         #power-domain-cells = <0>;
 244                         #reset-cells = <1>;
 245                 };
 246
 247                 rst: reset-controller@e6160000 {
 248                         compatible = "renesas,r8a774c0-rst";
 249                         reg = <0 0xe6160000 0 0x0200>;
 250                 };
 251
 252                 sysc: system-controller@e6180000 {
 253                         compatible = "renesas,r8a774c0-sysc";
 254                         reg = <0 0xe6180000 0 0x0400>;
 255                         #power-domain-cells = <1>;
 256                 };
 257
 258                 thermal: thermal@e6190000 {
 259                         compatible = "renesas,thermal-r8a774c0";
 260                         reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
 261                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 262                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 263                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 264                         clocks = <&cpg CPG_MOD 522>;
 265                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 266                         resets = <&cpg 522>;
 267                         #thermal-sensor-cells = <0>;
 268                 };
 269
 270                 intc_ex: interrupt-controller@e61c0000 {
 271                         compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc";
 272                         #interrupt-cells = <2>;
 273                         interrupt-controller;
 274                         reg = <0 0xe61c0000 0 0x200>;
 275                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 276                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 277                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 278                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 279                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 280                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 281                         clocks = <&cpg CPG_MOD 407>;
 282                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 283                         resets = <&cpg 407>;
 284                 };
 285
 286                 i2c0: i2c@e6500000 {
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         compatible = "renesas,i2c-r8a774c0",
 290                                      "renesas,rcar-gen3-i2c";
 291                         reg = <0 0xe6500000 0 0x40>;
 292                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 293                         clocks = <&cpg CPG_MOD 931>;
 294                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 295                         resets = <&cpg 931>;
 296                         dmas = <&dmac1 0x91>, <&dmac1 0x90>,
 297                                <&dmac2 0x91>, <&dmac2 0x90>;
 298                         dma-names = "tx", "rx", "tx", "rx";
 299                         i2c-scl-internal-delay-ns = <110>;
 300                         status = "disabled";
 301                 };
 302
 303                 i2c1: i2c@e6508000 {
 304                         #address-cells = <1>;
 305                         #size-cells = <0>;
 306                         compatible = "renesas,i2c-r8a774c0",
 307                                      "renesas,rcar-gen3-i2c";
 308                         reg = <0 0xe6508000 0 0x40>;
 309                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 310                         clocks = <&cpg CPG_MOD 930>;
 311                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 312                         resets = <&cpg 930>;
 313                         dmas = <&dmac1 0x93>, <&dmac1 0x92>,
 314                                <&dmac2 0x93>, <&dmac2 0x92>;
 315                         dma-names = "tx", "rx", "tx", "rx";
 316                         i2c-scl-internal-delay-ns = <6>;
 317                         status = "disabled";
 318                 };
 319
 320                 i2c2: i2c@e6510000 {
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                         compatible = "renesas,i2c-r8a774c0",
 324                                      "renesas,rcar-gen3-i2c";
 325                         reg = <0 0xe6510000 0 0x40>;
 326                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 327                         clocks = <&cpg CPG_MOD 929>;
 328                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 329                         resets = <&cpg 929>;
 330                         dmas = <&dmac1 0x95>, <&dmac1 0x94>,
 331                                <&dmac2 0x95>, <&dmac2 0x94>;
 332                         dma-names = "tx", "rx", "tx", "rx";
 333                         i2c-scl-internal-delay-ns = <6>;
 334                         status = "disabled";
 335                 };
 336
 337                 i2c3: i2c@e66d0000 {
 338                         #address-cells = <1>;
 339                         #size-cells = <0>;
 340                         compatible = "renesas,i2c-r8a774c0",
 341                                      "renesas,rcar-gen3-i2c";
 342                         reg = <0 0xe66d0000 0 0x40>;
 343                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 344                         clocks = <&cpg CPG_MOD 928>;
 345                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 346                         resets = <&cpg 928>;
 347                         dmas = <&dmac0 0x97>, <&dmac0 0x96>;
 348                         dma-names = "tx", "rx";
 349                         i2c-scl-internal-delay-ns = <110>;
 350                         status = "disabled";
 351                 };
 352
 353                 i2c4: i2c@e66d8000 {
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                         compatible = "renesas,i2c-r8a774c0",
 357                                      "renesas,rcar-gen3-i2c";
 358                         reg = <0 0xe66d8000 0 0x40>;
 359                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 360                         clocks = <&cpg CPG_MOD 927>;
 361                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 362                         resets = <&cpg 927>;
 363                         dmas = <&dmac0 0x99>, <&dmac0 0x98>;
 364                         dma-names = "tx", "rx";
 365                         i2c-scl-internal-delay-ns = <6>;
 366                         status = "disabled";
 367                 };
 368
 369                 i2c5: i2c@e66e0000 {
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         compatible = "renesas,i2c-r8a774c0",
 373                                      "renesas,rcar-gen3-i2c";
 374                         reg = <0 0xe66e0000 0 0x40>;
 375                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 376                         clocks = <&cpg CPG_MOD 919>;
 377                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 378                         resets = <&cpg 919>;
 379                         dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
 380                         dma-names = "tx", "rx";
 381                         i2c-scl-internal-delay-ns = <6>;
 382                         status = "disabled";
 383                 };
 384
 385                 i2c6: i2c@e66e8000 {
 386                         #address-cells = <1>;
 387                         #size-cells = <0>;
 388                         compatible = "renesas,i2c-r8a774c0",
 389                                      "renesas,rcar-gen3-i2c";
 390                         reg = <0 0xe66e8000 0 0x40>;
 391                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 392                         clocks = <&cpg CPG_MOD 918>;
 393                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 394                         resets = <&cpg 918>;
 395                         dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
 396                         dma-names = "tx", "rx";
 397                         i2c-scl-internal-delay-ns = <6>;
 398                         status = "disabled";
 399                 };
 400
 401                 i2c7: i2c@e6690000 {
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         compatible = "renesas,i2c-r8a774c0",
 405                                      "renesas,rcar-gen3-i2c";
 406                         reg = <0 0xe6690000 0 0x40>;
 407                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 408                         clocks = <&cpg CPG_MOD 1003>;
 409                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 410                         resets = <&cpg 1003>;
 411                         i2c-scl-internal-delay-ns = <6>;
 412                         status = "disabled";
 413                 };
 414
 415                 i2c_dvfs: i2c@e60b0000 {
 416                         #address-cells = <1>;
 417                         #size-cells = <0>;
 418                         compatible = "renesas,iic-r8a774c0";
 419                         reg = <0 0xe60b0000 0 0x15>;
 420                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&cpg CPG_MOD 926>;
 422                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 423                         resets = <&cpg 926>;
 424                         dmas = <&dmac0 0x11>, <&dmac0 0x10>;
 425                         dma-names = "tx", "rx";
 426                         status = "disabled";
 427                 };
 428
 429                 hscif0: serial@e6540000 {
 430                         compatible = "renesas,hscif-r8a774c0",
 431                                      "renesas,rcar-gen3-hscif",
 432                                      "renesas,hscif";
 433                         reg = <0 0xe6540000 0 0x60>;
 434                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 435                         clocks = <&cpg CPG_MOD 520>,
 436                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 437                                  <&scif_clk>;
 438                         clock-names = "fck", "brg_int", "scif_clk";
 439                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 440                                <&dmac2 0x31>, <&dmac2 0x30>;
 441                         dma-names = "tx", "rx", "tx", "rx";
 442                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 443                         resets = <&cpg 520>;
 444                         status = "disabled";
 445                 };
 446
 447                 hscif1: serial@e6550000 {
 448                         compatible = "renesas,hscif-r8a774c0",
 449                                      "renesas,rcar-gen3-hscif",
 450                                      "renesas,hscif";
 451                         reg = <0 0xe6550000 0 0x60>;
 452                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 453                         clocks = <&cpg CPG_MOD 519>,
 454                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 455                                  <&scif_clk>;
 456                         clock-names = "fck", "brg_int", "scif_clk";
 457                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 458                                <&dmac2 0x33>, <&dmac2 0x32>;
 459                         dma-names = "tx", "rx", "tx", "rx";
 460                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 461                         resets = <&cpg 519>;
 462                         status = "disabled";
 463                 };
 464
 465                 hscif2: serial@e6560000 {
 466                         compatible = "renesas,hscif-r8a774c0",
 467                                      "renesas,rcar-gen3-hscif",
 468                                      "renesas,hscif";
 469                         reg = <0 0xe6560000 0 0x60>;
 470                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 471                         clocks = <&cpg CPG_MOD 518>,
 472                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 473                                  <&scif_clk>;
 474                         clock-names = "fck", "brg_int", "scif_clk";
 475                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 476                                <&dmac2 0x35>, <&dmac2 0x34>;
 477                         dma-names = "tx", "rx", "tx", "rx";
 478                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 479                         resets = <&cpg 518>;
 480                         status = "disabled";
 481                 };
 482
 483                 hscif3: serial@e66a0000 {
 484                         compatible = "renesas,hscif-r8a774c0",
 485                                      "renesas,rcar-gen3-hscif",
 486                                      "renesas,hscif";
 487                         reg = <0 0xe66a0000 0 0x60>;
 488                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 489                         clocks = <&cpg CPG_MOD 517>,
 490                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 491                                  <&scif_clk>;
 492                         clock-names = "fck", "brg_int", "scif_clk";
 493                         dmas = <&dmac0 0x37>, <&dmac0 0x36>;
 494                         dma-names = "tx", "rx";
 495                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 496                         resets = <&cpg 517>;
 497                         status = "disabled";
 498                 };
 499
 500                 hscif4: serial@e66b0000 {
 501                         compatible = "renesas,hscif-r8a774c0",
 502                                      "renesas,rcar-gen3-hscif",
 503                                      "renesas,hscif";
 504                         reg = <0 0xe66b0000 0 0x60>;
 505                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 506                         clocks = <&cpg CPG_MOD 516>,
 507                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 508                                  <&scif_clk>;
 509                         clock-names = "fck", "brg_int", "scif_clk";
 510                         dmas = <&dmac0 0x39>, <&dmac0 0x38>;
 511                         dma-names = "tx", "rx";
 512                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 513                         resets = <&cpg 516>;
 514                         status = "disabled";
 515                 };
 516
 517                 dmac0: dma-controller@e6700000 {
 518                         compatible = "renesas,dmac-r8a774c0",
 519                                      "renesas,rcar-dmac";
 520                         reg = <0 0xe6700000 0 0x10000>;
 521                         interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
 522                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 523                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 524                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 525                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 526                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 527                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 528                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 529                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 530                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 531                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 532                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 533                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 534                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 535                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 536                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
 537                                       GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 538                         interrupt-names = "error",
 539                                         "ch0", "ch1", "ch2", "ch3",
 540                                         "ch4", "ch5", "ch6", "ch7",
 541                                         "ch8", "ch9", "ch10", "ch11",
 542                                         "ch12", "ch13", "ch14", "ch15";
 543                         clocks = <&cpg CPG_MOD 219>;
 544                         clock-names = "fck";
 545                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 546                         resets = <&cpg 219>;
 547                         #dma-cells = <1>;
 548                         dma-channels = <16>;
 549                 };
 550
 551                 dmac1: dma-controller@e7300000 {
 552                         compatible = "renesas,dmac-r8a774c0",
 553                                      "renesas,rcar-dmac";
 554                         reg = <0 0xe7300000 0 0x10000>;
 555                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 556                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 557                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 558                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 559                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 560                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 561                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 562                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 563                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 564                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 565                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 566                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 567                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 568                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 569                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 570                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 571                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 572                         interrupt-names = "error",
 573                                         "ch0", "ch1", "ch2", "ch3",
 574                                         "ch4", "ch5", "ch6", "ch7",
 575                                         "ch8", "ch9", "ch10", "ch11",
 576                                         "ch12", "ch13", "ch14", "ch15";
 577                         clocks = <&cpg CPG_MOD 218>;
 578                         clock-names = "fck";
 579                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 580                         resets = <&cpg 218>;
 581                         #dma-cells = <1>;
 582                         dma-channels = <16>;
 583                 };
 584
 585                 dmac2: dma-controller@e7310000 {
 586                         compatible = "renesas,dmac-r8a774c0",
 587                                      "renesas,rcar-dmac";
 588                         reg = <0 0xe7310000 0 0x10000>;
 589                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
 590                                       GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
 591                                       GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
 592                                       GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
 593                                       GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
 594                                       GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
 595                                       GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
 596                                       GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
 597                                       GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
 598                                       GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
 599                                       GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
 600                                       GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
 601                                       GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
 602                                       GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
 603                                       GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
 604                                       GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
 605                                       GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 606                         interrupt-names = "error",
 607                                         "ch0", "ch1", "ch2", "ch3",
 608                                         "ch4", "ch5", "ch6", "ch7",
 609                                         "ch8", "ch9", "ch10", "ch11",
 610                                         "ch12", "ch13", "ch14", "ch15";
 611                         clocks = <&cpg CPG_MOD 217>;
 612                         clock-names = "fck";
 613                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 614                         resets = <&cpg 217>;
 615                         #dma-cells = <1>;
 616                         dma-channels = <16>;
 617                 };
 618
 619                 ipmmu_ds0: mmu@e6740000 {
 620                         compatible = "renesas,ipmmu-r8a774c0";
 621                         reg = <0 0xe6740000 0 0x1000>;
 622                         renesas,ipmmu-main = <&ipmmu_mm 0>;
 623                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 624                         #iommu-cells = <1>;
 625                 };
 626
 627                 ipmmu_ds1: mmu@e7740000 {
 628                         compatible = "renesas,ipmmu-r8a774c0";
 629                         reg = <0 0xe7740000 0 0x1000>;
 630                         renesas,ipmmu-main = <&ipmmu_mm 1>;
 631                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 632                         #iommu-cells = <1>;
 633                 };
 634
 635                 ipmmu_hc: mmu@e6570000 {
 636                         compatible = "renesas,ipmmu-r8a774c0";
 637                         reg = <0 0xe6570000 0 0x1000>;
 638                         renesas,ipmmu-main = <&ipmmu_mm 2>;
 639                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 640                         #iommu-cells = <1>;
 641                 };
 642
 643                 ipmmu_mm: mmu@e67b0000 {
 644                         compatible = "renesas,ipmmu-r8a774c0";
 645                         reg = <0 0xe67b0000 0 0x1000>;
 646                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 647                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 648                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 649                         #iommu-cells = <1>;
 650                 };
 651
 652                 ipmmu_mp: mmu@ec670000 {
 653                         compatible = "renesas,ipmmu-r8a774c0";
 654                         reg = <0 0xec670000 0 0x1000>;
 655                         renesas,ipmmu-main = <&ipmmu_mm 4>;
 656                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 657                         #iommu-cells = <1>;
 658                 };
 659
 660                 ipmmu_pv0: mmu@fd800000 {
 661                         compatible = "renesas,ipmmu-r8a774c0";
 662                         reg = <0 0xfd800000 0 0x1000>;
 663                         renesas,ipmmu-main = <&ipmmu_mm 6>;
 664                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 665                         #iommu-cells = <1>;
 666                 };
 667
 668                 ipmmu_vc0: mmu@fe6b0000 {
 669                         compatible = "renesas,ipmmu-r8a774c0";
 670                         reg = <0 0xfe6b0000 0 0x1000>;
 671                         renesas,ipmmu-main = <&ipmmu_mm 12>;
 672                         power-domains = <&sysc R8A774C0_PD_A3VC>;
 673                         #iommu-cells = <1>;
 674                 };
 675
 676                 ipmmu_vi0: mmu@febd0000 {
 677                         compatible = "renesas,ipmmu-r8a774c0";
 678                         reg = <0 0xfebd0000 0 0x1000>;
 679                         renesas,ipmmu-main = <&ipmmu_mm 14>;
 680                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 681                         #iommu-cells = <1>;
 682                 };
 683
 684                 ipmmu_vp0: mmu@fe990000 {
 685                         compatible = "renesas,ipmmu-r8a774c0";
 686                         reg = <0 0xfe990000 0 0x1000>;
 687                         renesas,ipmmu-main = <&ipmmu_mm 16>;
 688                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 689                         #iommu-cells = <1>;
 690                 };
 691
 692                 avb: ethernet@e6800000 {
 693                         compatible = "renesas,etheravb-r8a774c0",
 694                                      "renesas,etheravb-rcar-gen3";
 695                         reg = <0 0xe6800000 0 0x800>;
 696                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 697                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 698                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 699                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 700                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 701                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 702                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 703                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 704                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 706                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 707                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 708                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 709                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 710                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 711                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 712                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 713                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 714                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 715                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 716                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 717                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 718                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 719                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 720                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 721                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 722                                           "ch4", "ch5", "ch6", "ch7",
 723                                           "ch8", "ch9", "ch10", "ch11",
 724                                           "ch12", "ch13", "ch14", "ch15",
 725                                           "ch16", "ch17", "ch18", "ch19",
 726                                           "ch20", "ch21", "ch22", "ch23",
 727                                           "ch24";
 728                         clocks = <&cpg CPG_MOD 812>;
 729                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 730                         resets = <&cpg 812>;
 731                         phy-mode = "rgmii";
 732                         #address-cells = <1>;
 733                         #size-cells = <0>;
 734                         status = "disabled";
 735                 };
 736
 737                 can0: can@e6c30000 {
 738                         compatible = "renesas,can-r8a774c0",
 739                                      "renesas,rcar-gen3-can";
 740                         reg = <0 0xe6c30000 0 0x1000>;
 741                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 742                         clocks = <&cpg CPG_MOD 916>, <&can_clk>;
 743                         clock-names = "clkp1", "can_clk";
 744                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 745                         resets = <&cpg 916>;
 746                         status = "disabled";
 747                 };
 748
 749                 can1: can@e6c38000 {
 750                         compatible = "renesas,can-r8a774c0",
 751                                      "renesas,rcar-gen3-can";
 752                         reg = <0 0xe6c38000 0 0x1000>;
 753                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 754                         clocks = <&cpg CPG_MOD 915>, <&can_clk>;
 755                         clock-names = "clkp1", "can_clk";
 756                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 757                         resets = <&cpg 915>;
 758                         status = "disabled";
 759                 };
 760
 761                 pwm0: pwm@e6e30000 {
 762                         compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
 763                         reg = <0 0xe6e30000 0 0x8>;
 764                         clocks = <&cpg CPG_MOD 523>;
 765                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 766                         resets = <&cpg 523>;
 767                         #pwm-cells = <2>;
 768                         status = "disabled";
 769                 };
 770
 771                 pwm1: pwm@e6e31000 {
 772                         compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
 773                         reg = <0 0xe6e31000 0 0x8>;
 774                         clocks = <&cpg CPG_MOD 523>;
 775                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 776                         resets = <&cpg 523>;
 777                         #pwm-cells = <2>;
 778                         status = "disabled";
 779                 };
 780
 781                 pwm2: pwm@e6e32000 {
 782                         compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
 783                         reg = <0 0xe6e32000 0 0x8>;
 784                         clocks = <&cpg CPG_MOD 523>;
 785                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 786                         resets = <&cpg 523>;
 787                         #pwm-cells = <2>;
 788                         status = "disabled";
 789                 };
 790
 791                 pwm3: pwm@e6e33000 {
 792                         compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
 793                         reg = <0 0xe6e33000 0 0x8>;
 794                         clocks = <&cpg CPG_MOD 523>;
 795                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 796                         resets = <&cpg 523>;
 797                         #pwm-cells = <2>;
 798                         status = "disabled";
 799                 };
 800
 801                 pwm4: pwm@e6e34000 {
 802                         compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
 803                         reg = <0 0xe6e34000 0 0x8>;
 804                         clocks = <&cpg CPG_MOD 523>;
 805                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 806                         resets = <&cpg 523>;
 807                         #pwm-cells = <2>;
 808                         status = "disabled";
 809                 };
 810
 811                 pwm5: pwm@e6e35000 {
 812                         compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
 813                         reg = <0 0xe6e35000 0 0x8>;
 814                         clocks = <&cpg CPG_MOD 523>;
 815                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 816                         resets = <&cpg 523>;
 817                         #pwm-cells = <2>;
 818                         status = "disabled";
 819                 };
 820
 821                 pwm6: pwm@e6e36000 {
 822                         compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar";
 823                         reg = <0 0xe6e36000 0 0x8>;
 824                         clocks = <&cpg CPG_MOD 523>;
 825                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 826                         resets = <&cpg 523>;
 827                         #pwm-cells = <2>;
 828                         status = "disabled";
 829                 };
 830
 831                 scif0: serial@e6e60000 {
 832                         compatible = "renesas,scif-r8a774c0",
 833                                      "renesas,rcar-gen3-scif", "renesas,scif";
 834                         reg = <0 0xe6e60000 0 64>;
 835                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 836                         clocks = <&cpg CPG_MOD 207>,
 837                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 838                                  <&scif_clk>;
 839                         clock-names = "fck", "brg_int", "scif_clk";
 840                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 841                                <&dmac2 0x51>, <&dmac2 0x50>;
 842                         dma-names = "tx", "rx", "tx", "rx";
 843                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 844                         resets = <&cpg 207>;
 845                         status = "disabled";
 846                 };
 847
 848                 scif1: serial@e6e68000 {
 849                         compatible = "renesas,scif-r8a774c0",
 850                                      "renesas,rcar-gen3-scif", "renesas,scif";
 851                         reg = <0 0xe6e68000 0 64>;
 852                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 853                         clocks = <&cpg CPG_MOD 206>,
 854                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 855                                  <&scif_clk>;
 856                         clock-names = "fck", "brg_int", "scif_clk";
 857                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 858                                <&dmac2 0x53>, <&dmac2 0x52>;
 859                         dma-names = "tx", "rx", "tx", "rx";
 860                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 861                         resets = <&cpg 206>;
 862                         status = "disabled";
 863                 };
 864
 865                 scif2: serial@e6e88000 {
 866                         compatible = "renesas,scif-r8a774c0",
 867                                      "renesas,rcar-gen3-scif", "renesas,scif";
 868                         reg = <0 0xe6e88000 0 64>;
 869                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 870                         clocks = <&cpg CPG_MOD 310>,
 871                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 872                                  <&scif_clk>;
 873                         clock-names = "fck", "brg_int", "scif_clk";
 874                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 875                         resets = <&cpg 310>;
 876                         status = "disabled";
 877                 };
 878
 879                 scif3: serial@e6c50000 {
 880                         compatible = "renesas,scif-r8a774c0",
 881                                      "renesas,rcar-gen3-scif", "renesas,scif";
 882                         reg = <0 0xe6c50000 0 64>;
 883                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 884                         clocks = <&cpg CPG_MOD 204>,
 885                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 886                                  <&scif_clk>;
 887                         clock-names = "fck", "brg_int", "scif_clk";
 888                         dmas = <&dmac0 0x57>, <&dmac0 0x56>;
 889                         dma-names = "tx", "rx";
 890                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 891                         resets = <&cpg 204>;
 892                         status = "disabled";
 893                 };
 894
 895                 scif4: serial@e6c40000 {
 896                         compatible = "renesas,scif-r8a774c0",
 897                                      "renesas,rcar-gen3-scif", "renesas,scif";
 898                         reg = <0 0xe6c40000 0 64>;
 899                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 900                         clocks = <&cpg CPG_MOD 203>,
 901                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 902                                  <&scif_clk>;
 903                         clock-names = "fck", "brg_int", "scif_clk";
 904                         dmas = <&dmac0 0x59>, <&dmac0 0x58>;
 905                         dma-names = "tx", "rx";
 906                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 907                         resets = <&cpg 203>;
 908                         status = "disabled";
 909                 };
 910
 911                 scif5: serial@e6f30000 {
 912                         compatible = "renesas,scif-r8a774c0",
 913                                      "renesas,rcar-gen3-scif", "renesas,scif";
 914                         reg = <0 0xe6f30000 0 64>;
 915                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 916                         clocks = <&cpg CPG_MOD 202>,
 917                                  <&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
 918                                  <&scif_clk>;
 919                         clock-names = "fck", "brg_int", "scif_clk";
 920                         dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
 921                                <&dmac2 0x5b>, <&dmac2 0x5a>;
 922                         dma-names = "tx", "rx", "tx", "rx";
 923                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 924                         resets = <&cpg 202>;
 925                         status = "disabled";
 926                 };
 927
 928                 msiof0: spi@e6e90000 {
 929                         compatible = "renesas,msiof-r8a774c0",
 930                                      "renesas,rcar-gen3-msiof";
 931                         reg = <0 0xe6e90000 0 0x0064>;
 932                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 933                         clocks = <&cpg CPG_MOD 211>;
 934                         dmas = <&dmac1 0x41>, <&dmac1 0x40>,
 935                                <&dmac2 0x41>, <&dmac2 0x40>;
 936                         dma-names = "tx", "rx", "tx", "rx";
 937                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 938                         resets = <&cpg 211>;
 939                         #address-cells = <1>;
 940                         #size-cells = <0>;
 941                         status = "disabled";
 942                 };
 943
 944                 msiof1: spi@e6ea0000 {
 945                         compatible = "renesas,msiof-r8a774c0",
 946                                      "renesas,rcar-gen3-msiof";
 947                         reg = <0 0xe6ea0000 0 0x0064>;
 948                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 949                         clocks = <&cpg CPG_MOD 210>;
 950                         dmas = <&dmac1 0x43>, <&dmac1 0x42>,
 951                                <&dmac2 0x43>, <&dmac2 0x42>;
 952                         dma-names = "tx", "rx", "tx", "rx";
 953                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 954                         resets = <&cpg 210>;
 955                         #address-cells = <1>;
 956                         #size-cells = <0>;
 957                         status = "disabled";
 958                 };
 959
 960                 msiof2: spi@e6c00000 {
 961                         compatible = "renesas,msiof-r8a774c0",
 962                                      "renesas,rcar-gen3-msiof";
 963                         reg = <0 0xe6c00000 0 0x0064>;
 964                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 965                         clocks = <&cpg CPG_MOD 209>;
 966                         dmas = <&dmac0 0x45>, <&dmac0 0x44>;
 967                         dma-names = "tx", "rx";
 968                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 969                         resets = <&cpg 209>;
 970                         #address-cells = <1>;
 971                         #size-cells = <0>;
 972                         status = "disabled";
 973                 };
 974
 975                 msiof3: spi@e6c10000 {
 976                         compatible = "renesas,msiof-r8a774c0",
 977                                      "renesas,rcar-gen3-msiof";
 978                         reg = <0 0xe6c10000 0 0x0064>;
 979                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 980                         clocks = <&cpg CPG_MOD 208>;
 981                         dmas = <&dmac0 0x47>, <&dmac0 0x46>;
 982                         dma-names = "tx", "rx";
 983                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
 984                         resets = <&cpg 208>;
 985                         #address-cells = <1>;
 986                         #size-cells = <0>;
 987                         status = "disabled";
 988                 };
 989
 990                 rcar_sound: sound@ec500000 {
 991                         /*
 992                          * #sound-dai-cells is required
 993                          *
 994                          * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
 995                          * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
 996                          */
 997                         /*
 998                          * #clock-cells is required for audio_clkout0/1/2/3
 999                          *
1000                          * clkout       : #clock-cells = <0>;   <&rcar_sound>;
1001                          * clkout0/1/2/3: #clock-cells = <1>;   <&rcar_sound N>;
1002                          */
1003                         compatible = "renesas,rcar_sound-r8a774c0",
1004                                      "renesas,rcar_sound-gen3";
1005                         reg =   <0 0xec500000 0 0x1000>, /* SCU */
1006                                 <0 0xec5a0000 0 0x100>,  /* ADG */
1007                                 <0 0xec540000 0 0x1000>, /* SSIU */
1008                                 <0 0xec541000 0 0x280>,  /* SSI */
1009                                 <0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
1010                         reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1011
1012                         clocks = <&cpg CPG_MOD 1005>,
1013                                  <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1014                                  <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1015                                  <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1016                                  <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1017                                  <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1018                                  <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1019                                  <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1020                                  <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1021                                  <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1022                                  <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1023                                  <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1024                                  <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1025                                  <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1026                                  <&audio_clk_a>, <&audio_clk_b>,
1027                                  <&audio_clk_c>,
1028                                  <&cpg CPG_CORE R8A774C0_CLK_ZA2>;
1029                         clock-names = "ssi-all",
1030                                       "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1031                                       "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1032                                       "ssi.1", "ssi.0",
1033                                       "src.9", "src.8", "src.7", "src.6",
1034                                       "src.5", "src.4", "src.3", "src.2",
1035                                       "src.1", "src.0",
1036                                       "mix.1", "mix.0",
1037                                       "ctu.1", "ctu.0",
1038                                       "dvc.0", "dvc.1",
1039                                       "clk_a", "clk_b", "clk_c", "clk_i";
1040                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1041                         resets = <&cpg 1005>,
1042                                  <&cpg 1006>, <&cpg 1007>,
1043                                  <&cpg 1008>, <&cpg 1009>,
1044                                  <&cpg 1010>, <&cpg 1011>,
1045                                  <&cpg 1012>, <&cpg 1013>,
1046                                  <&cpg 1014>, <&cpg 1015>;
1047                         reset-names = "ssi-all",
1048                                       "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1049                                       "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1050                                       "ssi.1", "ssi.0";
1051                         status = "disabled";
1052
1053                         rcar_sound,dvc {
1054                                 dvc0: dvc-0 {
1055                                         dmas = <&audma0 0xbc>;
1056                                         dma-names = "tx";
1057                                 };
1058                                 dvc1: dvc-1 {
1059                                         dmas = <&audma0 0xbe>;
1060                                         dma-names = "tx";
1061                                 };
1062                         };
1063
1064                         rcar_sound,mix {
1065                                 mix0: mix-0 { };
1066                                 mix1: mix-1 { };
1067                         };
1068
1069                         rcar_sound,ctu {
1070                                 ctu00: ctu-0 { };
1071                                 ctu01: ctu-1 { };
1072                                 ctu02: ctu-2 { };
1073                                 ctu03: ctu-3 { };
1074                                 ctu10: ctu-4 { };
1075                                 ctu11: ctu-5 { };
1076                                 ctu12: ctu-6 { };
1077                                 ctu13: ctu-7 { };
1078                         };
1079
1080                         rcar_sound,src {
1081                                 src0: src-0 {
1082                                         interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1083                                         dmas = <&audma0 0x85>, <&audma0 0x9a>;
1084                                         dma-names = "rx", "tx";
1085                                 };
1086                                 src1: src-1 {
1087                                         interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1088                                         dmas = <&audma0 0x87>, <&audma0 0x9c>;
1089                                         dma-names = "rx", "tx";
1090                                 };
1091                                 src2: src-2 {
1092                                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1093                                         dmas = <&audma0 0x89>, <&audma0 0x9e>;
1094                                         dma-names = "rx", "tx";
1095                                 };
1096                                 src3: src-3 {
1097                                         interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1098                                         dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1099                                         dma-names = "rx", "tx";
1100                                 };
1101                                 src4: src-4 {
1102                                         interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1103                                         dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1104                                         dma-names = "rx", "tx";
1105                                 };
1106                                 src5: src-5 {
1107                                         interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1108                                         dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1109                                         dma-names = "rx", "tx";
1110                                 };
1111                                 src6: src-6 {
1112                                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1113                                         dmas = <&audma0 0x91>, <&audma0 0xb4>;
1114                                         dma-names = "rx", "tx";
1115                                 };
1116                                 src7: src-7 {
1117                                         interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1118                                         dmas = <&audma0 0x93>, <&audma0 0xb6>;
1119                                         dma-names = "rx", "tx";
1120                                 };
1121                                 src8: src-8 {
1122                                         interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1123                                         dmas = <&audma0 0x95>, <&audma0 0xb8>;
1124                                         dma-names = "rx", "tx";
1125                                 };
1126                                 src9: src-9 {
1127                                         interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1128                                         dmas = <&audma0 0x97>, <&audma0 0xba>;
1129                                         dma-names = "rx", "tx";
1130                                 };
1131                         };
1132
1133                         rcar_sound,ssi {
1134                                 ssi0: ssi-0 {
1135                                         interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1136                                         dmas = <&audma0 0x01>, <&audma0 0x02>,
1137                                                <&audma0 0x15>, <&audma0 0x16>;
1138                                         dma-names = "rx", "tx", "rxu", "txu";
1139                                 };
1140                                 ssi1: ssi-1 {
1141                                         interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1142                                         dmas = <&audma0 0x03>, <&audma0 0x04>,
1143                                                <&audma0 0x49>, <&audma0 0x4a>;
1144                                         dma-names = "rx", "tx", "rxu", "txu";
1145                                 };
1146                                 ssi2: ssi-2 {
1147                                         interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1148                                         dmas = <&audma0 0x05>, <&audma0 0x06>,
1149                                                <&audma0 0x63>, <&audma0 0x64>;
1150                                         dma-names = "rx", "tx", "rxu", "txu";
1151                                 };
1152                                 ssi3: ssi-3 {
1153                                         interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1154                                         dmas = <&audma0 0x07>, <&audma0 0x08>,
1155                                                <&audma0 0x6f>, <&audma0 0x70>;
1156                                         dma-names = "rx", "tx", "rxu", "txu";
1157                                 };
1158                                 ssi4: ssi-4 {
1159                                         interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1160                                         dmas = <&audma0 0x09>, <&audma0 0x0a>,
1161                                                <&audma0 0x71>, <&audma0 0x72>;
1162                                         dma-names = "rx", "tx", "rxu", "txu";
1163                                 };
1164                                 ssi5: ssi-5 {
1165                                         interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1166                                         dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1167                                                <&audma0 0x73>, <&audma0 0x74>;
1168                                         dma-names = "rx", "tx", "rxu", "txu";
1169                                 };
1170                                 ssi6: ssi-6 {
1171                                         interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1172                                         dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1173                                                <&audma0 0x75>, <&audma0 0x76>;
1174                                         dma-names = "rx", "tx", "rxu", "txu";
1175                                 };
1176                                 ssi7: ssi-7 {
1177                                         interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1178                                         dmas = <&audma0 0x0f>, <&audma0 0x10>,
1179                                                <&audma0 0x79>, <&audma0 0x7a>;
1180                                         dma-names = "rx", "tx", "rxu", "txu";
1181                                 };
1182                                 ssi8: ssi-8 {
1183                                         interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1184                                         dmas = <&audma0 0x11>, <&audma0 0x12>,
1185                                                <&audma0 0x7b>, <&audma0 0x7c>;
1186                                         dma-names = "rx", "tx", "rxu", "txu";
1187                                 };
1188                                 ssi9: ssi-9 {
1189                                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1190                                         dmas = <&audma0 0x13>, <&audma0 0x14>,
1191                                                <&audma0 0x7d>, <&audma0 0x7e>;
1192                                         dma-names = "rx", "tx", "rxu", "txu";
1193                                 };
1194                         };
1195                 };
1196
1197                 audma0: dma-controller@ec700000 {
1198                         compatible = "renesas,dmac-r8a774c0",
1199                                      "renesas,rcar-dmac";
1200                         reg = <0 0xec700000 0 0x10000>;
1201                         interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1202                                       GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1203                                       GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1204                                       GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1205                                       GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1206                                       GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1207                                       GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1208                                       GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1209                                       GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1210                                       GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1211                                       GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1212                                       GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1213                                       GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1214                                       GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
1215                                       GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1216                                       GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1217                                       GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1218                         interrupt-names = "error",
1219                                         "ch0", "ch1", "ch2", "ch3",
1220                                         "ch4", "ch5", "ch6", "ch7",
1221                                         "ch8", "ch9", "ch10", "ch11",
1222                                         "ch12", "ch13", "ch14", "ch15";
1223                         clocks = <&cpg CPG_MOD 502>;
1224                         clock-names = "fck";
1225                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1226                         resets = <&cpg 502>;
1227                         #dma-cells = <1>;
1228                         dma-channels = <16>;
1229                 };
1230
1231                 sdhi0: sd@ee100000 {
1232                         compatible = "renesas,sdhi-r8a774c0",
1233                                      "renesas,rcar-gen3-sdhi";
1234                         reg = <0 0xee100000 0 0x2000>;
1235                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1236                         clocks = <&cpg CPG_MOD 314>;
1237                         max-frequency = <200000000>;
1238                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1239                         resets = <&cpg 314>;
1240                         status = "disabled";
1241                 };
1242
1243                 sdhi1: sd@ee120000 {
1244                         compatible = "renesas,sdhi-r8a774c0",
1245                                      "renesas,rcar-gen3-sdhi";
1246                         reg = <0 0xee120000 0 0x2000>;
1247                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1248                         clocks = <&cpg CPG_MOD 313>;
1249                         max-frequency = <200000000>;
1250                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1251                         resets = <&cpg 313>;
1252                         status = "disabled";
1253                 };
1254
1255                 sdhi3: sd@ee160000 {
1256                         compatible = "renesas,sdhi-r8a774c0",
1257                                      "renesas,rcar-gen3-sdhi";
1258                         reg = <0 0xee160000 0 0x2000>;
1259                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1260                         clocks = <&cpg CPG_MOD 311>;
1261                         max-frequency = <200000000>;
1262                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1263                         resets = <&cpg 311>;
1264                         status = "disabled";
1265                 };
1266
1267                 gic: interrupt-controller@f1010000 {
1268                         compatible = "arm,gic-400";
1269                         #interrupt-cells = <3>;
1270                         #address-cells = <0>;
1271                         interrupt-controller;
1272                         reg = <0x0 0xf1010000 0 0x1000>,
1273                               <0x0 0xf1020000 0 0x20000>,
1274                               <0x0 0xf1040000 0 0x20000>,
1275                               <0x0 0xf1060000 0 0x20000>;
1276                         interrupts = <GIC_PPI 9
1277                                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1278                         clocks = <&cpg CPG_MOD 408>;
1279                         clock-names = "clk";
1280                         power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
1281                         resets = <&cpg 408>;
1282                 };
1283
1284                 prr: chipid@fff00044 {
1285                         compatible = "renesas,prr";
1286                         reg = <0 0xfff00044 0 4>;
1287                 };
1288         };
1289
1290         thermal-zones {
1291                 cpu-thermal {
1292                         polling-delay-passive = <250>;
1293                         polling-delay = <1000>;
1294                         thermal-sensors = <&thermal>;
1295
1296                         trips {
1297                                 cpu-crit {
1298                                         temperature = <120000>;
1299                                         hysteresis = <2000>;
1300                                         type = "critical";
1301                                 };
1302                         };
1303
1304                         cooling-maps {
1305                         };
1306                 };
1307         };
1308
1309         timer {
1310                 compatible = "arm,armv8-timer";
1311                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1312                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1313                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1314                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1315         };
1316
1317         /* External USB clocks - can be overridden by the board */
1318         usb3s0_clk: usb3s0 {
1319                 compatible = "fixed-clock";
1320                 #clock-cells = <0>;
1321                 clock-frequency = <0>;
1322         };
1323
1324         usb_extal_clk: usb_extal {
1325                 compatible = "fixed-clock";
1326                 #clock-cells = <0>;
1327                 clock-frequency = <0>;
1328         };
1329 };