arm64: dts: renesas: hihope-common: Add uSD and eMMC
[platform/kernel/linux-starfive.git] / arch / arm64 / boot / dts / renesas / hihope-common.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Device Tree Source for the HiHope RZ/G2[MN] main board common parts
4  *
5  * Copyright (C) 2019 Renesas Electronics Corp.
6  */
7
8 #include <dt-bindings/gpio/gpio.h>
9
10 / {
11         aliases {
12                 serial0 = &scif2;
13         };
14
15         chosen {
16                 bootargs = "ignore_loglevel";
17                 stdout-path = "serial0:115200n8";
18         };
19
20         reg_1p8v: regulator0 {
21                 compatible = "regulator-fixed";
22                 regulator-name = "fixed-1.8V";
23                 regulator-min-microvolt = <1800000>;
24                 regulator-max-microvolt = <1800000>;
25                 regulator-boot-on;
26                 regulator-always-on;
27         };
28
29         reg_3p3v: regulator1 {
30                 compatible = "regulator-fixed";
31                 regulator-name = "fixed-3.3V";
32                 regulator-min-microvolt = <3300000>;
33                 regulator-max-microvolt = <3300000>;
34                 regulator-boot-on;
35                 regulator-always-on;
36         };
37
38         vccq_sdhi0: regulator-vccq-sdhi0 {
39                 compatible = "regulator-gpio";
40
41                 regulator-name = "SDHI0 VccQ";
42                 regulator-min-microvolt = <1800000>;
43                 regulator-max-microvolt = <3300000>;
44
45                 gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
46                 gpios-states = <1>;
47                 states = <3300000 1
48                           1800000 0>;
49         };
50 };
51
52 &extal_clk {
53         clock-frequency = <16666666>;
54 };
55
56 &extalr_clk {
57         clock-frequency = <32768>;
58 };
59
60 &pcie_bus_clk {
61         clock-frequency = <100000000>;
62 };
63
64 &pfc {
65         pinctrl-0 = <&scif_clk_pins>;
66         pinctrl-names = "default";
67
68         scif2_pins: scif2 {
69                 groups = "scif2_data_a";
70                 function = "scif2";
71         };
72
73         scif_clk_pins: scif_clk {
74                 groups = "scif_clk_a";
75                 function = "scif_clk";
76         };
77
78         sdhi0_pins: sd0 {
79                 groups = "sdhi0_data4", "sdhi0_ctrl";
80                 function = "sdhi0";
81                 power-source = <3300>;
82         };
83
84         sdhi0_pins_uhs: sd0_uhs {
85                 groups = "sdhi0_data4", "sdhi0_ctrl";
86                 function = "sdhi0";
87                 power-source = <1800>;
88         };
89
90         sdhi3_pins: sd3 {
91                 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
92                 function = "sdhi3";
93                 power-source = <1800>;
94         };
95 };
96
97 &rwdt {
98         timeout-sec = <60>;
99         status = "okay";
100 };
101
102 &scif2 {
103         pinctrl-0 = <&scif2_pins>;
104         pinctrl-names = "default";
105
106         status = "okay";
107 };
108
109 &scif_clk {
110         clock-frequency = <14745600>;
111 };
112
113 &sdhi0 {
114         pinctrl-0 = <&sdhi0_pins>;
115         pinctrl-1 = <&sdhi0_pins_uhs>;
116         pinctrl-names = "default", "state_uhs";
117
118         vmmc-supply = <&reg_3p3v>;
119         vqmmc-supply = <&vccq_sdhi0>;
120         cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
121         bus-width = <4>;
122         sd-uhs-sdr50;
123         sd-uhs-sdr104;
124         status = "okay";
125 };
126
127 &sdhi3 {
128         pinctrl-0 = <&sdhi3_pins>;
129         pinctrl-1 = <&sdhi3_pins>;
130         pinctrl-names = "default", "state_uhs";
131
132         vmmc-supply = <&reg_3p3v>;
133         vqmmc-supply = <&reg_1p8v>;
134         bus-width = <8>;
135         mmc-hs200-1_8v;
136         non-removable;
137         fixed-emmc-driver-type = <1>;
138         status = "okay";
139 };