arch/arm64/boot/dts/qcom/sm8550.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2022, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/clock/qcom,rpmh.h>
   7 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
   8 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
   9 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
  10 #include <dt-bindings/dma/qcom-gpi.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
  14 #include <dt-bindings/mailbox/qcom-ipcc.h>
  15 #include <dt-bindings/power/qcom-rpmpd.h>
  16 #include <dt-bindings/soc/qcom,gpr.h>
  17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  18 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
  19 #include <dt-bindings/phy/phy-qcom-qmp.h>
  20 #include <dt-bindings/thermal/thermal.h>
  21
  22 / {
  23         interrupt-parent = <&intc>;
  24
  25         #address-cells = <2>;
  26         #size-cells = <2>;
  27
  28         chosen { };
  29
  30         clocks {
  31                 xo_board: xo-board {
  32                         compatible = "fixed-clock";
  33                         #clock-cells = <0>;
  34                 };
  35
  36                 sleep_clk: sleep-clk {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                 };
  40
  41                 bi_tcxo_div2: bi-tcxo-div2-clk {
  42                         #clock-cells = <0>;
  43                         compatible = "fixed-factor-clock";
  44                         clocks = <&rpmhcc RPMH_CXO_CLK>;
  45                         clock-mult = <1>;
  46                         clock-div = <2>;
  47                 };
  48
  49                 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
  50                         #clock-cells = <0>;
  51                         compatible = "fixed-factor-clock";
  52                         clocks = <&rpmhcc RPMH_CXO_CLK_A>;
  53                         clock-mult = <1>;
  54                         clock-div = <2>;
  55                 };
  56
  57                 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
  58                         compatible = "fixed-clock";
  59                         #clock-cells = <0>;
  60                 };
  61         };
  62
  63         cpus {
  64                 #address-cells = <2>;
  65                 #size-cells = <0>;
  66
  67                 CPU0: cpu@0 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a510";
  70                         reg = <0 0>;
  71                         clocks = <&cpufreq_hw 0>;
  72                         enable-method = "psci";
  73                         next-level-cache = <&L2_0>;
  74                         power-domains = <&CPU_PD0>;
  75                         power-domain-names = "psci";
  76                         qcom,freq-domain = <&cpufreq_hw 0>;
  77                         capacity-dmips-mhz = <1024>;
  78                         dynamic-power-coefficient = <100>;
  79                         #cooling-cells = <2>;
  80                         L2_0: l2-cache {
  81                                 compatible = "cache";
  82                                 cache-level = <2>;
  83                                 cache-unified;
  84                                 next-level-cache = <&L3_0>;
  85                                 L3_0: l3-cache {
  86                                         compatible = "cache";
  87                                         cache-level = <3>;
  88                                         cache-unified;
  89                                 };
  90                         };
  91                 };
  92
  93                 CPU1: cpu@100 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a510";
  96                         reg = <0 0x100>;
  97                         clocks = <&cpufreq_hw 0>;
  98                         enable-method = "psci";
  99                         next-level-cache = <&L2_100>;
 100                         power-domains = <&CPU_PD1>;
 101                         power-domain-names = "psci";
 102                         qcom,freq-domain = <&cpufreq_hw 0>;
 103                         capacity-dmips-mhz = <1024>;
 104                         dynamic-power-coefficient = <100>;
 105                         #cooling-cells = <2>;
 106                         L2_100: l2-cache {
 107                                 compatible = "cache";
 108                                 cache-level = <2>;
 109                                 cache-unified;
 110                                 next-level-cache = <&L3_0>;
 111                         };
 112                 };
 113
 114                 CPU2: cpu@200 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a510";
 117                         reg = <0 0x200>;
 118                         clocks = <&cpufreq_hw 0>;
 119                         enable-method = "psci";
 120                         next-level-cache = <&L2_200>;
 121                         power-domains = <&CPU_PD2>;
 122                         power-domain-names = "psci";
 123                         qcom,freq-domain = <&cpufreq_hw 0>;
 124                         capacity-dmips-mhz = <1024>;
 125                         dynamic-power-coefficient = <100>;
 126                         #cooling-cells = <2>;
 127                         L2_200: l2-cache {
 128                                 compatible = "cache";
 129                                 cache-level = <2>;
 130                                 cache-unified;
 131                                 next-level-cache = <&L3_0>;
 132                         };
 133                 };
 134
 135                 CPU3: cpu@300 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a715";
 138                         reg = <0 0x300>;
 139                         clocks = <&cpufreq_hw 1>;
 140                         enable-method = "psci";
 141                         next-level-cache = <&L2_300>;
 142                         power-domains = <&CPU_PD3>;
 143                         power-domain-names = "psci";
 144                         qcom,freq-domain = <&cpufreq_hw 1>;
 145                         capacity-dmips-mhz = <1792>;
 146                         dynamic-power-coefficient = <270>;
 147                         #cooling-cells = <2>;
 148                         L2_300: l2-cache {
 149                                 compatible = "cache";
 150                                 cache-level = <2>;
 151                                 cache-unified;
 152                                 next-level-cache = <&L3_0>;
 153                         };
 154                 };
 155
 156                 CPU4: cpu@400 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a715";
 159                         reg = <0 0x400>;
 160                         clocks = <&cpufreq_hw 1>;
 161                         enable-method = "psci";
 162                         next-level-cache = <&L2_400>;
 163                         power-domains = <&CPU_PD4>;
 164                         power-domain-names = "psci";
 165                         qcom,freq-domain = <&cpufreq_hw 1>;
 166                         capacity-dmips-mhz = <1792>;
 167                         dynamic-power-coefficient = <270>;
 168                         #cooling-cells = <2>;
 169                         L2_400: l2-cache {
 170                                 compatible = "cache";
 171                                 cache-level = <2>;
 172                                 cache-unified;
 173                                 next-level-cache = <&L3_0>;
 174                         };
 175                 };
 176
 177                 CPU5: cpu@500 {
 178                         device_type = "cpu";
 179                         compatible = "arm,cortex-a710";
 180                         reg = <0 0x500>;
 181                         clocks = <&cpufreq_hw 1>;
 182                         enable-method = "psci";
 183                         next-level-cache = <&L2_500>;
 184                         power-domains = <&CPU_PD5>;
 185                         power-domain-names = "psci";
 186                         qcom,freq-domain = <&cpufreq_hw 1>;
 187                         capacity-dmips-mhz = <1792>;
 188                         dynamic-power-coefficient = <270>;
 189                         #cooling-cells = <2>;
 190                         L2_500: l2-cache {
 191                                 compatible = "cache";
 192                                 cache-level = <2>;
 193                                 cache-unified;
 194                                 next-level-cache = <&L3_0>;
 195                         };
 196                 };
 197
 198                 CPU6: cpu@600 {
 199                         device_type = "cpu";
 200                         compatible = "arm,cortex-a710";
 201                         reg = <0 0x600>;
 202                         clocks = <&cpufreq_hw 1>;
 203                         enable-method = "psci";
 204                         next-level-cache = <&L2_600>;
 205                         power-domains = <&CPU_PD6>;
 206                         power-domain-names = "psci";
 207                         qcom,freq-domain = <&cpufreq_hw 1>;
 208                         capacity-dmips-mhz = <1792>;
 209                         dynamic-power-coefficient = <270>;
 210                         #cooling-cells = <2>;
 211                         L2_600: l2-cache {
 212                                 compatible = "cache";
 213                                 cache-level = <2>;
 214                                 cache-unified;
 215                                 next-level-cache = <&L3_0>;
 216                         };
 217                 };
 218
 219                 CPU7: cpu@700 {
 220                         device_type = "cpu";
 221                         compatible = "arm,cortex-x3";
 222                         reg = <0 0x700>;
 223                         clocks = <&cpufreq_hw 2>;
 224                         enable-method = "psci";
 225                         next-level-cache = <&L2_700>;
 226                         power-domains = <&CPU_PD7>;
 227                         power-domain-names = "psci";
 228                         qcom,freq-domain = <&cpufreq_hw 2>;
 229                         capacity-dmips-mhz = <1894>;
 230                         dynamic-power-coefficient = <588>;
 231                         #cooling-cells = <2>;
 232                         L2_700: l2-cache {
 233                                 compatible = "cache";
 234                                 cache-level = <2>;
 235                                 cache-unified;
 236                                 next-level-cache = <&L3_0>;
 237                         };
 238                 };
 239
 240                 cpu-map {
 241                         cluster0 {
 242                                 core0 {
 243                                         cpu = <&CPU0>;
 244                                 };
 245
 246                                 core1 {
 247                                         cpu = <&CPU1>;
 248                                 };
 249
 250                                 core2 {
 251                                         cpu = <&CPU2>;
 252                                 };
 253
 254                                 core3 {
 255                                         cpu = <&CPU3>;
 256                                 };
 257
 258                                 core4 {
 259                                         cpu = <&CPU4>;
 260                                 };
 261
 262                                 core5 {
 263                                         cpu = <&CPU5>;
 264                                 };
 265
 266                                 core6 {
 267                                         cpu = <&CPU6>;
 268                                 };
 269
 270                                 core7 {
 271                                         cpu = <&CPU7>;
 272                                 };
 273                         };
 274                 };
 275
 276                 idle-states {
 277                         entry-method = "psci";
 278
 279                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 280                                 compatible = "arm,idle-state";
 281                                 idle-state-name = "silver-rail-power-collapse";
 282                                 arm,psci-suspend-param = <0x40000004>;
 283                                 entry-latency-us = <800>;
 284                                 exit-latency-us = <750>;
 285                                 min-residency-us = <4090>;
 286                                 local-timer-stop;
 287                         };
 288
 289                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 290                                 compatible = "arm,idle-state";
 291                                 idle-state-name = "gold-rail-power-collapse";
 292                                 arm,psci-suspend-param = <0x40000004>;
 293                                 entry-latency-us = <600>;
 294                                 exit-latency-us = <1550>;
 295                                 min-residency-us = <4791>;
 296                                 local-timer-stop;
 297                         };
 298                 };
 299
 300                 domain-idle-states {
 301                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 302                                 compatible = "domain-idle-state";
 303                                 arm,psci-suspend-param = <0x41000044>;
 304                                 entry-latency-us = <1050>;
 305                                 exit-latency-us = <2500>;
 306                                 min-residency-us = <5309>;
 307                         };
 308
 309                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 310                                 compatible = "domain-idle-state";
 311                                 arm,psci-suspend-param = <0x4100c344>;
 312                                 entry-latency-us = <2700>;
 313                                 exit-latency-us = <3500>;
 314                                 min-residency-us = <13959>;
 315                         };
 316                 };
 317         };
 318
 319         firmware {
 320                 scm: scm {
 321                         compatible = "qcom,scm-sm8550", "qcom,scm";
 322                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 323                 };
 324         };
 325
 326         clk_virt: interconnect-0 {
 327                 compatible = "qcom,sm8550-clk-virt";
 328                 #interconnect-cells = <2>;
 329                 qcom,bcm-voters = <&apps_bcm_voter>;
 330         };
 331
 332         mc_virt: interconnect-1 {
 333                 compatible = "qcom,sm8550-mc-virt";
 334                 #interconnect-cells = <2>;
 335                 qcom,bcm-voters = <&apps_bcm_voter>;
 336         };
 337
 338         memory@a0000000 {
 339                 device_type = "memory";
 340                 /* We expect the bootloader to fill in the size */
 341                 reg = <0 0xa0000000 0 0>;
 342         };
 343
 344         pmu {
 345                 compatible = "arm,armv8-pmuv3";
 346                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 347         };
 348
 349         psci {
 350                 compatible = "arm,psci-1.0";
 351                 method = "smc";
 352
 353                 CPU_PD0: power-domain-cpu0 {
 354                         #power-domain-cells = <0>;
 355                         power-domains = <&CLUSTER_PD>;
 356                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 357                 };
 358
 359                 CPU_PD1: power-domain-cpu1 {
 360                         #power-domain-cells = <0>;
 361                         power-domains = <&CLUSTER_PD>;
 362                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 363                 };
 364
 365                 CPU_PD2: power-domain-cpu2 {
 366                         #power-domain-cells = <0>;
 367                         power-domains = <&CLUSTER_PD>;
 368                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 369                 };
 370
 371                 CPU_PD3: power-domain-cpu3 {
 372                         #power-domain-cells = <0>;
 373                         power-domains = <&CLUSTER_PD>;
 374                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 375                 };
 376
 377                 CPU_PD4: power-domain-cpu4 {
 378                         #power-domain-cells = <0>;
 379                         power-domains = <&CLUSTER_PD>;
 380                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 381                 };
 382
 383                 CPU_PD5: power-domain-cpu5 {
 384                         #power-domain-cells = <0>;
 385                         power-domains = <&CLUSTER_PD>;
 386                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 387                 };
 388
 389                 CPU_PD6: power-domain-cpu6 {
 390                         #power-domain-cells = <0>;
 391                         power-domains = <&CLUSTER_PD>;
 392                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 393                 };
 394
 395                 CPU_PD7: power-domain-cpu7 {
 396                         #power-domain-cells = <0>;
 397                         power-domains = <&CLUSTER_PD>;
 398                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 399                 };
 400
 401                 CLUSTER_PD: power-domain-cluster {
 402                         #power-domain-cells = <0>;
 403                         domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
 404                 };
 405         };
 406
 407         reserved_memory: reserved-memory {
 408                 #address-cells = <2>;
 409                 #size-cells = <2>;
 410                 ranges;
 411
 412                 hyp_mem: hyp-region@80000000 {
 413                         reg = <0 0x80000000 0 0xa00000>;
 414                         no-map;
 415                 };
 416
 417                 cpusys_vm_mem: cpusys-vm-region@80a00000 {
 418                         reg = <0 0x80a00000 0 0x400000>;
 419                         no-map;
 420                 };
 421
 422                 hyp_tags_mem: hyp-tags-region@80e00000 {
 423                         reg = <0 0x80e00000 0 0x3d0000>;
 424                         no-map;
 425                 };
 426
 427                 xbl_sc_mem: xbl-sc-region@d8100000 {
 428                         reg = <0 0xd8100000 0 0x40000>;
 429                         no-map;
 430                 };
 431
 432                 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
 433                         reg = <0 0x811d0000 0 0x30000>;
 434                         no-map;
 435                 };
 436
 437                 /* merged xbl_dt_log, xbl_ramdump, aop_image */
 438                 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
 439                         reg = <0 0x81a00000 0 0x260000>;
 440                         no-map;
 441                 };
 442
 443                 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
 444                         compatible = "qcom,cmd-db";
 445                         reg = <0 0x81c60000 0 0x20000>;
 446                         no-map;
 447                 };
 448
 449                 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */
 450                 aop_config_merged_mem: aop-config-merged-region@81c80000 {
 451                         reg = <0 0x81c80000 0 0x74000>;
 452                         no-map;
 453                 };
 454
 455                 /* secdata region can be reused by apps */
 456                 smem: smem@81d00000 {
 457                         compatible = "qcom,smem";
 458                         reg = <0 0x81d00000 0 0x200000>;
 459                         hwlocks = <&tcsr_mutex 3>;
 460                         no-map;
 461                 };
 462
 463                 adsp_mhi_mem: adsp-mhi-region@81f00000 {
 464                         reg = <0 0x81f00000 0 0x20000>;
 465                         no-map;
 466                 };
 467
 468                 global_sync_mem: global-sync-region@82600000 {
 469                         reg = <0 0x82600000 0 0x100000>;
 470                         no-map;
 471                 };
 472
 473                 tz_stat_mem: tz-stat-region@82700000 {
 474                         reg = <0 0x82700000 0 0x100000>;
 475                         no-map;
 476                 };
 477
 478                 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
 479                         reg = <0 0x82800000 0 0x4600000>;
 480                         no-map;
 481                 };
 482
 483                 mpss_mem: mpss-region@8a800000 {
 484                         reg = <0 0x8a800000 0 0x10800000>;
 485                         no-map;
 486                 };
 487
 488                 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
 489                         reg = <0 0x9b000000 0 0x80000>;
 490                         no-map;
 491                 };
 492
 493                 ipa_fw_mem: ipa-fw-region@9b080000 {
 494                         reg = <0 0x9b080000 0 0x10000>;
 495                         no-map;
 496                 };
 497
 498                 ipa_gsi_mem: ipa-gsi-region@9b090000 {
 499                         reg = <0 0x9b090000 0 0xa000>;
 500                         no-map;
 501                 };
 502
 503                 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
 504                         reg = <0 0x9b09a000 0 0x2000>;
 505                         no-map;
 506                 };
 507
 508                 spss_region_mem: spss-region@9b100000 {
 509                         reg = <0 0x9b100000 0 0x180000>;
 510                         no-map;
 511                 };
 512
 513                 /* First part of the "SPU secure shared memory" region */
 514                 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
 515                         reg = <0 0x9b280000 0 0x60000>;
 516                         no-map;
 517                 };
 518
 519                 /* Second part of the "SPU secure shared memory" region */
 520                 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
 521                         reg = <0 0x9b2e0000 0 0x20000>;
 522                         no-map;
 523                 };
 524
 525                 camera_mem: camera-region@9b300000 {
 526                         reg = <0 0x9b300000 0 0x800000>;
 527                         no-map;
 528                 };
 529
 530                 video_mem: video-region@9bb00000 {
 531                         reg = <0 0x9bb00000 0 0x700000>;
 532                         no-map;
 533                 };
 534
 535                 cvp_mem: cvp-region@9c200000 {
 536                         reg = <0 0x9c200000 0 0x700000>;
 537                         no-map;
 538                 };
 539
 540                 cdsp_mem: cdsp-region@9c900000 {
 541                         reg = <0 0x9c900000 0 0x2000000>;
 542                         no-map;
 543                 };
 544
 545                 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
 546                         reg = <0 0x9e900000 0 0x80000>;
 547                         no-map;
 548                 };
 549
 550                 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
 551                         reg = <0 0x9e980000 0 0x80000>;
 552                         no-map;
 553                 };
 554
 555                 adspslpi_mem: adspslpi-region@9ea00000 {
 556                         reg = <0 0x9ea00000 0 0x4080000>;
 557                         no-map;
 558                 };
 559
 560                 /* uefi region can be reused by apps */
 561
 562                 /* Linux kernel image is loaded at 0xa8000000 */
 563
 564                 rmtfs_mem: rmtfs-region@d4a80000 {
 565                         compatible = "qcom,rmtfs-mem";
 566                         reg = <0x0 0xd4a80000 0x0 0x280000>;
 567                         no-map;
 568
 569                         qcom,client-id = <1>;
 570                         qcom,vmid = <15>;
 571                 };
 572
 573                 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
 574                         reg = <0 0xd4d00000 0 0x3300000>;
 575                         no-map;
 576                 };
 577
 578                 tz_reserved_mem: tz-reserved-region@d8000000 {
 579                         reg = <0 0xd8000000 0 0x100000>;
 580                         no-map;
 581                 };
 582
 583                 cpucp_fw_mem: cpucp-fw-region@d8140000 {
 584                         reg = <0 0xd8140000 0 0x1c0000>;
 585                         no-map;
 586                 };
 587
 588                 qtee_mem: qtee-region@d8300000 {
 589                         reg = <0 0xd8300000 0 0x500000>;
 590                         no-map;
 591                 };
 592
 593                 ta_mem: ta-region@d8800000 {
 594                         reg = <0 0xd8800000 0 0x8a00000>;
 595                         no-map;
 596                 };
 597
 598                 tz_tags_mem: tz-tags-region@e1200000 {
 599                         reg = <0 0xe1200000 0 0x2740000>;
 600                         no-map;
 601                 };
 602
 603                 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
 604                         reg = <0 0xe6440000 0 0x279000>;
 605                         no-map;
 606                 };
 607
 608                 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
 609                         reg = <0 0xf3600000 0 0x4aee000>;
 610                         no-map;
 611                 };
 612
 613                 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
 614                         reg = <0 0xf80ee000 0 0x1000>;
 615                         no-map;
 616                 };
 617
 618                 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
 619                         reg = <0 0xf80ef000 0 0x9000>;
 620                         no-map;
 621                 };
 622
 623                 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
 624                         reg = <0 0xf80f8000 0 0x4000>;
 625                         no-map;
 626                 };
 627
 628                 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
 629                         reg = <0 0xf80fc000 0 0x4000>;
 630                         no-map;
 631                 };
 632
 633                 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
 634                         reg = <0 0xf8100000 0 0x100000>;
 635                         no-map;
 636                 };
 637
 638                 oem_vm_mem: oem-vm-region@f8400000 {
 639                         reg = <0 0xf8400000 0 0x4800000>;
 640                         no-map;
 641                 };
 642
 643                 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
 644                         reg = <0 0xfcc00000 0 0x4000>;
 645                         no-map;
 646                 };
 647
 648                 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
 649                         reg = <0 0xfcc04000 0 0x100000>;
 650                         no-map;
 651                 };
 652
 653                 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
 654                         reg = <0 0xfce00000 0 0x2900000>;
 655                         no-map;
 656                 };
 657
 658                 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
 659                         reg = <0 0xff700000 0 0x100000>;
 660                         no-map;
 661                 };
 662         };
 663
 664         smp2p-adsp {
 665                 compatible = "qcom,smp2p";
 666                 qcom,smem = <443>, <429>;
 667                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 668                                              IPCC_MPROC_SIGNAL_SMP2P
 669                                              IRQ_TYPE_EDGE_RISING>;
 670                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 671                                 IPCC_MPROC_SIGNAL_SMP2P>;
 672
 673                 qcom,local-pid = <0>;
 674                 qcom,remote-pid = <2>;
 675
 676                 smp2p_adsp_out: master-kernel {
 677                         qcom,entry-name = "master-kernel";
 678                         #qcom,smem-state-cells = <1>;
 679                 };
 680
 681                 smp2p_adsp_in: slave-kernel {
 682                         qcom,entry-name = "slave-kernel";
 683                         interrupt-controller;
 684                         #interrupt-cells = <2>;
 685                 };
 686         };
 687
 688         smp2p-cdsp {
 689                 compatible = "qcom,smp2p";
 690                 qcom,smem = <94>, <432>;
 691                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 692                                              IPCC_MPROC_SIGNAL_SMP2P
 693                                              IRQ_TYPE_EDGE_RISING>;
 694                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 695                                 IPCC_MPROC_SIGNAL_SMP2P>;
 696
 697                 qcom,local-pid = <0>;
 698                 qcom,remote-pid = <5>;
 699
 700                 smp2p_cdsp_out: master-kernel {
 701                         qcom,entry-name = "master-kernel";
 702                         #qcom,smem-state-cells = <1>;
 703                 };
 704
 705                 smp2p_cdsp_in: slave-kernel {
 706                         qcom,entry-name = "slave-kernel";
 707                         interrupt-controller;
 708                         #interrupt-cells = <2>;
 709                 };
 710         };
 711
 712         smp2p-modem {
 713                 compatible = "qcom,smp2p";
 714                 qcom,smem = <435>, <428>;
 715                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 716                                              IPCC_MPROC_SIGNAL_SMP2P
 717                                              IRQ_TYPE_EDGE_RISING>;
 718                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 719                                 IPCC_MPROC_SIGNAL_SMP2P>;
 720
 721                 qcom,local-pid = <0>;
 722                 qcom,remote-pid = <1>;
 723
 724                 smp2p_modem_out: master-kernel {
 725                         qcom,entry-name = "master-kernel";
 726                         #qcom,smem-state-cells = <1>;
 727                 };
 728
 729                 smp2p_modem_in: slave-kernel {
 730                         qcom,entry-name = "slave-kernel";
 731                         interrupt-controller;
 732                         #interrupt-cells = <2>;
 733                 };
 734
 735                 ipa_smp2p_out: ipa-ap-to-modem {
 736                         qcom,entry-name = "ipa";
 737                         #qcom,smem-state-cells = <1>;
 738                 };
 739
 740                 ipa_smp2p_in: ipa-modem-to-ap {
 741                         qcom,entry-name = "ipa";
 742                         interrupt-controller;
 743                         #interrupt-cells = <2>;
 744                 };
 745         };
 746
 747         soc: soc@0 {
 748                 compatible = "simple-bus";
 749                 ranges = <0 0 0 0 0x10 0>;
 750                 dma-ranges = <0 0 0 0 0x10 0>;
 751
 752                 #address-cells = <2>;
 753                 #size-cells = <2>;
 754
 755                 gcc: clock-controller@100000 {
 756                         compatible = "qcom,sm8550-gcc";
 757                         reg = <0 0x00100000 0 0x1f4200>;
 758                         #clock-cells = <1>;
 759                         #reset-cells = <1>;
 760                         #power-domain-cells = <1>;
 761                         clocks = <&bi_tcxo_div2>, <&sleep_clk>,
 762                                  <&pcie0_phy>,
 763                                  <&pcie1_phy>,
 764                                  <&pcie_1_phy_aux_clk>,
 765                                  <&ufs_mem_phy 0>,
 766                                  <&ufs_mem_phy 1>,
 767                                  <&ufs_mem_phy 2>,
 768                                  <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 769                 };
 770
 771                 ipcc: mailbox@408000 {
 772                         compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
 773                         reg = <0 0x00408000 0 0x1000>;
 774                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 775                         interrupt-controller;
 776                         #interrupt-cells = <3>;
 777                         #mbox-cells = <2>;
 778                 };
 779
 780                 gpi_dma2: dma-controller@800000 {
 781                         compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
 782                         #dma-cells = <3>;
 783                         reg = <0 0x00800000 0 0x60000>;
 784                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 785                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 786                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 787                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 788                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 789                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 790                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 791                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 792                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 793                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 794                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 795                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 796                         dma-channels = <12>;
 797                         dma-channel-mask = <0x3e>;
 798                         iommus = <&apps_smmu 0x436 0>;
 799                         status = "disabled";
 800                 };
 801
 802                 qupv3_id_1: geniqup@8c0000 {
 803                         compatible = "qcom,geni-se-qup";
 804                         reg = <0 0x008c0000 0 0x2000>;
 805                         ranges;
 806                         clock-names = "m-ahb", "s-ahb";
 807                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 808                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 809                         iommus = <&apps_smmu 0x423 0>;
 810                         #address-cells = <2>;
 811                         #size-cells = <2>;
 812                         status = "disabled";
 813
 814                         i2c8: i2c@880000 {
 815                                 compatible = "qcom,geni-i2c";
 816                                 reg = <0 0x00880000 0 0x4000>;
 817                                 clock-names = "se";
 818                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 819                                 pinctrl-names = "default";
 820                                 pinctrl-0 = <&qup_i2c8_data_clk>;
 821                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 822                                 #address-cells = <1>;
 823                                 #size-cells = <0>;
 824                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 825                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 826                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 827                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 828                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 829                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 830                                 dma-names = "tx", "rx";
 831                                 status = "disabled";
 832                         };
 833
 834                         spi8: spi@880000 {
 835                                 compatible = "qcom,geni-spi";
 836                                 reg = <0 0x00880000 0 0x4000>;
 837                                 clock-names = "se";
 838                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 839                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 840                                 pinctrl-names = "default";
 841                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
 842                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 843                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 844                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 845                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 846                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 847                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 848                                 dma-names = "tx", "rx";
 849                                 #address-cells = <1>;
 850                                 #size-cells = <0>;
 851                                 status = "disabled";
 852                         };
 853
 854                         i2c9: i2c@884000 {
 855                                 compatible = "qcom,geni-i2c";
 856                                 reg = <0 0x00884000 0 0x4000>;
 857                                 clock-names = "se";
 858                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 859                                 pinctrl-names = "default";
 860                                 pinctrl-0 = <&qup_i2c9_data_clk>;
 861                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 862                                 #address-cells = <1>;
 863                                 #size-cells = <0>;
 864                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 865                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 866                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 867                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 868                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 869                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 870                                 dma-names = "tx", "rx";
 871                                 status = "disabled";
 872                         };
 873
 874                         spi9: spi@884000 {
 875                                 compatible = "qcom,geni-spi";
 876                                 reg = <0 0x00884000 0 0x4000>;
 877                                 clock-names = "se";
 878                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 879                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 880                                 pinctrl-names = "default";
 881                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
 882                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 883                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 884                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 885                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 886                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 887                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 888                                 dma-names = "tx", "rx";
 889                                 #address-cells = <1>;
 890                                 #size-cells = <0>;
 891                                 status = "disabled";
 892                         };
 893
 894                         i2c10: i2c@888000 {
 895                                 compatible = "qcom,geni-i2c";
 896                                 reg = <0 0x00888000 0 0x4000>;
 897                                 clock-names = "se";
 898                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 899                                 pinctrl-names = "default";
 900                                 pinctrl-0 = <&qup_i2c10_data_clk>;
 901                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 902                                 #address-cells = <1>;
 903                                 #size-cells = <0>;
 904                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 905                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 906                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 907                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 908                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 909                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 910                                 dma-names = "tx", "rx";
 911                                 status = "disabled";
 912                         };
 913
 914                         spi10: spi@888000 {
 915                                 compatible = "qcom,geni-spi";
 916                                 reg = <0 0x00888000 0 0x4000>;
 917                                 clock-names = "se";
 918                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 919                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 920                                 pinctrl-names = "default";
 921                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
 922                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 923                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 924                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 925                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 926                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 927                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 928                                 dma-names = "tx", "rx";
 929                                 #address-cells = <1>;
 930                                 #size-cells = <0>;
 931                                 status = "disabled";
 932                         };
 933
 934                         i2c11: i2c@88c000 {
 935                                 compatible = "qcom,geni-i2c";
 936                                 reg = <0 0x0088c000 0 0x4000>;
 937                                 clock-names = "se";
 938                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 939                                 pinctrl-names = "default";
 940                                 pinctrl-0 = <&qup_i2c11_data_clk>;
 941                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 942                                 #address-cells = <1>;
 943                                 #size-cells = <0>;
 944                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 945                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 946                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 947                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 948                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 949                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 950                                 dma-names = "tx", "rx";
 951                                 status = "disabled";
 952                         };
 953
 954                         spi11: spi@88c000 {
 955                                 compatible = "qcom,geni-spi";
 956                                 reg = <0 0x0088c000 0 0x4000>;
 957                                 clock-names = "se";
 958                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 959                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 960                                 pinctrl-names = "default";
 961                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
 962                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 963                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 964                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 965                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 966                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 967                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 968                                 dma-names = "tx", "rx";
 969                                 #address-cells = <1>;
 970                                 #size-cells = <0>;
 971                                 status = "disabled";
 972                         };
 973
 974                         i2c12: i2c@890000 {
 975                                 compatible = "qcom,geni-i2c";
 976                                 reg = <0 0x00890000 0 0x4000>;
 977                                 clock-names = "se";
 978                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 979                                 pinctrl-names = "default";
 980                                 pinctrl-0 = <&qup_i2c12_data_clk>;
 981                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 982                                 #address-cells = <1>;
 983                                 #size-cells = <0>;
 984                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 985                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 986                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 987                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 988                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 989                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 990                                 dma-names = "tx", "rx";
 991                                 status = "disabled";
 992                         };
 993
 994                         spi12: spi@890000 {
 995                                 compatible = "qcom,geni-spi";
 996                                 reg = <0 0x00890000 0 0x4000>;
 997                                 clock-names = "se";
 998                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 999                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1000                                 pinctrl-names = "default";
1001                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1002                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1003                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1004                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1005                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1006                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1007                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1008                                 dma-names = "tx", "rx";
1009                                 #address-cells = <1>;
1010                                 #size-cells = <0>;
1011                                 status = "disabled";
1012                         };
1013
1014                         i2c13: i2c@894000 {
1015                                 compatible = "qcom,geni-i2c";
1016                                 reg = <0 0x00894000 0 0x4000>;
1017                                 clock-names = "se";
1018                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1019                                 pinctrl-names = "default";
1020                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1021                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1022                                 #address-cells = <1>;
1023                                 #size-cells = <0>;
1024                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1025                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1026                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1027                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1028                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1029                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1030                                 dma-names = "tx", "rx";
1031                                 status = "disabled";
1032                         };
1033
1034                         spi13: spi@894000 {
1035                                 compatible = "qcom,geni-spi";
1036                                 reg = <0 0x00894000 0 0x4000>;
1037                                 clock-names = "se";
1038                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1039                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1040                                 pinctrl-names = "default";
1041                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1042                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1043                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1044                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1045                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1046                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1047                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1048                                 dma-names = "tx", "rx";
1049                                 #address-cells = <1>;
1050                                 #size-cells = <0>;
1051                                 status = "disabled";
1052                         };
1053
1054                         i2c15: i2c@89c000 {
1055                                 compatible = "qcom,geni-i2c";
1056                                 reg = <0 0x0089c000 0 0x4000>;
1057                                 clock-names = "se";
1058                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1059                                 pinctrl-names = "default";
1060                                 pinctrl-0 = <&qup_i2c15_data_clk>;
1061                                 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1062                                 #address-cells = <1>;
1063                                 #size-cells = <0>;
1064                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1065                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1066                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1067                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1068                                 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1069                                        <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1070                                 dma-names = "tx", "rx";
1071                                 status = "disabled";
1072                         };
1073
1074                         spi15: spi@89c000 {
1075                                 compatible = "qcom,geni-spi";
1076                                 reg = <0 0x0089c000 0 0x4000>;
1077                                 clock-names = "se";
1078                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1079                                 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1080                                 pinctrl-names = "default";
1081                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1082                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1083                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1084                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1085                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1086                                 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1087                                        <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1088                                 dma-names = "tx", "rx";
1089                                 #address-cells = <1>;
1090                                 #size-cells = <0>;
1091                                 status = "disabled";
1092                         };
1093                 };
1094
1095                 i2c_master_hub_0: geniqup@9c0000 {
1096                         compatible = "qcom,geni-se-i2c-master-hub";
1097                         reg = <0x0 0x009c0000 0x0 0x2000>;
1098                         clock-names = "s-ahb";
1099                         clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
1100                         #address-cells = <2>;
1101                         #size-cells = <2>;
1102                         ranges;
1103                         status = "disabled";
1104
1105                         i2c_hub_0: i2c@980000 {
1106                                 compatible = "qcom,geni-i2c-master-hub";
1107                                 reg = <0x0 0x00980000 0x0 0x4000>;
1108                                 clock-names = "se", "core";
1109                                 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
1110                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1111                                 pinctrl-names = "default";
1112                                 pinctrl-0 = <&hub_i2c0_data_clk>;
1113                                 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
1114                                 #address-cells = <1>;
1115                                 #size-cells = <0>;
1116                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1117                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1118                                 interconnect-names = "qup-core", "qup-config";
1119                                 status = "disabled";
1120                         };
1121
1122                         i2c_hub_1: i2c@984000 {
1123                                 compatible = "qcom,geni-i2c-master-hub";
1124                                 reg = <0x0 0x00984000 0x0 0x4000>;
1125                                 clock-names = "se", "core";
1126                                 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
1127                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1128                                 pinctrl-names = "default";
1129                                 pinctrl-0 = <&hub_i2c1_data_clk>;
1130                                 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
1131                                 #address-cells = <1>;
1132                                 #size-cells = <0>;
1133                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1134                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1135                                 interconnect-names = "qup-core", "qup-config";
1136                                 status = "disabled";
1137                         };
1138
1139                         i2c_hub_2: i2c@988000 {
1140                                 compatible = "qcom,geni-i2c-master-hub";
1141                                 reg = <0x0 0x00988000 0x0 0x4000>;
1142                                 clock-names = "se", "core";
1143                                 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
1144                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1145                                 pinctrl-names = "default";
1146                                 pinctrl-0 = <&hub_i2c2_data_clk>;
1147                                 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1148                                 #address-cells = <1>;
1149                                 #size-cells = <0>;
1150                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1151                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1152                                 interconnect-names = "qup-core", "qup-config";
1153                                 status = "disabled";
1154                         };
1155
1156                         i2c_hub_3: i2c@98c000 {
1157                                 compatible = "qcom,geni-i2c-master-hub";
1158                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1159                                 clock-names = "se", "core";
1160                                 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
1161                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1162                                 pinctrl-names = "default";
1163                                 pinctrl-0 = <&hub_i2c3_data_clk>;
1164                                 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1165                                 #address-cells = <1>;
1166                                 #size-cells = <0>;
1167                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1168                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1169                                 interconnect-names = "qup-core", "qup-config";
1170                                 status = "disabled";
1171                         };
1172
1173                         i2c_hub_4: i2c@990000 {
1174                                 compatible = "qcom,geni-i2c-master-hub";
1175                                 reg = <0x0 0x00990000 0x0 0x4000>;
1176                                 clock-names = "se", "core";
1177                                 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
1178                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1179                                 pinctrl-names = "default";
1180                                 pinctrl-0 = <&hub_i2c4_data_clk>;
1181                                 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1182                                 #address-cells = <1>;
1183                                 #size-cells = <0>;
1184                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1185                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1186                                 interconnect-names = "qup-core", "qup-config";
1187                                 status = "disabled";
1188                         };
1189
1190                         i2c_hub_5: i2c@994000 {
1191                                 compatible = "qcom,geni-i2c-master-hub";
1192                                 reg = <0 0x00994000 0 0x4000>;
1193                                 clock-names = "se", "core";
1194                                 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
1195                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1196                                 pinctrl-names = "default";
1197                                 pinctrl-0 = <&hub_i2c5_data_clk>;
1198                                 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
1199                                 #address-cells = <1>;
1200                                 #size-cells = <0>;
1201                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1202                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1203                                 interconnect-names = "qup-core", "qup-config";
1204                                 status = "disabled";
1205                         };
1206
1207                         i2c_hub_6: i2c@998000 {
1208                                 compatible = "qcom,geni-i2c-master-hub";
1209                                 reg = <0 0x00998000 0 0x4000>;
1210                                 clock-names = "se", "core";
1211                                 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
1212                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1213                                 pinctrl-names = "default";
1214                                 pinctrl-0 = <&hub_i2c6_data_clk>;
1215                                 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
1216                                 #address-cells = <1>;
1217                                 #size-cells = <0>;
1218                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1219                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1220                                 interconnect-names = "qup-core", "qup-config";
1221                                 status = "disabled";
1222                         };
1223
1224                         i2c_hub_7: i2c@99c000 {
1225                                 compatible = "qcom,geni-i2c-master-hub";
1226                                 reg = <0 0x0099c000 0 0x4000>;
1227                                 clock-names = "se", "core";
1228                                 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
1229                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1230                                 pinctrl-names = "default";
1231                                 pinctrl-0 = <&hub_i2c7_data_clk>;
1232                                 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
1233                                 #address-cells = <1>;
1234                                 #size-cells = <0>;
1235                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1236                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1237                                 interconnect-names = "qup-core", "qup-config";
1238                                 status = "disabled";
1239                         };
1240
1241                         i2c_hub_8: i2c@9a0000 {
1242                                 compatible = "qcom,geni-i2c-master-hub";
1243                                 reg = <0 0x009a0000 0 0x4000>;
1244                                 clock-names = "se", "core";
1245                                 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
1246                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1247                                 pinctrl-names = "default";
1248                                 pinctrl-0 = <&hub_i2c8_data_clk>;
1249                                 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
1250                                 #address-cells = <1>;
1251                                 #size-cells = <0>;
1252                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1253                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1254                                 interconnect-names = "qup-core", "qup-config";
1255                                 status = "disabled";
1256                         };
1257
1258                         i2c_hub_9: i2c@9a4000 {
1259                                 compatible = "qcom,geni-i2c-master-hub";
1260                                 reg = <0 0x009a4000 0 0x4000>;
1261                                 clock-names = "se", "core";
1262                                 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
1263                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1264                                 pinctrl-names = "default";
1265                                 pinctrl-0 = <&hub_i2c9_data_clk>;
1266                                 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
1267                                 #address-cells = <1>;
1268                                 #size-cells = <0>;
1269                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1270                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1271                                 interconnect-names = "qup-core", "qup-config";
1272                                 status = "disabled";
1273                         };
1274                 };
1275
1276                 gpi_dma1: dma-controller@a00000 {
1277                         compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1278                         #dma-cells = <3>;
1279                         reg = <0 0x00a00000 0 0x60000>;
1280                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1281                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1282                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1283                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1284                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1285                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1286                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1287                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1288                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1289                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1290                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1291                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1292                         dma-channels = <12>;
1293                         dma-channel-mask = <0x1e>;
1294                         iommus = <&apps_smmu 0xb6 0>;
1295                         status = "disabled";
1296                 };
1297
1298                 qupv3_id_0: geniqup@ac0000 {
1299                         compatible = "qcom,geni-se-qup";
1300                         reg = <0 0x00ac0000 0 0x2000>;
1301                         ranges;
1302                         clock-names = "m-ahb", "s-ahb";
1303                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1304                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1305                         iommus = <&apps_smmu 0xa3 0>;
1306                         interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1307                         interconnect-names = "qup-core";
1308                         #address-cells = <2>;
1309                         #size-cells = <2>;
1310                         status = "disabled";
1311
1312                         i2c0: i2c@a80000 {
1313                                 compatible = "qcom,geni-i2c";
1314                                 reg = <0 0x00a80000 0 0x4000>;
1315                                 clock-names = "se";
1316                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1317                                 pinctrl-names = "default";
1318                                 pinctrl-0 = <&qup_i2c0_data_clk>;
1319                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1320                                 #address-cells = <1>;
1321                                 #size-cells = <0>;
1322                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1323                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1324                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1325                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1326                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1327                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1328                                 dma-names = "tx", "rx";
1329                                 status = "disabled";
1330                         };
1331
1332                         spi0: spi@a80000 {
1333                                 compatible = "qcom,geni-spi";
1334                                 reg = <0 0x00a80000 0 0x4000>;
1335                                 clock-names = "se";
1336                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1337                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1338                                 pinctrl-names = "default";
1339                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1340                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1341                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1342                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1343                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1344                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1345                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1346                                 dma-names = "tx", "rx";
1347                                 #address-cells = <1>;
1348                                 #size-cells = <0>;
1349                                 status = "disabled";
1350                         };
1351
1352                         i2c1: i2c@a84000 {
1353                                 compatible = "qcom,geni-i2c";
1354                                 reg = <0 0x00a84000 0 0x4000>;
1355                                 clock-names = "se";
1356                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1357                                 pinctrl-names = "default";
1358                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1359                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360                                 #address-cells = <1>;
1361                                 #size-cells = <0>;
1362                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1363                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1364                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1365                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1366                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1367                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1368                                 dma-names = "tx", "rx";
1369                                 status = "disabled";
1370                         };
1371
1372                         spi1: spi@a84000 {
1373                                 compatible = "qcom,geni-spi";
1374                                 reg = <0 0x00a84000 0 0x4000>;
1375                                 clock-names = "se";
1376                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1377                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1378                                 pinctrl-names = "default";
1379                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1380                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1381                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1383                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1384                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1385                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1386                                 dma-names = "tx", "rx";
1387                                 #address-cells = <1>;
1388                                 #size-cells = <0>;
1389                                 status = "disabled";
1390                         };
1391
1392                         i2c2: i2c@a88000 {
1393                                 compatible = "qcom,geni-i2c";
1394                                 reg = <0 0x00a88000 0 0x4000>;
1395                                 clock-names = "se";
1396                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1397                                 pinctrl-names = "default";
1398                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1399                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1400                                 #address-cells = <1>;
1401                                 #size-cells = <0>;
1402                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1403                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1404                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1405                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1407                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1408                                 dma-names = "tx", "rx";
1409                                 status = "disabled";
1410                         };
1411
1412                         spi2: spi@a88000 {
1413                                 compatible = "qcom,geni-spi";
1414                                 reg = <0 0x00a88000 0 0x4000>;
1415                                 clock-names = "se";
1416                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1417                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1418                                 pinctrl-names = "default";
1419                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1420                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1421                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1422                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1423                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1424                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1425                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1426                                 dma-names = "tx", "rx";
1427                                 #address-cells = <1>;
1428                                 #size-cells = <0>;
1429                                 status = "disabled";
1430                         };
1431
1432                         i2c3: i2c@a8c000 {
1433                                 compatible = "qcom,geni-i2c";
1434                                 reg = <0 0x00a8c000 0 0x4000>;
1435                                 clock-names = "se";
1436                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1437                                 pinctrl-names = "default";
1438                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1439                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1440                                 #address-cells = <1>;
1441                                 #size-cells = <0>;
1442                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1443                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1444                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1445                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1446                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1447                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1448                                 dma-names = "tx", "rx";
1449                                 status = "disabled";
1450                         };
1451
1452                         spi3: spi@a8c000 {
1453                                 compatible = "qcom,geni-spi";
1454                                 reg = <0 0x00a8c000 0 0x4000>;
1455                                 clock-names = "se";
1456                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1457                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1458                                 pinctrl-names = "default";
1459                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1460                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1461                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1462                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1463                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1464                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1465                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1466                                 dma-names = "tx", "rx";
1467                                 #address-cells = <1>;
1468                                 #size-cells = <0>;
1469                                 status = "disabled";
1470                         };
1471
1472                         i2c4: i2c@a90000 {
1473                                 compatible = "qcom,geni-i2c";
1474                                 reg = <0 0x00a90000 0 0x4000>;
1475                                 clock-names = "se";
1476                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1477                                 pinctrl-names = "default";
1478                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1479                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1480                                 #address-cells = <1>;
1481                                 #size-cells = <0>;
1482                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1483                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1484                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1485                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1486                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1487                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1488                                 dma-names = "tx", "rx";
1489                                 status = "disabled";
1490                         };
1491
1492                         spi4: spi@a90000 {
1493                                 compatible = "qcom,geni-spi";
1494                                 reg = <0 0x00a90000 0 0x4000>;
1495                                 clock-names = "se";
1496                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1497                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1498                                 pinctrl-names = "default";
1499                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1500                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1501                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1502                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1503                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1504                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1505                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1506                                 dma-names = "tx", "rx";
1507                                 #address-cells = <1>;
1508                                 #size-cells = <0>;
1509                                 status = "disabled";
1510                         };
1511
1512                         i2c5: i2c@a94000 {
1513                                 compatible = "qcom,geni-i2c";
1514                                 reg = <0 0x00a94000 0 0x4000>;
1515                                 clock-names = "se";
1516                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1517                                 pinctrl-names = "default";
1518                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1519                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1520                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1521                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1522                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1523                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1524                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1525                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1526                                 dma-names = "tx", "rx";
1527                                 #address-cells = <1>;
1528                                 #size-cells = <0>;
1529                                 status = "disabled";
1530                         };
1531
1532                         spi5: spi@a94000 {
1533                                 compatible = "qcom,geni-spi";
1534                                 reg = <0 0x00a94000 0 0x4000>;
1535                                 clock-names = "se";
1536                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1537                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1538                                 pinctrl-names = "default";
1539                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1540                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1541                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1542                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1543                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1544                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1545                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1546                                 dma-names = "tx", "rx";
1547                                 #address-cells = <1>;
1548                                 #size-cells = <0>;
1549                                 status = "disabled";
1550                         };
1551
1552                         i2c6: i2c@a98000 {
1553                                 compatible = "qcom,geni-i2c";
1554                                 reg = <0 0x00a98000 0 0x4000>;
1555                                 clock-names = "se";
1556                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1557                                 pinctrl-names = "default";
1558                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1559                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1560                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1561                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1562                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1563                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1564                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1565                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1566                                 dma-names = "tx", "rx";
1567                                 #address-cells = <1>;
1568                                 #size-cells = <0>;
1569                                 status = "disabled";
1570                         };
1571
1572                         spi6: spi@a98000 {
1573                                 compatible = "qcom,geni-spi";
1574                                 reg = <0 0x00a98000 0 0x4000>;
1575                                 clock-names = "se";
1576                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1577                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1578                                 pinctrl-names = "default";
1579                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1580                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1581                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1582                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1583                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1584                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1585                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1586                                 dma-names = "tx", "rx";
1587                                 #address-cells = <1>;
1588                                 #size-cells = <0>;
1589                                 status = "disabled";
1590                         };
1591
1592                         uart7: serial@a9c000 {
1593                                 compatible = "qcom,geni-debug-uart";
1594                                 reg = <0 0x00a9c000 0 0x4000>;
1595                                 clock-names = "se";
1596                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1597                                 pinctrl-names = "default";
1598                                 pinctrl-0 = <&qup_uart7_default>;
1599                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1600                                 interconnect-names = "qup-core", "qup-config";
1601                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1602                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1603                                 status = "disabled";
1604                         };
1605                 };
1606
1607                 cnoc_main: interconnect@1500000 {
1608                         compatible = "qcom,sm8550-cnoc-main";
1609                         reg = <0 0x01500000 0 0x13080>;
1610                         #interconnect-cells = <2>;
1611                         qcom,bcm-voters = <&apps_bcm_voter>;
1612                 };
1613
1614                 config_noc: interconnect@1600000 {
1615                         compatible = "qcom,sm8550-config-noc";
1616                         reg = <0 0x01600000 0 0x6200>;
1617                         #interconnect-cells = <2>;
1618                         qcom,bcm-voters = <&apps_bcm_voter>;
1619                 };
1620
1621                 system_noc: interconnect@1680000 {
1622                         compatible = "qcom,sm8550-system-noc";
1623                         reg = <0 0x01680000 0 0x1d080>;
1624                         #interconnect-cells = <2>;
1625                         qcom,bcm-voters = <&apps_bcm_voter>;
1626                 };
1627
1628                 pcie_noc: interconnect@16c0000 {
1629                         compatible = "qcom,sm8550-pcie-anoc";
1630                         reg = <0 0x016c0000 0 0x12200>;
1631                         #interconnect-cells = <2>;
1632                         clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1633                                  <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
1634                         qcom,bcm-voters = <&apps_bcm_voter>;
1635                 };
1636
1637                 aggre1_noc: interconnect@16e0000 {
1638                         compatible = "qcom,sm8550-aggre1-noc";
1639                         reg = <0 0x016e0000 0 0x14400>;
1640                         #interconnect-cells = <2>;
1641                         clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1642                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
1643                         qcom,bcm-voters = <&apps_bcm_voter>;
1644                 };
1645
1646                 aggre2_noc: interconnect@1700000 {
1647                         compatible = "qcom,sm8550-aggre2-noc";
1648                         reg = <0 0x01700000 0 0x1e400>;
1649                         #interconnect-cells = <2>;
1650                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1651                         qcom,bcm-voters = <&apps_bcm_voter>;
1652                 };
1653
1654                 mmss_noc: interconnect@1780000 {
1655                         compatible = "qcom,sm8550-mmss-noc";
1656                         reg = <0 0x01780000 0 0x5b800>;
1657                         #interconnect-cells = <2>;
1658                         qcom,bcm-voters = <&apps_bcm_voter>;
1659                 };
1660
1661                 pcie0: pci@1c00000 {
1662                         device_type = "pci";
1663                         compatible = "qcom,pcie-sm8550";
1664                         reg = <0 0x01c00000 0 0x3000>,
1665                               <0 0x60000000 0 0xf1d>,
1666                               <0 0x60000f20 0 0xa8>,
1667                               <0 0x60001000 0 0x1000>,
1668                               <0 0x60100000 0 0x100000>;
1669                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1670                         #address-cells = <3>;
1671                         #size-cells = <2>;
1672                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1673                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1674                         bus-range = <0x00 0xff>;
1675
1676                         dma-coherent;
1677
1678                         linux,pci-domain = <0>;
1679                         num-lanes = <2>;
1680
1681                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1682                         interrupt-names = "msi";
1683
1684                         #interrupt-cells = <1>;
1685                         interrupt-map-mask = <0 0 0 0x7>;
1686                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1687                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1688                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1689                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1690
1691                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1692                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1693                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1694                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1695                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1696                                  <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1697                                  <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
1698                         clock-names = "aux",
1699                                       "cfg",
1700                                       "bus_master",
1701                                       "bus_slave",
1702                                       "slave_q2a",
1703                                       "ddrss_sf_tbu",
1704                                       "noc_aggr";
1705
1706                         interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1707                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1708                         interconnect-names = "pcie-mem", "cpu-pcie";
1709
1710                         iommu-map = <0x0   &apps_smmu 0x1400 0x1>,
1711                                     <0x100 &apps_smmu 0x1401 0x1>;
1712
1713                         resets = <&gcc GCC_PCIE_0_BCR>;
1714                         reset-names = "pci";
1715
1716                         power-domains = <&gcc PCIE_0_GDSC>;
1717
1718                         phys = <&pcie0_phy>;
1719                         phy-names = "pciephy";
1720
1721                         status = "disabled";
1722                 };
1723
1724                 pcie0_phy: phy@1c06000 {
1725                         compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1726                         reg = <0 0x01c06000 0 0x2000>;
1727
1728                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1729                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1730                                  <&tcsr TCSR_PCIE_0_CLKREF_EN>,
1731                                  <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1732                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
1733                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1734                                       "pipe";
1735
1736                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1737                         reset-names = "phy";
1738
1739                         assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1740                         assigned-clock-rates = <100000000>;
1741
1742                         power-domains = <&gcc PCIE_0_PHY_GDSC>;
1743
1744                         #clock-cells = <0>;
1745                         clock-output-names = "pcie0_pipe_clk";
1746
1747                         #phy-cells = <0>;
1748
1749                         status = "disabled";
1750                 };
1751
1752                 pcie1: pci@1c08000 {
1753                         device_type = "pci";
1754                         compatible = "qcom,pcie-sm8550";
1755                         reg = <0x0 0x01c08000 0x0 0x3000>,
1756                               <0x0 0x40000000 0x0 0xf1d>,
1757                               <0x0 0x40000f20 0x0 0xa8>,
1758                               <0x0 0x40001000 0x0 0x1000>,
1759                               <0x0 0x40100000 0x0 0x100000>;
1760                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1761                         #address-cells = <3>;
1762                         #size-cells = <2>;
1763                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1764                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1765                         bus-range = <0x00 0xff>;
1766
1767                         dma-coherent;
1768
1769                         linux,pci-domain = <1>;
1770                         num-lanes = <2>;
1771
1772                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1773                         interrupt-names = "msi";
1774
1775                         #interrupt-cells = <1>;
1776                         interrupt-map-mask = <0 0 0 0x7>;
1777                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1778                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1779                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1780                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1781
1782                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1783                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1784                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1785                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1786                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1787                                  <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1788                                  <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1789                                  <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
1790                         clock-names = "aux",
1791                                       "cfg",
1792                                       "bus_master",
1793                                       "bus_slave",
1794                                       "slave_q2a",
1795                                       "ddrss_sf_tbu",
1796                                       "noc_aggr",
1797                                       "cnoc_sf_axi";
1798
1799                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1800                         assigned-clock-rates = <19200000>;
1801
1802                         interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1803                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1804                         interconnect-names = "pcie-mem", "cpu-pcie";
1805
1806                         iommu-map = <0x0   &apps_smmu 0x1480 0x1>,
1807                                     <0x100 &apps_smmu 0x1481 0x1>;
1808
1809                         resets = <&gcc GCC_PCIE_1_BCR>,
1810                                 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
1811                         reset-names = "pci", "link_down";
1812
1813                         power-domains = <&gcc PCIE_1_GDSC>;
1814
1815                         phys = <&pcie1_phy>;
1816                         phy-names = "pciephy";
1817
1818                         status = "disabled";
1819                 };
1820
1821                 pcie1_phy: phy@1c0e000 {
1822                         compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1823                         reg = <0x0 0x01c0e000 0x0 0x2000>;
1824
1825                         clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1826                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1827                                  <&tcsr TCSR_PCIE_1_CLKREF_EN>,
1828                                  <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1829                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
1830                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1831                                       "pipe";
1832
1833                         resets = <&gcc GCC_PCIE_1_PHY_BCR>,
1834                                  <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
1835                         reset-names = "phy", "phy_nocsr";
1836
1837                         assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1838                         assigned-clock-rates = <100000000>;
1839
1840                         power-domains = <&gcc PCIE_1_PHY_GDSC>;
1841
1842                         #clock-cells = <0>;
1843                         clock-output-names = "pcie1_pipe_clk";
1844
1845                         #phy-cells = <0>;
1846
1847                         status = "disabled";
1848                 };
1849
1850                 cryptobam: dma-controller@1dc4000 {
1851                         compatible = "qcom,bam-v1.7.0";
1852                         reg = <0x0 0x01dc4000 0x0 0x28000>;
1853                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1854                         #dma-cells = <1>;
1855                         qcom,ee = <0>;
1856                         qcom,controlled-remotely;
1857                         iommus = <&apps_smmu 0x480 0x0>,
1858                                  <&apps_smmu 0x481 0x0>;
1859                 };
1860
1861                 crypto: crypto@1de0000 {
1862                         compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1863                         reg = <0x0 0x01dfa000 0x0 0x6000>;
1864                         dmas = <&cryptobam 4>, <&cryptobam 5>;
1865                         dma-names = "rx", "tx";
1866                         iommus = <&apps_smmu 0x480 0x0>,
1867                                  <&apps_smmu 0x481 0x0>;
1868                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1869                         interconnect-names = "memory";
1870                 };
1871
1872                 ufs_mem_phy: phy@1d80000 {
1873                         compatible = "qcom,sm8550-qmp-ufs-phy";
1874                         reg = <0x0 0x01d80000 0x0 0x2000>;
1875                         clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
1876                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1877                         clock-names = "ref", "ref_aux";
1878
1879                         power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1880
1881                         resets = <&ufs_mem_hc 0>;
1882                         reset-names = "ufsphy";
1883
1884                         #clock-cells = <1>;
1885                         #phy-cells = <0>;
1886
1887                         status = "disabled";
1888                 };
1889
1890                 ufs_mem_hc: ufs@1d84000 {
1891                         compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1892                                      "jedec,ufs-2.0";
1893                         reg = <0x0 0x01d84000 0x0 0x3000>;
1894                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1895                         phys = <&ufs_mem_phy>;
1896                         phy-names = "ufsphy";
1897                         lanes-per-direction = <2>;
1898                         #reset-cells = <1>;
1899                         resets = <&gcc GCC_UFS_PHY_BCR>;
1900                         reset-names = "rst";
1901
1902                         power-domains = <&gcc UFS_PHY_GDSC>;
1903                         required-opps = <&rpmhpd_opp_nom>;
1904
1905                         iommus = <&apps_smmu 0x60 0x0>;
1906                         dma-coherent;
1907
1908                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1909                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
1910
1911                         interconnect-names = "ufs-ddr", "cpu-ufs";
1912                         clock-names = "core_clk",
1913                                       "bus_aggr_clk",
1914                                       "iface_clk",
1915                                       "core_clk_unipro",
1916                                       "ref_clk",
1917                                       "tx_lane0_sync_clk",
1918                                       "rx_lane0_sync_clk",
1919                                       "rx_lane1_sync_clk";
1920                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1921                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1922                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
1923                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1924                                  <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
1925                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1926                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1927                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1928                         freq-table-hz =
1929                                 <75000000 300000000>,
1930                                 <0 0>,
1931                                 <0 0>,
1932                                 <75000000 300000000>,
1933                                 <100000000 403000000>,
1934                                 <0 0>,
1935                                 <0 0>,
1936                                 <0 0>;
1937                         qcom,ice = <&ice>;
1938
1939                         status = "disabled";
1940                 };
1941
1942                 ice: crypto@1d88000 {
1943                         compatible = "qcom,sm8550-inline-crypto-engine",
1944                                      "qcom,inline-crypto-engine";
1945                         reg = <0 0x01d88000 0 0x8000>;
1946                         clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1947                 };
1948
1949                 tcsr_mutex: hwlock@1f40000 {
1950                         compatible = "qcom,tcsr-mutex";
1951                         reg = <0 0x01f40000 0 0x20000>;
1952                         #hwlock-cells = <1>;
1953                 };
1954
1955                 tcsr: clock-controller@1fc0000 {
1956                         compatible = "qcom,sm8550-tcsr", "syscon";
1957                         reg = <0 0x01fc0000 0 0x30000>;
1958                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1959                         #clock-cells = <1>;
1960                         #reset-cells = <1>;
1961                 };
1962
1963                 remoteproc_mpss: remoteproc@4080000 {
1964                         compatible = "qcom,sm8550-mpss-pas";
1965                         reg = <0x0 0x04080000 0x0 0x4040>;
1966
1967                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
1968                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1969                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1970                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1971                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1972                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1973                         interrupt-names = "wdog", "fatal", "ready", "handover",
1974                                           "stop-ack", "shutdown-ack";
1975
1976                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1977                         clock-names = "xo";
1978
1979                         power-domains = <&rpmhpd SM8550_CX>,
1980                                         <&rpmhpd SM8550_MSS>;
1981                         power-domain-names = "cx", "mss";
1982
1983                         interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
1984
1985                         memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
1986
1987                         qcom,qmp = <&aoss_qmp>;
1988
1989                         qcom,smem-states = <&smp2p_modem_out 0>;
1990                         qcom,smem-state-names = "stop";
1991
1992                         status = "disabled";
1993
1994                         glink-edge {
1995                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1996                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1997                                                              IRQ_TYPE_EDGE_RISING>;
1998                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
1999                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2000                                 label = "mpss";
2001                                 qcom,remote-pid = <1>;
2002                         };
2003                 };
2004
2005                 lpass_wsa2macro: codec@6aa0000 {
2006                         compatible = "qcom,sm8550-lpass-wsa-macro";
2007                         reg = <0 0x06aa0000 0 0x1000>;
2008                         clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2009                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2010                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2011                                  <&lpass_vamacro>;
2012                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2013                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2014                         assigned-clock-rates = <19200000>;
2015
2016                         #clock-cells = <0>;
2017                         clock-output-names = "wsa2-mclk";
2018                         pinctrl-names = "default";
2019                         pinctrl-0 = <&wsa2_swr_active>;
2020                         #sound-dai-cells = <1>;
2021                 };
2022
2023                 swr3: soundwire-controller@6ab0000 {
2024                         compatible = "qcom,soundwire-v2.0.0";
2025                         reg = <0 0x06ab0000 0 0x10000>;
2026                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2027                         clocks = <&lpass_wsa2macro>;
2028                         clock-names = "iface";
2029                         label = "WSA2";
2030
2031                         qcom,din-ports = <4>;
2032                         qcom,dout-ports = <9>;
2033
2034                         qcom,ports-sinterval =          /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2035                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2036                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2037                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2038                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2039                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2040                         qcom,ports-block-pack-mode =    /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2041                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2042                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2043
2044                         #address-cells = <2>;
2045                         #size-cells = <0>;
2046                         #sound-dai-cells = <1>;
2047                         status = "disabled";
2048                 };
2049
2050                 lpass_rxmacro: codec@6ac0000 {
2051                         compatible = "qcom,sm8550-lpass-rx-macro";
2052                         reg = <0 0x06ac0000 0 0x1000>;
2053                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2054                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2055                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2056                                  <&lpass_vamacro>;
2057                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2058
2059                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2060                         assigned-clock-rates = <19200000>;
2061
2062                         #clock-cells = <0>;
2063                         clock-output-names = "mclk";
2064                         pinctrl-names = "default";
2065                         pinctrl-0 = <&rx_swr_active>;
2066                         #sound-dai-cells = <1>;
2067                 };
2068
2069                 swr1: soundwire-controller@6ad0000 {
2070                         compatible = "qcom,soundwire-v2.0.0";
2071                         reg = <0 0x06ad0000 0 0x10000>;
2072                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2073                         clocks = <&lpass_rxmacro>;
2074                         clock-names = "iface";
2075                         label = "RX";
2076
2077                         qcom,din-ports = <0>;
2078                         qcom,dout-ports = <10>;
2079
2080                         qcom,ports-sinterval =          /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
2081                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
2082                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2083                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2084                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2085                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
2086                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
2087                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2088                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2089
2090                         #address-cells = <2>;
2091                         #size-cells = <0>;
2092                         #sound-dai-cells = <1>;
2093                         status = "disabled";
2094                 };
2095
2096                 lpass_txmacro: codec@6ae0000 {
2097                         compatible = "qcom,sm8550-lpass-tx-macro";
2098                         reg = <0 0x06ae0000 0 0x1000>;
2099                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2100                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2101                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2102                                  <&lpass_vamacro>;
2103                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2104                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2105
2106                         assigned-clock-rates = <19200000>;
2107
2108                         #clock-cells = <0>;
2109                         clock-output-names = "mclk";
2110                         pinctrl-names = "default";
2111                         pinctrl-0 = <&tx_swr_active>;
2112                         #sound-dai-cells = <1>;
2113                 };
2114
2115                 lpass_wsamacro: codec@6b00000 {
2116                         compatible = "qcom,sm8550-lpass-wsa-macro";
2117                         reg = <0 0x06b00000 0 0x1000>;
2118                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2119                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2120                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2121                                  <&lpass_vamacro>;
2122                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2123
2124                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2125                         assigned-clock-rates = <19200000>;
2126
2127                         #clock-cells = <0>;
2128                         clock-output-names = "mclk";
2129                         pinctrl-names = "default";
2130                         pinctrl-0 = <&wsa_swr_active>;
2131                         #sound-dai-cells = <1>;
2132                 };
2133
2134                 swr0: soundwire-controller@6b10000 {
2135                         compatible = "qcom,soundwire-v2.0.0";
2136                         reg = <0 0x06b10000 0 0x10000>;
2137                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2138                         clocks = <&lpass_wsamacro>;
2139                         clock-names = "iface";
2140                         label = "WSA";
2141
2142                         qcom,din-ports = <4>;
2143                         qcom,dout-ports = <9>;
2144
2145                         qcom,ports-sinterval =          /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2146                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2147                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2148                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2149                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2150                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2151                         qcom,ports-block-pack-mode =    /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2152                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2153                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2154
2155                         #address-cells = <2>;
2156                         #size-cells = <0>;
2157                         #sound-dai-cells = <1>;
2158                         status = "disabled";
2159                 };
2160
2161                 swr2: soundwire-controller@6d30000 {
2162                         compatible = "qcom,soundwire-v2.0.0";
2163                         reg = <0 0x06d30000 0 0x10000>;
2164                         interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2165                                      <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2166                         interrupt-names = "core", "wakeup";
2167                         clocks = <&lpass_vamacro>;
2168                         clock-names = "iface";
2169                         label = "TX";
2170
2171                         qcom,din-ports = <4>;
2172                         qcom,dout-ports = <0>;
2173                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x01 0x03 0x03>;
2174                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x01 0x01>;
2175                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
2176                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
2177                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
2178                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff>;
2179                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
2180                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
2181                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x02 0x00 0x00>;
2182
2183                         #address-cells = <2>;
2184                         #size-cells = <0>;
2185                         #sound-dai-cells = <1>;
2186                         status = "disabled";
2187                 };
2188
2189                 lpass_vamacro: codec@6d44000 {
2190                         compatible = "qcom,sm8550-lpass-va-macro";
2191                         reg = <0 0x06d44000 0 0x1000>;
2192                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2193                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2194                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2195                         clock-names = "mclk", "macro", "dcodec";
2196
2197                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2198                         assigned-clock-rates = <19200000>;
2199
2200                         #clock-cells = <0>;
2201                         clock-output-names = "fsgen";
2202                         #sound-dai-cells = <1>;
2203                 };
2204
2205                 lpass_tlmm: pinctrl@6e80000 {
2206                         compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2207                         reg = <0 0x06e80000 0 0x20000>,
2208                               <0 0x07250000 0 0x10000>;
2209                         gpio-controller;
2210                         #gpio-cells = <2>;
2211                         gpio-ranges = <&lpass_tlmm 0 0 23>;
2212
2213                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2214                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2215                         clock-names = "core", "audio";
2216
2217                         tx_swr_active: tx-swr-active-state {
2218                                 clk-pins {
2219                                         pins = "gpio0";
2220                                         function = "swr_tx_clk";
2221                                         drive-strength = <2>;
2222                                         slew-rate = <1>;
2223                                         bias-disable;
2224                                 };
2225
2226                                 data-pins {
2227                                         pins = "gpio1", "gpio2", "gpio14";
2228                                         function = "swr_tx_data";
2229                                         drive-strength = <2>;
2230                                         slew-rate = <1>;
2231                                         bias-bus-hold;
2232                                 };
2233                         };
2234
2235                         rx_swr_active: rx-swr-active-state {
2236                                 clk-pins {
2237                                         pins = "gpio3";
2238                                         function = "swr_rx_clk";
2239                                         drive-strength = <2>;
2240                                         slew-rate = <1>;
2241                                         bias-disable;
2242                                 };
2243
2244                                 data-pins {
2245                                         pins = "gpio4", "gpio5";
2246                                         function = "swr_rx_data";
2247                                         drive-strength = <2>;
2248                                         slew-rate = <1>;
2249                                         bias-bus-hold;
2250                                 };
2251                         };
2252
2253                         dmic01_default: dmic01-default-state {
2254                                 clk-pins {
2255                                         pins = "gpio6";
2256                                         function = "dmic1_clk";
2257                                         drive-strength = <8>;
2258                                         output-high;
2259                                 };
2260
2261                                 data-pins {
2262                                         pins = "gpio7";
2263                                         function = "dmic1_data";
2264                                         drive-strength = <8>;
2265                                         input-enable;
2266                                 };
2267                         };
2268
2269                         dmic02_default: dmic02-default-state {
2270                                 clk-pins {
2271                                         pins = "gpio8";
2272                                         function = "dmic2_clk";
2273                                         drive-strength = <8>;
2274                                         output-high;
2275                                 };
2276
2277                                 data-pins {
2278                                         pins = "gpio9";
2279                                         function = "dmic2_data";
2280                                         drive-strength = <8>;
2281                                         input-enable;
2282                                 };
2283                         };
2284
2285                         wsa_swr_active: wsa-swr-active-state {
2286                                 clk-pins {
2287                                         pins = "gpio10";
2288                                         function = "wsa_swr_clk";
2289                                         drive-strength = <2>;
2290                                         slew-rate = <1>;
2291                                         bias-disable;
2292                                 };
2293
2294                                 data-pins {
2295                                         pins = "gpio11";
2296                                         function = "wsa_swr_data";
2297                                         drive-strength = <2>;
2298                                         slew-rate = <1>;
2299                                         bias-bus-hold;
2300                                 };
2301                         };
2302
2303                         wsa2_swr_active: wsa2-swr-active-state {
2304                                 clk-pins {
2305                                         pins = "gpio15";
2306                                         function = "wsa2_swr_clk";
2307                                         drive-strength = <2>;
2308                                         slew-rate = <1>;
2309                                         bias-disable;
2310                                 };
2311
2312                                 data-pins {
2313                                         pins = "gpio16";
2314                                         function = "wsa2_swr_data";
2315                                         drive-strength = <2>;
2316                                         slew-rate = <1>;
2317                                         bias-bus-hold;
2318                                 };
2319                         };
2320                 };
2321
2322                 lpass_lpiaon_noc: interconnect@7400000 {
2323                         compatible = "qcom,sm8550-lpass-lpiaon-noc";
2324                         reg = <0 0x07400000 0 0x19080>;
2325                         #interconnect-cells = <2>;
2326                         qcom,bcm-voters = <&apps_bcm_voter>;
2327                 };
2328
2329                 lpass_lpicx_noc: interconnect@7430000 {
2330                         compatible = "qcom,sm8550-lpass-lpicx-noc";
2331                         reg = <0 0x07430000 0 0x3a200>;
2332                         #interconnect-cells = <2>;
2333                         qcom,bcm-voters = <&apps_bcm_voter>;
2334                 };
2335
2336                 lpass_ag_noc: interconnect@7e40000 {
2337                         compatible = "qcom,sm8550-lpass-ag-noc";
2338                         reg = <0 0x07e40000 0 0xe080>;
2339                         #interconnect-cells = <2>;
2340                         qcom,bcm-voters = <&apps_bcm_voter>;
2341                 };
2342
2343                 sdhc_2: mmc@8804000 {
2344                         compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2345                         reg = <0 0x08804000 0 0x1000>;
2346
2347                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2348                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2349                         interrupt-names = "hc_irq", "pwr_irq";
2350
2351                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2352                                  <&gcc GCC_SDCC2_APPS_CLK>,
2353                                  <&rpmhcc RPMH_CXO_CLK>;
2354                         clock-names = "iface", "core", "xo";
2355                         iommus = <&apps_smmu 0x540 0>;
2356                         qcom,dll-config = <0x0007642c>;
2357                         qcom,ddr-config = <0x80040868>;
2358                         power-domains = <&rpmhpd SM8550_CX>;
2359                         operating-points-v2 = <&sdhc2_opp_table>;
2360
2361                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2362                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2363                         interconnect-names = "sdhc-ddr", "cpu-sdhc";
2364                         bus-width = <4>;
2365                         dma-coherent;
2366
2367                         /* Forbid SDR104/SDR50 - broken hw! */
2368                         sdhci-caps-mask = <0x3 0>;
2369
2370                         status = "disabled";
2371
2372                         sdhc2_opp_table: opp-table {
2373                                 compatible = "operating-points-v2";
2374
2375                                 opp-19200000 {
2376                                         opp-hz = /bits/ 64 <19200000>;
2377                                         required-opps = <&rpmhpd_opp_min_svs>;
2378                                 };
2379
2380                                 opp-50000000 {
2381                                         opp-hz = /bits/ 64 <50000000>;
2382                                         required-opps = <&rpmhpd_opp_low_svs>;
2383                                 };
2384
2385                                 opp-100000000 {
2386                                         opp-hz = /bits/ 64 <100000000>;
2387                                         required-opps = <&rpmhpd_opp_svs>;
2388                                 };
2389
2390                                 opp-202000000 {
2391                                         opp-hz = /bits/ 64 <202000000>;
2392                                         required-opps = <&rpmhpd_opp_svs_l1>;
2393                                 };
2394                         };
2395                 };
2396
2397                 mdss: display-subsystem@ae00000 {
2398                         compatible = "qcom,sm8550-mdss";
2399                         reg = <0 0x0ae00000 0 0x1000>;
2400                         reg-names = "mdss";
2401
2402                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2403                         interrupt-controller;
2404                         #interrupt-cells = <1>;
2405
2406                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2407                                  <&gcc GCC_DISP_AHB_CLK>,
2408                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2409                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2410
2411                         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2412
2413                         power-domains = <&dispcc MDSS_GDSC>;
2414
2415                         interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
2416                                         <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2417                         interconnect-names = "mdp0-mem", "mdp1-mem";
2418
2419                         iommus = <&apps_smmu 0x1c00 0x2>;
2420
2421                         #address-cells = <2>;
2422                         #size-cells = <2>;
2423                         ranges;
2424
2425                         status = "disabled";
2426
2427                         mdss_mdp: display-controller@ae01000 {
2428                                 compatible = "qcom,sm8550-dpu";
2429                                 reg = <0 0x0ae01000 0 0x8f000>,
2430                                       <0 0x0aeb0000 0 0x2008>;
2431                                 reg-names = "mdp", "vbif";
2432
2433                                 interrupt-parent = <&mdss>;
2434                                 interrupts = <0>;
2435
2436                                 clocks = <&gcc GCC_DISP_AHB_CLK>,
2437                                          <&gcc GCC_DISP_HF_AXI_CLK>,
2438                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2439                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2440                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2441                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2442                                 clock-names = "bus",
2443                                               "nrt_bus",
2444                                               "iface",
2445                                               "lut",
2446                                               "core",
2447                                               "vsync";
2448
2449                                 power-domains = <&rpmhpd SM8550_MMCX>;
2450
2451                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2452                                 assigned-clock-rates = <19200000>;
2453
2454                                 operating-points-v2 = <&mdp_opp_table>;
2455
2456                                 ports {
2457                                         #address-cells = <1>;
2458                                         #size-cells = <0>;
2459
2460                                         port@0 {
2461                                                 reg = <0>;
2462                                                 dpu_intf1_out: endpoint {
2463                                                         remote-endpoint = <&mdss_dsi0_in>;
2464                                                 };
2465                                         };
2466
2467                                         port@1 {
2468                                                 reg = <1>;
2469                                                 dpu_intf2_out: endpoint {
2470                                                         remote-endpoint = <&mdss_dsi1_in>;
2471                                                 };
2472                                         };
2473                                 };
2474
2475                                 mdp_opp_table: opp-table {
2476                                         compatible = "operating-points-v2";
2477
2478                                         opp-200000000 {
2479                                                 opp-hz = /bits/ 64 <200000000>;
2480                                                 required-opps = <&rpmhpd_opp_low_svs>;
2481                                         };
2482
2483                                         opp-325000000 {
2484                                                 opp-hz = /bits/ 64 <325000000>;
2485                                                 required-opps = <&rpmhpd_opp_svs>;
2486                                         };
2487
2488                                         opp-375000000 {
2489                                                 opp-hz = /bits/ 64 <375000000>;
2490                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2491                                         };
2492
2493                                         opp-514000000 {
2494                                                 opp-hz = /bits/ 64 <514000000>;
2495                                                 required-opps = <&rpmhpd_opp_nom>;
2496                                         };
2497                                 };
2498                         };
2499
2500                         mdss_dsi0: dsi@ae94000 {
2501                                 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2502                                 reg = <0 0x0ae94000 0 0x400>;
2503                                 reg-names = "dsi_ctrl";
2504
2505                                 interrupt-parent = <&mdss>;
2506                                 interrupts = <4>;
2507
2508                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2509                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2510                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2511                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2512                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2513                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2514                                 clock-names = "byte",
2515                                               "byte_intf",
2516                                               "pixel",
2517                                               "core",
2518                                               "iface",
2519                                               "bus";
2520
2521                                 power-domains = <&rpmhpd SM8550_MMCX>;
2522
2523                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2524                                                   <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2525                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2526                                                          <&mdss_dsi0_phy 1>;
2527
2528                                 operating-points-v2 = <&mdss_dsi_opp_table>;
2529
2530                                 phys = <&mdss_dsi0_phy>;
2531                                 phy-names = "dsi";
2532
2533                                 #address-cells = <1>;
2534                                 #size-cells = <0>;
2535
2536                                 status = "disabled";
2537
2538                                 ports {
2539                                         #address-cells = <1>;
2540                                         #size-cells = <0>;
2541
2542                                         port@0 {
2543                                                 reg = <0>;
2544                                                 mdss_dsi0_in: endpoint {
2545                                                         remote-endpoint = <&dpu_intf1_out>;
2546                                                 };
2547                                         };
2548
2549                                         port@1 {
2550                                                 reg = <1>;
2551                                                 mdss_dsi0_out: endpoint {
2552                                                 };
2553                                         };
2554                                 };
2555
2556                                 mdss_dsi_opp_table: opp-table {
2557                                         compatible = "operating-points-v2";
2558
2559                                         opp-187500000 {
2560                                                 opp-hz = /bits/ 64 <187500000>;
2561                                                 required-opps = <&rpmhpd_opp_low_svs>;
2562                                         };
2563
2564                                         opp-300000000 {
2565                                                 opp-hz = /bits/ 64 <300000000>;
2566                                                 required-opps = <&rpmhpd_opp_svs>;
2567                                         };
2568
2569                                         opp-358000000 {
2570                                                 opp-hz = /bits/ 64 <358000000>;
2571                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2572                                         };
2573                                 };
2574                         };
2575
2576                         mdss_dsi0_phy: phy@ae95000 {
2577                                 compatible = "qcom,sm8550-dsi-phy-4nm";
2578                                 reg = <0 0x0ae95000 0 0x200>,
2579                                       <0 0x0ae95200 0 0x280>,
2580                                       <0 0x0ae95500 0 0x400>;
2581                                 reg-names = "dsi_phy",
2582                                             "dsi_phy_lane",
2583                                             "dsi_pll";
2584
2585                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2586                                          <&rpmhcc RPMH_CXO_CLK>;
2587                                 clock-names = "iface", "ref";
2588
2589                                 #clock-cells = <1>;
2590                                 #phy-cells = <0>;
2591
2592                                 status = "disabled";
2593                         };
2594
2595                         mdss_dsi1: dsi@ae96000 {
2596                                 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2597                                 reg = <0 0x0ae96000 0 0x400>;
2598                                 reg-names = "dsi_ctrl";
2599
2600                                 interrupt-parent = <&mdss>;
2601                                 interrupts = <5>;
2602
2603                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2604                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2605                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2606                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2607                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2608                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2609                                 clock-names = "byte",
2610                                               "byte_intf",
2611                                               "pixel",
2612                                               "core",
2613                                               "iface",
2614                                               "bus";
2615
2616                                 power-domains = <&rpmhpd SM8550_MMCX>;
2617
2618                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2619                                                   <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2620                                 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2621                                                          <&mdss_dsi1_phy 1>;
2622
2623                                 operating-points-v2 = <&mdss_dsi_opp_table>;
2624
2625                                 phys = <&mdss_dsi1_phy>;
2626                                 phy-names = "dsi";
2627
2628                                 #address-cells = <1>;
2629                                 #size-cells = <0>;
2630
2631                                 status = "disabled";
2632
2633                                 ports {
2634                                         #address-cells = <1>;
2635                                         #size-cells = <0>;
2636
2637                                         port@0 {
2638                                                 reg = <0>;
2639                                                 mdss_dsi1_in: endpoint {
2640                                                         remote-endpoint = <&dpu_intf2_out>;
2641                                                 };
2642                                         };
2643
2644                                         port@1 {
2645                                                 reg = <1>;
2646                                                 mdss_dsi1_out: endpoint {
2647                                                 };
2648                                         };
2649                                 };
2650                         };
2651
2652                         mdss_dsi1_phy: phy@ae97000 {
2653                                 compatible = "qcom,sm8550-dsi-phy-4nm";
2654                                 reg = <0 0x0ae97000 0 0x200>,
2655                                       <0 0x0ae97200 0 0x280>,
2656                                       <0 0x0ae97500 0 0x400>;
2657                                 reg-names = "dsi_phy",
2658                                             "dsi_phy_lane",
2659                                             "dsi_pll";
2660
2661                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2662                                          <&rpmhcc RPMH_CXO_CLK>;
2663                                 clock-names = "iface", "ref";
2664
2665                                 #clock-cells = <1>;
2666                                 #phy-cells = <0>;
2667
2668                                 status = "disabled";
2669                         };
2670                 };
2671
2672                 dispcc: clock-controller@af00000 {
2673                         compatible = "qcom,sm8550-dispcc";
2674                         reg = <0 0x0af00000 0 0x20000>;
2675                         clocks = <&bi_tcxo_div2>,
2676                                  <&bi_tcxo_ao_div2>,
2677                                  <&gcc GCC_DISP_AHB_CLK>,
2678                                  <&sleep_clk>,
2679                                  <&mdss_dsi0_phy 0>,
2680                                  <&mdss_dsi0_phy 1>,
2681                                  <&mdss_dsi1_phy 0>,
2682                                  <&mdss_dsi1_phy 1>,
2683                                  <0>, /* dp0 */
2684                                  <0>,
2685                                  <0>, /* dp1 */
2686                                  <0>,
2687                                  <0>, /* dp2 */
2688                                  <0>,
2689                                  <0>, /* dp3 */
2690                                  <0>;
2691                         power-domains = <&rpmhpd SM8550_MMCX>;
2692                         required-opps = <&rpmhpd_opp_low_svs>;
2693                         #clock-cells = <1>;
2694                         #reset-cells = <1>;
2695                         #power-domain-cells = <1>;
2696                         status = "disabled";
2697                 };
2698
2699                 usb_1_hsphy: phy@88e3000 {
2700                         compatible = "qcom,sm8550-snps-eusb2-phy";
2701                         reg = <0x0 0x088e3000 0x0 0x154>;
2702                         #phy-cells = <0>;
2703
2704                         clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
2705                         clock-names = "ref";
2706
2707                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2708
2709                         status = "disabled";
2710                 };
2711
2712                 usb_dp_qmpphy: phy@88e8000 {
2713                         compatible = "qcom,sm8550-qmp-usb3-dp-phy";
2714                         reg = <0x0 0x088e8000 0x0 0x3000>;
2715
2716                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2717                                  <&rpmhcc RPMH_CXO_CLK>,
2718                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2719                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2720                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2721
2722                         power-domains = <&gcc USB3_PHY_GDSC>;
2723
2724                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2725                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2726                         reset-names = "phy", "common";
2727
2728                         #clock-cells = <1>;
2729                         #phy-cells = <1>;
2730
2731                         status = "disabled";
2732                 };
2733
2734                 usb_1: usb@a6f8800 {
2735                         compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
2736                         reg = <0x0 0x0a6f8800 0x0 0x400>;
2737                         #address-cells = <2>;
2738                         #size-cells = <2>;
2739                         ranges;
2740
2741                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2742                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2743                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2744                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2745                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2746                                  <&tcsr TCSR_USB3_CLKREF_EN>;
2747                         clock-names = "cfg_noc",
2748                                       "core",
2749                                       "iface",
2750                                       "sleep",
2751                                       "mock_utmi",
2752                                       "xo";
2753
2754                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2755                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2756                         assigned-clock-rates = <19200000>, <200000000>;
2757
2758                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2759                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
2760                                               <&pdc 15 IRQ_TYPE_EDGE_RISING>,
2761                                               <&pdc 14 IRQ_TYPE_EDGE_RISING>;
2762                         interrupt-names = "hs_phy_irq",
2763                                           "ss_phy_irq",
2764                                           "dm_hs_phy_irq",
2765                                           "dp_hs_phy_irq";
2766
2767                         power-domains = <&gcc USB30_PRIM_GDSC>;
2768                         required-opps = <&rpmhpd_opp_nom>;
2769
2770                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2771
2772                         status = "disabled";
2773
2774                         usb_1_dwc3: usb@a600000 {
2775                                 compatible = "snps,dwc3";
2776                                 reg = <0x0 0x0a600000 0x0 0xcd00>;
2777                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2778                                 iommus = <&apps_smmu 0x40 0x0>;
2779                                 snps,dis_u2_susphy_quirk;
2780                                 snps,dis_enblslpm_quirk;
2781                                 snps,usb3_lpm_capable;
2782                                 phys = <&usb_1_hsphy>,
2783                                        <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
2784                                 phy-names = "usb2-phy", "usb3-phy";
2785
2786                                 ports {
2787                                         #address-cells = <1>;
2788                                         #size-cells = <0>;
2789
2790                                         port@0 {
2791                                                 reg = <0>;
2792
2793                                                 usb_1_dwc3_hs: endpoint {
2794                                                 };
2795                                         };
2796
2797                                         port@1 {
2798                                                 reg = <1>;
2799
2800                                                 usb_1_dwc3_ss: endpoint {
2801                                                 };
2802                                         };
2803                                 };
2804                         };
2805                 };
2806
2807                 pdc: interrupt-controller@b220000 {
2808                         compatible = "qcom,sm8550-pdc", "qcom,pdc";
2809                         reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
2810                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2811                                           <125 63 1>, <126 716 12>,
2812                                           <138 251 5>;
2813                         #interrupt-cells = <2>;
2814                         interrupt-parent = <&intc>;
2815                         interrupt-controller;
2816                 };
2817
2818                 tsens0: thermal-sensor@c271000 {
2819                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2820                         reg = <0 0x0c271000 0 0x1000>, /* TM */
2821                               <0 0x0c222000 0 0x1000>; /* SROT */
2822                         #qcom,sensors = <16>;
2823                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2824                                      <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
2825                         interrupt-names = "uplow", "critical";
2826                         #thermal-sensor-cells = <1>;
2827                 };
2828
2829                 tsens1: thermal-sensor@c272000 {
2830                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2831                         reg = <0 0x0c272000 0 0x1000>, /* TM */
2832                               <0 0x0c223000 0 0x1000>; /* SROT */
2833                         #qcom,sensors = <16>;
2834                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2835                                      <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
2836                         interrupt-names = "uplow", "critical";
2837                         #thermal-sensor-cells = <1>;
2838                 };
2839
2840                 tsens2: thermal-sensor@c273000 {
2841                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2842                         reg = <0 0x0c273000 0 0x1000>, /* TM */
2843                               <0 0x0c224000 0 0x1000>; /* SROT */
2844                         #qcom,sensors = <16>;
2845                         interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
2846                                      <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
2847                         interrupt-names = "uplow", "critical";
2848                         #thermal-sensor-cells = <1>;
2849                 };
2850
2851                 aoss_qmp: power-management@c300000 {
2852                         compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
2853                         reg = <0 0x0c300000 0 0x400>;
2854                         interrupt-parent = <&ipcc>;
2855                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2856                                                      IRQ_TYPE_EDGE_RISING>;
2857                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2858
2859                         #clock-cells = <0>;
2860                 };
2861
2862                 sram@c3f0000 {
2863                         compatible = "qcom,rpmh-stats";
2864                         reg = <0 0x0c3f0000 0 0x400>;
2865                 };
2866
2867                 spmi_bus: spmi@c400000 {
2868                         compatible = "qcom,spmi-pmic-arb";
2869                         reg = <0 0x0c400000 0 0x3000>,
2870                               <0 0x0c500000 0 0x4000000>,
2871                               <0 0x0c440000 0 0x80000>,
2872                               <0 0x0c4c0000 0 0x20000>,
2873                               <0 0x0c42d000 0 0x4000>;
2874                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2875                         interrupt-names = "periph_irq";
2876                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2877                         qcom,ee = <0>;
2878                         qcom,channel = <0>;
2879                         qcom,bus-id = <0>;
2880                         #address-cells = <2>;
2881                         #size-cells = <0>;
2882                         interrupt-controller;
2883                         #interrupt-cells = <4>;
2884                 };
2885
2886                 tlmm: pinctrl@f000000 {
2887                         compatible = "qcom,sm8550-tlmm";
2888                         reg = <0 0x0f100000 0 0x300000>;
2889                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2890                         gpio-controller;
2891                         #gpio-cells = <2>;
2892                         interrupt-controller;
2893                         #interrupt-cells = <2>;
2894                         gpio-ranges = <&tlmm 0 0 211>;
2895                         wakeup-parent = <&pdc>;
2896
2897                         hub_i2c0_data_clk: hub-i2c0-data-clk-state {
2898                                 /* SDA, SCL */
2899                                 pins = "gpio16", "gpio17";
2900                                 function = "i2chub0_se0";
2901                                 drive-strength = <2>;
2902                                 bias-pull-up;
2903                         };
2904
2905                         hub_i2c1_data_clk: hub-i2c1-data-clk-state {
2906                                 /* SDA, SCL */
2907                                 pins = "gpio18", "gpio19";
2908                                 function = "i2chub0_se1";
2909                                 drive-strength = <2>;
2910                                 bias-pull-up;
2911                         };
2912
2913                         hub_i2c2_data_clk: hub-i2c2-data-clk-state {
2914                                 /* SDA, SCL */
2915                                 pins = "gpio20", "gpio21";
2916                                 function = "i2chub0_se2";
2917                                 drive-strength = <2>;
2918                                 bias-pull-up;
2919                         };
2920
2921                         hub_i2c3_data_clk: hub-i2c3-data-clk-state {
2922                                 /* SDA, SCL */
2923                                 pins = "gpio22", "gpio23";
2924                                 function = "i2chub0_se3";
2925                                 drive-strength = <2>;
2926                                 bias-pull-up;
2927                         };
2928
2929                         hub_i2c4_data_clk: hub-i2c4-data-clk-state {
2930                                 /* SDA, SCL */
2931                                 pins = "gpio4", "gpio5";
2932                                 function = "i2chub0_se4";
2933                                 drive-strength = <2>;
2934                                 bias-pull-up;
2935                         };
2936
2937                         hub_i2c5_data_clk: hub-i2c5-data-clk-state {
2938                                 /* SDA, SCL */
2939                                 pins = "gpio6", "gpio7";
2940                                 function = "i2chub0_se5";
2941                                 drive-strength = <2>;
2942                                 bias-pull-up;
2943                         };
2944
2945                         hub_i2c6_data_clk: hub-i2c6-data-clk-state {
2946                                 /* SDA, SCL */
2947                                 pins = "gpio8", "gpio9";
2948                                 function = "i2chub0_se6";
2949                                 drive-strength = <2>;
2950                                 bias-pull-up;
2951                         };
2952
2953                         hub_i2c7_data_clk: hub-i2c7-data-clk-state {
2954                                 /* SDA, SCL */
2955                                 pins = "gpio10", "gpio11";
2956                                 function = "i2chub0_se7";
2957                                 drive-strength = <2>;
2958                                 bias-pull-up;
2959                         };
2960
2961                         hub_i2c8_data_clk: hub-i2c8-data-clk-state {
2962                                 /* SDA, SCL */
2963                                 pins = "gpio206", "gpio207";
2964                                 function = "i2chub0_se8";
2965                                 drive-strength = <2>;
2966                                 bias-pull-up;
2967                         };
2968
2969                         hub_i2c9_data_clk: hub-i2c9-data-clk-state {
2970                                 /* SDA, SCL */
2971                                 pins = "gpio84", "gpio85";
2972                                 function = "i2chub0_se9";
2973                                 drive-strength = <2>;
2974                                 bias-pull-up;
2975                         };
2976
2977                         pcie0_default_state: pcie0-default-state {
2978                                 perst-pins {
2979                                         pins = "gpio94";
2980                                         function = "gpio";
2981                                         drive-strength = <2>;
2982                                         bias-pull-down;
2983                                 };
2984
2985                                 clkreq-pins {
2986                                         pins = "gpio95";
2987                                         function = "pcie0_clk_req_n";
2988                                         drive-strength = <2>;
2989                                         bias-pull-up;
2990                                 };
2991
2992                                 wake-pins {
2993                                         pins = "gpio96";
2994                                         function = "gpio";
2995                                         drive-strength = <2>;
2996                                         bias-pull-up;
2997                                 };
2998                         };
2999
3000                         pcie1_default_state: pcie1-default-state {
3001                                 perst-pins {
3002                                         pins = "gpio97";
3003                                         function = "gpio";
3004                                         drive-strength = <2>;
3005                                         bias-pull-down;
3006                                 };
3007
3008                                 clkreq-pins {
3009                                         pins = "gpio98";
3010                                         function = "pcie1_clk_req_n";
3011                                         drive-strength = <2>;
3012                                         bias-pull-up;
3013                                 };
3014
3015                                 wake-pins {
3016                                         pins = "gpio99";
3017                                         function = "gpio";
3018                                         drive-strength = <2>;
3019                                         bias-pull-up;
3020                                 };
3021                         };
3022
3023                         qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3024                                 /* SDA, SCL */
3025                                 pins = "gpio28", "gpio29";
3026                                 function = "qup1_se0";
3027                                 drive-strength = <2>;
3028                                 bias-pull-up = <2200>;
3029                         };
3030
3031                         qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3032                                 /* SDA, SCL */
3033                                 pins = "gpio32", "gpio33";
3034                                 function = "qup1_se1";
3035                                 drive-strength = <2>;
3036                                 bias-pull-up = <2200>;
3037                         };
3038
3039                         qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3040                                 /* SDA, SCL */
3041                                 pins = "gpio36", "gpio37";
3042                                 function = "qup1_se2";
3043                                 drive-strength = <2>;
3044                                 bias-pull-up = <2200>;
3045                         };
3046
3047                         qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3048                                 /* SDA, SCL */
3049                                 pins = "gpio40", "gpio41";
3050                                 function = "qup1_se3";
3051                                 drive-strength = <2>;
3052                                 bias-pull-up = <2200>;
3053                         };
3054
3055                         qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3056                                 /* SDA, SCL */
3057                                 pins = "gpio44", "gpio45";
3058                                 function = "qup1_se4";
3059                                 drive-strength = <2>;
3060                                 bias-pull-up = <2200>;
3061                         };
3062
3063                         qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3064                                 /* SDA, SCL */
3065                                 pins = "gpio52", "gpio53";
3066                                 function = "qup1_se5";
3067                                 drive-strength = <2>;
3068                                 bias-pull-up = <2200>;
3069                         };
3070
3071                         qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3072                                 /* SDA, SCL */
3073                                 pins = "gpio48", "gpio49";
3074                                 function = "qup1_se6";
3075                                 drive-strength = <2>;
3076                                 bias-pull-up = <2200>;
3077                         };
3078
3079                         qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3080                                 scl-pins {
3081                                         pins = "gpio57";
3082                                         function = "qup2_se0_l1_mira";
3083                                         drive-strength = <2>;
3084                                         bias-pull-up = <2200>;
3085                                 };
3086
3087                                 sda-pins {
3088                                         pins = "gpio56";
3089                                         function = "qup2_se0_l0_mira";
3090                                         drive-strength = <2>;
3091                                         bias-pull-up = <2200>;
3092                                 };
3093                         };
3094
3095                         qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3096                                 /* SDA, SCL */
3097                                 pins = "gpio60", "gpio61";
3098                                 function = "qup2_se1";
3099                                 drive-strength = <2>;
3100                                 bias-pull-up = <2200>;
3101                         };
3102
3103                         qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3104                                 /* SDA, SCL */
3105                                 pins = "gpio64", "gpio65";
3106                                 function = "qup2_se2";
3107                                 drive-strength = <2>;
3108                                 bias-pull-up = <2200>;
3109                         };
3110
3111                         qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3112                                 /* SDA, SCL */
3113                                 pins = "gpio68", "gpio69";
3114                                 function = "qup2_se3";
3115                                 drive-strength = <2>;
3116                                 bias-pull-up = <2200>;
3117                         };
3118
3119                         qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3120                                 /* SDA, SCL */
3121                                 pins = "gpio2", "gpio3";
3122                                 function = "qup2_se4";
3123                                 drive-strength = <2>;
3124                                 bias-pull-up = <2200>;
3125                         };
3126
3127                         qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3128                                 /* SDA, SCL */
3129                                 pins = "gpio80", "gpio81";
3130                                 function = "qup2_se5";
3131                                 drive-strength = <2>;
3132                                 bias-pull-up = <2200>;
3133                         };
3134
3135                         qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3136                                 /* SDA, SCL */
3137                                 pins = "gpio72", "gpio106";
3138                                 function = "qup2_se7";
3139                                 drive-strength = <2>;
3140                                 bias-pull-up = <2200>;
3141                         };
3142
3143                         qup_spi0_cs: qup-spi0-cs-state {
3144                                 pins = "gpio31";
3145                                 function = "qup1_se0";
3146                                 drive-strength = <6>;
3147                                 bias-disable;
3148                         };
3149
3150                         qup_spi0_data_clk: qup-spi0-data-clk-state {
3151                                 /* MISO, MOSI, CLK */
3152                                 pins = "gpio28", "gpio29", "gpio30";
3153                                 function = "qup1_se0";
3154                                 drive-strength = <6>;
3155                                 bias-disable;
3156                         };
3157
3158                         qup_spi1_cs: qup-spi1-cs-state {
3159                                 pins = "gpio35";
3160                                 function = "qup1_se1";
3161                                 drive-strength = <6>;
3162                                 bias-disable;
3163                         };
3164
3165                         qup_spi1_data_clk: qup-spi1-data-clk-state {
3166                                 /* MISO, MOSI, CLK */
3167                                 pins = "gpio32", "gpio33", "gpio34";
3168                                 function = "qup1_se1";
3169                                 drive-strength = <6>;
3170                                 bias-disable;
3171                         };
3172
3173                         qup_spi2_cs: qup-spi2-cs-state {
3174                                 pins = "gpio39";
3175                                 function = "qup1_se2";
3176                                 drive-strength = <6>;
3177                                 bias-disable;
3178                         };
3179
3180                         qup_spi2_data_clk: qup-spi2-data-clk-state {
3181                                 /* MISO, MOSI, CLK */
3182                                 pins = "gpio36", "gpio37", "gpio38";
3183                                 function = "qup1_se2";
3184                                 drive-strength = <6>;
3185                                 bias-disable;
3186                         };
3187
3188                         qup_spi3_cs: qup-spi3-cs-state {
3189                                 pins = "gpio43";
3190                                 function = "qup1_se3";
3191                                 drive-strength = <6>;
3192                                 bias-disable;
3193                         };
3194
3195                         qup_spi3_data_clk: qup-spi3-data-clk-state {
3196                                 /* MISO, MOSI, CLK */
3197                                 pins = "gpio40", "gpio41", "gpio42";
3198                                 function = "qup1_se3";
3199                                 drive-strength = <6>;
3200                                 bias-disable;
3201                         };
3202
3203                         qup_spi4_cs: qup-spi4-cs-state {
3204                                 pins = "gpio47";
3205                                 function = "qup1_se4";
3206                                 drive-strength = <6>;
3207                                 bias-disable;
3208                         };
3209
3210                         qup_spi4_data_clk: qup-spi4-data-clk-state {
3211                                 /* MISO, MOSI, CLK */
3212                                 pins = "gpio44", "gpio45", "gpio46";
3213                                 function = "qup1_se4";
3214                                 drive-strength = <6>;
3215                                 bias-disable;
3216                         };
3217
3218                         qup_spi5_cs: qup-spi5-cs-state {
3219                                 pins = "gpio55";
3220                                 function = "qup1_se5";
3221                                 drive-strength = <6>;
3222                                 bias-disable;
3223                         };
3224
3225                         qup_spi5_data_clk: qup-spi5-data-clk-state {
3226                                 /* MISO, MOSI, CLK */
3227                                 pins = "gpio52", "gpio53", "gpio54";
3228                                 function = "qup1_se5";
3229                                 drive-strength = <6>;
3230                                 bias-disable;
3231                         };
3232
3233                         qup_spi6_cs: qup-spi6-cs-state {
3234                                 pins = "gpio51";
3235                                 function = "qup1_se6";
3236                                 drive-strength = <6>;
3237                                 bias-disable;
3238                         };
3239
3240                         qup_spi6_data_clk: qup-spi6-data-clk-state {
3241                                 /* MISO, MOSI, CLK */
3242                                 pins = "gpio48", "gpio49", "gpio50";
3243                                 function = "qup1_se6";
3244                                 drive-strength = <6>;
3245                                 bias-disable;
3246                         };
3247
3248                         qup_spi8_cs: qup-spi8-cs-state {
3249                                 pins = "gpio59";
3250                                 function = "qup2_se0_l3_mira";
3251                                 drive-strength = <6>;
3252                                 bias-disable;
3253                         };
3254
3255                         qup_spi8_data_clk: qup-spi8-data-clk-state {
3256                                 /* MISO, MOSI, CLK */
3257                                 pins = "gpio56", "gpio57", "gpio58";
3258                                 function = "qup2_se0_l2_mira";
3259                                 drive-strength = <6>;
3260                                 bias-disable;
3261                         };
3262
3263                         qup_spi9_cs: qup-spi9-cs-state {
3264                                 pins = "gpio63";
3265                                 function = "qup2_se1";
3266                                 drive-strength = <6>;
3267                                 bias-disable;
3268                         };
3269
3270                         qup_spi9_data_clk: qup-spi9-data-clk-state {
3271                                 /* MISO, MOSI, CLK */
3272                                 pins = "gpio60", "gpio61", "gpio62";
3273                                 function = "qup2_se1";
3274                                 drive-strength = <6>;
3275                                 bias-disable;
3276                         };
3277
3278                         qup_spi10_cs: qup-spi10-cs-state {
3279                                 pins = "gpio67";
3280                                 function = "qup2_se2";
3281                                 drive-strength = <6>;
3282                                 bias-disable;
3283                         };
3284
3285                         qup_spi10_data_clk: qup-spi10-data-clk-state {
3286                                 /* MISO, MOSI, CLK */
3287                                 pins = "gpio64", "gpio65", "gpio66";
3288                                 function = "qup2_se2";
3289                                 drive-strength = <6>;
3290                                 bias-disable;
3291                         };
3292
3293                         qup_spi11_cs: qup-spi11-cs-state {
3294                                 pins = "gpio71";
3295                                 function = "qup2_se3";
3296                                 drive-strength = <6>;
3297                                 bias-disable;
3298                         };
3299
3300                         qup_spi11_data_clk: qup-spi11-data-clk-state {
3301                                 /* MISO, MOSI, CLK */
3302                                 pins = "gpio68", "gpio69", "gpio70";
3303                                 function = "qup2_se3";
3304                                 drive-strength = <6>;
3305                                 bias-disable;
3306                         };
3307
3308                         qup_spi12_cs: qup-spi12-cs-state {
3309                                 pins = "gpio119";
3310                                 function = "qup2_se4";
3311                                 drive-strength = <6>;
3312                                 bias-disable;
3313                         };
3314
3315                         qup_spi12_data_clk: qup-spi12-data-clk-state {
3316                                 /* MISO, MOSI, CLK */
3317                                 pins = "gpio2", "gpio3", "gpio118";
3318                                 function = "qup2_se4";
3319                                 drive-strength = <6>;
3320                                 bias-disable;
3321                         };
3322
3323                         qup_spi13_cs: qup-spi13-cs-state {
3324                                 pins = "gpio83";
3325                                 function = "qup2_se5";
3326                                 drive-strength = <6>;
3327                                 bias-disable;
3328                         };
3329
3330                         qup_spi13_data_clk: qup-spi13-data-clk-state {
3331                                 /* MISO, MOSI, CLK */
3332                                 pins = "gpio80", "gpio81", "gpio82";
3333                                 function = "qup2_se5";
3334                                 drive-strength = <6>;
3335                                 bias-disable;
3336                         };
3337
3338                         qup_spi15_cs: qup-spi15-cs-state {
3339                                 pins = "gpio75";
3340                                 function = "qup2_se7";
3341                                 drive-strength = <6>;
3342                                 bias-disable;
3343                         };
3344
3345                         qup_spi15_data_clk: qup-spi15-data-clk-state {
3346                                 /* MISO, MOSI, CLK */
3347                                 pins = "gpio72", "gpio106", "gpio74";
3348                                 function = "qup2_se7";
3349                                 drive-strength = <6>;
3350                                 bias-disable;
3351                         };
3352
3353                         qup_uart7_default: qup-uart7-default-state {
3354                                 /* TX, RX */
3355                                 pins = "gpio26", "gpio27";
3356                                 function = "qup1_se7";
3357                                 drive-strength = <2>;
3358                                 bias-disable;
3359                         };
3360
3361                         sdc2_sleep: sdc2-sleep-state {
3362                                 clk-pins {
3363                                         pins = "sdc2_clk";
3364                                         bias-disable;
3365                                         drive-strength = <2>;
3366                                 };
3367
3368                                 cmd-pins {
3369                                         pins = "sdc2_cmd";
3370                                         bias-pull-up;
3371                                         drive-strength = <2>;
3372                                 };
3373
3374                                 data-pins {
3375                                         pins = "sdc2_data";
3376                                         bias-pull-up;
3377                                         drive-strength = <2>;
3378                                 };
3379                         };
3380
3381                         sdc2_default: sdc2-default-state {
3382                                 clk-pins {
3383                                         pins = "sdc2_clk";
3384                                         bias-disable;
3385                                         drive-strength = <16>;
3386                                 };
3387
3388                                 cmd-pins {
3389                                         pins = "sdc2_cmd";
3390                                         bias-pull-up;
3391                                         drive-strength = <10>;
3392                                 };
3393
3394                                 data-pins {
3395                                         pins = "sdc2_data";
3396                                         bias-pull-up;
3397                                         drive-strength = <10>;
3398                                 };
3399                         };
3400                 };
3401
3402                 apps_smmu: iommu@15000000 {
3403                         compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3404                         reg = <0 0x15000000 0 0x100000>;
3405                         #iommu-cells = <2>;
3406                         #global-interrupts = <1>;
3407                         interrupts =    <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3408                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3409                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3410                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3411                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3412                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3413                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3414                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3415                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3416                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3417                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3418                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3419                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3420                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3421                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3422                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3423                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3424                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3425                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3426                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3427                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3428                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3429                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3430                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3431                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3432                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3433                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3434                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3435                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3436                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3437                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3438                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3439                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3440                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3441                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3442                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3443                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3444                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3445                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3446                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3447                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3448                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3449                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3450                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3451                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3452                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3453                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3454                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3455                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3456                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3457                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3458                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3459                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3460                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3461                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3462                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3463                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3464                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3465                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3466                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3467                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3468                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3469                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3470                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3471                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3472                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3473                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3474                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3475                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3476                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3477                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3478                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3479                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3480                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3481                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3482                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3483                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3484                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3485                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3486                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3487                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3488                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3489                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3490                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3491                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3492                                         <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3493                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3494                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3495                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3496                                         <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
3497                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3498                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3499                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3500                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3501                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3502                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3503                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
3504                 };
3505
3506                 intc: interrupt-controller@17100000 {
3507                         compatible = "arm,gic-v3";
3508                         reg = <0 0x17100000 0 0x10000>,         /* GICD */
3509                               <0 0x17180000 0 0x200000>;        /* GICR * 8 */
3510                         ranges;
3511                         #interrupt-cells = <3>;
3512                         interrupt-controller;
3513                         #redistributor-regions = <1>;
3514                         redistributor-stride = <0 0x40000>;
3515                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
3516                         #address-cells = <2>;
3517                         #size-cells = <2>;
3518
3519                         gic_its: msi-controller@17140000 {
3520                                 compatible = "arm,gic-v3-its";
3521                                 reg = <0 0x17140000 0 0x20000>;
3522                                 msi-controller;
3523                                 #msi-cells = <1>;
3524                         };
3525                 };
3526
3527                 timer@17420000 {
3528                         compatible = "arm,armv7-timer-mem";
3529                         reg = <0 0x17420000 0 0x1000>;
3530                         ranges = <0 0 0 0x20000000>;
3531                         #address-cells = <1>;
3532                         #size-cells = <1>;
3533
3534                         frame@17421000 {
3535                                 reg = <0x17421000 0x1000>,
3536                                       <0x17422000 0x1000>;
3537                                 frame-number = <0>;
3538                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3539                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3540                         };
3541
3542                         frame@17423000 {
3543                                 reg = <0x17423000 0x1000>;
3544                                 frame-number = <1>;
3545                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3546                                 status = "disabled";
3547                         };
3548
3549                         frame@17425000 {
3550                                 reg = <0x17425000 0x1000>;
3551                                 frame-number = <2>;
3552                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3553                                 status = "disabled";
3554                         };
3555
3556                         frame@17427000 {
3557                                 reg = <0x17427000 0x1000>;
3558                                 frame-number = <3>;
3559                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3560                                 status = "disabled";
3561                         };
3562
3563                         frame@17429000 {
3564                                 reg = <0x17429000 0x1000>;
3565                                 frame-number = <4>;
3566                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3567                                 status = "disabled";
3568                         };
3569
3570                         frame@1742b000 {
3571                                 reg = <0x1742b000 0x1000>;
3572                                 frame-number = <5>;
3573                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3574                                 status = "disabled";
3575                         };
3576
3577                         frame@1742d000 {
3578                                 reg = <0x1742d000 0x1000>;
3579                                 frame-number = <6>;
3580                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3581                                 status = "disabled";
3582                         };
3583                 };
3584
3585                 apps_rsc: rsc@17a00000 {
3586                         label = "apps_rsc";
3587                         compatible = "qcom,rpmh-rsc";
3588                         reg = <0 0x17a00000 0 0x10000>,
3589                               <0 0x17a10000 0 0x10000>,
3590                               <0 0x17a20000 0 0x10000>,
3591                               <0 0x17a30000 0 0x10000>;
3592                         reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3593                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3594                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3595                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3596                         qcom,tcs-offset = <0xd00>;
3597                         qcom,drv-id = <2>;
3598                         qcom,tcs-config = <ACTIVE_TCS    3>, <SLEEP_TCS     2>,
3599                                           <WAKE_TCS      2>, <CONTROL_TCS   0>;
3600
3601                         apps_bcm_voter: bcm-voter {
3602                                 compatible = "qcom,bcm-voter";
3603                         };
3604
3605                         rpmhcc: clock-controller {
3606                                 compatible = "qcom,sm8550-rpmh-clk";
3607                                 #clock-cells = <1>;
3608                                 clock-names = "xo";
3609                                 clocks = <&xo_board>;
3610                         };
3611
3612                         rpmhpd: power-controller {
3613                                 compatible = "qcom,sm8550-rpmhpd";
3614                                 #power-domain-cells = <1>;
3615                                 operating-points-v2 = <&rpmhpd_opp_table>;
3616
3617                                 rpmhpd_opp_table: opp-table {
3618                                         compatible = "operating-points-v2";
3619
3620                                         rpmhpd_opp_ret: opp1 {
3621                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3622                                         };
3623
3624                                         rpmhpd_opp_min_svs: opp2 {
3625                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3626                                         };
3627
3628                                         rpmhpd_opp_low_svs: opp3 {
3629                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3630                                         };
3631
3632                                         rpmhpd_opp_svs: opp4 {
3633                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3634                                         };
3635
3636                                         rpmhpd_opp_svs_l1: opp5 {
3637                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3638                                         };
3639
3640                                         rpmhpd_opp_nom: opp6 {
3641                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3642                                         };
3643
3644                                         rpmhpd_opp_nom_l1: opp7 {
3645                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3646                                         };
3647
3648                                         rpmhpd_opp_nom_l2: opp8 {
3649                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3650                                         };
3651
3652                                         rpmhpd_opp_turbo: opp9 {
3653                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3654                                         };
3655
3656                                         rpmhpd_opp_turbo_l1: opp10 {
3657                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3658                                         };
3659                                 };
3660                         };
3661                 };
3662
3663                 cpufreq_hw: cpufreq@17d91000 {
3664                         compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
3665                         reg = <0 0x17d91000 0 0x1000>,
3666                               <0 0x17d92000 0 0x1000>,
3667                               <0 0x17d93000 0 0x1000>;
3668                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3669                         clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
3670                         clock-names = "xo", "alternate";
3671                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
3672                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3673                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
3674                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3675                         #freq-domain-cells = <1>;
3676                         #clock-cells = <1>;
3677                 };
3678
3679                 pmu@24091000 {
3680                         compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3681                         reg = <0 0x24091000 0 0x1000>;
3682                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3683                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3684
3685                         operating-points-v2 = <&llcc_bwmon_opp_table>;
3686
3687                         llcc_bwmon_opp_table: opp-table {
3688                                 compatible = "operating-points-v2";
3689
3690                                 opp-0 {
3691                                         opp-peak-kBps = <2086000>;
3692                                 };
3693
3694                                 opp-1 {
3695                                         opp-peak-kBps = <2929000>;
3696                                 };
3697
3698                                 opp-2 {
3699                                         opp-peak-kBps = <5931000>;
3700                                 };
3701
3702                                 opp-3 {
3703                                         opp-peak-kBps = <6515000>;
3704                                 };
3705
3706                                 opp-4 {
3707                                         opp-peak-kBps = <7980000>;
3708                                 };
3709
3710                                 opp-5 {
3711                                         opp-peak-kBps = <10437000>;
3712                                 };
3713
3714                                 opp-6 {
3715                                         opp-peak-kBps = <12157000>;
3716                                 };
3717
3718                                 opp-7 {
3719                                         opp-peak-kBps = <14060000>;
3720                                 };
3721
3722                                 opp-8 {
3723                                         opp-peak-kBps = <16113000>;
3724                                 };
3725                         };
3726                 };
3727
3728                 pmu@240b6400 {
3729                         compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
3730                         reg = <0 0x240b6400 0 0x600>;
3731                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3732                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3733
3734                         operating-points-v2 = <&cpu_bwmon_opp_table>;
3735
3736                         cpu_bwmon_opp_table: opp-table {
3737                                 compatible = "operating-points-v2";
3738
3739                                 opp-0 {
3740                                         opp-peak-kBps = <4577000>;
3741                                 };
3742
3743                                 opp-1 {
3744                                         opp-peak-kBps = <7110000>;
3745                                 };
3746
3747                                 opp-2 {
3748                                         opp-peak-kBps = <9155000>;
3749                                 };
3750
3751                                 opp-3 {
3752                                         opp-peak-kBps = <12298000>;
3753                                 };
3754
3755                                 opp-4 {
3756                                         opp-peak-kBps = <14236000>;
3757                                 };
3758
3759                                 opp-5 {
3760                                         opp-peak-kBps = <16265000>;
3761                                 };
3762                         };
3763                 };
3764
3765                 gem_noc: interconnect@24100000 {
3766                         compatible = "qcom,sm8550-gem-noc";
3767                         reg = <0 0x24100000 0 0xbb800>;
3768                         #interconnect-cells = <2>;
3769                         qcom,bcm-voters = <&apps_bcm_voter>;
3770                 };
3771
3772                 system-cache-controller@25000000 {
3773                         compatible = "qcom,sm8550-llcc";
3774                         reg = <0 0x25000000 0 0x200000>,
3775                               <0 0x25200000 0 0x200000>,
3776                               <0 0x25400000 0 0x200000>,
3777                               <0 0x25600000 0 0x200000>,
3778                               <0 0x25800000 0 0x200000>;
3779                         reg-names = "llcc0_base",
3780                                     "llcc1_base",
3781                                     "llcc2_base",
3782                                     "llcc3_base",
3783                                     "llcc_broadcast_base";
3784                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
3785                 };
3786
3787                 remoteproc_adsp: remoteproc@30000000 {
3788                         compatible = "qcom,sm8550-adsp-pas";
3789                         reg = <0x0 0x30000000 0x0 0x100>;
3790
3791                         interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3792                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3793                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3794                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3795                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3796                         interrupt-names = "wdog", "fatal", "ready",
3797                                           "handover", "stop-ack";
3798
3799                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3800                         clock-names = "xo";
3801
3802                         power-domains = <&rpmhpd SM8550_LCX>,
3803                                         <&rpmhpd SM8550_LMX>;
3804                         power-domain-names = "lcx", "lmx";
3805
3806                         interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
3807
3808                         memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
3809
3810                         qcom,qmp = <&aoss_qmp>;
3811
3812                         qcom,smem-states = <&smp2p_adsp_out 0>;
3813                         qcom,smem-state-names = "stop";
3814
3815                         status = "disabled";
3816
3817                         remoteproc_adsp_glink: glink-edge {
3818                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3819                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3820                                                              IRQ_TYPE_EDGE_RISING>;
3821                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
3822                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3823
3824                                 label = "lpass";
3825                                 qcom,remote-pid = <2>;
3826
3827                                 fastrpc {
3828                                         compatible = "qcom,fastrpc";
3829                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3830                                         label = "adsp";
3831                                         #address-cells = <1>;
3832                                         #size-cells = <0>;
3833
3834                                         compute-cb@3 {
3835                                                 compatible = "qcom,fastrpc-compute-cb";
3836                                                 reg = <3>;
3837                                                 iommus = <&apps_smmu 0x1003 0x80>,
3838                                                          <&apps_smmu 0x1063 0x0>;
3839                                         };
3840
3841                                         compute-cb@4 {
3842                                                 compatible = "qcom,fastrpc-compute-cb";
3843                                                 reg = <4>;
3844                                                 iommus = <&apps_smmu 0x1004 0x80>,
3845                                                          <&apps_smmu 0x1064 0x0>;
3846                                         };
3847
3848                                         compute-cb@5 {
3849                                                 compatible = "qcom,fastrpc-compute-cb";
3850                                                 reg = <5>;
3851                                                 iommus = <&apps_smmu 0x1005 0x80>,
3852                                                          <&apps_smmu 0x1065 0x0>;
3853                                         };
3854
3855                                         compute-cb@6 {
3856                                                 compatible = "qcom,fastrpc-compute-cb";
3857                                                 reg = <6>;
3858                                                 iommus = <&apps_smmu 0x1006 0x80>,
3859                                                          <&apps_smmu 0x1066 0x0>;
3860                                         };
3861
3862                                         compute-cb@7 {
3863                                                 compatible = "qcom,fastrpc-compute-cb";
3864                                                 reg = <7>;
3865                                                 iommus = <&apps_smmu 0x1007 0x80>,
3866                                                          <&apps_smmu 0x1067 0x0>;
3867                                         };
3868                                 };
3869
3870                                 gpr {
3871                                         compatible = "qcom,gpr";
3872                                         qcom,glink-channels = "adsp_apps";
3873                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
3874                                         qcom,intents = <512 20>;
3875                                         #address-cells = <1>;
3876                                         #size-cells = <0>;
3877
3878                                         q6apm: service@1 {
3879                                                 compatible = "qcom,q6apm";
3880                                                 reg = <GPR_APM_MODULE_IID>;
3881                                                 #sound-dai-cells = <0>;
3882                                                 qcom,protection-domain = "avs/audio",
3883                                                                          "msm/adsp/audio_pd";
3884
3885                                                 q6apmdai: dais {
3886                                                         compatible = "qcom,q6apm-dais";
3887                                                         iommus = <&apps_smmu 0x1001 0x80>,
3888                                                                  <&apps_smmu 0x1061 0x0>;
3889                                                 };
3890
3891                                                 q6apmbedai: bedais {
3892                                                         compatible = "qcom,q6apm-lpass-dais";
3893                                                         #sound-dai-cells = <1>;
3894                                                 };
3895                                         };
3896
3897                                         q6prm: service@2 {
3898                                                 compatible = "qcom,q6prm";
3899                                                 reg = <GPR_PRM_MODULE_IID>;
3900                                                 qcom,protection-domain = "avs/audio",
3901                                                                          "msm/adsp/audio_pd";
3902
3903                                                 q6prmcc: clock-controller {
3904                                                         compatible = "qcom,q6prm-lpass-clocks";
3905                                                         #clock-cells = <2>;
3906                                                 };
3907                                         };
3908                                 };
3909                         };
3910                 };
3911
3912                 nsp_noc: interconnect@320c0000 {
3913                         compatible = "qcom,sm8550-nsp-noc";
3914                         reg = <0 0x320c0000 0 0xe080>;
3915                         #interconnect-cells = <2>;
3916                         qcom,bcm-voters = <&apps_bcm_voter>;
3917                 };
3918
3919                 remoteproc_cdsp: remoteproc@32300000 {
3920                         compatible = "qcom,sm8550-cdsp-pas";
3921                         reg = <0x0 0x32300000 0x0 0x1400000>;
3922
3923                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3924                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3925                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3926                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3927                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3928                         interrupt-names = "wdog", "fatal", "ready",
3929                                           "handover", "stop-ack";
3930
3931                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3932                         clock-names = "xo";
3933
3934                         power-domains = <&rpmhpd SM8550_CX>,
3935                                         <&rpmhpd SM8550_MXC>,
3936                                         <&rpmhpd SM8550_NSP>;
3937                         power-domain-names = "cx", "mxc", "nsp";
3938
3939                         interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3940
3941                         memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
3942
3943                         qcom,qmp = <&aoss_qmp>;
3944
3945                         qcom,smem-states = <&smp2p_cdsp_out 0>;
3946                         qcom,smem-state-names = "stop";
3947
3948                         status = "disabled";
3949
3950                         glink-edge {
3951                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3952                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3953                                                              IRQ_TYPE_EDGE_RISING>;
3954                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
3955                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3956
3957                                 label = "cdsp";
3958                                 qcom,remote-pid = <5>;
3959
3960                                 fastrpc {
3961                                         compatible = "qcom,fastrpc";
3962                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3963                                         label = "cdsp";
3964                                         #address-cells = <1>;
3965                                         #size-cells = <0>;
3966
3967                                         compute-cb@1 {
3968                                                 compatible = "qcom,fastrpc-compute-cb";
3969                                                 reg = <1>;
3970                                                 iommus = <&apps_smmu 0x1961 0x0>,
3971                                                          <&apps_smmu 0x0c01 0x20>,
3972                                                          <&apps_smmu 0x19c1 0x10>;
3973                                         };
3974
3975                                         compute-cb@2 {
3976                                                 compatible = "qcom,fastrpc-compute-cb";
3977                                                 reg = <2>;
3978                                                 iommus = <&apps_smmu 0x1962 0x0>,
3979                                                          <&apps_smmu 0x0c02 0x20>,
3980                                                          <&apps_smmu 0x19c2 0x10>;
3981                                         };
3982
3983                                         compute-cb@3 {
3984                                                 compatible = "qcom,fastrpc-compute-cb";
3985                                                 reg = <3>;
3986                                                 iommus = <&apps_smmu 0x1963 0x0>,
3987                                                          <&apps_smmu 0x0c03 0x20>,
3988                                                          <&apps_smmu 0x19c3 0x10>;
3989                                         };
3990
3991                                         compute-cb@4 {
3992                                                 compatible = "qcom,fastrpc-compute-cb";
3993                                                 reg = <4>;
3994                                                 iommus = <&apps_smmu 0x1964 0x0>,
3995                                                          <&apps_smmu 0x0c04 0x20>,
3996                                                          <&apps_smmu 0x19c4 0x10>;
3997                                         };
3998
3999                                         compute-cb@5 {
4000                                                 compatible = "qcom,fastrpc-compute-cb";
4001                                                 reg = <5>;
4002                                                 iommus = <&apps_smmu 0x1965 0x0>,
4003                                                          <&apps_smmu 0x0c05 0x20>,
4004                                                          <&apps_smmu 0x19c5 0x10>;
4005                                         };
4006
4007                                         compute-cb@6 {
4008                                                 compatible = "qcom,fastrpc-compute-cb";
4009                                                 reg = <6>;
4010                                                 iommus = <&apps_smmu 0x1966 0x0>,
4011                                                          <&apps_smmu 0x0c06 0x20>,
4012                                                          <&apps_smmu 0x19c6 0x10>;
4013                                         };
4014
4015                                         compute-cb@7 {
4016                                                 compatible = "qcom,fastrpc-compute-cb";
4017                                                 reg = <7>;
4018                                                 iommus = <&apps_smmu 0x1967 0x0>,
4019                                                          <&apps_smmu 0x0c07 0x20>,
4020                                                          <&apps_smmu 0x19c7 0x10>;
4021                                         };
4022
4023                                         compute-cb@8 {
4024                                                 compatible = "qcom,fastrpc-compute-cb";
4025                                                 reg = <8>;
4026                                                 iommus = <&apps_smmu 0x1968 0x0>,
4027                                                          <&apps_smmu 0x0c08 0x20>,
4028                                                          <&apps_smmu 0x19c8 0x10>;
4029                                         };
4030
4031                                         /* note: secure cb9 in downstream */
4032                                 };
4033                         };
4034                 };
4035         };
4036
4037         thermal-zones {
4038                 aoss0-thermal {
4039                         polling-delay-passive = <0>;
4040                         polling-delay = <0>;
4041                         thermal-sensors = <&tsens0 0>;
4042
4043                         trips {
4044                                 thermal-engine-config {
4045                                         temperature = <125000>;
4046                                         hysteresis = <1000>;
4047                                         type = "passive";
4048                                 };
4049
4050                                 reset-mon-config {
4051                                         temperature = <115000>;
4052                                         hysteresis = <5000>;
4053                                         type = "passive";
4054                                 };
4055                         };
4056                 };
4057
4058                 cpuss0-thermal {
4059                         polling-delay-passive = <0>;
4060                         polling-delay = <0>;
4061                         thermal-sensors = <&tsens0 1>;
4062
4063                         trips {
4064                                 thermal-engine-config {
4065                                         temperature = <125000>;
4066                                         hysteresis = <1000>;
4067                                         type = "passive";
4068                                 };
4069
4070                                 reset-mon-config {
4071                                         temperature = <115000>;
4072                                         hysteresis = <5000>;
4073                                         type = "passive";
4074                                 };
4075                         };
4076                 };
4077
4078                 cpuss1-thermal {
4079                         polling-delay-passive = <0>;
4080                         polling-delay = <0>;
4081                         thermal-sensors = <&tsens0 2>;
4082
4083                         trips {
4084                                 thermal-engine-config {
4085                                         temperature = <125000>;
4086                                         hysteresis = <1000>;
4087                                         type = "passive";
4088                                 };
4089
4090                                 reset-mon-config {
4091                                         temperature = <115000>;
4092                                         hysteresis = <5000>;
4093                                         type = "passive";
4094                                 };
4095                         };
4096                 };
4097
4098                 cpuss2-thermal {
4099                         polling-delay-passive = <0>;
4100                         polling-delay = <0>;
4101                         thermal-sensors = <&tsens0 3>;
4102
4103                         trips {
4104                                 thermal-engine-config {
4105                                         temperature = <125000>;
4106                                         hysteresis = <1000>;
4107                                         type = "passive";
4108                                 };
4109
4110                                 reset-mon-config {
4111                                         temperature = <115000>;
4112                                         hysteresis = <5000>;
4113                                         type = "passive";
4114                                 };
4115                         };
4116                 };
4117
4118                 cpuss3-thermal {
4119                         polling-delay-passive = <0>;
4120                         polling-delay = <0>;
4121                         thermal-sensors = <&tsens0 4>;
4122
4123                         trips {
4124                                 thermal-engine-config {
4125                                         temperature = <125000>;
4126                                         hysteresis = <1000>;
4127                                         type = "passive";
4128                                 };
4129
4130                                 reset-mon-config {
4131                                         temperature = <115000>;
4132                                         hysteresis = <5000>;
4133                                         type = "passive";
4134                                 };
4135                         };
4136                 };
4137
4138                 cpu3-top-thermal {
4139                         polling-delay-passive = <0>;
4140                         polling-delay = <0>;
4141                         thermal-sensors = <&tsens0 5>;
4142
4143                         trips {
4144                                 cpu3_top_alert0: trip-point0 {
4145                                         temperature = <90000>;
4146                                         hysteresis = <2000>;
4147                                         type = "passive";
4148                                 };
4149
4150                                 cpu3_top_alert1: trip-point1 {
4151                                         temperature = <95000>;
4152                                         hysteresis = <2000>;
4153                                         type = "passive";
4154                                 };
4155
4156                                 cpu3_top_crit: cpu-critical {
4157                                         temperature = <110000>;
4158                                         hysteresis = <1000>;
4159                                         type = "critical";
4160                                 };
4161                         };
4162                 };
4163
4164                 cpu3-bottom-thermal {
4165                         polling-delay-passive = <0>;
4166                         polling-delay = <0>;
4167                         thermal-sensors = <&tsens0 6>;
4168
4169                         trips {
4170                                 cpu3_bottom_alert0: trip-point0 {
4171                                         temperature = <90000>;
4172                                         hysteresis = <2000>;
4173                                         type = "passive";
4174                                 };
4175
4176                                 cpu3_bottom_alert1: trip-point1 {
4177                                         temperature = <95000>;
4178                                         hysteresis = <2000>;
4179                                         type = "passive";
4180                                 };
4181
4182                                 cpu3_bottom_crit: cpu-critical {
4183                                         temperature = <110000>;
4184                                         hysteresis = <1000>;
4185                                         type = "critical";
4186                                 };
4187                         };
4188                 };
4189
4190                 cpu4-top-thermal {
4191                         polling-delay-passive = <0>;
4192                         polling-delay = <0>;
4193                         thermal-sensors = <&tsens0 7>;
4194
4195                         trips {
4196                                 cpu4_top_alert0: trip-point0 {
4197                                         temperature = <90000>;
4198                                         hysteresis = <2000>;
4199                                         type = "passive";
4200                                 };
4201
4202                                 cpu4_top_alert1: trip-point1 {
4203                                         temperature = <95000>;
4204                                         hysteresis = <2000>;
4205                                         type = "passive";
4206                                 };
4207
4208                                 cpu4_top_crit: cpu-critical {
4209                                         temperature = <110000>;
4210                                         hysteresis = <1000>;
4211                                         type = "critical";
4212                                 };
4213                         };
4214                 };
4215
4216                 cpu4-bottom-thermal {
4217                         polling-delay-passive = <0>;
4218                         polling-delay = <0>;
4219                         thermal-sensors = <&tsens0 8>;
4220
4221                         trips {
4222                                 cpu4_bottom_alert0: trip-point0 {
4223                                         temperature = <90000>;
4224                                         hysteresis = <2000>;
4225                                         type = "passive";
4226                                 };
4227
4228                                 cpu4_bottom_alert1: trip-point1 {
4229                                         temperature = <95000>;
4230                                         hysteresis = <2000>;
4231                                         type = "passive";
4232                                 };
4233
4234                                 cpu4_bottom_crit: cpu-critical {
4235                                         temperature = <110000>;
4236                                         hysteresis = <1000>;
4237                                         type = "critical";
4238                                 };
4239                         };
4240                 };
4241
4242                 cpu5-top-thermal {
4243                         polling-delay-passive = <0>;
4244                         polling-delay = <0>;
4245                         thermal-sensors = <&tsens0 9>;
4246
4247                         trips {
4248                                 cpu5_top_alert0: trip-point0 {
4249                                         temperature = <90000>;
4250                                         hysteresis = <2000>;
4251                                         type = "passive";
4252                                 };
4253
4254                                 cpu5_top_alert1: trip-point1 {
4255                                         temperature = <95000>;
4256                                         hysteresis = <2000>;
4257                                         type = "passive";
4258                                 };
4259
4260                                 cpu5_top_crit: cpu-critical {
4261                                         temperature = <110000>;
4262                                         hysteresis = <1000>;
4263                                         type = "critical";
4264                                 };
4265                         };
4266                 };
4267
4268                 cpu5-bottom-thermal {
4269                         polling-delay-passive = <0>;
4270                         polling-delay = <0>;
4271                         thermal-sensors = <&tsens0 10>;
4272
4273                         trips {
4274                                 cpu5_bottom_alert0: trip-point0 {
4275                                         temperature = <90000>;
4276                                         hysteresis = <2000>;
4277                                         type = "passive";
4278                                 };
4279
4280                                 cpu5_bottom_alert1: trip-point1 {
4281                                         temperature = <95000>;
4282                                         hysteresis = <2000>;
4283                                         type = "passive";
4284                                 };
4285
4286                                 cpu5_bottom_crit: cpu-critical {
4287                                         temperature = <110000>;
4288                                         hysteresis = <1000>;
4289                                         type = "critical";
4290                                 };
4291                         };
4292                 };
4293
4294                 cpu6-top-thermal {
4295                         polling-delay-passive = <0>;
4296                         polling-delay = <0>;
4297                         thermal-sensors = <&tsens0 11>;
4298
4299                         trips {
4300                                 cpu6_top_alert0: trip-point0 {
4301                                         temperature = <90000>;
4302                                         hysteresis = <2000>;
4303                                         type = "passive";
4304                                 };
4305
4306                                 cpu6_top_alert1: trip-point1 {
4307                                         temperature = <95000>;
4308                                         hysteresis = <2000>;
4309                                         type = "passive";
4310                                 };
4311
4312                                 cpu6_top_crit: cpu-critical {
4313                                         temperature = <110000>;
4314                                         hysteresis = <1000>;
4315                                         type = "critical";
4316                                 };
4317                         };
4318                 };
4319
4320                 cpu6-bottom-thermal {
4321                         polling-delay-passive = <0>;
4322                         polling-delay = <0>;
4323                         thermal-sensors = <&tsens0 12>;
4324
4325                         trips {
4326                                 cpu6_bottom_alert0: trip-point0 {
4327                                         temperature = <90000>;
4328                                         hysteresis = <2000>;
4329                                         type = "passive";
4330                                 };
4331
4332                                 cpu6_bottom_alert1: trip-point1 {
4333                                         temperature = <95000>;
4334                                         hysteresis = <2000>;
4335                                         type = "passive";
4336                                 };
4337
4338                                 cpu6_bottom_crit: cpu-critical {
4339                                         temperature = <110000>;
4340                                         hysteresis = <1000>;
4341                                         type = "critical";
4342                                 };
4343                         };
4344                 };
4345
4346                 cpu7-top-thermal {
4347                         polling-delay-passive = <0>;
4348                         polling-delay = <0>;
4349                         thermal-sensors = <&tsens0 13>;
4350
4351                         trips {
4352                                 cpu7_top_alert0: trip-point0 {
4353                                         temperature = <90000>;
4354                                         hysteresis = <2000>;
4355                                         type = "passive";
4356                                 };
4357
4358                                 cpu7_top_alert1: trip-point1 {
4359                                         temperature = <95000>;
4360                                         hysteresis = <2000>;
4361                                         type = "passive";
4362                                 };
4363
4364                                 cpu7_top_crit: cpu-critical {
4365                                         temperature = <110000>;
4366                                         hysteresis = <1000>;
4367                                         type = "critical";
4368                                 };
4369                         };
4370                 };
4371
4372                 cpu7-middle-thermal {
4373                         polling-delay-passive = <0>;
4374                         polling-delay = <0>;
4375                         thermal-sensors = <&tsens0 14>;
4376
4377                         trips {
4378                                 cpu7_middle_alert0: trip-point0 {
4379                                         temperature = <90000>;
4380                                         hysteresis = <2000>;
4381                                         type = "passive";
4382                                 };
4383
4384                                 cpu7_middle_alert1: trip-point1 {
4385                                         temperature = <95000>;
4386                                         hysteresis = <2000>;
4387                                         type = "passive";
4388                                 };
4389
4390                                 cpu7_middle_crit: cpu-critical {
4391                                         temperature = <110000>;
4392                                         hysteresis = <1000>;
4393                                         type = "critical";
4394                                 };
4395                         };
4396                 };
4397
4398                 cpu7-bottom-thermal {
4399                         polling-delay-passive = <0>;
4400                         polling-delay = <0>;
4401                         thermal-sensors = <&tsens0 15>;
4402
4403                         trips {
4404                                 cpu7_bottom_alert0: trip-point0 {
4405                                         temperature = <90000>;
4406                                         hysteresis = <2000>;
4407                                         type = "passive";
4408                                 };
4409
4410                                 cpu7_bottom_alert1: trip-point1 {
4411                                         temperature = <95000>;
4412                                         hysteresis = <2000>;
4413                                         type = "passive";
4414                                 };
4415
4416                                 cpu7_bottom_crit: cpu-critical {
4417                                         temperature = <110000>;
4418                                         hysteresis = <1000>;
4419                                         type = "critical";
4420                                 };
4421                         };
4422                 };
4423
4424                 aoss1-thermal {
4425                         polling-delay-passive = <0>;
4426                         polling-delay = <0>;
4427                         thermal-sensors = <&tsens1 0>;
4428
4429                         trips {
4430                                 thermal-engine-config {
4431                                         temperature = <125000>;
4432                                         hysteresis = <1000>;
4433                                         type = "passive";
4434                                 };
4435
4436                                 reset-mon-config {
4437                                         temperature = <115000>;
4438                                         hysteresis = <5000>;
4439                                         type = "passive";
4440                                 };
4441                         };
4442                 };
4443
4444                 cpu0-thermal {
4445                         polling-delay-passive = <0>;
4446                         polling-delay = <0>;
4447                         thermal-sensors = <&tsens1 1>;
4448
4449                         trips {
4450                                 cpu0_alert0: trip-point0 {
4451                                         temperature = <90000>;
4452                                         hysteresis = <2000>;
4453                                         type = "passive";
4454                                 };
4455
4456                                 cpu0_alert1: trip-point1 {
4457                                         temperature = <95000>;
4458                                         hysteresis = <2000>;
4459                                         type = "passive";
4460                                 };
4461
4462                                 cpu0_crit: cpu-critical {
4463                                         temperature = <110000>;
4464                                         hysteresis = <1000>;
4465                                         type = "critical";
4466                                 };
4467                         };
4468                 };
4469
4470                 cpu1-thermal {
4471                         polling-delay-passive = <0>;
4472                         polling-delay = <0>;
4473                         thermal-sensors = <&tsens1 2>;
4474
4475                         trips {
4476                                 cpu1_alert0: trip-point0 {
4477                                         temperature = <90000>;
4478                                         hysteresis = <2000>;
4479                                         type = "passive";
4480                                 };
4481
4482                                 cpu1_alert1: trip-point1 {
4483                                         temperature = <95000>;
4484                                         hysteresis = <2000>;
4485                                         type = "passive";
4486                                 };
4487
4488                                 cpu1_crit: cpu-critical {
4489                                         temperature = <110000>;
4490                                         hysteresis = <1000>;
4491                                         type = "critical";
4492                                 };
4493                         };
4494                 };
4495
4496                 cpu2-thermal {
4497                         polling-delay-passive = <0>;
4498                         polling-delay = <0>;
4499                         thermal-sensors = <&tsens1 3>;
4500
4501                         trips {
4502                                 cpu2_alert0: trip-point0 {
4503                                         temperature = <90000>;
4504                                         hysteresis = <2000>;
4505                                         type = "passive";
4506                                 };
4507
4508                                 cpu2_alert1: trip-point1 {
4509                                         temperature = <95000>;
4510                                         hysteresis = <2000>;
4511                                         type = "passive";
4512                                 };
4513
4514                                 cpu2_crit: cpu-critical {
4515                                         temperature = <110000>;
4516                                         hysteresis = <1000>;
4517                                         type = "critical";
4518                                 };
4519                         };
4520                 };
4521
4522                 cdsp0-thermal {
4523                         polling-delay-passive = <10>;
4524                         polling-delay = <0>;
4525                         thermal-sensors = <&tsens2 4>;
4526
4527                         trips {
4528                                 thermal-engine-config {
4529                                         temperature = <125000>;
4530                                         hysteresis = <1000>;
4531                                         type = "passive";
4532                                 };
4533
4534                                 thermal-hal-config {
4535                                         temperature = <125000>;
4536                                         hysteresis = <1000>;
4537                                         type = "passive";
4538                                 };
4539
4540                                 reset-mon-config {
4541                                         temperature = <115000>;
4542                                         hysteresis = <5000>;
4543                                         type = "passive";
4544                                 };
4545
4546                                 cdsp0_junction_config: junction-config {
4547                                         temperature = <95000>;
4548                                         hysteresis = <5000>;
4549                                         type = "passive";
4550                                 };
4551                         };
4552                 };
4553
4554                 cdsp1-thermal {
4555                         polling-delay-passive = <10>;
4556                         polling-delay = <0>;
4557                         thermal-sensors = <&tsens2 5>;
4558
4559                         trips {
4560                                 thermal-engine-config {
4561                                         temperature = <125000>;
4562                                         hysteresis = <1000>;
4563                                         type = "passive";
4564                                 };
4565
4566                                 thermal-hal-config {
4567                                         temperature = <125000>;
4568                                         hysteresis = <1000>;
4569                                         type = "passive";
4570                                 };
4571
4572                                 reset-mon-config {
4573                                         temperature = <115000>;
4574                                         hysteresis = <5000>;
4575                                         type = "passive";
4576                                 };
4577
4578                                 cdsp1_junction_config: junction-config {
4579                                         temperature = <95000>;
4580                                         hysteresis = <5000>;
4581                                         type = "passive";
4582                                 };
4583                         };
4584                 };
4585
4586                 cdsp2-thermal {
4587                         polling-delay-passive = <10>;
4588                         polling-delay = <0>;
4589                         thermal-sensors = <&tsens2 6>;
4590
4591                         trips {
4592                                 thermal-engine-config {
4593                                         temperature = <125000>;
4594                                         hysteresis = <1000>;
4595                                         type = "passive";
4596                                 };
4597
4598                                 thermal-hal-config {
4599                                         temperature = <125000>;
4600                                         hysteresis = <1000>;
4601                                         type = "passive";
4602                                 };
4603
4604                                 reset-mon-config {
4605                                         temperature = <115000>;
4606                                         hysteresis = <5000>;
4607                                         type = "passive";
4608                                 };
4609
4610                                 cdsp2_junction_config: junction-config {
4611                                         temperature = <95000>;
4612                                         hysteresis = <5000>;
4613                                         type = "passive";
4614                                 };
4615                         };
4616                 };
4617
4618                 cdsp3-thermal {
4619                         polling-delay-passive = <10>;
4620                         polling-delay = <0>;
4621                         thermal-sensors = <&tsens2 7>;
4622
4623                         trips {
4624                                 thermal-engine-config {
4625                                         temperature = <125000>;
4626                                         hysteresis = <1000>;
4627                                         type = "passive";
4628                                 };
4629
4630                                 thermal-hal-config {
4631                                         temperature = <125000>;
4632                                         hysteresis = <1000>;
4633                                         type = "passive";
4634                                 };
4635
4636                                 reset-mon-config {
4637                                         temperature = <115000>;
4638                                         hysteresis = <5000>;
4639                                         type = "passive";
4640                                 };
4641
4642                                 cdsp3_junction_config: junction-config {
4643                                         temperature = <95000>;
4644                                         hysteresis = <5000>;
4645                                         type = "passive";
4646                                 };
4647                         };
4648                 };
4649
4650                 video-thermal {
4651                         polling-delay-passive = <0>;
4652                         polling-delay = <0>;
4653                         thermal-sensors = <&tsens1 8>;
4654
4655                         trips {
4656                                 thermal-engine-config {
4657                                         temperature = <125000>;
4658                                         hysteresis = <1000>;
4659                                         type = "passive";
4660                                 };
4661
4662                                 reset-mon-config {
4663                                         temperature = <115000>;
4664                                         hysteresis = <5000>;
4665                                         type = "passive";
4666                                 };
4667                         };
4668                 };
4669
4670                 mem-thermal {
4671                         polling-delay-passive = <10>;
4672                         polling-delay = <0>;
4673                         thermal-sensors = <&tsens1 9>;
4674
4675                         trips {
4676                                 thermal-engine-config {
4677                                         temperature = <125000>;
4678                                         hysteresis = <1000>;
4679                                         type = "passive";
4680                                 };
4681
4682                                 ddr_config0: ddr0-config {
4683                                         temperature = <90000>;
4684                                         hysteresis = <5000>;
4685                                         type = "passive";
4686                                 };
4687
4688                                 reset-mon-config {
4689                                         temperature = <115000>;
4690                                         hysteresis = <5000>;
4691                                         type = "passive";
4692                                 };
4693                         };
4694                 };
4695
4696                 modem0-thermal {
4697                         polling-delay-passive = <0>;
4698                         polling-delay = <0>;
4699                         thermal-sensors = <&tsens1 10>;
4700
4701                         trips {
4702                                 thermal-engine-config {
4703                                         temperature = <125000>;
4704                                         hysteresis = <1000>;
4705                                         type = "passive";
4706                                 };
4707
4708                                 mdmss0_config0: mdmss0-config0 {
4709                                         temperature = <102000>;
4710                                         hysteresis = <3000>;
4711                                         type = "passive";
4712                                 };
4713
4714                                 mdmss0_config1: mdmss0-config1 {
4715                                         temperature = <105000>;
4716                                         hysteresis = <3000>;
4717                                         type = "passive";
4718                                 };
4719
4720                                 reset-mon-config {
4721                                         temperature = <115000>;
4722                                         hysteresis = <5000>;
4723                                         type = "passive";
4724                                 };
4725                         };
4726                 };
4727
4728                 modem1-thermal {
4729                         polling-delay-passive = <0>;
4730                         polling-delay = <0>;
4731                         thermal-sensors = <&tsens1 11>;
4732
4733                         trips {
4734                                 thermal-engine-config {
4735                                         temperature = <125000>;
4736                                         hysteresis = <1000>;
4737                                         type = "passive";
4738                                 };
4739
4740                                 mdmss1_config0: mdmss1-config0 {
4741                                         temperature = <102000>;
4742                                         hysteresis = <3000>;
4743                                         type = "passive";
4744                                 };
4745
4746                                 mdmss1_config1: mdmss1-config1 {
4747                                         temperature = <105000>;
4748                                         hysteresis = <3000>;
4749                                         type = "passive";
4750                                 };
4751
4752                                 reset-mon-config {
4753                                         temperature = <115000>;
4754                                         hysteresis = <5000>;
4755                                         type = "passive";
4756                                 };
4757                         };
4758                 };
4759
4760                 modem2-thermal {
4761                         polling-delay-passive = <0>;
4762                         polling-delay = <0>;
4763                         thermal-sensors = <&tsens1 12>;
4764
4765                         trips {
4766                                 thermal-engine-config {
4767                                         temperature = <125000>;
4768                                         hysteresis = <1000>;
4769                                         type = "passive";
4770                                 };
4771
4772                                 mdmss2_config0: mdmss2-config0 {
4773                                         temperature = <102000>;
4774                                         hysteresis = <3000>;
4775                                         type = "passive";
4776                                 };
4777
4778                                 mdmss2_config1: mdmss2-config1 {
4779                                         temperature = <105000>;
4780                                         hysteresis = <3000>;
4781                                         type = "passive";
4782                                 };
4783
4784                                 reset-mon-config {
4785                                         temperature = <115000>;
4786                                         hysteresis = <5000>;
4787                                         type = "passive";
4788                                 };
4789                         };
4790                 };
4791
4792                 modem3-thermal {
4793                         polling-delay-passive = <0>;
4794                         polling-delay = <0>;
4795                         thermal-sensors = <&tsens1 13>;
4796
4797                         trips {
4798                                 thermal-engine-config {
4799                                         temperature = <125000>;
4800                                         hysteresis = <1000>;
4801                                         type = "passive";
4802                                 };
4803
4804                                 mdmss3_config0: mdmss3-config0 {
4805                                         temperature = <102000>;
4806                                         hysteresis = <3000>;
4807                                         type = "passive";
4808                                 };
4809
4810                                 mdmss3_config1: mdmss3-config1 {
4811                                         temperature = <105000>;
4812                                         hysteresis = <3000>;
4813                                         type = "passive";
4814                                 };
4815
4816                                 reset-mon-config {
4817                                         temperature = <115000>;
4818                                         hysteresis = <5000>;
4819                                         type = "passive";
4820                                 };
4821                         };
4822                 };
4823
4824                 camera0-thermal {
4825                         polling-delay-passive = <0>;
4826                         polling-delay = <0>;
4827                         thermal-sensors = <&tsens1 14>;
4828
4829                         trips {
4830                                 thermal-engine-config {
4831                                         temperature = <125000>;
4832                                         hysteresis = <1000>;
4833                                         type = "passive";
4834                                 };
4835
4836                                 reset-mon-config {
4837                                         temperature = <115000>;
4838                                         hysteresis = <5000>;
4839                                         type = "passive";
4840                                 };
4841                         };
4842                 };
4843
4844                 camera1-thermal {
4845                         polling-delay-passive = <0>;
4846                         polling-delay = <0>;
4847                         thermal-sensors = <&tsens1 15>;
4848
4849                         trips {
4850                                 thermal-engine-config {
4851                                         temperature = <125000>;
4852                                         hysteresis = <1000>;
4853                                         type = "passive";
4854                                 };
4855
4856                                 reset-mon-config {
4857                                         temperature = <115000>;
4858                                         hysteresis = <5000>;
4859                                         type = "passive";
4860                                 };
4861                         };
4862                 };
4863
4864                 aoss2-thermal {
4865                         polling-delay-passive = <0>;
4866                         polling-delay = <0>;
4867                         thermal-sensors = <&tsens2 0>;
4868
4869                         trips {
4870                                 thermal-engine-config {
4871                                         temperature = <125000>;
4872                                         hysteresis = <1000>;
4873                                         type = "passive";
4874                                 };
4875
4876                                 reset-mon-config {
4877                                         temperature = <115000>;
4878                                         hysteresis = <5000>;
4879                                         type = "passive";
4880                                 };
4881                         };
4882                 };
4883
4884                 gpuss-0-thermal {
4885                         polling-delay-passive = <10>;
4886                         polling-delay = <0>;
4887                         thermal-sensors = <&tsens2 1>;
4888
4889                         trips {
4890                                 thermal-engine-config {
4891                                         temperature = <125000>;
4892                                         hysteresis = <1000>;
4893                                         type = "passive";
4894                                 };
4895
4896                                 thermal-hal-config {
4897                                         temperature = <125000>;
4898                                         hysteresis = <1000>;
4899                                         type = "passive";
4900                                 };
4901
4902                                 reset-mon-config {
4903                                         temperature = <115000>;
4904                                         hysteresis = <5000>;
4905                                         type = "passive";
4906                                 };
4907
4908                                 gpu0_junction_config: junction-config {
4909                                         temperature = <95000>;
4910                                         hysteresis = <5000>;
4911                                         type = "passive";
4912                                 };
4913                         };
4914                 };
4915
4916                 gpuss-1-thermal {
4917                         polling-delay-passive = <10>;
4918                         polling-delay = <0>;
4919                         thermal-sensors = <&tsens2 2>;
4920
4921                         trips {
4922                                 thermal-engine-config {
4923                                         temperature = <125000>;
4924                                         hysteresis = <1000>;
4925                                         type = "passive";
4926                                 };
4927
4928                                 thermal-hal-config {
4929                                         temperature = <125000>;
4930                                         hysteresis = <1000>;
4931                                         type = "passive";
4932                                 };
4933
4934                                 reset-mon-config {
4935                                         temperature = <115000>;
4936                                         hysteresis = <5000>;
4937                                         type = "passive";
4938                                 };
4939
4940                                 gpu1_junction_config: junction-config {
4941                                         temperature = <95000>;
4942                                         hysteresis = <5000>;
4943                                         type = "passive";
4944                                 };
4945                         };
4946                 };
4947
4948                 gpuss-2-thermal {
4949                         polling-delay-passive = <10>;
4950                         polling-delay = <0>;
4951                         thermal-sensors = <&tsens2 3>;
4952
4953                         trips {
4954                                 thermal-engine-config {
4955                                         temperature = <125000>;
4956                                         hysteresis = <1000>;
4957                                         type = "passive";
4958                                 };
4959
4960                                 thermal-hal-config {
4961                                         temperature = <125000>;
4962                                         hysteresis = <1000>;
4963                                         type = "passive";
4964                                 };
4965
4966                                 reset-mon-config {
4967                                         temperature = <115000>;
4968                                         hysteresis = <5000>;
4969                                         type = "passive";
4970                                 };
4971
4972                                 gpu2_junction_config: junction-config {
4973                                         temperature = <95000>;
4974                                         hysteresis = <5000>;
4975                                         type = "passive";
4976                                 };
4977                         };
4978                 };
4979
4980                 gpuss-3-thermal {
4981                         polling-delay-passive = <10>;
4982                         polling-delay = <0>;
4983                         thermal-sensors = <&tsens2 4>;
4984
4985                         trips {
4986                                 thermal-engine-config {
4987                                         temperature = <125000>;
4988                                         hysteresis = <1000>;
4989                                         type = "passive";
4990                                 };
4991
4992                                 thermal-hal-config {
4993                                         temperature = <125000>;
4994                                         hysteresis = <1000>;
4995                                         type = "passive";
4996                                 };
4997
4998                                 reset-mon-config {
4999                                         temperature = <115000>;
5000                                         hysteresis = <5000>;
5001                                         type = "passive";
5002                                 };
5003
5004                                 gpu3_junction_config: junction-config {
5005                                         temperature = <95000>;
5006                                         hysteresis = <5000>;
5007                                         type = "passive";
5008                                 };
5009                         };
5010                 };
5011
5012                 gpuss-4-thermal {
5013                         polling-delay-passive = <10>;
5014                         polling-delay = <0>;
5015                         thermal-sensors = <&tsens2 5>;
5016
5017                         trips {
5018                                 thermal-engine-config {
5019                                         temperature = <125000>;
5020                                         hysteresis = <1000>;
5021                                         type = "passive";
5022                                 };
5023
5024                                 thermal-hal-config {
5025                                         temperature = <125000>;
5026                                         hysteresis = <1000>;
5027                                         type = "passive";
5028                                 };
5029
5030                                 reset-mon-config {
5031                                         temperature = <115000>;
5032                                         hysteresis = <5000>;
5033                                         type = "passive";
5034                                 };
5035
5036                                 gpu4_junction_config: junction-config {
5037                                         temperature = <95000>;
5038                                         hysteresis = <5000>;
5039                                         type = "passive";
5040                                 };
5041                         };
5042                 };
5043
5044                 gpuss-5-thermal {
5045                         polling-delay-passive = <10>;
5046                         polling-delay = <0>;
5047                         thermal-sensors = <&tsens2 6>;
5048
5049                         trips {
5050                                 thermal-engine-config {
5051                                         temperature = <125000>;
5052                                         hysteresis = <1000>;
5053                                         type = "passive";
5054                                 };
5055
5056                                 thermal-hal-config {
5057                                         temperature = <125000>;
5058                                         hysteresis = <1000>;
5059                                         type = "passive";
5060                                 };
5061
5062                                 reset-mon-config {
5063                                         temperature = <115000>;
5064                                         hysteresis = <5000>;
5065                                         type = "passive";
5066                                 };
5067
5068                                 gpu5_junction_config: junction-config {
5069                                         temperature = <95000>;
5070                                         hysteresis = <5000>;
5071                                         type = "passive";
5072                                 };
5073                         };
5074                 };
5075
5076                 gpuss-6-thermal {
5077                         polling-delay-passive = <10>;
5078                         polling-delay = <0>;
5079                         thermal-sensors = <&tsens2 7>;
5080
5081                         trips {
5082                                 thermal-engine-config {
5083                                         temperature = <125000>;
5084                                         hysteresis = <1000>;
5085                                         type = "passive";
5086                                 };
5087
5088                                 thermal-hal-config {
5089                                         temperature = <125000>;
5090                                         hysteresis = <1000>;
5091                                         type = "passive";
5092                                 };
5093
5094                                 reset-mon-config {
5095                                         temperature = <115000>;
5096                                         hysteresis = <5000>;
5097                                         type = "passive";
5098                                 };
5099
5100                                 gpu6_junction_config: junction-config {
5101                                         temperature = <95000>;
5102                                         hysteresis = <5000>;
5103                                         type = "passive";
5104                                 };
5105                         };
5106                 };
5107
5108                 gpuss-7-thermal {
5109                         polling-delay-passive = <10>;
5110                         polling-delay = <0>;
5111                         thermal-sensors = <&tsens2 8>;
5112
5113                         trips {
5114                                 thermal-engine-config {
5115                                         temperature = <125000>;
5116                                         hysteresis = <1000>;
5117                                         type = "passive";
5118                                 };
5119
5120                                 thermal-hal-config {
5121                                         temperature = <125000>;
5122                                         hysteresis = <1000>;
5123                                         type = "passive";
5124                                 };
5125
5126                                 reset-mon-config {
5127                                         temperature = <115000>;
5128                                         hysteresis = <5000>;
5129                                         type = "passive";
5130                                 };
5131
5132                                 gpu7_junction_config: junction-config {
5133                                         temperature = <95000>;
5134                                         hysteresis = <5000>;
5135                                         type = "passive";
5136                                 };
5137                         };
5138                 };
5139         };
5140
5141         timer {
5142                 compatible = "arm,armv8-timer";
5143                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5144                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5145                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5146                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5147         };
5148 };