arch/arm64/boot/dts/qcom/sm8550.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2022, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/clock/qcom,rpmh.h>
   7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
   8 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
   9 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
  10 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
  11 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
  12 #include <dt-bindings/dma/qcom-gpi.h>
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
  16 #include <dt-bindings/mailbox/qcom-ipcc.h>
  17 #include <dt-bindings/power/qcom-rpmpd.h>
  18 #include <dt-bindings/power/qcom,rpmhpd.h>
  19 #include <dt-bindings/soc/qcom,gpr.h>
  20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  21 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
  22 #include <dt-bindings/phy/phy-qcom-qmp.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24
  25 / {
  26         interrupt-parent = <&intc>;
  27
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         chosen { };
  32
  33         clocks {
  34                 xo_board: xo-board {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                 };
  38
  39                 sleep_clk: sleep-clk {
  40                         compatible = "fixed-clock";
  41                         #clock-cells = <0>;
  42                 };
  43
  44                 bi_tcxo_div2: bi-tcxo-div2-clk {
  45                         #clock-cells = <0>;
  46                         compatible = "fixed-factor-clock";
  47                         clocks = <&rpmhcc RPMH_CXO_CLK>;
  48                         clock-mult = <1>;
  49                         clock-div = <2>;
  50                 };
  51
  52                 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
  53                         #clock-cells = <0>;
  54                         compatible = "fixed-factor-clock";
  55                         clocks = <&rpmhcc RPMH_CXO_CLK_A>;
  56                         clock-mult = <1>;
  57                         clock-div = <2>;
  58                 };
  59
  60                 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
  61                         compatible = "fixed-clock";
  62                         #clock-cells = <0>;
  63                 };
  64         };
  65
  66         cpus {
  67                 #address-cells = <2>;
  68                 #size-cells = <0>;
  69
  70                 CPU0: cpu@0 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a510";
  73                         reg = <0 0>;
  74                         clocks = <&cpufreq_hw 0>;
  75                         enable-method = "psci";
  76                         next-level-cache = <&L2_0>;
  77                         power-domains = <&CPU_PD0>;
  78                         power-domain-names = "psci";
  79                         qcom,freq-domain = <&cpufreq_hw 0>;
  80                         capacity-dmips-mhz = <1024>;
  81                         dynamic-power-coefficient = <100>;
  82                         #cooling-cells = <2>;
  83                         L2_0: l2-cache {
  84                                 compatible = "cache";
  85                                 cache-level = <2>;
  86                                 cache-unified;
  87                                 next-level-cache = <&L3_0>;
  88                                 L3_0: l3-cache {
  89                                         compatible = "cache";
  90                                         cache-level = <3>;
  91                                         cache-unified;
  92                                 };
  93                         };
  94                 };
  95
  96                 CPU1: cpu@100 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a510";
  99                         reg = <0 0x100>;
 100                         clocks = <&cpufreq_hw 0>;
 101                         enable-method = "psci";
 102                         next-level-cache = <&L2_100>;
 103                         power-domains = <&CPU_PD1>;
 104                         power-domain-names = "psci";
 105                         qcom,freq-domain = <&cpufreq_hw 0>;
 106                         capacity-dmips-mhz = <1024>;
 107                         dynamic-power-coefficient = <100>;
 108                         #cooling-cells = <2>;
 109                         L2_100: l2-cache {
 110                                 compatible = "cache";
 111                                 cache-level = <2>;
 112                                 cache-unified;
 113                                 next-level-cache = <&L3_0>;
 114                         };
 115                 };
 116
 117                 CPU2: cpu@200 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a510";
 120                         reg = <0 0x200>;
 121                         clocks = <&cpufreq_hw 0>;
 122                         enable-method = "psci";
 123                         next-level-cache = <&L2_200>;
 124                         power-domains = <&CPU_PD2>;
 125                         power-domain-names = "psci";
 126                         qcom,freq-domain = <&cpufreq_hw 0>;
 127                         capacity-dmips-mhz = <1024>;
 128                         dynamic-power-coefficient = <100>;
 129                         #cooling-cells = <2>;
 130                         L2_200: l2-cache {
 131                                 compatible = "cache";
 132                                 cache-level = <2>;
 133                                 cache-unified;
 134                                 next-level-cache = <&L3_0>;
 135                         };
 136                 };
 137
 138                 CPU3: cpu@300 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a715";
 141                         reg = <0 0x300>;
 142                         clocks = <&cpufreq_hw 1>;
 143                         enable-method = "psci";
 144                         next-level-cache = <&L2_300>;
 145                         power-domains = <&CPU_PD3>;
 146                         power-domain-names = "psci";
 147                         qcom,freq-domain = <&cpufreq_hw 1>;
 148                         capacity-dmips-mhz = <1792>;
 149                         dynamic-power-coefficient = <270>;
 150                         #cooling-cells = <2>;
 151                         L2_300: l2-cache {
 152                                 compatible = "cache";
 153                                 cache-level = <2>;
 154                                 cache-unified;
 155                                 next-level-cache = <&L3_0>;
 156                         };
 157                 };
 158
 159                 CPU4: cpu@400 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a715";
 162                         reg = <0 0x400>;
 163                         clocks = <&cpufreq_hw 1>;
 164                         enable-method = "psci";
 165                         next-level-cache = <&L2_400>;
 166                         power-domains = <&CPU_PD4>;
 167                         power-domain-names = "psci";
 168                         qcom,freq-domain = <&cpufreq_hw 1>;
 169                         capacity-dmips-mhz = <1792>;
 170                         dynamic-power-coefficient = <270>;
 171                         #cooling-cells = <2>;
 172                         L2_400: l2-cache {
 173                                 compatible = "cache";
 174                                 cache-level = <2>;
 175                                 cache-unified;
 176                                 next-level-cache = <&L3_0>;
 177                         };
 178                 };
 179
 180                 CPU5: cpu@500 {
 181                         device_type = "cpu";
 182                         compatible = "arm,cortex-a710";
 183                         reg = <0 0x500>;
 184                         clocks = <&cpufreq_hw 1>;
 185                         enable-method = "psci";
 186                         next-level-cache = <&L2_500>;
 187                         power-domains = <&CPU_PD5>;
 188                         power-domain-names = "psci";
 189                         qcom,freq-domain = <&cpufreq_hw 1>;
 190                         capacity-dmips-mhz = <1792>;
 191                         dynamic-power-coefficient = <270>;
 192                         #cooling-cells = <2>;
 193                         L2_500: l2-cache {
 194                                 compatible = "cache";
 195                                 cache-level = <2>;
 196                                 cache-unified;
 197                                 next-level-cache = <&L3_0>;
 198                         };
 199                 };
 200
 201                 CPU6: cpu@600 {
 202                         device_type = "cpu";
 203                         compatible = "arm,cortex-a710";
 204                         reg = <0 0x600>;
 205                         clocks = <&cpufreq_hw 1>;
 206                         enable-method = "psci";
 207                         next-level-cache = <&L2_600>;
 208                         power-domains = <&CPU_PD6>;
 209                         power-domain-names = "psci";
 210                         qcom,freq-domain = <&cpufreq_hw 1>;
 211                         capacity-dmips-mhz = <1792>;
 212                         dynamic-power-coefficient = <270>;
 213                         #cooling-cells = <2>;
 214                         L2_600: l2-cache {
 215                                 compatible = "cache";
 216                                 cache-level = <2>;
 217                                 cache-unified;
 218                                 next-level-cache = <&L3_0>;
 219                         };
 220                 };
 221
 222                 CPU7: cpu@700 {
 223                         device_type = "cpu";
 224                         compatible = "arm,cortex-x3";
 225                         reg = <0 0x700>;
 226                         clocks = <&cpufreq_hw 2>;
 227                         enable-method = "psci";
 228                         next-level-cache = <&L2_700>;
 229                         power-domains = <&CPU_PD7>;
 230                         power-domain-names = "psci";
 231                         qcom,freq-domain = <&cpufreq_hw 2>;
 232                         capacity-dmips-mhz = <1894>;
 233                         dynamic-power-coefficient = <588>;
 234                         #cooling-cells = <2>;
 235                         L2_700: l2-cache {
 236                                 compatible = "cache";
 237                                 cache-level = <2>;
 238                                 cache-unified;
 239                                 next-level-cache = <&L3_0>;
 240                         };
 241                 };
 242
 243                 cpu-map {
 244                         cluster0 {
 245                                 core0 {
 246                                         cpu = <&CPU0>;
 247                                 };
 248
 249                                 core1 {
 250                                         cpu = <&CPU1>;
 251                                 };
 252
 253                                 core2 {
 254                                         cpu = <&CPU2>;
 255                                 };
 256
 257                                 core3 {
 258                                         cpu = <&CPU3>;
 259                                 };
 260
 261                                 core4 {
 262                                         cpu = <&CPU4>;
 263                                 };
 264
 265                                 core5 {
 266                                         cpu = <&CPU5>;
 267                                 };
 268
 269                                 core6 {
 270                                         cpu = <&CPU6>;
 271                                 };
 272
 273                                 core7 {
 274                                         cpu = <&CPU7>;
 275                                 };
 276                         };
 277                 };
 278
 279                 idle-states {
 280                         entry-method = "psci";
 281
 282                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 283                                 compatible = "arm,idle-state";
 284                                 idle-state-name = "silver-rail-power-collapse";
 285                                 arm,psci-suspend-param = <0x40000004>;
 286                                 entry-latency-us = <800>;
 287                                 exit-latency-us = <750>;
 288                                 min-residency-us = <4090>;
 289                                 local-timer-stop;
 290                         };
 291
 292                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 293                                 compatible = "arm,idle-state";
 294                                 idle-state-name = "gold-rail-power-collapse";
 295                                 arm,psci-suspend-param = <0x40000004>;
 296                                 entry-latency-us = <600>;
 297                                 exit-latency-us = <1550>;
 298                                 min-residency-us = <4791>;
 299                                 local-timer-stop;
 300                         };
 301
 302                         PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
 303                                 compatible = "arm,idle-state";
 304                                 idle-state-name = "goldplus-rail-power-collapse";
 305                                 arm,psci-suspend-param = <0x40000004>;
 306                                 entry-latency-us = <500>;
 307                                 exit-latency-us = <1350>;
 308                                 min-residency-us = <7480>;
 309                                 local-timer-stop;
 310                         };
 311                 };
 312
 313                 domain-idle-states {
 314                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 315                                 compatible = "domain-idle-state";
 316                                 arm,psci-suspend-param = <0x41000044>;
 317                                 entry-latency-us = <1050>;
 318                                 exit-latency-us = <2500>;
 319                                 min-residency-us = <5309>;
 320                         };
 321
 322                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 323                                 compatible = "domain-idle-state";
 324                                 arm,psci-suspend-param = <0x4100c344>;
 325                                 entry-latency-us = <2700>;
 326                                 exit-latency-us = <3500>;
 327                                 min-residency-us = <13959>;
 328                         };
 329                 };
 330         };
 331
 332         firmware {
 333                 scm: scm {
 334                         compatible = "qcom,scm-sm8550", "qcom,scm";
 335                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 336                 };
 337         };
 338
 339         clk_virt: interconnect-0 {
 340                 compatible = "qcom,sm8550-clk-virt";
 341                 #interconnect-cells = <2>;
 342                 qcom,bcm-voters = <&apps_bcm_voter>;
 343         };
 344
 345         mc_virt: interconnect-1 {
 346                 compatible = "qcom,sm8550-mc-virt";
 347                 #interconnect-cells = <2>;
 348                 qcom,bcm-voters = <&apps_bcm_voter>;
 349         };
 350
 351         memory@a0000000 {
 352                 device_type = "memory";
 353                 /* We expect the bootloader to fill in the size */
 354                 reg = <0 0xa0000000 0 0>;
 355         };
 356
 357         pmu {
 358                 compatible = "arm,armv8-pmuv3";
 359                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 360         };
 361
 362         psci {
 363                 compatible = "arm,psci-1.0";
 364                 method = "smc";
 365
 366                 CPU_PD0: power-domain-cpu0 {
 367                         #power-domain-cells = <0>;
 368                         power-domains = <&CLUSTER_PD>;
 369                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 370                 };
 371
 372                 CPU_PD1: power-domain-cpu1 {
 373                         #power-domain-cells = <0>;
 374                         power-domains = <&CLUSTER_PD>;
 375                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 376                 };
 377
 378                 CPU_PD2: power-domain-cpu2 {
 379                         #power-domain-cells = <0>;
 380                         power-domains = <&CLUSTER_PD>;
 381                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 382                 };
 383
 384                 CPU_PD3: power-domain-cpu3 {
 385                         #power-domain-cells = <0>;
 386                         power-domains = <&CLUSTER_PD>;
 387                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 388                 };
 389
 390                 CPU_PD4: power-domain-cpu4 {
 391                         #power-domain-cells = <0>;
 392                         power-domains = <&CLUSTER_PD>;
 393                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 394                 };
 395
 396                 CPU_PD5: power-domain-cpu5 {
 397                         #power-domain-cells = <0>;
 398                         power-domains = <&CLUSTER_PD>;
 399                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 400                 };
 401
 402                 CPU_PD6: power-domain-cpu6 {
 403                         #power-domain-cells = <0>;
 404                         power-domains = <&CLUSTER_PD>;
 405                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 406                 };
 407
 408                 CPU_PD7: power-domain-cpu7 {
 409                         #power-domain-cells = <0>;
 410                         power-domains = <&CLUSTER_PD>;
 411                         domain-idle-states = <&PRIME_CPU_SLEEP_0>;
 412                 };
 413
 414                 CLUSTER_PD: power-domain-cluster {
 415                         #power-domain-cells = <0>;
 416                         domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
 417                 };
 418         };
 419
 420         reserved_memory: reserved-memory {
 421                 #address-cells = <2>;
 422                 #size-cells = <2>;
 423                 ranges;
 424
 425                 hyp_mem: hyp-region@80000000 {
 426                         reg = <0 0x80000000 0 0xa00000>;
 427                         no-map;
 428                 };
 429
 430                 cpusys_vm_mem: cpusys-vm-region@80a00000 {
 431                         reg = <0 0x80a00000 0 0x400000>;
 432                         no-map;
 433                 };
 434
 435                 hyp_tags_mem: hyp-tags-region@80e00000 {
 436                         reg = <0 0x80e00000 0 0x3d0000>;
 437                         no-map;
 438                 };
 439
 440                 xbl_sc_mem: xbl-sc-region@d8100000 {
 441                         reg = <0 0xd8100000 0 0x40000>;
 442                         no-map;
 443                 };
 444
 445                 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
 446                         reg = <0 0x811d0000 0 0x30000>;
 447                         no-map;
 448                 };
 449
 450                 /* merged xbl_dt_log, xbl_ramdump, aop_image */
 451                 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
 452                         reg = <0 0x81a00000 0 0x260000>;
 453                         no-map;
 454                 };
 455
 456                 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
 457                         compatible = "qcom,cmd-db";
 458                         reg = <0 0x81c60000 0 0x20000>;
 459                         no-map;
 460                 };
 461
 462                 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */
 463                 aop_config_merged_mem: aop-config-merged-region@81c80000 {
 464                         reg = <0 0x81c80000 0 0x74000>;
 465                         no-map;
 466                 };
 467
 468                 /* secdata region can be reused by apps */
 469                 smem: smem@81d00000 {
 470                         compatible = "qcom,smem";
 471                         reg = <0 0x81d00000 0 0x200000>;
 472                         hwlocks = <&tcsr_mutex 3>;
 473                         no-map;
 474                 };
 475
 476                 adsp_mhi_mem: adsp-mhi-region@81f00000 {
 477                         reg = <0 0x81f00000 0 0x20000>;
 478                         no-map;
 479                 };
 480
 481                 global_sync_mem: global-sync-region@82600000 {
 482                         reg = <0 0x82600000 0 0x100000>;
 483                         no-map;
 484                 };
 485
 486                 tz_stat_mem: tz-stat-region@82700000 {
 487                         reg = <0 0x82700000 0 0x100000>;
 488                         no-map;
 489                 };
 490
 491                 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
 492                         reg = <0 0x82800000 0 0x4600000>;
 493                         no-map;
 494                 };
 495
 496                 mpss_mem: mpss-region@8a800000 {
 497                         reg = <0 0x8a800000 0 0x10800000>;
 498                         no-map;
 499                 };
 500
 501                 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
 502                         reg = <0 0x9b000000 0 0x80000>;
 503                         no-map;
 504                 };
 505
 506                 ipa_fw_mem: ipa-fw-region@9b080000 {
 507                         reg = <0 0x9b080000 0 0x10000>;
 508                         no-map;
 509                 };
 510
 511                 ipa_gsi_mem: ipa-gsi-region@9b090000 {
 512                         reg = <0 0x9b090000 0 0xa000>;
 513                         no-map;
 514                 };
 515
 516                 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
 517                         reg = <0 0x9b09a000 0 0x2000>;
 518                         no-map;
 519                 };
 520
 521                 spss_region_mem: spss-region@9b100000 {
 522                         reg = <0 0x9b100000 0 0x180000>;
 523                         no-map;
 524                 };
 525
 526                 /* First part of the "SPU secure shared memory" region */
 527                 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
 528                         reg = <0 0x9b280000 0 0x60000>;
 529                         no-map;
 530                 };
 531
 532                 /* Second part of the "SPU secure shared memory" region */
 533                 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
 534                         reg = <0 0x9b2e0000 0 0x20000>;
 535                         no-map;
 536                 };
 537
 538                 camera_mem: camera-region@9b300000 {
 539                         reg = <0 0x9b300000 0 0x800000>;
 540                         no-map;
 541                 };
 542
 543                 video_mem: video-region@9bb00000 {
 544                         reg = <0 0x9bb00000 0 0x700000>;
 545                         no-map;
 546                 };
 547
 548                 cvp_mem: cvp-region@9c200000 {
 549                         reg = <0 0x9c200000 0 0x700000>;
 550                         no-map;
 551                 };
 552
 553                 cdsp_mem: cdsp-region@9c900000 {
 554                         reg = <0 0x9c900000 0 0x2000000>;
 555                         no-map;
 556                 };
 557
 558                 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
 559                         reg = <0 0x9e900000 0 0x80000>;
 560                         no-map;
 561                 };
 562
 563                 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
 564                         reg = <0 0x9e980000 0 0x80000>;
 565                         no-map;
 566                 };
 567
 568                 adspslpi_mem: adspslpi-region@9ea00000 {
 569                         reg = <0 0x9ea00000 0 0x4080000>;
 570                         no-map;
 571                 };
 572
 573                 /* uefi region can be reused by apps */
 574
 575                 /* Linux kernel image is loaded at 0xa8000000 */
 576
 577                 rmtfs_mem: rmtfs-region@d4a80000 {
 578                         compatible = "qcom,rmtfs-mem";
 579                         reg = <0x0 0xd4a80000 0x0 0x280000>;
 580                         no-map;
 581
 582                         qcom,client-id = <1>;
 583                         qcom,vmid = <15>;
 584                 };
 585
 586                 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
 587                         reg = <0 0xd4d00000 0 0x3300000>;
 588                         no-map;
 589                 };
 590
 591                 tz_reserved_mem: tz-reserved-region@d8000000 {
 592                         reg = <0 0xd8000000 0 0x100000>;
 593                         no-map;
 594                 };
 595
 596                 cpucp_fw_mem: cpucp-fw-region@d8140000 {
 597                         reg = <0 0xd8140000 0 0x1c0000>;
 598                         no-map;
 599                 };
 600
 601                 qtee_mem: qtee-region@d8300000 {
 602                         reg = <0 0xd8300000 0 0x500000>;
 603                         no-map;
 604                 };
 605
 606                 ta_mem: ta-region@d8800000 {
 607                         reg = <0 0xd8800000 0 0x8a00000>;
 608                         no-map;
 609                 };
 610
 611                 tz_tags_mem: tz-tags-region@e1200000 {
 612                         reg = <0 0xe1200000 0 0x2740000>;
 613                         no-map;
 614                 };
 615
 616                 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
 617                         reg = <0 0xe6440000 0 0x279000>;
 618                         no-map;
 619                 };
 620
 621                 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
 622                         reg = <0 0xf3600000 0 0x4aee000>;
 623                         no-map;
 624                 };
 625
 626                 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
 627                         reg = <0 0xf80ee000 0 0x1000>;
 628                         no-map;
 629                 };
 630
 631                 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
 632                         reg = <0 0xf80ef000 0 0x9000>;
 633                         no-map;
 634                 };
 635
 636                 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
 637                         reg = <0 0xf80f8000 0 0x4000>;
 638                         no-map;
 639                 };
 640
 641                 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
 642                         reg = <0 0xf80fc000 0 0x4000>;
 643                         no-map;
 644                 };
 645
 646                 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
 647                         reg = <0 0xf8100000 0 0x100000>;
 648                         no-map;
 649                 };
 650
 651                 oem_vm_mem: oem-vm-region@f8400000 {
 652                         reg = <0 0xf8400000 0 0x4800000>;
 653                         no-map;
 654                 };
 655
 656                 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
 657                         reg = <0 0xfcc00000 0 0x4000>;
 658                         no-map;
 659                 };
 660
 661                 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
 662                         reg = <0 0xfcc04000 0 0x100000>;
 663                         no-map;
 664                 };
 665
 666                 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
 667                         reg = <0 0xfce00000 0 0x2900000>;
 668                         no-map;
 669                 };
 670
 671                 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
 672                         reg = <0 0xff700000 0 0x100000>;
 673                         no-map;
 674                 };
 675         };
 676
 677         smp2p-adsp {
 678                 compatible = "qcom,smp2p";
 679                 qcom,smem = <443>, <429>;
 680                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 681                                              IPCC_MPROC_SIGNAL_SMP2P
 682                                              IRQ_TYPE_EDGE_RISING>;
 683                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 684                                 IPCC_MPROC_SIGNAL_SMP2P>;
 685
 686                 qcom,local-pid = <0>;
 687                 qcom,remote-pid = <2>;
 688
 689                 smp2p_adsp_out: master-kernel {
 690                         qcom,entry-name = "master-kernel";
 691                         #qcom,smem-state-cells = <1>;
 692                 };
 693
 694                 smp2p_adsp_in: slave-kernel {
 695                         qcom,entry-name = "slave-kernel";
 696                         interrupt-controller;
 697                         #interrupt-cells = <2>;
 698                 };
 699         };
 700
 701         smp2p-cdsp {
 702                 compatible = "qcom,smp2p";
 703                 qcom,smem = <94>, <432>;
 704                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 705                                              IPCC_MPROC_SIGNAL_SMP2P
 706                                              IRQ_TYPE_EDGE_RISING>;
 707                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 708                                 IPCC_MPROC_SIGNAL_SMP2P>;
 709
 710                 qcom,local-pid = <0>;
 711                 qcom,remote-pid = <5>;
 712
 713                 smp2p_cdsp_out: master-kernel {
 714                         qcom,entry-name = "master-kernel";
 715                         #qcom,smem-state-cells = <1>;
 716                 };
 717
 718                 smp2p_cdsp_in: slave-kernel {
 719                         qcom,entry-name = "slave-kernel";
 720                         interrupt-controller;
 721                         #interrupt-cells = <2>;
 722                 };
 723         };
 724
 725         smp2p-modem {
 726                 compatible = "qcom,smp2p";
 727                 qcom,smem = <435>, <428>;
 728                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 729                                              IPCC_MPROC_SIGNAL_SMP2P
 730                                              IRQ_TYPE_EDGE_RISING>;
 731                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 732                                 IPCC_MPROC_SIGNAL_SMP2P>;
 733
 734                 qcom,local-pid = <0>;
 735                 qcom,remote-pid = <1>;
 736
 737                 smp2p_modem_out: master-kernel {
 738                         qcom,entry-name = "master-kernel";
 739                         #qcom,smem-state-cells = <1>;
 740                 };
 741
 742                 smp2p_modem_in: slave-kernel {
 743                         qcom,entry-name = "slave-kernel";
 744                         interrupt-controller;
 745                         #interrupt-cells = <2>;
 746                 };
 747
 748                 ipa_smp2p_out: ipa-ap-to-modem {
 749                         qcom,entry-name = "ipa";
 750                         #qcom,smem-state-cells = <1>;
 751                 };
 752
 753                 ipa_smp2p_in: ipa-modem-to-ap {
 754                         qcom,entry-name = "ipa";
 755                         interrupt-controller;
 756                         #interrupt-cells = <2>;
 757                 };
 758         };
 759
 760         soc: soc@0 {
 761                 compatible = "simple-bus";
 762                 ranges = <0 0 0 0 0x10 0>;
 763                 dma-ranges = <0 0 0 0 0x10 0>;
 764
 765                 #address-cells = <2>;
 766                 #size-cells = <2>;
 767
 768                 gcc: clock-controller@100000 {
 769                         compatible = "qcom,sm8550-gcc";
 770                         reg = <0 0x00100000 0 0x1f4200>;
 771                         #clock-cells = <1>;
 772                         #reset-cells = <1>;
 773                         #power-domain-cells = <1>;
 774                         clocks = <&bi_tcxo_div2>, <&sleep_clk>,
 775                                  <&pcie0_phy>,
 776                                  <&pcie1_phy>,
 777                                  <&pcie_1_phy_aux_clk>,
 778                                  <&ufs_mem_phy 0>,
 779                                  <&ufs_mem_phy 1>,
 780                                  <&ufs_mem_phy 2>,
 781                                  <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 782                 };
 783
 784                 ipcc: mailbox@408000 {
 785                         compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
 786                         reg = <0 0x00408000 0 0x1000>;
 787                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 788                         interrupt-controller;
 789                         #interrupt-cells = <3>;
 790                         #mbox-cells = <2>;
 791                 };
 792
 793                 gpi_dma2: dma-controller@800000 {
 794                         compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
 795                         #dma-cells = <3>;
 796                         reg = <0 0x00800000 0 0x60000>;
 797                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 798                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 799                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 800                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 801                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 802                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 803                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 804                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 805                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 806                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 807                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 808                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 809                         dma-channels = <12>;
 810                         dma-channel-mask = <0x3e>;
 811                         iommus = <&apps_smmu 0x436 0>;
 812                         status = "disabled";
 813                 };
 814
 815                 qupv3_id_1: geniqup@8c0000 {
 816                         compatible = "qcom,geni-se-qup";
 817                         reg = <0 0x008c0000 0 0x2000>;
 818                         ranges;
 819                         clock-names = "m-ahb", "s-ahb";
 820                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 821                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 822                         iommus = <&apps_smmu 0x423 0>;
 823                         #address-cells = <2>;
 824                         #size-cells = <2>;
 825                         status = "disabled";
 826
 827                         i2c8: i2c@880000 {
 828                                 compatible = "qcom,geni-i2c";
 829                                 reg = <0 0x00880000 0 0x4000>;
 830                                 clock-names = "se";
 831                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 832                                 pinctrl-names = "default";
 833                                 pinctrl-0 = <&qup_i2c8_data_clk>;
 834                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 835                                 #address-cells = <1>;
 836                                 #size-cells = <0>;
 837                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 838                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 839                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 840                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 841                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 842                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 843                                 dma-names = "tx", "rx";
 844                                 status = "disabled";
 845                         };
 846
 847                         spi8: spi@880000 {
 848                                 compatible = "qcom,geni-spi";
 849                                 reg = <0 0x00880000 0 0x4000>;
 850                                 clock-names = "se";
 851                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 852                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 853                                 pinctrl-names = "default";
 854                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
 855                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 856                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 857                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 858                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 859                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 860                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 861                                 dma-names = "tx", "rx";
 862                                 #address-cells = <1>;
 863                                 #size-cells = <0>;
 864                                 status = "disabled";
 865                         };
 866
 867                         i2c9: i2c@884000 {
 868                                 compatible = "qcom,geni-i2c";
 869                                 reg = <0 0x00884000 0 0x4000>;
 870                                 clock-names = "se";
 871                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 872                                 pinctrl-names = "default";
 873                                 pinctrl-0 = <&qup_i2c9_data_clk>;
 874                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 875                                 #address-cells = <1>;
 876                                 #size-cells = <0>;
 877                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 878                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 879                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 880                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 881                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 882                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 883                                 dma-names = "tx", "rx";
 884                                 status = "disabled";
 885                         };
 886
 887                         spi9: spi@884000 {
 888                                 compatible = "qcom,geni-spi";
 889                                 reg = <0 0x00884000 0 0x4000>;
 890                                 clock-names = "se";
 891                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 892                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 893                                 pinctrl-names = "default";
 894                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
 895                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 896                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 897                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 898                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 899                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 900                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 901                                 dma-names = "tx", "rx";
 902                                 #address-cells = <1>;
 903                                 #size-cells = <0>;
 904                                 status = "disabled";
 905                         };
 906
 907                         i2c10: i2c@888000 {
 908                                 compatible = "qcom,geni-i2c";
 909                                 reg = <0 0x00888000 0 0x4000>;
 910                                 clock-names = "se";
 911                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 912                                 pinctrl-names = "default";
 913                                 pinctrl-0 = <&qup_i2c10_data_clk>;
 914                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 915                                 #address-cells = <1>;
 916                                 #size-cells = <0>;
 917                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 918                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 919                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 920                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 921                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 922                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 923                                 dma-names = "tx", "rx";
 924                                 status = "disabled";
 925                         };
 926
 927                         spi10: spi@888000 {
 928                                 compatible = "qcom,geni-spi";
 929                                 reg = <0 0x00888000 0 0x4000>;
 930                                 clock-names = "se";
 931                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 932                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 933                                 pinctrl-names = "default";
 934                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
 935                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 936                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 937                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 938                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 939                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 940                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 941                                 dma-names = "tx", "rx";
 942                                 #address-cells = <1>;
 943                                 #size-cells = <0>;
 944                                 status = "disabled";
 945                         };
 946
 947                         i2c11: i2c@88c000 {
 948                                 compatible = "qcom,geni-i2c";
 949                                 reg = <0 0x0088c000 0 0x4000>;
 950                                 clock-names = "se";
 951                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 952                                 pinctrl-names = "default";
 953                                 pinctrl-0 = <&qup_i2c11_data_clk>;
 954                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 955                                 #address-cells = <1>;
 956                                 #size-cells = <0>;
 957                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 958                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 959                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 960                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 961                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 962                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 963                                 dma-names = "tx", "rx";
 964                                 status = "disabled";
 965                         };
 966
 967                         spi11: spi@88c000 {
 968                                 compatible = "qcom,geni-spi";
 969                                 reg = <0 0x0088c000 0 0x4000>;
 970                                 clock-names = "se";
 971                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 972                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 973                                 pinctrl-names = "default";
 974                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
 975                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 976                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 977                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 978                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 979                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 980                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 981                                 dma-names = "tx", "rx";
 982                                 #address-cells = <1>;
 983                                 #size-cells = <0>;
 984                                 status = "disabled";
 985                         };
 986
 987                         i2c12: i2c@890000 {
 988                                 compatible = "qcom,geni-i2c";
 989                                 reg = <0 0x00890000 0 0x4000>;
 990                                 clock-names = "se";
 991                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 992                                 pinctrl-names = "default";
 993                                 pinctrl-0 = <&qup_i2c12_data_clk>;
 994                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 995                                 #address-cells = <1>;
 996                                 #size-cells = <0>;
 997                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 998                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 999                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1000                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1001                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1002                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1003                                 dma-names = "tx", "rx";
1004                                 status = "disabled";
1005                         };
1006
1007                         spi12: spi@890000 {
1008                                 compatible = "qcom,geni-spi";
1009                                 reg = <0 0x00890000 0 0x4000>;
1010                                 clock-names = "se";
1011                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1012                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1013                                 pinctrl-names = "default";
1014                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1015                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1016                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1017                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1018                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1019                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1020                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1021                                 dma-names = "tx", "rx";
1022                                 #address-cells = <1>;
1023                                 #size-cells = <0>;
1024                                 status = "disabled";
1025                         };
1026
1027                         i2c13: i2c@894000 {
1028                                 compatible = "qcom,geni-i2c";
1029                                 reg = <0 0x00894000 0 0x4000>;
1030                                 clock-names = "se";
1031                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1032                                 pinctrl-names = "default";
1033                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1034                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1035                                 #address-cells = <1>;
1036                                 #size-cells = <0>;
1037                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1038                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1039                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1040                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1041                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1042                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1043                                 dma-names = "tx", "rx";
1044                                 status = "disabled";
1045                         };
1046
1047                         spi13: spi@894000 {
1048                                 compatible = "qcom,geni-spi";
1049                                 reg = <0 0x00894000 0 0x4000>;
1050                                 clock-names = "se";
1051                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1052                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1053                                 pinctrl-names = "default";
1054                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1055                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1056                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1057                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1058                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1059                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1060                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1061                                 dma-names = "tx", "rx";
1062                                 #address-cells = <1>;
1063                                 #size-cells = <0>;
1064                                 status = "disabled";
1065                         };
1066
1067                         i2c15: i2c@89c000 {
1068                                 compatible = "qcom,geni-i2c";
1069                                 reg = <0 0x0089c000 0 0x4000>;
1070                                 clock-names = "se";
1071                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1072                                 pinctrl-names = "default";
1073                                 pinctrl-0 = <&qup_i2c15_data_clk>;
1074                                 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1075                                 #address-cells = <1>;
1076                                 #size-cells = <0>;
1077                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1078                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1079                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1080                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1081                                 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1082                                        <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1083                                 dma-names = "tx", "rx";
1084                                 status = "disabled";
1085                         };
1086
1087                         spi15: spi@89c000 {
1088                                 compatible = "qcom,geni-spi";
1089                                 reg = <0 0x0089c000 0 0x4000>;
1090                                 clock-names = "se";
1091                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1092                                 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1093                                 pinctrl-names = "default";
1094                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1095                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1096                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1097                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1098                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1099                                 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1100                                        <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1101                                 dma-names = "tx", "rx";
1102                                 #address-cells = <1>;
1103                                 #size-cells = <0>;
1104                                 status = "disabled";
1105                         };
1106                 };
1107
1108                 i2c_master_hub_0: geniqup@9c0000 {
1109                         compatible = "qcom,geni-se-i2c-master-hub";
1110                         reg = <0x0 0x009c0000 0x0 0x2000>;
1111                         clock-names = "s-ahb";
1112                         clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
1113                         #address-cells = <2>;
1114                         #size-cells = <2>;
1115                         ranges;
1116                         status = "disabled";
1117
1118                         i2c_hub_0: i2c@980000 {
1119                                 compatible = "qcom,geni-i2c-master-hub";
1120                                 reg = <0x0 0x00980000 0x0 0x4000>;
1121                                 clock-names = "se", "core";
1122                                 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
1123                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1124                                 pinctrl-names = "default";
1125                                 pinctrl-0 = <&hub_i2c0_data_clk>;
1126                                 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
1127                                 #address-cells = <1>;
1128                                 #size-cells = <0>;
1129                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1130                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1131                                 interconnect-names = "qup-core", "qup-config";
1132                                 status = "disabled";
1133                         };
1134
1135                         i2c_hub_1: i2c@984000 {
1136                                 compatible = "qcom,geni-i2c-master-hub";
1137                                 reg = <0x0 0x00984000 0x0 0x4000>;
1138                                 clock-names = "se", "core";
1139                                 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
1140                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1141                                 pinctrl-names = "default";
1142                                 pinctrl-0 = <&hub_i2c1_data_clk>;
1143                                 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
1144                                 #address-cells = <1>;
1145                                 #size-cells = <0>;
1146                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1147                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1148                                 interconnect-names = "qup-core", "qup-config";
1149                                 status = "disabled";
1150                         };
1151
1152                         i2c_hub_2: i2c@988000 {
1153                                 compatible = "qcom,geni-i2c-master-hub";
1154                                 reg = <0x0 0x00988000 0x0 0x4000>;
1155                                 clock-names = "se", "core";
1156                                 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
1157                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1158                                 pinctrl-names = "default";
1159                                 pinctrl-0 = <&hub_i2c2_data_clk>;
1160                                 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1161                                 #address-cells = <1>;
1162                                 #size-cells = <0>;
1163                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1164                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1165                                 interconnect-names = "qup-core", "qup-config";
1166                                 status = "disabled";
1167                         };
1168
1169                         i2c_hub_3: i2c@98c000 {
1170                                 compatible = "qcom,geni-i2c-master-hub";
1171                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1172                                 clock-names = "se", "core";
1173                                 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
1174                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1175                                 pinctrl-names = "default";
1176                                 pinctrl-0 = <&hub_i2c3_data_clk>;
1177                                 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1178                                 #address-cells = <1>;
1179                                 #size-cells = <0>;
1180                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1181                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1182                                 interconnect-names = "qup-core", "qup-config";
1183                                 status = "disabled";
1184                         };
1185
1186                         i2c_hub_4: i2c@990000 {
1187                                 compatible = "qcom,geni-i2c-master-hub";
1188                                 reg = <0x0 0x00990000 0x0 0x4000>;
1189                                 clock-names = "se", "core";
1190                                 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
1191                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1192                                 pinctrl-names = "default";
1193                                 pinctrl-0 = <&hub_i2c4_data_clk>;
1194                                 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1195                                 #address-cells = <1>;
1196                                 #size-cells = <0>;
1197                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1198                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1199                                 interconnect-names = "qup-core", "qup-config";
1200                                 status = "disabled";
1201                         };
1202
1203                         i2c_hub_5: i2c@994000 {
1204                                 compatible = "qcom,geni-i2c-master-hub";
1205                                 reg = <0 0x00994000 0 0x4000>;
1206                                 clock-names = "se", "core";
1207                                 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
1208                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1209                                 pinctrl-names = "default";
1210                                 pinctrl-0 = <&hub_i2c5_data_clk>;
1211                                 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
1212                                 #address-cells = <1>;
1213                                 #size-cells = <0>;
1214                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1215                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1216                                 interconnect-names = "qup-core", "qup-config";
1217                                 status = "disabled";
1218                         };
1219
1220                         i2c_hub_6: i2c@998000 {
1221                                 compatible = "qcom,geni-i2c-master-hub";
1222                                 reg = <0 0x00998000 0 0x4000>;
1223                                 clock-names = "se", "core";
1224                                 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
1225                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1226                                 pinctrl-names = "default";
1227                                 pinctrl-0 = <&hub_i2c6_data_clk>;
1228                                 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
1229                                 #address-cells = <1>;
1230                                 #size-cells = <0>;
1231                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1232                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1233                                 interconnect-names = "qup-core", "qup-config";
1234                                 status = "disabled";
1235                         };
1236
1237                         i2c_hub_7: i2c@99c000 {
1238                                 compatible = "qcom,geni-i2c-master-hub";
1239                                 reg = <0 0x0099c000 0 0x4000>;
1240                                 clock-names = "se", "core";
1241                                 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
1242                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1243                                 pinctrl-names = "default";
1244                                 pinctrl-0 = <&hub_i2c7_data_clk>;
1245                                 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
1246                                 #address-cells = <1>;
1247                                 #size-cells = <0>;
1248                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1249                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1250                                 interconnect-names = "qup-core", "qup-config";
1251                                 status = "disabled";
1252                         };
1253
1254                         i2c_hub_8: i2c@9a0000 {
1255                                 compatible = "qcom,geni-i2c-master-hub";
1256                                 reg = <0 0x009a0000 0 0x4000>;
1257                                 clock-names = "se", "core";
1258                                 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
1259                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1260                                 pinctrl-names = "default";
1261                                 pinctrl-0 = <&hub_i2c8_data_clk>;
1262                                 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
1263                                 #address-cells = <1>;
1264                                 #size-cells = <0>;
1265                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1266                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1267                                 interconnect-names = "qup-core", "qup-config";
1268                                 status = "disabled";
1269                         };
1270
1271                         i2c_hub_9: i2c@9a4000 {
1272                                 compatible = "qcom,geni-i2c-master-hub";
1273                                 reg = <0 0x009a4000 0 0x4000>;
1274                                 clock-names = "se", "core";
1275                                 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
1276                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1277                                 pinctrl-names = "default";
1278                                 pinctrl-0 = <&hub_i2c9_data_clk>;
1279                                 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
1280                                 #address-cells = <1>;
1281                                 #size-cells = <0>;
1282                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1283                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1284                                 interconnect-names = "qup-core", "qup-config";
1285                                 status = "disabled";
1286                         };
1287                 };
1288
1289                 gpi_dma1: dma-controller@a00000 {
1290                         compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1291                         #dma-cells = <3>;
1292                         reg = <0 0x00a00000 0 0x60000>;
1293                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1294                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1295                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1296                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1297                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1298                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1299                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1300                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1301                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1302                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1303                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1304                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1305                         dma-channels = <12>;
1306                         dma-channel-mask = <0x1e>;
1307                         iommus = <&apps_smmu 0xb6 0>;
1308                         status = "disabled";
1309                 };
1310
1311                 qupv3_id_0: geniqup@ac0000 {
1312                         compatible = "qcom,geni-se-qup";
1313                         reg = <0 0x00ac0000 0 0x2000>;
1314                         ranges;
1315                         clock-names = "m-ahb", "s-ahb";
1316                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1317                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1318                         iommus = <&apps_smmu 0xa3 0>;
1319                         interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1320                         interconnect-names = "qup-core";
1321                         #address-cells = <2>;
1322                         #size-cells = <2>;
1323                         status = "disabled";
1324
1325                         i2c0: i2c@a80000 {
1326                                 compatible = "qcom,geni-i2c";
1327                                 reg = <0 0x00a80000 0 0x4000>;
1328                                 clock-names = "se";
1329                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1330                                 pinctrl-names = "default";
1331                                 pinctrl-0 = <&qup_i2c0_data_clk>;
1332                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1333                                 #address-cells = <1>;
1334                                 #size-cells = <0>;
1335                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1336                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1337                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1338                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1339                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1340                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1341                                 dma-names = "tx", "rx";
1342                                 status = "disabled";
1343                         };
1344
1345                         spi0: spi@a80000 {
1346                                 compatible = "qcom,geni-spi";
1347                                 reg = <0 0x00a80000 0 0x4000>;
1348                                 clock-names = "se";
1349                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1350                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1351                                 pinctrl-names = "default";
1352                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1353                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1354                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1355                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1356                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1357                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1358                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1359                                 dma-names = "tx", "rx";
1360                                 #address-cells = <1>;
1361                                 #size-cells = <0>;
1362                                 status = "disabled";
1363                         };
1364
1365                         i2c1: i2c@a84000 {
1366                                 compatible = "qcom,geni-i2c";
1367                                 reg = <0 0x00a84000 0 0x4000>;
1368                                 clock-names = "se";
1369                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1370                                 pinctrl-names = "default";
1371                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1372                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1373                                 #address-cells = <1>;
1374                                 #size-cells = <0>;
1375                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1376                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1377                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1378                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1379                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1380                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1381                                 dma-names = "tx", "rx";
1382                                 status = "disabled";
1383                         };
1384
1385                         spi1: spi@a84000 {
1386                                 compatible = "qcom,geni-spi";
1387                                 reg = <0 0x00a84000 0 0x4000>;
1388                                 clock-names = "se";
1389                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1390                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1391                                 pinctrl-names = "default";
1392                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1393                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1394                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1395                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1396                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1397                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1398                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1399                                 dma-names = "tx", "rx";
1400                                 #address-cells = <1>;
1401                                 #size-cells = <0>;
1402                                 status = "disabled";
1403                         };
1404
1405                         i2c2: i2c@a88000 {
1406                                 compatible = "qcom,geni-i2c";
1407                                 reg = <0 0x00a88000 0 0x4000>;
1408                                 clock-names = "se";
1409                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1410                                 pinctrl-names = "default";
1411                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1412                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1413                                 #address-cells = <1>;
1414                                 #size-cells = <0>;
1415                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1416                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1417                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1418                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1419                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1420                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1421                                 dma-names = "tx", "rx";
1422                                 status = "disabled";
1423                         };
1424
1425                         spi2: spi@a88000 {
1426                                 compatible = "qcom,geni-spi";
1427                                 reg = <0 0x00a88000 0 0x4000>;
1428                                 clock-names = "se";
1429                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1430                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1431                                 pinctrl-names = "default";
1432                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1433                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1434                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1435                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1436                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1437                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1438                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1439                                 dma-names = "tx", "rx";
1440                                 #address-cells = <1>;
1441                                 #size-cells = <0>;
1442                                 status = "disabled";
1443                         };
1444
1445                         i2c3: i2c@a8c000 {
1446                                 compatible = "qcom,geni-i2c";
1447                                 reg = <0 0x00a8c000 0 0x4000>;
1448                                 clock-names = "se";
1449                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1450                                 pinctrl-names = "default";
1451                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1452                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1453                                 #address-cells = <1>;
1454                                 #size-cells = <0>;
1455                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1456                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1457                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1458                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1459                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1460                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1461                                 dma-names = "tx", "rx";
1462                                 status = "disabled";
1463                         };
1464
1465                         spi3: spi@a8c000 {
1466                                 compatible = "qcom,geni-spi";
1467                                 reg = <0 0x00a8c000 0 0x4000>;
1468                                 clock-names = "se";
1469                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1470                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1471                                 pinctrl-names = "default";
1472                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1473                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1474                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1475                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1476                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1477                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1478                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1479                                 dma-names = "tx", "rx";
1480                                 #address-cells = <1>;
1481                                 #size-cells = <0>;
1482                                 status = "disabled";
1483                         };
1484
1485                         i2c4: i2c@a90000 {
1486                                 compatible = "qcom,geni-i2c";
1487                                 reg = <0 0x00a90000 0 0x4000>;
1488                                 clock-names = "se";
1489                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1490                                 pinctrl-names = "default";
1491                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1492                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1493                                 #address-cells = <1>;
1494                                 #size-cells = <0>;
1495                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1496                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1497                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1498                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1499                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1500                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1501                                 dma-names = "tx", "rx";
1502                                 status = "disabled";
1503                         };
1504
1505                         spi4: spi@a90000 {
1506                                 compatible = "qcom,geni-spi";
1507                                 reg = <0 0x00a90000 0 0x4000>;
1508                                 clock-names = "se";
1509                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1510                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1511                                 pinctrl-names = "default";
1512                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1513                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1514                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1515                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1516                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1517                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1518                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1519                                 dma-names = "tx", "rx";
1520                                 #address-cells = <1>;
1521                                 #size-cells = <0>;
1522                                 status = "disabled";
1523                         };
1524
1525                         i2c5: i2c@a94000 {
1526                                 compatible = "qcom,geni-i2c";
1527                                 reg = <0 0x00a94000 0 0x4000>;
1528                                 clock-names = "se";
1529                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1530                                 pinctrl-names = "default";
1531                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1532                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1533                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1534                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1535                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1536                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1537                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1538                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1539                                 dma-names = "tx", "rx";
1540                                 #address-cells = <1>;
1541                                 #size-cells = <0>;
1542                                 status = "disabled";
1543                         };
1544
1545                         spi5: spi@a94000 {
1546                                 compatible = "qcom,geni-spi";
1547                                 reg = <0 0x00a94000 0 0x4000>;
1548                                 clock-names = "se";
1549                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1550                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1551                                 pinctrl-names = "default";
1552                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1553                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1554                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1555                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1556                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1557                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1558                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1559                                 dma-names = "tx", "rx";
1560                                 #address-cells = <1>;
1561                                 #size-cells = <0>;
1562                                 status = "disabled";
1563                         };
1564
1565                         i2c6: i2c@a98000 {
1566                                 compatible = "qcom,geni-i2c";
1567                                 reg = <0 0x00a98000 0 0x4000>;
1568                                 clock-names = "se";
1569                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1570                                 pinctrl-names = "default";
1571                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1572                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1573                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1574                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1575                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1576                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1578                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1579                                 dma-names = "tx", "rx";
1580                                 #address-cells = <1>;
1581                                 #size-cells = <0>;
1582                                 status = "disabled";
1583                         };
1584
1585                         spi6: spi@a98000 {
1586                                 compatible = "qcom,geni-spi";
1587                                 reg = <0 0x00a98000 0 0x4000>;
1588                                 clock-names = "se";
1589                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1590                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1591                                 pinctrl-names = "default";
1592                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1593                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1594                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1595                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1596                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1597                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1598                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1599                                 dma-names = "tx", "rx";
1600                                 #address-cells = <1>;
1601                                 #size-cells = <0>;
1602                                 status = "disabled";
1603                         };
1604
1605                         uart7: serial@a9c000 {
1606                                 compatible = "qcom,geni-debug-uart";
1607                                 reg = <0 0x00a9c000 0 0x4000>;
1608                                 clock-names = "se";
1609                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1610                                 pinctrl-names = "default";
1611                                 pinctrl-0 = <&qup_uart7_default>;
1612                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1613                                 interconnect-names = "qup-core", "qup-config";
1614                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1615                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1616                                 status = "disabled";
1617                         };
1618                 };
1619
1620                 cnoc_main: interconnect@1500000 {
1621                         compatible = "qcom,sm8550-cnoc-main";
1622                         reg = <0 0x01500000 0 0x13080>;
1623                         #interconnect-cells = <2>;
1624                         qcom,bcm-voters = <&apps_bcm_voter>;
1625                 };
1626
1627                 config_noc: interconnect@1600000 {
1628                         compatible = "qcom,sm8550-config-noc";
1629                         reg = <0 0x01600000 0 0x6200>;
1630                         #interconnect-cells = <2>;
1631                         qcom,bcm-voters = <&apps_bcm_voter>;
1632                 };
1633
1634                 system_noc: interconnect@1680000 {
1635                         compatible = "qcom,sm8550-system-noc";
1636                         reg = <0 0x01680000 0 0x1d080>;
1637                         #interconnect-cells = <2>;
1638                         qcom,bcm-voters = <&apps_bcm_voter>;
1639                 };
1640
1641                 pcie_noc: interconnect@16c0000 {
1642                         compatible = "qcom,sm8550-pcie-anoc";
1643                         reg = <0 0x016c0000 0 0x12200>;
1644                         #interconnect-cells = <2>;
1645                         clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1646                                  <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
1647                         qcom,bcm-voters = <&apps_bcm_voter>;
1648                 };
1649
1650                 aggre1_noc: interconnect@16e0000 {
1651                         compatible = "qcom,sm8550-aggre1-noc";
1652                         reg = <0 0x016e0000 0 0x14400>;
1653                         #interconnect-cells = <2>;
1654                         clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1655                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
1656                         qcom,bcm-voters = <&apps_bcm_voter>;
1657                 };
1658
1659                 aggre2_noc: interconnect@1700000 {
1660                         compatible = "qcom,sm8550-aggre2-noc";
1661                         reg = <0 0x01700000 0 0x1e400>;
1662                         #interconnect-cells = <2>;
1663                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1664                         qcom,bcm-voters = <&apps_bcm_voter>;
1665                 };
1666
1667                 mmss_noc: interconnect@1780000 {
1668                         compatible = "qcom,sm8550-mmss-noc";
1669                         reg = <0 0x01780000 0 0x5b800>;
1670                         #interconnect-cells = <2>;
1671                         qcom,bcm-voters = <&apps_bcm_voter>;
1672                 };
1673
1674                 pcie0: pci@1c00000 {
1675                         device_type = "pci";
1676                         compatible = "qcom,pcie-sm8550";
1677                         reg = <0 0x01c00000 0 0x3000>,
1678                               <0 0x60000000 0 0xf1d>,
1679                               <0 0x60000f20 0 0xa8>,
1680                               <0 0x60001000 0 0x1000>,
1681                               <0 0x60100000 0 0x100000>;
1682                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1683                         #address-cells = <3>;
1684                         #size-cells = <2>;
1685                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1686                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1687                         bus-range = <0x00 0xff>;
1688
1689                         dma-coherent;
1690
1691                         linux,pci-domain = <0>;
1692                         num-lanes = <2>;
1693
1694                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1695                         interrupt-names = "msi";
1696
1697                         #interrupt-cells = <1>;
1698                         interrupt-map-mask = <0 0 0 0x7>;
1699                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1700                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1701                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1702                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1703
1704                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1705                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1706                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1707                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1708                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1709                                  <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1710                                  <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
1711                         clock-names = "aux",
1712                                       "cfg",
1713                                       "bus_master",
1714                                       "bus_slave",
1715                                       "slave_q2a",
1716                                       "ddrss_sf_tbu",
1717                                       "noc_aggr";
1718
1719                         interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1720                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1721                         interconnect-names = "pcie-mem", "cpu-pcie";
1722
1723                         iommu-map = <0x0   &apps_smmu 0x1400 0x1>,
1724                                     <0x100 &apps_smmu 0x1401 0x1>;
1725
1726                         resets = <&gcc GCC_PCIE_0_BCR>;
1727                         reset-names = "pci";
1728
1729                         power-domains = <&gcc PCIE_0_GDSC>;
1730
1731                         phys = <&pcie0_phy>;
1732                         phy-names = "pciephy";
1733
1734                         status = "disabled";
1735                 };
1736
1737                 pcie0_phy: phy@1c06000 {
1738                         compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1739                         reg = <0 0x01c06000 0 0x2000>;
1740
1741                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1742                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1743                                  <&tcsr TCSR_PCIE_0_CLKREF_EN>,
1744                                  <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1745                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
1746                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1747                                       "pipe";
1748
1749                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1750                         reset-names = "phy";
1751
1752                         assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1753                         assigned-clock-rates = <100000000>;
1754
1755                         power-domains = <&gcc PCIE_0_PHY_GDSC>;
1756
1757                         #clock-cells = <0>;
1758                         clock-output-names = "pcie0_pipe_clk";
1759
1760                         #phy-cells = <0>;
1761
1762                         status = "disabled";
1763                 };
1764
1765                 pcie1: pci@1c08000 {
1766                         device_type = "pci";
1767                         compatible = "qcom,pcie-sm8550";
1768                         reg = <0x0 0x01c08000 0x0 0x3000>,
1769                               <0x0 0x40000000 0x0 0xf1d>,
1770                               <0x0 0x40000f20 0x0 0xa8>,
1771                               <0x0 0x40001000 0x0 0x1000>,
1772                               <0x0 0x40100000 0x0 0x100000>;
1773                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1774                         #address-cells = <3>;
1775                         #size-cells = <2>;
1776                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1777                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1778                         bus-range = <0x00 0xff>;
1779
1780                         dma-coherent;
1781
1782                         linux,pci-domain = <1>;
1783                         num-lanes = <2>;
1784
1785                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1786                         interrupt-names = "msi";
1787
1788                         #interrupt-cells = <1>;
1789                         interrupt-map-mask = <0 0 0 0x7>;
1790                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1791                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1792                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1793                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1794
1795                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1796                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1797                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1798                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1799                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1800                                  <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1801                                  <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1802                                  <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
1803                         clock-names = "aux",
1804                                       "cfg",
1805                                       "bus_master",
1806                                       "bus_slave",
1807                                       "slave_q2a",
1808                                       "ddrss_sf_tbu",
1809                                       "noc_aggr",
1810                                       "cnoc_sf_axi";
1811
1812                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1813                         assigned-clock-rates = <19200000>;
1814
1815                         interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1816                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1817                         interconnect-names = "pcie-mem", "cpu-pcie";
1818
1819                         iommu-map = <0x0   &apps_smmu 0x1480 0x1>,
1820                                     <0x100 &apps_smmu 0x1481 0x1>;
1821
1822                         resets = <&gcc GCC_PCIE_1_BCR>,
1823                                 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
1824                         reset-names = "pci", "link_down";
1825
1826                         power-domains = <&gcc PCIE_1_GDSC>;
1827
1828                         phys = <&pcie1_phy>;
1829                         phy-names = "pciephy";
1830
1831                         status = "disabled";
1832                 };
1833
1834                 pcie1_phy: phy@1c0e000 {
1835                         compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1836                         reg = <0x0 0x01c0e000 0x0 0x2000>;
1837
1838                         clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1839                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1840                                  <&tcsr TCSR_PCIE_1_CLKREF_EN>,
1841                                  <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1842                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
1843                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1844                                       "pipe";
1845
1846                         resets = <&gcc GCC_PCIE_1_PHY_BCR>,
1847                                  <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
1848                         reset-names = "phy", "phy_nocsr";
1849
1850                         assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1851                         assigned-clock-rates = <100000000>;
1852
1853                         power-domains = <&gcc PCIE_1_PHY_GDSC>;
1854
1855                         #clock-cells = <0>;
1856                         clock-output-names = "pcie1_pipe_clk";
1857
1858                         #phy-cells = <0>;
1859
1860                         status = "disabled";
1861                 };
1862
1863                 cryptobam: dma-controller@1dc4000 {
1864                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1865                         reg = <0x0 0x01dc4000 0x0 0x28000>;
1866                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1867                         #dma-cells = <1>;
1868                         qcom,ee = <0>;
1869                         qcom,controlled-remotely;
1870                         iommus = <&apps_smmu 0x480 0x0>,
1871                                  <&apps_smmu 0x481 0x0>;
1872                 };
1873
1874                 crypto: crypto@1dfa000 {
1875                         compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1876                         reg = <0x0 0x01dfa000 0x0 0x6000>;
1877                         dmas = <&cryptobam 4>, <&cryptobam 5>;
1878                         dma-names = "rx", "tx";
1879                         iommus = <&apps_smmu 0x480 0x0>,
1880                                  <&apps_smmu 0x481 0x0>;
1881                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1882                         interconnect-names = "memory";
1883                 };
1884
1885                 ufs_mem_phy: phy@1d80000 {
1886                         compatible = "qcom,sm8550-qmp-ufs-phy";
1887                         reg = <0x0 0x01d80000 0x0 0x2000>;
1888                         clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
1889                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1890                         clock-names = "ref", "ref_aux";
1891
1892                         power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1893
1894                         resets = <&ufs_mem_hc 0>;
1895                         reset-names = "ufsphy";
1896
1897                         #clock-cells = <1>;
1898                         #phy-cells = <0>;
1899
1900                         status = "disabled";
1901                 };
1902
1903                 ufs_mem_hc: ufs@1d84000 {
1904                         compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1905                                      "jedec,ufs-2.0";
1906                         reg = <0x0 0x01d84000 0x0 0x3000>;
1907                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1908                         phys = <&ufs_mem_phy>;
1909                         phy-names = "ufsphy";
1910                         lanes-per-direction = <2>;
1911                         #reset-cells = <1>;
1912                         resets = <&gcc GCC_UFS_PHY_BCR>;
1913                         reset-names = "rst";
1914
1915                         power-domains = <&gcc UFS_PHY_GDSC>;
1916                         required-opps = <&rpmhpd_opp_nom>;
1917
1918                         iommus = <&apps_smmu 0x60 0x0>;
1919                         dma-coherent;
1920
1921                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1922                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
1923
1924                         interconnect-names = "ufs-ddr", "cpu-ufs";
1925                         clock-names = "core_clk",
1926                                       "bus_aggr_clk",
1927                                       "iface_clk",
1928                                       "core_clk_unipro",
1929                                       "ref_clk",
1930                                       "tx_lane0_sync_clk",
1931                                       "rx_lane0_sync_clk",
1932                                       "rx_lane1_sync_clk";
1933                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1934                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1935                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
1936                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1937                                  <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
1938                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1939                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1940                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1941                         freq-table-hz =
1942                                 <75000000 300000000>,
1943                                 <0 0>,
1944                                 <0 0>,
1945                                 <75000000 300000000>,
1946                                 <100000000 403000000>,
1947                                 <0 0>,
1948                                 <0 0>,
1949                                 <0 0>;
1950                         qcom,ice = <&ice>;
1951
1952                         status = "disabled";
1953                 };
1954
1955                 ice: crypto@1d88000 {
1956                         compatible = "qcom,sm8550-inline-crypto-engine",
1957                                      "qcom,inline-crypto-engine";
1958                         reg = <0 0x01d88000 0 0x8000>;
1959                         clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1960                 };
1961
1962                 tcsr_mutex: hwlock@1f40000 {
1963                         compatible = "qcom,tcsr-mutex";
1964                         reg = <0 0x01f40000 0 0x20000>;
1965                         #hwlock-cells = <1>;
1966                 };
1967
1968                 tcsr: clock-controller@1fc0000 {
1969                         compatible = "qcom,sm8550-tcsr", "syscon";
1970                         reg = <0 0x01fc0000 0 0x30000>;
1971                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1972                         #clock-cells = <1>;
1973                         #reset-cells = <1>;
1974                 };
1975
1976                 gpucc: clock-controller@3d90000 {
1977                         compatible = "qcom,sm8550-gpucc";
1978                         reg = <0 0x03d90000 0 0xa000>;
1979                         clocks = <&bi_tcxo_div2>,
1980                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1981                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1982                         #clock-cells = <1>;
1983                         #reset-cells = <1>;
1984                         #power-domain-cells = <1>;
1985                 };
1986
1987                 remoteproc_mpss: remoteproc@4080000 {
1988                         compatible = "qcom,sm8550-mpss-pas";
1989                         reg = <0x0 0x04080000 0x0 0x4040>;
1990
1991                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
1992                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1993                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1994                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1995                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1996                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1997                         interrupt-names = "wdog", "fatal", "ready", "handover",
1998                                           "stop-ack", "shutdown-ack";
1999
2000                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2001                         clock-names = "xo";
2002
2003                         power-domains = <&rpmhpd RPMHPD_CX>,
2004                                         <&rpmhpd RPMHPD_MSS>;
2005                         power-domain-names = "cx", "mss";
2006
2007                         interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2008
2009                         memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2010
2011                         qcom,qmp = <&aoss_qmp>;
2012
2013                         qcom,smem-states = <&smp2p_modem_out 0>;
2014                         qcom,smem-state-names = "stop";
2015
2016                         status = "disabled";
2017
2018                         glink-edge {
2019                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2020                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2021                                                              IRQ_TYPE_EDGE_RISING>;
2022                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2023                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2024                                 label = "mpss";
2025                                 qcom,remote-pid = <1>;
2026                         };
2027                 };
2028
2029                 lpass_wsa2macro: codec@6aa0000 {
2030                         compatible = "qcom,sm8550-lpass-wsa-macro";
2031                         reg = <0 0x06aa0000 0 0x1000>;
2032                         clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2033                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2034                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2035                                  <&lpass_vamacro>;
2036                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2037                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2038                         assigned-clock-rates = <19200000>;
2039
2040                         #clock-cells = <0>;
2041                         clock-output-names = "wsa2-mclk";
2042                         pinctrl-names = "default";
2043                         pinctrl-0 = <&wsa2_swr_active>;
2044                         #sound-dai-cells = <1>;
2045                 };
2046
2047                 swr3: soundwire-controller@6ab0000 {
2048                         compatible = "qcom,soundwire-v2.0.0";
2049                         reg = <0 0x06ab0000 0 0x10000>;
2050                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2051                         clocks = <&lpass_wsa2macro>;
2052                         clock-names = "iface";
2053                         label = "WSA2";
2054
2055                         qcom,din-ports = <4>;
2056                         qcom,dout-ports = <9>;
2057
2058                         qcom,ports-sinterval =          /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2059                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2060                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2061                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2062                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2063                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2064                         qcom,ports-block-pack-mode =    /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2065                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2066                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2067
2068                         #address-cells = <2>;
2069                         #size-cells = <0>;
2070                         #sound-dai-cells = <1>;
2071                         status = "disabled";
2072                 };
2073
2074                 lpass_rxmacro: codec@6ac0000 {
2075                         compatible = "qcom,sm8550-lpass-rx-macro";
2076                         reg = <0 0x06ac0000 0 0x1000>;
2077                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2078                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2079                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2080                                  <&lpass_vamacro>;
2081                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2082
2083                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2084                         assigned-clock-rates = <19200000>;
2085
2086                         #clock-cells = <0>;
2087                         clock-output-names = "mclk";
2088                         pinctrl-names = "default";
2089                         pinctrl-0 = <&rx_swr_active>;
2090                         #sound-dai-cells = <1>;
2091                 };
2092
2093                 swr1: soundwire-controller@6ad0000 {
2094                         compatible = "qcom,soundwire-v2.0.0";
2095                         reg = <0 0x06ad0000 0 0x10000>;
2096                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2097                         clocks = <&lpass_rxmacro>;
2098                         clock-names = "iface";
2099                         label = "RX";
2100
2101                         qcom,din-ports = <0>;
2102                         qcom,dout-ports = <10>;
2103
2104                         qcom,ports-sinterval =          /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
2105                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
2106                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2107                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2108                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2109                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
2110                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
2111                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2112                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2113
2114                         #address-cells = <2>;
2115                         #size-cells = <0>;
2116                         #sound-dai-cells = <1>;
2117                         status = "disabled";
2118                 };
2119
2120                 lpass_txmacro: codec@6ae0000 {
2121                         compatible = "qcom,sm8550-lpass-tx-macro";
2122                         reg = <0 0x06ae0000 0 0x1000>;
2123                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2124                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2125                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2126                                  <&lpass_vamacro>;
2127                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2128                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2129
2130                         assigned-clock-rates = <19200000>;
2131
2132                         #clock-cells = <0>;
2133                         clock-output-names = "mclk";
2134                         pinctrl-names = "default";
2135                         pinctrl-0 = <&tx_swr_active>;
2136                         #sound-dai-cells = <1>;
2137                 };
2138
2139                 lpass_wsamacro: codec@6b00000 {
2140                         compatible = "qcom,sm8550-lpass-wsa-macro";
2141                         reg = <0 0x06b00000 0 0x1000>;
2142                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2143                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2144                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2145                                  <&lpass_vamacro>;
2146                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2147
2148                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2149                         assigned-clock-rates = <19200000>;
2150
2151                         #clock-cells = <0>;
2152                         clock-output-names = "mclk";
2153                         pinctrl-names = "default";
2154                         pinctrl-0 = <&wsa_swr_active>;
2155                         #sound-dai-cells = <1>;
2156                 };
2157
2158                 swr0: soundwire-controller@6b10000 {
2159                         compatible = "qcom,soundwire-v2.0.0";
2160                         reg = <0 0x06b10000 0 0x10000>;
2161                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2162                         clocks = <&lpass_wsamacro>;
2163                         clock-names = "iface";
2164                         label = "WSA";
2165
2166                         qcom,din-ports = <4>;
2167                         qcom,dout-ports = <9>;
2168
2169                         qcom,ports-sinterval =          /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2170                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2171                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2172                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2173                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2174                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2175                         qcom,ports-block-pack-mode =    /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2176                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2177                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2178
2179                         #address-cells = <2>;
2180                         #size-cells = <0>;
2181                         #sound-dai-cells = <1>;
2182                         status = "disabled";
2183                 };
2184
2185                 swr2: soundwire-controller@6d30000 {
2186                         compatible = "qcom,soundwire-v2.0.0";
2187                         reg = <0 0x06d30000 0 0x10000>;
2188                         interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2189                                      <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2190                         interrupt-names = "core", "wakeup";
2191                         clocks = <&lpass_txmacro>;
2192                         clock-names = "iface";
2193                         label = "TX";
2194
2195                         qcom,din-ports = <4>;
2196                         qcom,dout-ports = <0>;
2197                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x01 0x03 0x03>;
2198                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x01 0x01>;
2199                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
2200                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
2201                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
2202                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff>;
2203                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
2204                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
2205                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x02 0x00 0x00>;
2206
2207                         #address-cells = <2>;
2208                         #size-cells = <0>;
2209                         #sound-dai-cells = <1>;
2210                         status = "disabled";
2211                 };
2212
2213                 lpass_vamacro: codec@6d44000 {
2214                         compatible = "qcom,sm8550-lpass-va-macro";
2215                         reg = <0 0x06d44000 0 0x1000>;
2216                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2217                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2218                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2219                         clock-names = "mclk", "macro", "dcodec";
2220
2221                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2222                         assigned-clock-rates = <19200000>;
2223
2224                         #clock-cells = <0>;
2225                         clock-output-names = "fsgen";
2226                         #sound-dai-cells = <1>;
2227                 };
2228
2229                 lpass_tlmm: pinctrl@6e80000 {
2230                         compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2231                         reg = <0 0x06e80000 0 0x20000>,
2232                               <0 0x07250000 0 0x10000>;
2233                         gpio-controller;
2234                         #gpio-cells = <2>;
2235                         gpio-ranges = <&lpass_tlmm 0 0 23>;
2236
2237                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2238                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2239                         clock-names = "core", "audio";
2240
2241                         tx_swr_active: tx-swr-active-state {
2242                                 clk-pins {
2243                                         pins = "gpio0";
2244                                         function = "swr_tx_clk";
2245                                         drive-strength = <2>;
2246                                         slew-rate = <1>;
2247                                         bias-disable;
2248                                 };
2249
2250                                 data-pins {
2251                                         pins = "gpio1", "gpio2", "gpio14";
2252                                         function = "swr_tx_data";
2253                                         drive-strength = <2>;
2254                                         slew-rate = <1>;
2255                                         bias-bus-hold;
2256                                 };
2257                         };
2258
2259                         rx_swr_active: rx-swr-active-state {
2260                                 clk-pins {
2261                                         pins = "gpio3";
2262                                         function = "swr_rx_clk";
2263                                         drive-strength = <2>;
2264                                         slew-rate = <1>;
2265                                         bias-disable;
2266                                 };
2267
2268                                 data-pins {
2269                                         pins = "gpio4", "gpio5";
2270                                         function = "swr_rx_data";
2271                                         drive-strength = <2>;
2272                                         slew-rate = <1>;
2273                                         bias-bus-hold;
2274                                 };
2275                         };
2276
2277                         dmic01_default: dmic01-default-state {
2278                                 clk-pins {
2279                                         pins = "gpio6";
2280                                         function = "dmic1_clk";
2281                                         drive-strength = <8>;
2282                                         output-high;
2283                                 };
2284
2285                                 data-pins {
2286                                         pins = "gpio7";
2287                                         function = "dmic1_data";
2288                                         drive-strength = <8>;
2289                                         input-enable;
2290                                 };
2291                         };
2292
2293                         dmic02_default: dmic02-default-state {
2294                                 clk-pins {
2295                                         pins = "gpio8";
2296                                         function = "dmic2_clk";
2297                                         drive-strength = <8>;
2298                                         output-high;
2299                                 };
2300
2301                                 data-pins {
2302                                         pins = "gpio9";
2303                                         function = "dmic2_data";
2304                                         drive-strength = <8>;
2305                                         input-enable;
2306                                 };
2307                         };
2308
2309                         wsa_swr_active: wsa-swr-active-state {
2310                                 clk-pins {
2311                                         pins = "gpio10";
2312                                         function = "wsa_swr_clk";
2313                                         drive-strength = <2>;
2314                                         slew-rate = <1>;
2315                                         bias-disable;
2316                                 };
2317
2318                                 data-pins {
2319                                         pins = "gpio11";
2320                                         function = "wsa_swr_data";
2321                                         drive-strength = <2>;
2322                                         slew-rate = <1>;
2323                                         bias-bus-hold;
2324                                 };
2325                         };
2326
2327                         wsa2_swr_active: wsa2-swr-active-state {
2328                                 clk-pins {
2329                                         pins = "gpio15";
2330                                         function = "wsa2_swr_clk";
2331                                         drive-strength = <2>;
2332                                         slew-rate = <1>;
2333                                         bias-disable;
2334                                 };
2335
2336                                 data-pins {
2337                                         pins = "gpio16";
2338                                         function = "wsa2_swr_data";
2339                                         drive-strength = <2>;
2340                                         slew-rate = <1>;
2341                                         bias-bus-hold;
2342                                 };
2343                         };
2344                 };
2345
2346                 lpass_lpiaon_noc: interconnect@7400000 {
2347                         compatible = "qcom,sm8550-lpass-lpiaon-noc";
2348                         reg = <0 0x07400000 0 0x19080>;
2349                         #interconnect-cells = <2>;
2350                         qcom,bcm-voters = <&apps_bcm_voter>;
2351                 };
2352
2353                 lpass_lpicx_noc: interconnect@7430000 {
2354                         compatible = "qcom,sm8550-lpass-lpicx-noc";
2355                         reg = <0 0x07430000 0 0x3a200>;
2356                         #interconnect-cells = <2>;
2357                         qcom,bcm-voters = <&apps_bcm_voter>;
2358                 };
2359
2360                 lpass_ag_noc: interconnect@7e40000 {
2361                         compatible = "qcom,sm8550-lpass-ag-noc";
2362                         reg = <0 0x07e40000 0 0xe080>;
2363                         #interconnect-cells = <2>;
2364                         qcom,bcm-voters = <&apps_bcm_voter>;
2365                 };
2366
2367                 sdhc_2: mmc@8804000 {
2368                         compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2369                         reg = <0 0x08804000 0 0x1000>;
2370
2371                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2372                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2373                         interrupt-names = "hc_irq", "pwr_irq";
2374
2375                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2376                                  <&gcc GCC_SDCC2_APPS_CLK>,
2377                                  <&rpmhcc RPMH_CXO_CLK>;
2378                         clock-names = "iface", "core", "xo";
2379                         iommus = <&apps_smmu 0x540 0>;
2380                         qcom,dll-config = <0x0007642c>;
2381                         qcom,ddr-config = <0x80040868>;
2382                         power-domains = <&rpmhpd RPMHPD_CX>;
2383                         operating-points-v2 = <&sdhc2_opp_table>;
2384
2385                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2386                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2387                         interconnect-names = "sdhc-ddr", "cpu-sdhc";
2388                         bus-width = <4>;
2389                         dma-coherent;
2390
2391                         /* Forbid SDR104/SDR50 - broken hw! */
2392                         sdhci-caps-mask = <0x3 0>;
2393
2394                         status = "disabled";
2395
2396                         sdhc2_opp_table: opp-table {
2397                                 compatible = "operating-points-v2";
2398
2399                                 opp-19200000 {
2400                                         opp-hz = /bits/ 64 <19200000>;
2401                                         required-opps = <&rpmhpd_opp_min_svs>;
2402                                 };
2403
2404                                 opp-50000000 {
2405                                         opp-hz = /bits/ 64 <50000000>;
2406                                         required-opps = <&rpmhpd_opp_low_svs>;
2407                                 };
2408
2409                                 opp-100000000 {
2410                                         opp-hz = /bits/ 64 <100000000>;
2411                                         required-opps = <&rpmhpd_opp_svs>;
2412                                 };
2413
2414                                 opp-202000000 {
2415                                         opp-hz = /bits/ 64 <202000000>;
2416                                         required-opps = <&rpmhpd_opp_svs_l1>;
2417                                 };
2418                         };
2419                 };
2420
2421                 videocc: clock-controller@aaf0000 {
2422                         compatible = "qcom,sm8550-videocc";
2423                         reg = <0 0x0aaf0000 0 0x10000>;
2424                         clocks = <&bi_tcxo_div2>,
2425                                  <&gcc GCC_VIDEO_AHB_CLK>;
2426                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2427                         required-opps = <&rpmhpd_opp_low_svs>;
2428                         #clock-cells = <1>;
2429                         #reset-cells = <1>;
2430                         #power-domain-cells = <1>;
2431                 };
2432
2433                 mdss: display-subsystem@ae00000 {
2434                         compatible = "qcom,sm8550-mdss";
2435                         reg = <0 0x0ae00000 0 0x1000>;
2436                         reg-names = "mdss";
2437
2438                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2439                         interrupt-controller;
2440                         #interrupt-cells = <1>;
2441
2442                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2443                                  <&gcc GCC_DISP_AHB_CLK>,
2444                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2445                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2446
2447                         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2448
2449                         power-domains = <&dispcc MDSS_GDSC>;
2450
2451                         interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
2452                                         <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2453                         interconnect-names = "mdp0-mem", "mdp1-mem";
2454
2455                         iommus = <&apps_smmu 0x1c00 0x2>;
2456
2457                         #address-cells = <2>;
2458                         #size-cells = <2>;
2459                         ranges;
2460
2461                         status = "disabled";
2462
2463                         mdss_mdp: display-controller@ae01000 {
2464                                 compatible = "qcom,sm8550-dpu";
2465                                 reg = <0 0x0ae01000 0 0x8f000>,
2466                                       <0 0x0aeb0000 0 0x2008>;
2467                                 reg-names = "mdp", "vbif";
2468
2469                                 interrupt-parent = <&mdss>;
2470                                 interrupts = <0>;
2471
2472                                 clocks = <&gcc GCC_DISP_AHB_CLK>,
2473                                          <&gcc GCC_DISP_HF_AXI_CLK>,
2474                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2475                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2476                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2477                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2478                                 clock-names = "bus",
2479                                               "nrt_bus",
2480                                               "iface",
2481                                               "lut",
2482                                               "core",
2483                                               "vsync";
2484
2485                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2486
2487                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2488                                 assigned-clock-rates = <19200000>;
2489
2490                                 operating-points-v2 = <&mdp_opp_table>;
2491
2492                                 ports {
2493                                         #address-cells = <1>;
2494                                         #size-cells = <0>;
2495
2496                                         port@0 {
2497                                                 reg = <0>;
2498                                                 dpu_intf1_out: endpoint {
2499                                                         remote-endpoint = <&mdss_dsi0_in>;
2500                                                 };
2501                                         };
2502
2503                                         port@1 {
2504                                                 reg = <1>;
2505                                                 dpu_intf2_out: endpoint {
2506                                                         remote-endpoint = <&mdss_dsi1_in>;
2507                                                 };
2508                                         };
2509
2510                                         port@2 {
2511                                                 reg = <2>;
2512                                                 dpu_intf0_out: endpoint {
2513                                                         remote-endpoint = <&mdss_dp0_in>;
2514                                                 };
2515                                         };
2516                                 };
2517
2518                                 mdp_opp_table: opp-table {
2519                                         compatible = "operating-points-v2";
2520
2521                                         opp-200000000 {
2522                                                 opp-hz = /bits/ 64 <200000000>;
2523                                                 required-opps = <&rpmhpd_opp_low_svs>;
2524                                         };
2525
2526                                         opp-325000000 {
2527                                                 opp-hz = /bits/ 64 <325000000>;
2528                                                 required-opps = <&rpmhpd_opp_svs>;
2529                                         };
2530
2531                                         opp-375000000 {
2532                                                 opp-hz = /bits/ 64 <375000000>;
2533                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2534                                         };
2535
2536                                         opp-514000000 {
2537                                                 opp-hz = /bits/ 64 <514000000>;
2538                                                 required-opps = <&rpmhpd_opp_nom>;
2539                                         };
2540                                 };
2541                         };
2542
2543                         mdss_dp0: displayport-controller@ae90000 {
2544                                 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2545                                 reg = <0 0xae90000 0 0x200>,
2546                                       <0 0xae90200 0 0x200>,
2547                                       <0 0xae90400 0 0xc00>,
2548                                       <0 0xae91000 0 0x400>,
2549                                       <0 0xae91400 0 0x400>;
2550                                 interrupt-parent = <&mdss>;
2551                                 interrupts = <12>;
2552                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2553                                          <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
2554                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
2555                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
2556                                          <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
2557                                 clock-names = "core_iface",
2558                                               "core_aux",
2559                                               "ctrl_link",
2560                                               "ctrl_link_iface",
2561                                               "stream_pixel";
2562
2563                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2564                                                   <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
2565                                 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2566                                                          <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2567
2568                                 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
2569                                 phy-names = "dp";
2570
2571                                 #sound-dai-cells = <0>;
2572
2573                                 operating-points-v2 = <&dp_opp_table>;
2574                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2575
2576                                 status = "disabled";
2577
2578                                 ports {
2579                                         #address-cells = <1>;
2580                                         #size-cells = <0>;
2581
2582                                         port@0 {
2583                                                 reg = <0>;
2584                                                 mdss_dp0_in: endpoint {
2585                                                         remote-endpoint = <&dpu_intf0_out>;
2586                                                 };
2587                                         };
2588
2589                                         port@1 {
2590                                                 reg = <1>;
2591                                                 mdss_dp0_out: endpoint {
2592                                                 };
2593                                         };
2594                                 };
2595
2596                                 dp_opp_table: opp-table {
2597                                         compatible = "operating-points-v2";
2598
2599                                         opp-162000000 {
2600                                                 opp-hz = /bits/ 64 <162000000>;
2601                                                 required-opps = <&rpmhpd_opp_low_svs_d1>;
2602                                         };
2603
2604                                         opp-270000000 {
2605                                                 opp-hz = /bits/ 64 <270000000>;
2606                                                 required-opps = <&rpmhpd_opp_low_svs>;
2607                                         };
2608
2609                                         opp-540000000 {
2610                                                 opp-hz = /bits/ 64 <540000000>;
2611                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2612                                         };
2613
2614                                         opp-810000000 {
2615                                                 opp-hz = /bits/ 64 <810000000>;
2616                                                 required-opps = <&rpmhpd_opp_nom>;
2617                                         };
2618                                 };
2619                         };
2620
2621                         mdss_dsi0: dsi@ae94000 {
2622                                 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2623                                 reg = <0 0x0ae94000 0 0x400>;
2624                                 reg-names = "dsi_ctrl";
2625
2626                                 interrupt-parent = <&mdss>;
2627                                 interrupts = <4>;
2628
2629                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2630                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2631                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2632                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2633                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2634                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2635                                 clock-names = "byte",
2636                                               "byte_intf",
2637                                               "pixel",
2638                                               "core",
2639                                               "iface",
2640                                               "bus";
2641
2642                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2643
2644                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2645                                                   <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2646                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2647                                                          <&mdss_dsi0_phy 1>;
2648
2649                                 operating-points-v2 = <&mdss_dsi_opp_table>;
2650
2651                                 phys = <&mdss_dsi0_phy>;
2652                                 phy-names = "dsi";
2653
2654                                 #address-cells = <1>;
2655                                 #size-cells = <0>;
2656
2657                                 status = "disabled";
2658
2659                                 ports {
2660                                         #address-cells = <1>;
2661                                         #size-cells = <0>;
2662
2663                                         port@0 {
2664                                                 reg = <0>;
2665                                                 mdss_dsi0_in: endpoint {
2666                                                         remote-endpoint = <&dpu_intf1_out>;
2667                                                 };
2668                                         };
2669
2670                                         port@1 {
2671                                                 reg = <1>;
2672                                                 mdss_dsi0_out: endpoint {
2673                                                 };
2674                                         };
2675                                 };
2676
2677                                 mdss_dsi_opp_table: opp-table {
2678                                         compatible = "operating-points-v2";
2679
2680                                         opp-187500000 {
2681                                                 opp-hz = /bits/ 64 <187500000>;
2682                                                 required-opps = <&rpmhpd_opp_low_svs>;
2683                                         };
2684
2685                                         opp-300000000 {
2686                                                 opp-hz = /bits/ 64 <300000000>;
2687                                                 required-opps = <&rpmhpd_opp_svs>;
2688                                         };
2689
2690                                         opp-358000000 {
2691                                                 opp-hz = /bits/ 64 <358000000>;
2692                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2693                                         };
2694                                 };
2695                         };
2696
2697                         mdss_dsi0_phy: phy@ae95000 {
2698                                 compatible = "qcom,sm8550-dsi-phy-4nm";
2699                                 reg = <0 0x0ae95000 0 0x200>,
2700                                       <0 0x0ae95200 0 0x280>,
2701                                       <0 0x0ae95500 0 0x400>;
2702                                 reg-names = "dsi_phy",
2703                                             "dsi_phy_lane",
2704                                             "dsi_pll";
2705
2706                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2707                                          <&rpmhcc RPMH_CXO_CLK>;
2708                                 clock-names = "iface", "ref";
2709
2710                                 #clock-cells = <1>;
2711                                 #phy-cells = <0>;
2712
2713                                 status = "disabled";
2714                         };
2715
2716                         mdss_dsi1: dsi@ae96000 {
2717                                 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2718                                 reg = <0 0x0ae96000 0 0x400>;
2719                                 reg-names = "dsi_ctrl";
2720
2721                                 interrupt-parent = <&mdss>;
2722                                 interrupts = <5>;
2723
2724                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2725                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2726                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2727                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2728                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2729                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2730                                 clock-names = "byte",
2731                                               "byte_intf",
2732                                               "pixel",
2733                                               "core",
2734                                               "iface",
2735                                               "bus";
2736
2737                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2738
2739                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2740                                                   <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2741                                 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2742                                                          <&mdss_dsi1_phy 1>;
2743
2744                                 operating-points-v2 = <&mdss_dsi_opp_table>;
2745
2746                                 phys = <&mdss_dsi1_phy>;
2747                                 phy-names = "dsi";
2748
2749                                 #address-cells = <1>;
2750                                 #size-cells = <0>;
2751
2752                                 status = "disabled";
2753
2754                                 ports {
2755                                         #address-cells = <1>;
2756                                         #size-cells = <0>;
2757
2758                                         port@0 {
2759                                                 reg = <0>;
2760                                                 mdss_dsi1_in: endpoint {
2761                                                         remote-endpoint = <&dpu_intf2_out>;
2762                                                 };
2763                                         };
2764
2765                                         port@1 {
2766                                                 reg = <1>;
2767                                                 mdss_dsi1_out: endpoint {
2768                                                 };
2769                                         };
2770                                 };
2771                         };
2772
2773                         mdss_dsi1_phy: phy@ae97000 {
2774                                 compatible = "qcom,sm8550-dsi-phy-4nm";
2775                                 reg = <0 0x0ae97000 0 0x200>,
2776                                       <0 0x0ae97200 0 0x280>,
2777                                       <0 0x0ae97500 0 0x400>;
2778                                 reg-names = "dsi_phy",
2779                                             "dsi_phy_lane",
2780                                             "dsi_pll";
2781
2782                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2783                                          <&rpmhcc RPMH_CXO_CLK>;
2784                                 clock-names = "iface", "ref";
2785
2786                                 #clock-cells = <1>;
2787                                 #phy-cells = <0>;
2788
2789                                 status = "disabled";
2790                         };
2791                 };
2792
2793                 dispcc: clock-controller@af00000 {
2794                         compatible = "qcom,sm8550-dispcc";
2795                         reg = <0 0x0af00000 0 0x20000>;
2796                         clocks = <&bi_tcxo_div2>,
2797                                  <&bi_tcxo_ao_div2>,
2798                                  <&gcc GCC_DISP_AHB_CLK>,
2799                                  <&sleep_clk>,
2800                                  <&mdss_dsi0_phy 0>,
2801                                  <&mdss_dsi0_phy 1>,
2802                                  <&mdss_dsi1_phy 0>,
2803                                  <&mdss_dsi1_phy 1>,
2804                                  <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2805                                  <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
2806                                  <0>, /* dp1 */
2807                                  <0>,
2808                                  <0>, /* dp2 */
2809                                  <0>,
2810                                  <0>, /* dp3 */
2811                                  <0>;
2812                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2813                         required-opps = <&rpmhpd_opp_low_svs>;
2814                         #clock-cells = <1>;
2815                         #reset-cells = <1>;
2816                         #power-domain-cells = <1>;
2817                 };
2818
2819                 usb_1_hsphy: phy@88e3000 {
2820                         compatible = "qcom,sm8550-snps-eusb2-phy";
2821                         reg = <0x0 0x088e3000 0x0 0x154>;
2822                         #phy-cells = <0>;
2823
2824                         clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
2825                         clock-names = "ref";
2826
2827                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2828
2829                         status = "disabled";
2830                 };
2831
2832                 usb_dp_qmpphy: phy@88e8000 {
2833                         compatible = "qcom,sm8550-qmp-usb3-dp-phy";
2834                         reg = <0x0 0x088e8000 0x0 0x3000>;
2835
2836                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2837                                  <&rpmhcc RPMH_CXO_CLK>,
2838                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2839                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2840                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2841
2842                         power-domains = <&gcc USB3_PHY_GDSC>;
2843
2844                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2845                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2846                         reset-names = "phy", "common";
2847
2848                         #clock-cells = <1>;
2849                         #phy-cells = <1>;
2850
2851                         status = "disabled";
2852
2853                         ports {
2854                                 #address-cells = <1>;
2855                                 #size-cells = <0>;
2856
2857                                 port@0 {
2858                                         reg = <0>;
2859
2860                                         usb_dp_qmpphy_out: endpoint {
2861                                         };
2862                                 };
2863
2864                                 port@1 {
2865                                         reg = <1>;
2866
2867                                         usb_dp_qmpphy_usb_ss_in: endpoint {
2868                                         };
2869                                 };
2870
2871                                 port@2 {
2872                                         reg = <2>;
2873
2874                                         usb_dp_qmpphy_dp_in: endpoint {
2875                                         };
2876                                 };
2877                         };
2878                 };
2879
2880                 usb_1: usb@a6f8800 {
2881                         compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
2882                         reg = <0x0 0x0a6f8800 0x0 0x400>;
2883                         #address-cells = <2>;
2884                         #size-cells = <2>;
2885                         ranges;
2886
2887                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2888                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2889                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2890                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2891                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2892                                  <&tcsr TCSR_USB3_CLKREF_EN>;
2893                         clock-names = "cfg_noc",
2894                                       "core",
2895                                       "iface",
2896                                       "sleep",
2897                                       "mock_utmi",
2898                                       "xo";
2899
2900                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2901                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2902                         assigned-clock-rates = <19200000>, <200000000>;
2903
2904                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2905                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
2906                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2907                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
2908                         interrupt-names = "hs_phy_irq",
2909                                           "ss_phy_irq",
2910                                           "dm_hs_phy_irq",
2911                                           "dp_hs_phy_irq";
2912
2913                         power-domains = <&gcc USB30_PRIM_GDSC>;
2914                         required-opps = <&rpmhpd_opp_nom>;
2915
2916                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2917
2918                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2919                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2920                         interconnect-names = "usb-ddr", "apps-usb";
2921
2922                         status = "disabled";
2923
2924                         usb_1_dwc3: usb@a600000 {
2925                                 compatible = "snps,dwc3";
2926                                 reg = <0x0 0x0a600000 0x0 0xcd00>;
2927                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2928                                 iommus = <&apps_smmu 0x40 0x0>;
2929                                 snps,dis_u2_susphy_quirk;
2930                                 snps,dis_enblslpm_quirk;
2931                                 snps,usb3_lpm_capable;
2932                                 phys = <&usb_1_hsphy>,
2933                                        <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
2934                                 phy-names = "usb2-phy", "usb3-phy";
2935
2936                                 ports {
2937                                         #address-cells = <1>;
2938                                         #size-cells = <0>;
2939
2940                                         port@0 {
2941                                                 reg = <0>;
2942
2943                                                 usb_1_dwc3_hs: endpoint {
2944                                                 };
2945                                         };
2946
2947                                         port@1 {
2948                                                 reg = <1>;
2949
2950                                                 usb_1_dwc3_ss: endpoint {
2951                                                 };
2952                                         };
2953                                 };
2954                         };
2955                 };
2956
2957                 pdc: interrupt-controller@b220000 {
2958                         compatible = "qcom,sm8550-pdc", "qcom,pdc";
2959                         reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
2960                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2961                                           <125 63 1>, <126 716 12>,
2962                                           <138 251 5>;
2963                         #interrupt-cells = <2>;
2964                         interrupt-parent = <&intc>;
2965                         interrupt-controller;
2966                 };
2967
2968                 tsens0: thermal-sensor@c271000 {
2969                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2970                         reg = <0 0x0c271000 0 0x1000>, /* TM */
2971                               <0 0x0c222000 0 0x1000>; /* SROT */
2972                         #qcom,sensors = <16>;
2973                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2974                                      <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
2975                         interrupt-names = "uplow", "critical";
2976                         #thermal-sensor-cells = <1>;
2977                 };
2978
2979                 tsens1: thermal-sensor@c272000 {
2980                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2981                         reg = <0 0x0c272000 0 0x1000>, /* TM */
2982                               <0 0x0c223000 0 0x1000>; /* SROT */
2983                         #qcom,sensors = <16>;
2984                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2985                                      <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
2986                         interrupt-names = "uplow", "critical";
2987                         #thermal-sensor-cells = <1>;
2988                 };
2989
2990                 tsens2: thermal-sensor@c273000 {
2991                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2992                         reg = <0 0x0c273000 0 0x1000>, /* TM */
2993                               <0 0x0c224000 0 0x1000>; /* SROT */
2994                         #qcom,sensors = <16>;
2995                         interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
2996                                      <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
2997                         interrupt-names = "uplow", "critical";
2998                         #thermal-sensor-cells = <1>;
2999                 };
3000
3001                 aoss_qmp: power-management@c300000 {
3002                         compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3003                         reg = <0 0x0c300000 0 0x400>;
3004                         interrupt-parent = <&ipcc>;
3005                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3006                                                      IRQ_TYPE_EDGE_RISING>;
3007                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3008
3009                         #clock-cells = <0>;
3010                 };
3011
3012                 sram@c3f0000 {
3013                         compatible = "qcom,rpmh-stats";
3014                         reg = <0 0x0c3f0000 0 0x400>;
3015                 };
3016
3017                 spmi_bus: spmi@c400000 {
3018                         compatible = "qcom,spmi-pmic-arb";
3019                         reg = <0 0x0c400000 0 0x3000>,
3020                               <0 0x0c500000 0 0x4000000>,
3021                               <0 0x0c440000 0 0x80000>,
3022                               <0 0x0c4c0000 0 0x20000>,
3023                               <0 0x0c42d000 0 0x4000>;
3024                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3025                         interrupt-names = "periph_irq";
3026                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3027                         qcom,ee = <0>;
3028                         qcom,channel = <0>;
3029                         qcom,bus-id = <0>;
3030                         #address-cells = <2>;
3031                         #size-cells = <0>;
3032                         interrupt-controller;
3033                         #interrupt-cells = <4>;
3034                 };
3035
3036                 tlmm: pinctrl@f100000 {
3037                         compatible = "qcom,sm8550-tlmm";
3038                         reg = <0 0x0f100000 0 0x300000>;
3039                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3040                         gpio-controller;
3041                         #gpio-cells = <2>;
3042                         interrupt-controller;
3043                         #interrupt-cells = <2>;
3044                         gpio-ranges = <&tlmm 0 0 211>;
3045                         wakeup-parent = <&pdc>;
3046
3047                         hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3048                                 /* SDA, SCL */
3049                                 pins = "gpio16", "gpio17";
3050                                 function = "i2chub0_se0";
3051                                 drive-strength = <2>;
3052                                 bias-pull-up;
3053                         };
3054
3055                         hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3056                                 /* SDA, SCL */
3057                                 pins = "gpio18", "gpio19";
3058                                 function = "i2chub0_se1";
3059                                 drive-strength = <2>;
3060                                 bias-pull-up;
3061                         };
3062
3063                         hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3064                                 /* SDA, SCL */
3065                                 pins = "gpio20", "gpio21";
3066                                 function = "i2chub0_se2";
3067                                 drive-strength = <2>;
3068                                 bias-pull-up;
3069                         };
3070
3071                         hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3072                                 /* SDA, SCL */
3073                                 pins = "gpio22", "gpio23";
3074                                 function = "i2chub0_se3";
3075                                 drive-strength = <2>;
3076                                 bias-pull-up;
3077                         };
3078
3079                         hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3080                                 /* SDA, SCL */
3081                                 pins = "gpio4", "gpio5";
3082                                 function = "i2chub0_se4";
3083                                 drive-strength = <2>;
3084                                 bias-pull-up;
3085                         };
3086
3087                         hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3088                                 /* SDA, SCL */
3089                                 pins = "gpio6", "gpio7";
3090                                 function = "i2chub0_se5";
3091                                 drive-strength = <2>;
3092                                 bias-pull-up;
3093                         };
3094
3095                         hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3096                                 /* SDA, SCL */
3097                                 pins = "gpio8", "gpio9";
3098                                 function = "i2chub0_se6";
3099                                 drive-strength = <2>;
3100                                 bias-pull-up;
3101                         };
3102
3103                         hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3104                                 /* SDA, SCL */
3105                                 pins = "gpio10", "gpio11";
3106                                 function = "i2chub0_se7";
3107                                 drive-strength = <2>;
3108                                 bias-pull-up;
3109                         };
3110
3111                         hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3112                                 /* SDA, SCL */
3113                                 pins = "gpio206", "gpio207";
3114                                 function = "i2chub0_se8";
3115                                 drive-strength = <2>;
3116                                 bias-pull-up;
3117                         };
3118
3119                         hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3120                                 /* SDA, SCL */
3121                                 pins = "gpio84", "gpio85";
3122                                 function = "i2chub0_se9";
3123                                 drive-strength = <2>;
3124                                 bias-pull-up;
3125                         };
3126
3127                         pcie0_default_state: pcie0-default-state {
3128                                 perst-pins {
3129                                         pins = "gpio94";
3130                                         function = "gpio";
3131                                         drive-strength = <2>;
3132                                         bias-pull-down;
3133                                 };
3134
3135                                 clkreq-pins {
3136                                         pins = "gpio95";
3137                                         function = "pcie0_clk_req_n";
3138                                         drive-strength = <2>;
3139                                         bias-pull-up;
3140                                 };
3141
3142                                 wake-pins {
3143                                         pins = "gpio96";
3144                                         function = "gpio";
3145                                         drive-strength = <2>;
3146                                         bias-pull-up;
3147                                 };
3148                         };
3149
3150                         pcie1_default_state: pcie1-default-state {
3151                                 perst-pins {
3152                                         pins = "gpio97";
3153                                         function = "gpio";
3154                                         drive-strength = <2>;
3155                                         bias-pull-down;
3156                                 };
3157
3158                                 clkreq-pins {
3159                                         pins = "gpio98";
3160                                         function = "pcie1_clk_req_n";
3161                                         drive-strength = <2>;
3162                                         bias-pull-up;
3163                                 };
3164
3165                                 wake-pins {
3166                                         pins = "gpio99";
3167                                         function = "gpio";
3168                                         drive-strength = <2>;
3169                                         bias-pull-up;
3170                                 };
3171                         };
3172
3173                         qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3174                                 /* SDA, SCL */
3175                                 pins = "gpio28", "gpio29";
3176                                 function = "qup1_se0";
3177                                 drive-strength = <2>;
3178                                 bias-pull-up = <2200>;
3179                         };
3180
3181                         qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3182                                 /* SDA, SCL */
3183                                 pins = "gpio32", "gpio33";
3184                                 function = "qup1_se1";
3185                                 drive-strength = <2>;
3186                                 bias-pull-up = <2200>;
3187                         };
3188
3189                         qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3190                                 /* SDA, SCL */
3191                                 pins = "gpio36", "gpio37";
3192                                 function = "qup1_se2";
3193                                 drive-strength = <2>;
3194                                 bias-pull-up = <2200>;
3195                         };
3196
3197                         qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3198                                 /* SDA, SCL */
3199                                 pins = "gpio40", "gpio41";
3200                                 function = "qup1_se3";
3201                                 drive-strength = <2>;
3202                                 bias-pull-up = <2200>;
3203                         };
3204
3205                         qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3206                                 /* SDA, SCL */
3207                                 pins = "gpio44", "gpio45";
3208                                 function = "qup1_se4";
3209                                 drive-strength = <2>;
3210                                 bias-pull-up = <2200>;
3211                         };
3212
3213                         qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3214                                 /* SDA, SCL */
3215                                 pins = "gpio52", "gpio53";
3216                                 function = "qup1_se5";
3217                                 drive-strength = <2>;
3218                                 bias-pull-up = <2200>;
3219                         };
3220
3221                         qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3222                                 /* SDA, SCL */
3223                                 pins = "gpio48", "gpio49";
3224                                 function = "qup1_se6";
3225                                 drive-strength = <2>;
3226                                 bias-pull-up = <2200>;
3227                         };
3228
3229                         qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3230                                 scl-pins {
3231                                         pins = "gpio57";
3232                                         function = "qup2_se0_l1_mira";
3233                                         drive-strength = <2>;
3234                                         bias-pull-up = <2200>;
3235                                 };
3236
3237                                 sda-pins {
3238                                         pins = "gpio56";
3239                                         function = "qup2_se0_l0_mira";
3240                                         drive-strength = <2>;
3241                                         bias-pull-up = <2200>;
3242                                 };
3243                         };
3244
3245                         qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3246                                 /* SDA, SCL */
3247                                 pins = "gpio60", "gpio61";
3248                                 function = "qup2_se1";
3249                                 drive-strength = <2>;
3250                                 bias-pull-up = <2200>;
3251                         };
3252
3253                         qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3254                                 /* SDA, SCL */
3255                                 pins = "gpio64", "gpio65";
3256                                 function = "qup2_se2";
3257                                 drive-strength = <2>;
3258                                 bias-pull-up = <2200>;
3259                         };
3260
3261                         qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3262                                 /* SDA, SCL */
3263                                 pins = "gpio68", "gpio69";
3264                                 function = "qup2_se3";
3265                                 drive-strength = <2>;
3266                                 bias-pull-up = <2200>;
3267                         };
3268
3269                         qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3270                                 /* SDA, SCL */
3271                                 pins = "gpio2", "gpio3";
3272                                 function = "qup2_se4";
3273                                 drive-strength = <2>;
3274                                 bias-pull-up = <2200>;
3275                         };
3276
3277                         qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3278                                 /* SDA, SCL */
3279                                 pins = "gpio80", "gpio81";
3280                                 function = "qup2_se5";
3281                                 drive-strength = <2>;
3282                                 bias-pull-up = <2200>;
3283                         };
3284
3285                         qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3286                                 /* SDA, SCL */
3287                                 pins = "gpio72", "gpio106";
3288                                 function = "qup2_se7";
3289                                 drive-strength = <2>;
3290                                 bias-pull-up = <2200>;
3291                         };
3292
3293                         qup_spi0_cs: qup-spi0-cs-state {
3294                                 pins = "gpio31";
3295                                 function = "qup1_se0";
3296                                 drive-strength = <6>;
3297                                 bias-disable;
3298                         };
3299
3300                         qup_spi0_data_clk: qup-spi0-data-clk-state {
3301                                 /* MISO, MOSI, CLK */
3302                                 pins = "gpio28", "gpio29", "gpio30";
3303                                 function = "qup1_se0";
3304                                 drive-strength = <6>;
3305                                 bias-disable;
3306                         };
3307
3308                         qup_spi1_cs: qup-spi1-cs-state {
3309                                 pins = "gpio35";
3310                                 function = "qup1_se1";
3311                                 drive-strength = <6>;
3312                                 bias-disable;
3313                         };
3314
3315                         qup_spi1_data_clk: qup-spi1-data-clk-state {
3316                                 /* MISO, MOSI, CLK */
3317                                 pins = "gpio32", "gpio33", "gpio34";
3318                                 function = "qup1_se1";
3319                                 drive-strength = <6>;
3320                                 bias-disable;
3321                         };
3322
3323                         qup_spi2_cs: qup-spi2-cs-state {
3324                                 pins = "gpio39";
3325                                 function = "qup1_se2";
3326                                 drive-strength = <6>;
3327                                 bias-disable;
3328                         };
3329
3330                         qup_spi2_data_clk: qup-spi2-data-clk-state {
3331                                 /* MISO, MOSI, CLK */
3332                                 pins = "gpio36", "gpio37", "gpio38";
3333                                 function = "qup1_se2";
3334                                 drive-strength = <6>;
3335                                 bias-disable;
3336                         };
3337
3338                         qup_spi3_cs: qup-spi3-cs-state {
3339                                 pins = "gpio43";
3340                                 function = "qup1_se3";
3341                                 drive-strength = <6>;
3342                                 bias-disable;
3343                         };
3344
3345                         qup_spi3_data_clk: qup-spi3-data-clk-state {
3346                                 /* MISO, MOSI, CLK */
3347                                 pins = "gpio40", "gpio41", "gpio42";
3348                                 function = "qup1_se3";
3349                                 drive-strength = <6>;
3350                                 bias-disable;
3351                         };
3352
3353                         qup_spi4_cs: qup-spi4-cs-state {
3354                                 pins = "gpio47";
3355                                 function = "qup1_se4";
3356                                 drive-strength = <6>;
3357                                 bias-disable;
3358                         };
3359
3360                         qup_spi4_data_clk: qup-spi4-data-clk-state {
3361                                 /* MISO, MOSI, CLK */
3362                                 pins = "gpio44", "gpio45", "gpio46";
3363                                 function = "qup1_se4";
3364                                 drive-strength = <6>;
3365                                 bias-disable;
3366                         };
3367
3368                         qup_spi5_cs: qup-spi5-cs-state {
3369                                 pins = "gpio55";
3370                                 function = "qup1_se5";
3371                                 drive-strength = <6>;
3372                                 bias-disable;
3373                         };
3374
3375                         qup_spi5_data_clk: qup-spi5-data-clk-state {
3376                                 /* MISO, MOSI, CLK */
3377                                 pins = "gpio52", "gpio53", "gpio54";
3378                                 function = "qup1_se5";
3379                                 drive-strength = <6>;
3380                                 bias-disable;
3381                         };
3382
3383                         qup_spi6_cs: qup-spi6-cs-state {
3384                                 pins = "gpio51";
3385                                 function = "qup1_se6";
3386                                 drive-strength = <6>;
3387                                 bias-disable;
3388                         };
3389
3390                         qup_spi6_data_clk: qup-spi6-data-clk-state {
3391                                 /* MISO, MOSI, CLK */
3392                                 pins = "gpio48", "gpio49", "gpio50";
3393                                 function = "qup1_se6";
3394                                 drive-strength = <6>;
3395                                 bias-disable;
3396                         };
3397
3398                         qup_spi8_cs: qup-spi8-cs-state {
3399                                 pins = "gpio59";
3400                                 function = "qup2_se0_l3_mira";
3401                                 drive-strength = <6>;
3402                                 bias-disable;
3403                         };
3404
3405                         qup_spi8_data_clk: qup-spi8-data-clk-state {
3406                                 /* MISO, MOSI, CLK */
3407                                 pins = "gpio56", "gpio57", "gpio58";
3408                                 function = "qup2_se0_l2_mira";
3409                                 drive-strength = <6>;
3410                                 bias-disable;
3411                         };
3412
3413                         qup_spi9_cs: qup-spi9-cs-state {
3414                                 pins = "gpio63";
3415                                 function = "qup2_se1";
3416                                 drive-strength = <6>;
3417                                 bias-disable;
3418                         };
3419
3420                         qup_spi9_data_clk: qup-spi9-data-clk-state {
3421                                 /* MISO, MOSI, CLK */
3422                                 pins = "gpio60", "gpio61", "gpio62";
3423                                 function = "qup2_se1";
3424                                 drive-strength = <6>;
3425                                 bias-disable;
3426                         };
3427
3428                         qup_spi10_cs: qup-spi10-cs-state {
3429                                 pins = "gpio67";
3430                                 function = "qup2_se2";
3431                                 drive-strength = <6>;
3432                                 bias-disable;
3433                         };
3434
3435                         qup_spi10_data_clk: qup-spi10-data-clk-state {
3436                                 /* MISO, MOSI, CLK */
3437                                 pins = "gpio64", "gpio65", "gpio66";
3438                                 function = "qup2_se2";
3439                                 drive-strength = <6>;
3440                                 bias-disable;
3441                         };
3442
3443                         qup_spi11_cs: qup-spi11-cs-state {
3444                                 pins = "gpio71";
3445                                 function = "qup2_se3";
3446                                 drive-strength = <6>;
3447                                 bias-disable;
3448                         };
3449
3450                         qup_spi11_data_clk: qup-spi11-data-clk-state {
3451                                 /* MISO, MOSI, CLK */
3452                                 pins = "gpio68", "gpio69", "gpio70";
3453                                 function = "qup2_se3";
3454                                 drive-strength = <6>;
3455                                 bias-disable;
3456                         };
3457
3458                         qup_spi12_cs: qup-spi12-cs-state {
3459                                 pins = "gpio119";
3460                                 function = "qup2_se4";
3461                                 drive-strength = <6>;
3462                                 bias-disable;
3463                         };
3464
3465                         qup_spi12_data_clk: qup-spi12-data-clk-state {
3466                                 /* MISO, MOSI, CLK */
3467                                 pins = "gpio2", "gpio3", "gpio118";
3468                                 function = "qup2_se4";
3469                                 drive-strength = <6>;
3470                                 bias-disable;
3471                         };
3472
3473                         qup_spi13_cs: qup-spi13-cs-state {
3474                                 pins = "gpio83";
3475                                 function = "qup2_se5";
3476                                 drive-strength = <6>;
3477                                 bias-disable;
3478                         };
3479
3480                         qup_spi13_data_clk: qup-spi13-data-clk-state {
3481                                 /* MISO, MOSI, CLK */
3482                                 pins = "gpio80", "gpio81", "gpio82";
3483                                 function = "qup2_se5";
3484                                 drive-strength = <6>;
3485                                 bias-disable;
3486                         };
3487
3488                         qup_spi15_cs: qup-spi15-cs-state {
3489                                 pins = "gpio75";
3490                                 function = "qup2_se7";
3491                                 drive-strength = <6>;
3492                                 bias-disable;
3493                         };
3494
3495                         qup_spi15_data_clk: qup-spi15-data-clk-state {
3496                                 /* MISO, MOSI, CLK */
3497                                 pins = "gpio72", "gpio106", "gpio74";
3498                                 function = "qup2_se7";
3499                                 drive-strength = <6>;
3500                                 bias-disable;
3501                         };
3502
3503                         qup_uart7_default: qup-uart7-default-state {
3504                                 /* TX, RX */
3505                                 pins = "gpio26", "gpio27";
3506                                 function = "qup1_se7";
3507                                 drive-strength = <2>;
3508                                 bias-disable;
3509                         };
3510
3511                         sdc2_sleep: sdc2-sleep-state {
3512                                 clk-pins {
3513                                         pins = "sdc2_clk";
3514                                         bias-disable;
3515                                         drive-strength = <2>;
3516                                 };
3517
3518                                 cmd-pins {
3519                                         pins = "sdc2_cmd";
3520                                         bias-pull-up;
3521                                         drive-strength = <2>;
3522                                 };
3523
3524                                 data-pins {
3525                                         pins = "sdc2_data";
3526                                         bias-pull-up;
3527                                         drive-strength = <2>;
3528                                 };
3529                         };
3530
3531                         sdc2_default: sdc2-default-state {
3532                                 clk-pins {
3533                                         pins = "sdc2_clk";
3534                                         bias-disable;
3535                                         drive-strength = <16>;
3536                                 };
3537
3538                                 cmd-pins {
3539                                         pins = "sdc2_cmd";
3540                                         bias-pull-up;
3541                                         drive-strength = <10>;
3542                                 };
3543
3544                                 data-pins {
3545                                         pins = "sdc2_data";
3546                                         bias-pull-up;
3547                                         drive-strength = <10>;
3548                                 };
3549                         };
3550                 };
3551
3552                 apps_smmu: iommu@15000000 {
3553                         compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3554                         reg = <0 0x15000000 0 0x100000>;
3555                         #iommu-cells = <2>;
3556                         #global-interrupts = <1>;
3557                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3558                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3559                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3560                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3561                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3562                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3563                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3564                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3565                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3566                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3567                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3568                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3569                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3570                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3571                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3572                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3573                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3574                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3575                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3576                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3577                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3578                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3579                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3580                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3581                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3582                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3583                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3584                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3585                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3586                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3587                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3588                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3589                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3590                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3591                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3592                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3593                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3594                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3595                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3596                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3597                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3598                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3599                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3600                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3601                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3602                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3603                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3604                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3605                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3606                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3607                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3608                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3609                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3610                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3611                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3612                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3613                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3614                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3615                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3616                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3617                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3618                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3619                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3620                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3621                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3622                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3623                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3624                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3625                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3626                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3627                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3628                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3629                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3630                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3631                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3632                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3633                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3634                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3635                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3636                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3637                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3638                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3639                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3640                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3641                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3642                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3643                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3644                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3645                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3646                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
3647                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3648                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3649                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3650                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3651                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3652                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3653                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
3654                 };
3655
3656                 intc: interrupt-controller@17100000 {
3657                         compatible = "arm,gic-v3";
3658                         reg = <0 0x17100000 0 0x10000>,         /* GICD */
3659                               <0 0x17180000 0 0x200000>;        /* GICR * 8 */
3660                         ranges;
3661                         #interrupt-cells = <3>;
3662                         interrupt-controller;
3663                         #redistributor-regions = <1>;
3664                         redistributor-stride = <0 0x40000>;
3665                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
3666                         #address-cells = <2>;
3667                         #size-cells = <2>;
3668
3669                         gic_its: msi-controller@17140000 {
3670                                 compatible = "arm,gic-v3-its";
3671                                 reg = <0 0x17140000 0 0x20000>;
3672                                 msi-controller;
3673                                 #msi-cells = <1>;
3674                         };
3675                 };
3676
3677                 timer@17420000 {
3678                         compatible = "arm,armv7-timer-mem";
3679                         reg = <0 0x17420000 0 0x1000>;
3680                         ranges = <0 0 0 0x20000000>;
3681                         #address-cells = <1>;
3682                         #size-cells = <1>;
3683
3684                         frame@17421000 {
3685                                 reg = <0x17421000 0x1000>,
3686                                       <0x17422000 0x1000>;
3687                                 frame-number = <0>;
3688                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3689                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3690                         };
3691
3692                         frame@17423000 {
3693                                 reg = <0x17423000 0x1000>;
3694                                 frame-number = <1>;
3695                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3696                                 status = "disabled";
3697                         };
3698
3699                         frame@17425000 {
3700                                 reg = <0x17425000 0x1000>;
3701                                 frame-number = <2>;
3702                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3703                                 status = "disabled";
3704                         };
3705
3706                         frame@17427000 {
3707                                 reg = <0x17427000 0x1000>;
3708                                 frame-number = <3>;
3709                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3710                                 status = "disabled";
3711                         };
3712
3713                         frame@17429000 {
3714                                 reg = <0x17429000 0x1000>;
3715                                 frame-number = <4>;
3716                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3717                                 status = "disabled";
3718                         };
3719
3720                         frame@1742b000 {
3721                                 reg = <0x1742b000 0x1000>;
3722                                 frame-number = <5>;
3723                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3724                                 status = "disabled";
3725                         };
3726
3727                         frame@1742d000 {
3728                                 reg = <0x1742d000 0x1000>;
3729                                 frame-number = <6>;
3730                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3731                                 status = "disabled";
3732                         };
3733                 };
3734
3735                 apps_rsc: rsc@17a00000 {
3736                         label = "apps_rsc";
3737                         compatible = "qcom,rpmh-rsc";
3738                         reg = <0 0x17a00000 0 0x10000>,
3739                               <0 0x17a10000 0 0x10000>,
3740                               <0 0x17a20000 0 0x10000>,
3741                               <0 0x17a30000 0 0x10000>;
3742                         reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3743                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3744                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3745                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3746                         qcom,tcs-offset = <0xd00>;
3747                         qcom,drv-id = <2>;
3748                         qcom,tcs-config = <ACTIVE_TCS    3>, <SLEEP_TCS     2>,
3749                                           <WAKE_TCS      2>, <CONTROL_TCS   0>;
3750                         power-domains = <&CLUSTER_PD>;
3751
3752                         apps_bcm_voter: bcm-voter {
3753                                 compatible = "qcom,bcm-voter";
3754                         };
3755
3756                         rpmhcc: clock-controller {
3757                                 compatible = "qcom,sm8550-rpmh-clk";
3758                                 #clock-cells = <1>;
3759                                 clock-names = "xo";
3760                                 clocks = <&xo_board>;
3761                         };
3762
3763                         rpmhpd: power-controller {
3764                                 compatible = "qcom,sm8550-rpmhpd";
3765                                 #power-domain-cells = <1>;
3766                                 operating-points-v2 = <&rpmhpd_opp_table>;
3767
3768                                 rpmhpd_opp_table: opp-table {
3769                                         compatible = "operating-points-v2";
3770
3771                                         rpmhpd_opp_ret: opp-16 {
3772                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3773                                         };
3774
3775                                         rpmhpd_opp_min_svs: opp-48 {
3776                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3777                                         };
3778
3779                                         rpmhpd_opp_low_svs_d2: opp-52 {
3780                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
3781                                         };
3782
3783                                         rpmhpd_opp_low_svs_d1: opp-56 {
3784                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3785                                         };
3786
3787                                         rpmhpd_opp_low_svs_d0: opp-60 {
3788                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
3789                                         };
3790
3791                                         rpmhpd_opp_low_svs: opp-64 {
3792                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3793                                         };
3794
3795                                         rpmhpd_opp_low_svs_l1: opp-80 {
3796                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
3797                                         };
3798
3799                                         rpmhpd_opp_svs: opp-128 {
3800                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3801                                         };
3802
3803                                         rpmhpd_opp_svs_l0: opp-144 {
3804                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
3805                                         };
3806
3807                                         rpmhpd_opp_svs_l1: opp-192 {
3808                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3809                                         };
3810
3811                                         rpmhpd_opp_nom: opp-256 {
3812                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3813                                         };
3814
3815                                         rpmhpd_opp_nom_l1: opp-320 {
3816                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3817                                         };
3818
3819                                         rpmhpd_opp_nom_l2: opp-336 {
3820                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3821                                         };
3822
3823                                         rpmhpd_opp_turbo: opp-384 {
3824                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3825                                         };
3826
3827                                         rpmhpd_opp_turbo_l1: opp-416 {
3828                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3829                                         };
3830                                 };
3831                         };
3832                 };
3833
3834                 cpufreq_hw: cpufreq@17d91000 {
3835                         compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
3836                         reg = <0 0x17d91000 0 0x1000>,
3837                               <0 0x17d92000 0 0x1000>,
3838                               <0 0x17d93000 0 0x1000>;
3839                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3840                         clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
3841                         clock-names = "xo", "alternate";
3842                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
3843                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3844                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
3845                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3846                         #freq-domain-cells = <1>;
3847                         #clock-cells = <1>;
3848                 };
3849
3850                 pmu@24091000 {
3851                         compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3852                         reg = <0 0x24091000 0 0x1000>;
3853                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3854                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3855
3856                         operating-points-v2 = <&llcc_bwmon_opp_table>;
3857
3858                         llcc_bwmon_opp_table: opp-table {
3859                                 compatible = "operating-points-v2";
3860
3861                                 opp-0 {
3862                                         opp-peak-kBps = <2086000>;
3863                                 };
3864
3865                                 opp-1 {
3866                                         opp-peak-kBps = <2929000>;
3867                                 };
3868
3869                                 opp-2 {
3870                                         opp-peak-kBps = <5931000>;
3871                                 };
3872
3873                                 opp-3 {
3874                                         opp-peak-kBps = <6515000>;
3875                                 };
3876
3877                                 opp-4 {
3878                                         opp-peak-kBps = <7980000>;
3879                                 };
3880
3881                                 opp-5 {
3882                                         opp-peak-kBps = <10437000>;
3883                                 };
3884
3885                                 opp-6 {
3886                                         opp-peak-kBps = <12157000>;
3887                                 };
3888
3889                                 opp-7 {
3890                                         opp-peak-kBps = <14060000>;
3891                                 };
3892
3893                                 opp-8 {
3894                                         opp-peak-kBps = <16113000>;
3895                                 };
3896                         };
3897                 };
3898
3899                 pmu@240b6400 {
3900                         compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
3901                         reg = <0 0x240b6400 0 0x600>;
3902                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3903                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3904
3905                         operating-points-v2 = <&cpu_bwmon_opp_table>;
3906
3907                         cpu_bwmon_opp_table: opp-table {
3908                                 compatible = "operating-points-v2";
3909
3910                                 opp-0 {
3911                                         opp-peak-kBps = <4577000>;
3912                                 };
3913
3914                                 opp-1 {
3915                                         opp-peak-kBps = <7110000>;
3916                                 };
3917
3918                                 opp-2 {
3919                                         opp-peak-kBps = <9155000>;
3920                                 };
3921
3922                                 opp-3 {
3923                                         opp-peak-kBps = <12298000>;
3924                                 };
3925
3926                                 opp-4 {
3927                                         opp-peak-kBps = <14236000>;
3928                                 };
3929
3930                                 opp-5 {
3931                                         opp-peak-kBps = <16265000>;
3932                                 };
3933                         };
3934                 };
3935
3936                 gem_noc: interconnect@24100000 {
3937                         compatible = "qcom,sm8550-gem-noc";
3938                         reg = <0 0x24100000 0 0xbb800>;
3939                         #interconnect-cells = <2>;
3940                         qcom,bcm-voters = <&apps_bcm_voter>;
3941                 };
3942
3943                 system-cache-controller@25000000 {
3944                         compatible = "qcom,sm8550-llcc";
3945                         reg = <0 0x25000000 0 0x200000>,
3946                               <0 0x25200000 0 0x200000>,
3947                               <0 0x25400000 0 0x200000>,
3948                               <0 0x25600000 0 0x200000>,
3949                               <0 0x25800000 0 0x200000>;
3950                         reg-names = "llcc0_base",
3951                                     "llcc1_base",
3952                                     "llcc2_base",
3953                                     "llcc3_base",
3954                                     "llcc_broadcast_base";
3955                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
3956                 };
3957
3958                 remoteproc_adsp: remoteproc@30000000 {
3959                         compatible = "qcom,sm8550-adsp-pas";
3960                         reg = <0x0 0x30000000 0x0 0x100>;
3961
3962                         interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3963                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3964                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3965                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3966                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3967                         interrupt-names = "wdog", "fatal", "ready",
3968                                           "handover", "stop-ack";
3969
3970                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3971                         clock-names = "xo";
3972
3973                         power-domains = <&rpmhpd RPMHPD_LCX>,
3974                                         <&rpmhpd RPMHPD_LMX>;
3975                         power-domain-names = "lcx", "lmx";
3976
3977                         interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
3978
3979                         memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
3980
3981                         qcom,qmp = <&aoss_qmp>;
3982
3983                         qcom,smem-states = <&smp2p_adsp_out 0>;
3984                         qcom,smem-state-names = "stop";
3985
3986                         status = "disabled";
3987
3988                         remoteproc_adsp_glink: glink-edge {
3989                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3990                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3991                                                              IRQ_TYPE_EDGE_RISING>;
3992                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
3993                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3994
3995                                 label = "lpass";
3996                                 qcom,remote-pid = <2>;
3997
3998                                 fastrpc {
3999                                         compatible = "qcom,fastrpc";
4000                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4001                                         label = "adsp";
4002                                         #address-cells = <1>;
4003                                         #size-cells = <0>;
4004
4005                                         compute-cb@3 {
4006                                                 compatible = "qcom,fastrpc-compute-cb";
4007                                                 reg = <3>;
4008                                                 iommus = <&apps_smmu 0x1003 0x80>,
4009                                                          <&apps_smmu 0x1063 0x0>;
4010                                         };
4011
4012                                         compute-cb@4 {
4013                                                 compatible = "qcom,fastrpc-compute-cb";
4014                                                 reg = <4>;
4015                                                 iommus = <&apps_smmu 0x1004 0x80>,
4016                                                          <&apps_smmu 0x1064 0x0>;
4017                                         };
4018
4019                                         compute-cb@5 {
4020                                                 compatible = "qcom,fastrpc-compute-cb";
4021                                                 reg = <5>;
4022                                                 iommus = <&apps_smmu 0x1005 0x80>,
4023                                                          <&apps_smmu 0x1065 0x0>;
4024                                         };
4025
4026                                         compute-cb@6 {
4027                                                 compatible = "qcom,fastrpc-compute-cb";
4028                                                 reg = <6>;
4029                                                 iommus = <&apps_smmu 0x1006 0x80>,
4030                                                          <&apps_smmu 0x1066 0x0>;
4031                                         };
4032
4033                                         compute-cb@7 {
4034                                                 compatible = "qcom,fastrpc-compute-cb";
4035                                                 reg = <7>;
4036                                                 iommus = <&apps_smmu 0x1007 0x80>,
4037                                                          <&apps_smmu 0x1067 0x0>;
4038                                         };
4039                                 };
4040
4041                                 gpr {
4042                                         compatible = "qcom,gpr";
4043                                         qcom,glink-channels = "adsp_apps";
4044                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
4045                                         qcom,intents = <512 20>;
4046                                         #address-cells = <1>;
4047                                         #size-cells = <0>;
4048
4049                                         q6apm: service@1 {
4050                                                 compatible = "qcom,q6apm";
4051                                                 reg = <GPR_APM_MODULE_IID>;
4052                                                 #sound-dai-cells = <0>;
4053                                                 qcom,protection-domain = "avs/audio",
4054                                                                          "msm/adsp/audio_pd";
4055
4056                                                 q6apmdai: dais {
4057                                                         compatible = "qcom,q6apm-dais";
4058                                                         iommus = <&apps_smmu 0x1001 0x80>,
4059                                                                  <&apps_smmu 0x1061 0x0>;
4060                                                 };
4061
4062                                                 q6apmbedai: bedais {
4063                                                         compatible = "qcom,q6apm-lpass-dais";
4064                                                         #sound-dai-cells = <1>;
4065                                                 };
4066                                         };
4067
4068                                         q6prm: service@2 {
4069                                                 compatible = "qcom,q6prm";
4070                                                 reg = <GPR_PRM_MODULE_IID>;
4071                                                 qcom,protection-domain = "avs/audio",
4072                                                                          "msm/adsp/audio_pd";
4073
4074                                                 q6prmcc: clock-controller {
4075                                                         compatible = "qcom,q6prm-lpass-clocks";
4076                                                         #clock-cells = <2>;
4077                                                 };
4078                                         };
4079                                 };
4080                         };
4081                 };
4082
4083                 nsp_noc: interconnect@320c0000 {
4084                         compatible = "qcom,sm8550-nsp-noc";
4085                         reg = <0 0x320c0000 0 0xe080>;
4086                         #interconnect-cells = <2>;
4087                         qcom,bcm-voters = <&apps_bcm_voter>;
4088                 };
4089
4090                 remoteproc_cdsp: remoteproc@32300000 {
4091                         compatible = "qcom,sm8550-cdsp-pas";
4092                         reg = <0x0 0x32300000 0x0 0x1400000>;
4093
4094                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4095                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
4096                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
4097                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
4098                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
4099                         interrupt-names = "wdog", "fatal", "ready",
4100                                           "handover", "stop-ack";
4101
4102                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4103                         clock-names = "xo";
4104
4105                         power-domains = <&rpmhpd RPMHPD_CX>,
4106                                         <&rpmhpd RPMHPD_MXC>,
4107                                         <&rpmhpd RPMHPD_NSP>;
4108                         power-domain-names = "cx", "mxc", "nsp";
4109
4110                         interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4111
4112                         memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4113
4114                         qcom,qmp = <&aoss_qmp>;
4115
4116                         qcom,smem-states = <&smp2p_cdsp_out 0>;
4117                         qcom,smem-state-names = "stop";
4118
4119                         status = "disabled";
4120
4121                         glink-edge {
4122                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4123                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4124                                                              IRQ_TYPE_EDGE_RISING>;
4125                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
4126                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4127
4128                                 label = "cdsp";
4129                                 qcom,remote-pid = <5>;
4130
4131                                 fastrpc {
4132                                         compatible = "qcom,fastrpc";
4133                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4134                                         label = "cdsp";
4135                                         #address-cells = <1>;
4136                                         #size-cells = <0>;
4137
4138                                         compute-cb@1 {
4139                                                 compatible = "qcom,fastrpc-compute-cb";
4140                                                 reg = <1>;
4141                                                 iommus = <&apps_smmu 0x1961 0x0>,
4142                                                          <&apps_smmu 0x0c01 0x20>,
4143                                                          <&apps_smmu 0x19c1 0x10>;
4144                                         };
4145
4146                                         compute-cb@2 {
4147                                                 compatible = "qcom,fastrpc-compute-cb";
4148                                                 reg = <2>;
4149                                                 iommus = <&apps_smmu 0x1962 0x0>,
4150                                                          <&apps_smmu 0x0c02 0x20>,
4151                                                          <&apps_smmu 0x19c2 0x10>;
4152                                         };
4153
4154                                         compute-cb@3 {
4155                                                 compatible = "qcom,fastrpc-compute-cb";
4156                                                 reg = <3>;
4157                                                 iommus = <&apps_smmu 0x1963 0x0>,
4158                                                          <&apps_smmu 0x0c03 0x20>,
4159                                                          <&apps_smmu 0x19c3 0x10>;
4160                                         };
4161
4162                                         compute-cb@4 {
4163                                                 compatible = "qcom,fastrpc-compute-cb";
4164                                                 reg = <4>;
4165                                                 iommus = <&apps_smmu 0x1964 0x0>,
4166                                                          <&apps_smmu 0x0c04 0x20>,
4167                                                          <&apps_smmu 0x19c4 0x10>;
4168                                         };
4169
4170                                         compute-cb@5 {
4171                                                 compatible = "qcom,fastrpc-compute-cb";
4172                                                 reg = <5>;
4173                                                 iommus = <&apps_smmu 0x1965 0x0>,
4174                                                          <&apps_smmu 0x0c05 0x20>,
4175                                                          <&apps_smmu 0x19c5 0x10>;
4176                                         };
4177
4178                                         compute-cb@6 {
4179                                                 compatible = "qcom,fastrpc-compute-cb";
4180                                                 reg = <6>;
4181                                                 iommus = <&apps_smmu 0x1966 0x0>,
4182                                                          <&apps_smmu 0x0c06 0x20>,
4183                                                          <&apps_smmu 0x19c6 0x10>;
4184                                         };
4185
4186                                         compute-cb@7 {
4187                                                 compatible = "qcom,fastrpc-compute-cb";
4188                                                 reg = <7>;
4189                                                 iommus = <&apps_smmu 0x1967 0x0>,
4190                                                          <&apps_smmu 0x0c07 0x20>,
4191                                                          <&apps_smmu 0x19c7 0x10>;
4192                                         };
4193
4194                                         compute-cb@8 {
4195                                                 compatible = "qcom,fastrpc-compute-cb";
4196                                                 reg = <8>;
4197                                                 iommus = <&apps_smmu 0x1968 0x0>,
4198                                                          <&apps_smmu 0x0c08 0x20>,
4199                                                          <&apps_smmu 0x19c8 0x10>;
4200                                         };
4201
4202                                         /* note: secure cb9 in downstream */
4203                                 };
4204                         };
4205                 };
4206         };
4207
4208         thermal-zones {
4209                 aoss0-thermal {
4210                         polling-delay-passive = <0>;
4211                         polling-delay = <0>;
4212                         thermal-sensors = <&tsens0 0>;
4213
4214                         trips {
4215                                 thermal-engine-config {
4216                                         temperature = <125000>;
4217                                         hysteresis = <1000>;
4218                                         type = "passive";
4219                                 };
4220
4221                                 reset-mon-config {
4222                                         temperature = <115000>;
4223                                         hysteresis = <5000>;
4224                                         type = "passive";
4225                                 };
4226                         };
4227                 };
4228
4229                 cpuss0-thermal {
4230                         polling-delay-passive = <0>;
4231                         polling-delay = <0>;
4232                         thermal-sensors = <&tsens0 1>;
4233
4234                         trips {
4235                                 thermal-engine-config {
4236                                         temperature = <125000>;
4237                                         hysteresis = <1000>;
4238                                         type = "passive";
4239                                 };
4240
4241                                 reset-mon-config {
4242                                         temperature = <115000>;
4243                                         hysteresis = <5000>;
4244                                         type = "passive";
4245                                 };
4246                         };
4247                 };
4248
4249                 cpuss1-thermal {
4250                         polling-delay-passive = <0>;
4251                         polling-delay = <0>;
4252                         thermal-sensors = <&tsens0 2>;
4253
4254                         trips {
4255                                 thermal-engine-config {
4256                                         temperature = <125000>;
4257                                         hysteresis = <1000>;
4258                                         type = "passive";
4259                                 };
4260
4261                                 reset-mon-config {
4262                                         temperature = <115000>;
4263                                         hysteresis = <5000>;
4264                                         type = "passive";
4265                                 };
4266                         };
4267                 };
4268
4269                 cpuss2-thermal {
4270                         polling-delay-passive = <0>;
4271                         polling-delay = <0>;
4272                         thermal-sensors = <&tsens0 3>;
4273
4274                         trips {
4275                                 thermal-engine-config {
4276                                         temperature = <125000>;
4277                                         hysteresis = <1000>;
4278                                         type = "passive";
4279                                 };
4280
4281                                 reset-mon-config {
4282                                         temperature = <115000>;
4283                                         hysteresis = <5000>;
4284                                         type = "passive";
4285                                 };
4286                         };
4287                 };
4288
4289                 cpuss3-thermal {
4290                         polling-delay-passive = <0>;
4291                         polling-delay = <0>;
4292                         thermal-sensors = <&tsens0 4>;
4293
4294                         trips {
4295                                 thermal-engine-config {
4296                                         temperature = <125000>;
4297                                         hysteresis = <1000>;
4298                                         type = "passive";
4299                                 };
4300
4301                                 reset-mon-config {
4302                                         temperature = <115000>;
4303                                         hysteresis = <5000>;
4304                                         type = "passive";
4305                                 };
4306                         };
4307                 };
4308
4309                 cpu3-top-thermal {
4310                         polling-delay-passive = <0>;
4311                         polling-delay = <0>;
4312                         thermal-sensors = <&tsens0 5>;
4313
4314                         trips {
4315                                 cpu3_top_alert0: trip-point0 {
4316                                         temperature = <90000>;
4317                                         hysteresis = <2000>;
4318                                         type = "passive";
4319                                 };
4320
4321                                 cpu3_top_alert1: trip-point1 {
4322                                         temperature = <95000>;
4323                                         hysteresis = <2000>;
4324                                         type = "passive";
4325                                 };
4326
4327                                 cpu3_top_crit: cpu-critical {
4328                                         temperature = <110000>;
4329                                         hysteresis = <1000>;
4330                                         type = "critical";
4331                                 };
4332                         };
4333                 };
4334
4335                 cpu3-bottom-thermal {
4336                         polling-delay-passive = <0>;
4337                         polling-delay = <0>;
4338                         thermal-sensors = <&tsens0 6>;
4339
4340                         trips {
4341                                 cpu3_bottom_alert0: trip-point0 {
4342                                         temperature = <90000>;
4343                                         hysteresis = <2000>;
4344                                         type = "passive";
4345                                 };
4346
4347                                 cpu3_bottom_alert1: trip-point1 {
4348                                         temperature = <95000>;
4349                                         hysteresis = <2000>;
4350                                         type = "passive";
4351                                 };
4352
4353                                 cpu3_bottom_crit: cpu-critical {
4354                                         temperature = <110000>;
4355                                         hysteresis = <1000>;
4356                                         type = "critical";
4357                                 };
4358                         };
4359                 };
4360
4361                 cpu4-top-thermal {
4362                         polling-delay-passive = <0>;
4363                         polling-delay = <0>;
4364                         thermal-sensors = <&tsens0 7>;
4365
4366                         trips {
4367                                 cpu4_top_alert0: trip-point0 {
4368                                         temperature = <90000>;
4369                                         hysteresis = <2000>;
4370                                         type = "passive";
4371                                 };
4372
4373                                 cpu4_top_alert1: trip-point1 {
4374                                         temperature = <95000>;
4375                                         hysteresis = <2000>;
4376                                         type = "passive";
4377                                 };
4378
4379                                 cpu4_top_crit: cpu-critical {
4380                                         temperature = <110000>;
4381                                         hysteresis = <1000>;
4382                                         type = "critical";
4383                                 };
4384                         };
4385                 };
4386
4387                 cpu4-bottom-thermal {
4388                         polling-delay-passive = <0>;
4389                         polling-delay = <0>;
4390                         thermal-sensors = <&tsens0 8>;
4391
4392                         trips {
4393                                 cpu4_bottom_alert0: trip-point0 {
4394                                         temperature = <90000>;
4395                                         hysteresis = <2000>;
4396                                         type = "passive";
4397                                 };
4398
4399                                 cpu4_bottom_alert1: trip-point1 {
4400                                         temperature = <95000>;
4401                                         hysteresis = <2000>;
4402                                         type = "passive";
4403                                 };
4404
4405                                 cpu4_bottom_crit: cpu-critical {
4406                                         temperature = <110000>;
4407                                         hysteresis = <1000>;
4408                                         type = "critical";
4409                                 };
4410                         };
4411                 };
4412
4413                 cpu5-top-thermal {
4414                         polling-delay-passive = <0>;
4415                         polling-delay = <0>;
4416                         thermal-sensors = <&tsens0 9>;
4417
4418                         trips {
4419                                 cpu5_top_alert0: trip-point0 {
4420                                         temperature = <90000>;
4421                                         hysteresis = <2000>;
4422                                         type = "passive";
4423                                 };
4424
4425                                 cpu5_top_alert1: trip-point1 {
4426                                         temperature = <95000>;
4427                                         hysteresis = <2000>;
4428                                         type = "passive";
4429                                 };
4430
4431                                 cpu5_top_crit: cpu-critical {
4432                                         temperature = <110000>;
4433                                         hysteresis = <1000>;
4434                                         type = "critical";
4435                                 };
4436                         };
4437                 };
4438
4439                 cpu5-bottom-thermal {
4440                         polling-delay-passive = <0>;
4441                         polling-delay = <0>;
4442                         thermal-sensors = <&tsens0 10>;
4443
4444                         trips {
4445                                 cpu5_bottom_alert0: trip-point0 {
4446                                         temperature = <90000>;
4447                                         hysteresis = <2000>;
4448                                         type = "passive";
4449                                 };
4450
4451                                 cpu5_bottom_alert1: trip-point1 {
4452                                         temperature = <95000>;
4453                                         hysteresis = <2000>;
4454                                         type = "passive";
4455                                 };
4456
4457                                 cpu5_bottom_crit: cpu-critical {
4458                                         temperature = <110000>;
4459                                         hysteresis = <1000>;
4460                                         type = "critical";
4461                                 };
4462                         };
4463                 };
4464
4465                 cpu6-top-thermal {
4466                         polling-delay-passive = <0>;
4467                         polling-delay = <0>;
4468                         thermal-sensors = <&tsens0 11>;
4469
4470                         trips {
4471                                 cpu6_top_alert0: trip-point0 {
4472                                         temperature = <90000>;
4473                                         hysteresis = <2000>;
4474                                         type = "passive";
4475                                 };
4476
4477                                 cpu6_top_alert1: trip-point1 {
4478                                         temperature = <95000>;
4479                                         hysteresis = <2000>;
4480                                         type = "passive";
4481                                 };
4482
4483                                 cpu6_top_crit: cpu-critical {
4484                                         temperature = <110000>;
4485                                         hysteresis = <1000>;
4486                                         type = "critical";
4487                                 };
4488                         };
4489                 };
4490
4491                 cpu6-bottom-thermal {
4492                         polling-delay-passive = <0>;
4493                         polling-delay = <0>;
4494                         thermal-sensors = <&tsens0 12>;
4495
4496                         trips {
4497                                 cpu6_bottom_alert0: trip-point0 {
4498                                         temperature = <90000>;
4499                                         hysteresis = <2000>;
4500                                         type = "passive";
4501                                 };
4502
4503                                 cpu6_bottom_alert1: trip-point1 {
4504                                         temperature = <95000>;
4505                                         hysteresis = <2000>;
4506                                         type = "passive";
4507                                 };
4508
4509                                 cpu6_bottom_crit: cpu-critical {
4510                                         temperature = <110000>;
4511                                         hysteresis = <1000>;
4512                                         type = "critical";
4513                                 };
4514                         };
4515                 };
4516
4517                 cpu7-top-thermal {
4518                         polling-delay-passive = <0>;
4519                         polling-delay = <0>;
4520                         thermal-sensors = <&tsens0 13>;
4521
4522                         trips {
4523                                 cpu7_top_alert0: trip-point0 {
4524                                         temperature = <90000>;
4525                                         hysteresis = <2000>;
4526                                         type = "passive";
4527                                 };
4528
4529                                 cpu7_top_alert1: trip-point1 {
4530                                         temperature = <95000>;
4531                                         hysteresis = <2000>;
4532                                         type = "passive";
4533                                 };
4534
4535                                 cpu7_top_crit: cpu-critical {
4536                                         temperature = <110000>;
4537                                         hysteresis = <1000>;
4538                                         type = "critical";
4539                                 };
4540                         };
4541                 };
4542
4543                 cpu7-middle-thermal {
4544                         polling-delay-passive = <0>;
4545                         polling-delay = <0>;
4546                         thermal-sensors = <&tsens0 14>;
4547
4548                         trips {
4549                                 cpu7_middle_alert0: trip-point0 {
4550                                         temperature = <90000>;
4551                                         hysteresis = <2000>;
4552                                         type = "passive";
4553                                 };
4554
4555                                 cpu7_middle_alert1: trip-point1 {
4556                                         temperature = <95000>;
4557                                         hysteresis = <2000>;
4558                                         type = "passive";
4559                                 };
4560
4561                                 cpu7_middle_crit: cpu-critical {
4562                                         temperature = <110000>;
4563                                         hysteresis = <1000>;
4564                                         type = "critical";
4565                                 };
4566                         };
4567                 };
4568
4569                 cpu7-bottom-thermal {
4570                         polling-delay-passive = <0>;
4571                         polling-delay = <0>;
4572                         thermal-sensors = <&tsens0 15>;
4573
4574                         trips {
4575                                 cpu7_bottom_alert0: trip-point0 {
4576                                         temperature = <90000>;
4577                                         hysteresis = <2000>;
4578                                         type = "passive";
4579                                 };
4580
4581                                 cpu7_bottom_alert1: trip-point1 {
4582                                         temperature = <95000>;
4583                                         hysteresis = <2000>;
4584                                         type = "passive";
4585                                 };
4586
4587                                 cpu7_bottom_crit: cpu-critical {
4588                                         temperature = <110000>;
4589                                         hysteresis = <1000>;
4590                                         type = "critical";
4591                                 };
4592                         };
4593                 };
4594
4595                 aoss1-thermal {
4596                         polling-delay-passive = <0>;
4597                         polling-delay = <0>;
4598                         thermal-sensors = <&tsens1 0>;
4599
4600                         trips {
4601                                 thermal-engine-config {
4602                                         temperature = <125000>;
4603                                         hysteresis = <1000>;
4604                                         type = "passive";
4605                                 };
4606
4607                                 reset-mon-config {
4608                                         temperature = <115000>;
4609                                         hysteresis = <5000>;
4610                                         type = "passive";
4611                                 };
4612                         };
4613                 };
4614
4615                 cpu0-thermal {
4616                         polling-delay-passive = <0>;
4617                         polling-delay = <0>;
4618                         thermal-sensors = <&tsens1 1>;
4619
4620                         trips {
4621                                 cpu0_alert0: trip-point0 {
4622                                         temperature = <90000>;
4623                                         hysteresis = <2000>;
4624                                         type = "passive";
4625                                 };
4626
4627                                 cpu0_alert1: trip-point1 {
4628                                         temperature = <95000>;
4629                                         hysteresis = <2000>;
4630                                         type = "passive";
4631                                 };
4632
4633                                 cpu0_crit: cpu-critical {
4634                                         temperature = <110000>;
4635                                         hysteresis = <1000>;
4636                                         type = "critical";
4637                                 };
4638                         };
4639                 };
4640
4641                 cpu1-thermal {
4642                         polling-delay-passive = <0>;
4643                         polling-delay = <0>;
4644                         thermal-sensors = <&tsens1 2>;
4645
4646                         trips {
4647                                 cpu1_alert0: trip-point0 {
4648                                         temperature = <90000>;
4649                                         hysteresis = <2000>;
4650                                         type = "passive";
4651                                 };
4652
4653                                 cpu1_alert1: trip-point1 {
4654                                         temperature = <95000>;
4655                                         hysteresis = <2000>;
4656                                         type = "passive";
4657                                 };
4658
4659                                 cpu1_crit: cpu-critical {
4660                                         temperature = <110000>;
4661                                         hysteresis = <1000>;
4662                                         type = "critical";
4663                                 };
4664                         };
4665                 };
4666
4667                 cpu2-thermal {
4668                         polling-delay-passive = <0>;
4669                         polling-delay = <0>;
4670                         thermal-sensors = <&tsens1 3>;
4671
4672                         trips {
4673                                 cpu2_alert0: trip-point0 {
4674                                         temperature = <90000>;
4675                                         hysteresis = <2000>;
4676                                         type = "passive";
4677                                 };
4678
4679                                 cpu2_alert1: trip-point1 {
4680                                         temperature = <95000>;
4681                                         hysteresis = <2000>;
4682                                         type = "passive";
4683                                 };
4684
4685                                 cpu2_crit: cpu-critical {
4686                                         temperature = <110000>;
4687                                         hysteresis = <1000>;
4688                                         type = "critical";
4689                                 };
4690                         };
4691                 };
4692
4693                 cdsp0-thermal {
4694                         polling-delay-passive = <10>;
4695                         polling-delay = <0>;
4696                         thermal-sensors = <&tsens2 4>;
4697
4698                         trips {
4699                                 thermal-engine-config {
4700                                         temperature = <125000>;
4701                                         hysteresis = <1000>;
4702                                         type = "passive";
4703                                 };
4704
4705                                 thermal-hal-config {
4706                                         temperature = <125000>;
4707                                         hysteresis = <1000>;
4708                                         type = "passive";
4709                                 };
4710
4711                                 reset-mon-config {
4712                                         temperature = <115000>;
4713                                         hysteresis = <5000>;
4714                                         type = "passive";
4715                                 };
4716
4717                                 cdsp0_junction_config: junction-config {
4718                                         temperature = <95000>;
4719                                         hysteresis = <5000>;
4720                                         type = "passive";
4721                                 };
4722                         };
4723                 };
4724
4725                 cdsp1-thermal {
4726                         polling-delay-passive = <10>;
4727                         polling-delay = <0>;
4728                         thermal-sensors = <&tsens2 5>;
4729
4730                         trips {
4731                                 thermal-engine-config {
4732                                         temperature = <125000>;
4733                                         hysteresis = <1000>;
4734                                         type = "passive";
4735                                 };
4736
4737                                 thermal-hal-config {
4738                                         temperature = <125000>;
4739                                         hysteresis = <1000>;
4740                                         type = "passive";
4741                                 };
4742
4743                                 reset-mon-config {
4744                                         temperature = <115000>;
4745                                         hysteresis = <5000>;
4746                                         type = "passive";
4747                                 };
4748
4749                                 cdsp1_junction_config: junction-config {
4750                                         temperature = <95000>;
4751                                         hysteresis = <5000>;
4752                                         type = "passive";
4753                                 };
4754                         };
4755                 };
4756
4757                 cdsp2-thermal {
4758                         polling-delay-passive = <10>;
4759                         polling-delay = <0>;
4760                         thermal-sensors = <&tsens2 6>;
4761
4762                         trips {
4763                                 thermal-engine-config {
4764                                         temperature = <125000>;
4765                                         hysteresis = <1000>;
4766                                         type = "passive";
4767                                 };
4768
4769                                 thermal-hal-config {
4770                                         temperature = <125000>;
4771                                         hysteresis = <1000>;
4772                                         type = "passive";
4773                                 };
4774
4775                                 reset-mon-config {
4776                                         temperature = <115000>;
4777                                         hysteresis = <5000>;
4778                                         type = "passive";
4779                                 };
4780
4781                                 cdsp2_junction_config: junction-config {
4782                                         temperature = <95000>;
4783                                         hysteresis = <5000>;
4784                                         type = "passive";
4785                                 };
4786                         };
4787                 };
4788
4789                 cdsp3-thermal {
4790                         polling-delay-passive = <10>;
4791                         polling-delay = <0>;
4792                         thermal-sensors = <&tsens2 7>;
4793
4794                         trips {
4795                                 thermal-engine-config {
4796                                         temperature = <125000>;
4797                                         hysteresis = <1000>;
4798                                         type = "passive";
4799                                 };
4800
4801                                 thermal-hal-config {
4802                                         temperature = <125000>;
4803                                         hysteresis = <1000>;
4804                                         type = "passive";
4805                                 };
4806
4807                                 reset-mon-config {
4808                                         temperature = <115000>;
4809                                         hysteresis = <5000>;
4810                                         type = "passive";
4811                                 };
4812
4813                                 cdsp3_junction_config: junction-config {
4814                                         temperature = <95000>;
4815                                         hysteresis = <5000>;
4816                                         type = "passive";
4817                                 };
4818                         };
4819                 };
4820
4821                 video-thermal {
4822                         polling-delay-passive = <0>;
4823                         polling-delay = <0>;
4824                         thermal-sensors = <&tsens1 8>;
4825
4826                         trips {
4827                                 thermal-engine-config {
4828                                         temperature = <125000>;
4829                                         hysteresis = <1000>;
4830                                         type = "passive";
4831                                 };
4832
4833                                 reset-mon-config {
4834                                         temperature = <115000>;
4835                                         hysteresis = <5000>;
4836                                         type = "passive";
4837                                 };
4838                         };
4839                 };
4840
4841                 mem-thermal {
4842                         polling-delay-passive = <10>;
4843                         polling-delay = <0>;
4844                         thermal-sensors = <&tsens1 9>;
4845
4846                         trips {
4847                                 thermal-engine-config {
4848                                         temperature = <125000>;
4849                                         hysteresis = <1000>;
4850                                         type = "passive";
4851                                 };
4852
4853                                 ddr_config0: ddr0-config {
4854                                         temperature = <90000>;
4855                                         hysteresis = <5000>;
4856                                         type = "passive";
4857                                 };
4858
4859                                 reset-mon-config {
4860                                         temperature = <115000>;
4861                                         hysteresis = <5000>;
4862                                         type = "passive";
4863                                 };
4864                         };
4865                 };
4866
4867                 modem0-thermal {
4868                         polling-delay-passive = <0>;
4869                         polling-delay = <0>;
4870                         thermal-sensors = <&tsens1 10>;
4871
4872                         trips {
4873                                 thermal-engine-config {
4874                                         temperature = <125000>;
4875                                         hysteresis = <1000>;
4876                                         type = "passive";
4877                                 };
4878
4879                                 mdmss0_config0: mdmss0-config0 {
4880                                         temperature = <102000>;
4881                                         hysteresis = <3000>;
4882                                         type = "passive";
4883                                 };
4884
4885                                 mdmss0_config1: mdmss0-config1 {
4886                                         temperature = <105000>;
4887                                         hysteresis = <3000>;
4888                                         type = "passive";
4889                                 };
4890
4891                                 reset-mon-config {
4892                                         temperature = <115000>;
4893                                         hysteresis = <5000>;
4894                                         type = "passive";
4895                                 };
4896                         };
4897                 };
4898
4899                 modem1-thermal {
4900                         polling-delay-passive = <0>;
4901                         polling-delay = <0>;
4902                         thermal-sensors = <&tsens1 11>;
4903
4904                         trips {
4905                                 thermal-engine-config {
4906                                         temperature = <125000>;
4907                                         hysteresis = <1000>;
4908                                         type = "passive";
4909                                 };
4910
4911                                 mdmss1_config0: mdmss1-config0 {
4912                                         temperature = <102000>;
4913                                         hysteresis = <3000>;
4914                                         type = "passive";
4915                                 };
4916
4917                                 mdmss1_config1: mdmss1-config1 {
4918                                         temperature = <105000>;
4919                                         hysteresis = <3000>;
4920                                         type = "passive";
4921                                 };
4922
4923                                 reset-mon-config {
4924                                         temperature = <115000>;
4925                                         hysteresis = <5000>;
4926                                         type = "passive";
4927                                 };
4928                         };
4929                 };
4930
4931                 modem2-thermal {
4932                         polling-delay-passive = <0>;
4933                         polling-delay = <0>;
4934                         thermal-sensors = <&tsens1 12>;
4935
4936                         trips {
4937                                 thermal-engine-config {
4938                                         temperature = <125000>;
4939                                         hysteresis = <1000>;
4940                                         type = "passive";
4941                                 };
4942
4943                                 mdmss2_config0: mdmss2-config0 {
4944                                         temperature = <102000>;
4945                                         hysteresis = <3000>;
4946                                         type = "passive";
4947                                 };
4948
4949                                 mdmss2_config1: mdmss2-config1 {
4950                                         temperature = <105000>;
4951                                         hysteresis = <3000>;
4952                                         type = "passive";
4953                                 };
4954
4955                                 reset-mon-config {
4956                                         temperature = <115000>;
4957                                         hysteresis = <5000>;
4958                                         type = "passive";
4959                                 };
4960                         };
4961                 };
4962
4963                 modem3-thermal {
4964                         polling-delay-passive = <0>;
4965                         polling-delay = <0>;
4966                         thermal-sensors = <&tsens1 13>;
4967
4968                         trips {
4969                                 thermal-engine-config {
4970                                         temperature = <125000>;
4971                                         hysteresis = <1000>;
4972                                         type = "passive";
4973                                 };
4974
4975                                 mdmss3_config0: mdmss3-config0 {
4976                                         temperature = <102000>;
4977                                         hysteresis = <3000>;
4978                                         type = "passive";
4979                                 };
4980
4981                                 mdmss3_config1: mdmss3-config1 {
4982                                         temperature = <105000>;
4983                                         hysteresis = <3000>;
4984                                         type = "passive";
4985                                 };
4986
4987                                 reset-mon-config {
4988                                         temperature = <115000>;
4989                                         hysteresis = <5000>;
4990                                         type = "passive";
4991                                 };
4992                         };
4993                 };
4994
4995                 camera0-thermal {
4996                         polling-delay-passive = <0>;
4997                         polling-delay = <0>;
4998                         thermal-sensors = <&tsens1 14>;
4999
5000                         trips {
5001                                 thermal-engine-config {
5002                                         temperature = <125000>;
5003                                         hysteresis = <1000>;
5004                                         type = "passive";
5005                                 };
5006
5007                                 reset-mon-config {
5008                                         temperature = <115000>;
5009                                         hysteresis = <5000>;
5010                                         type = "passive";
5011                                 };
5012                         };
5013                 };
5014
5015                 camera1-thermal {
5016                         polling-delay-passive = <0>;
5017                         polling-delay = <0>;
5018                         thermal-sensors = <&tsens1 15>;
5019
5020                         trips {
5021                                 thermal-engine-config {
5022                                         temperature = <125000>;
5023                                         hysteresis = <1000>;
5024                                         type = "passive";
5025                                 };
5026
5027                                 reset-mon-config {
5028                                         temperature = <115000>;
5029                                         hysteresis = <5000>;
5030                                         type = "passive";
5031                                 };
5032                         };
5033                 };
5034
5035                 aoss2-thermal {
5036                         polling-delay-passive = <0>;
5037                         polling-delay = <0>;
5038                         thermal-sensors = <&tsens2 0>;
5039
5040                         trips {
5041                                 thermal-engine-config {
5042                                         temperature = <125000>;
5043                                         hysteresis = <1000>;
5044                                         type = "passive";
5045                                 };
5046
5047                                 reset-mon-config {
5048                                         temperature = <115000>;
5049                                         hysteresis = <5000>;
5050                                         type = "passive";
5051                                 };
5052                         };
5053                 };
5054
5055                 gpuss-0-thermal {
5056                         polling-delay-passive = <10>;
5057                         polling-delay = <0>;
5058                         thermal-sensors = <&tsens2 1>;
5059
5060                         trips {
5061                                 thermal-engine-config {
5062                                         temperature = <125000>;
5063                                         hysteresis = <1000>;
5064                                         type = "passive";
5065                                 };
5066
5067                                 thermal-hal-config {
5068                                         temperature = <125000>;
5069                                         hysteresis = <1000>;
5070                                         type = "passive";
5071                                 };
5072
5073                                 reset-mon-config {
5074                                         temperature = <115000>;
5075                                         hysteresis = <5000>;
5076                                         type = "passive";
5077                                 };
5078
5079                                 gpu0_junction_config: junction-config {
5080                                         temperature = <95000>;
5081                                         hysteresis = <5000>;
5082                                         type = "passive";
5083                                 };
5084                         };
5085                 };
5086
5087                 gpuss-1-thermal {
5088                         polling-delay-passive = <10>;
5089                         polling-delay = <0>;
5090                         thermal-sensors = <&tsens2 2>;
5091
5092                         trips {
5093                                 thermal-engine-config {
5094                                         temperature = <125000>;
5095                                         hysteresis = <1000>;
5096                                         type = "passive";
5097                                 };
5098
5099                                 thermal-hal-config {
5100                                         temperature = <125000>;
5101                                         hysteresis = <1000>;
5102                                         type = "passive";
5103                                 };
5104
5105                                 reset-mon-config {
5106                                         temperature = <115000>;
5107                                         hysteresis = <5000>;
5108                                         type = "passive";
5109                                 };
5110
5111                                 gpu1_junction_config: junction-config {
5112                                         temperature = <95000>;
5113                                         hysteresis = <5000>;
5114                                         type = "passive";
5115                                 };
5116                         };
5117                 };
5118
5119                 gpuss-2-thermal {
5120                         polling-delay-passive = <10>;
5121                         polling-delay = <0>;
5122                         thermal-sensors = <&tsens2 3>;
5123
5124                         trips {
5125                                 thermal-engine-config {
5126                                         temperature = <125000>;
5127                                         hysteresis = <1000>;
5128                                         type = "passive";
5129                                 };
5130
5131                                 thermal-hal-config {
5132                                         temperature = <125000>;
5133                                         hysteresis = <1000>;
5134                                         type = "passive";
5135                                 };
5136
5137                                 reset-mon-config {
5138                                         temperature = <115000>;
5139                                         hysteresis = <5000>;
5140                                         type = "passive";
5141                                 };
5142
5143                                 gpu2_junction_config: junction-config {
5144                                         temperature = <95000>;
5145                                         hysteresis = <5000>;
5146                                         type = "passive";
5147                                 };
5148                         };
5149                 };
5150
5151                 gpuss-3-thermal {
5152                         polling-delay-passive = <10>;
5153                         polling-delay = <0>;
5154                         thermal-sensors = <&tsens2 4>;
5155
5156                         trips {
5157                                 thermal-engine-config {
5158                                         temperature = <125000>;
5159                                         hysteresis = <1000>;
5160                                         type = "passive";
5161                                 };
5162
5163                                 thermal-hal-config {
5164                                         temperature = <125000>;
5165                                         hysteresis = <1000>;
5166                                         type = "passive";
5167                                 };
5168
5169                                 reset-mon-config {
5170                                         temperature = <115000>;
5171                                         hysteresis = <5000>;
5172                                         type = "passive";
5173                                 };
5174
5175                                 gpu3_junction_config: junction-config {
5176                                         temperature = <95000>;
5177                                         hysteresis = <5000>;
5178                                         type = "passive";
5179                                 };
5180                         };
5181                 };
5182
5183                 gpuss-4-thermal {
5184                         polling-delay-passive = <10>;
5185                         polling-delay = <0>;
5186                         thermal-sensors = <&tsens2 5>;
5187
5188                         trips {
5189                                 thermal-engine-config {
5190                                         temperature = <125000>;
5191                                         hysteresis = <1000>;
5192                                         type = "passive";
5193                                 };
5194
5195                                 thermal-hal-config {
5196                                         temperature = <125000>;
5197                                         hysteresis = <1000>;
5198                                         type = "passive";
5199                                 };
5200
5201                                 reset-mon-config {
5202                                         temperature = <115000>;
5203                                         hysteresis = <5000>;
5204                                         type = "passive";
5205                                 };
5206
5207                                 gpu4_junction_config: junction-config {
5208                                         temperature = <95000>;
5209                                         hysteresis = <5000>;
5210                                         type = "passive";
5211                                 };
5212                         };
5213                 };
5214
5215                 gpuss-5-thermal {
5216                         polling-delay-passive = <10>;
5217                         polling-delay = <0>;
5218                         thermal-sensors = <&tsens2 6>;
5219
5220                         trips {
5221                                 thermal-engine-config {
5222                                         temperature = <125000>;
5223                                         hysteresis = <1000>;
5224                                         type = "passive";
5225                                 };
5226
5227                                 thermal-hal-config {
5228                                         temperature = <125000>;
5229                                         hysteresis = <1000>;
5230                                         type = "passive";
5231                                 };
5232
5233                                 reset-mon-config {
5234                                         temperature = <115000>;
5235                                         hysteresis = <5000>;
5236                                         type = "passive";
5237                                 };
5238
5239                                 gpu5_junction_config: junction-config {
5240                                         temperature = <95000>;
5241                                         hysteresis = <5000>;
5242                                         type = "passive";
5243                                 };
5244                         };
5245                 };
5246
5247                 gpuss-6-thermal {
5248                         polling-delay-passive = <10>;
5249                         polling-delay = <0>;
5250                         thermal-sensors = <&tsens2 7>;
5251
5252                         trips {
5253                                 thermal-engine-config {
5254                                         temperature = <125000>;
5255                                         hysteresis = <1000>;
5256                                         type = "passive";
5257                                 };
5258
5259                                 thermal-hal-config {
5260                                         temperature = <125000>;
5261                                         hysteresis = <1000>;
5262                                         type = "passive";
5263                                 };
5264
5265                                 reset-mon-config {
5266                                         temperature = <115000>;
5267                                         hysteresis = <5000>;
5268                                         type = "passive";
5269                                 };
5270
5271                                 gpu6_junction_config: junction-config {
5272                                         temperature = <95000>;
5273                                         hysteresis = <5000>;
5274                                         type = "passive";
5275                                 };
5276                         };
5277                 };
5278
5279                 gpuss-7-thermal {
5280                         polling-delay-passive = <10>;
5281                         polling-delay = <0>;
5282                         thermal-sensors = <&tsens2 8>;
5283
5284                         trips {
5285                                 thermal-engine-config {
5286                                         temperature = <125000>;
5287                                         hysteresis = <1000>;
5288                                         type = "passive";
5289                                 };
5290
5291                                 thermal-hal-config {
5292                                         temperature = <125000>;
5293                                         hysteresis = <1000>;
5294                                         type = "passive";
5295                                 };
5296
5297                                 reset-mon-config {
5298                                         temperature = <115000>;
5299                                         hysteresis = <5000>;
5300                                         type = "passive";
5301                                 };
5302
5303                                 gpu7_junction_config: junction-config {
5304                                         temperature = <95000>;
5305                                         hysteresis = <5000>;
5306                                         type = "passive";
5307                                 };
5308                         };
5309                 };
5310         };
5311
5312         timer {
5313                 compatible = "arm,armv8-timer";
5314                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5315                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5316                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5317                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5318         };
5319 };