arch/arm64/boot/dts/qcom/sm8450.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2021, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
  10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
  11 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
  12 #include <dt-bindings/dma/qcom-gpi.h>
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/mailbox/qcom-ipcc.h>
  15 #include <dt-bindings/phy/phy-qcom-qmp.h>
  16 #include <dt-bindings/power/qcom,rpmhpd.h>
  17 #include <dt-bindings/power/qcom-rpmpd.h>
  18 #include <dt-bindings/interconnect/qcom,icc.h>
  19 #include <dt-bindings/interconnect/qcom,sm8450.h>
  20 #include <dt-bindings/soc/qcom,gpr.h>
  21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24
  25 / {
  26         interrupt-parent = <&intc>;
  27
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         chosen { };
  32
  33         clocks {
  34                 xo_board: xo-board {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <76800000>;
  38                 };
  39
  40                 sleep_clk: sleep-clk {
  41                         compatible = "fixed-clock";
  42                         #clock-cells = <0>;
  43                         clock-frequency = <32000>;
  44                 };
  45         };
  46
  47         cpus {
  48                 #address-cells = <2>;
  49                 #size-cells = <0>;
  50
  51                 CPU0: cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "qcom,kryo780";
  54                         reg = <0x0 0x0>;
  55                         enable-method = "psci";
  56                         next-level-cache = <&L2_0>;
  57                         power-domains = <&CPU_PD0>;
  58                         power-domain-names = "psci";
  59                         qcom,freq-domain = <&cpufreq_hw 0>;
  60                         #cooling-cells = <2>;
  61                         clocks = <&cpufreq_hw 0>;
  62                         L2_0: l2-cache {
  63                                 compatible = "cache";
  64                                 cache-level = <2>;
  65                                 cache-unified;
  66                                 next-level-cache = <&L3_0>;
  67                                 L3_0: l3-cache {
  68                                         compatible = "cache";
  69                                         cache-level = <3>;
  70                                         cache-unified;
  71                                 };
  72                         };
  73                 };
  74
  75                 CPU1: cpu@100 {
  76                         device_type = "cpu";
  77                         compatible = "qcom,kryo780";
  78                         reg = <0x0 0x100>;
  79                         enable-method = "psci";
  80                         next-level-cache = <&L2_100>;
  81                         power-domains = <&CPU_PD1>;
  82                         power-domain-names = "psci";
  83                         qcom,freq-domain = <&cpufreq_hw 0>;
  84                         #cooling-cells = <2>;
  85                         clocks = <&cpufreq_hw 0>;
  86                         L2_100: l2-cache {
  87                                 compatible = "cache";
  88                                 cache-level = <2>;
  89                                 cache-unified;
  90                                 next-level-cache = <&L3_0>;
  91                         };
  92                 };
  93
  94                 CPU2: cpu@200 {
  95                         device_type = "cpu";
  96                         compatible = "qcom,kryo780";
  97                         reg = <0x0 0x200>;
  98                         enable-method = "psci";
  99                         next-level-cache = <&L2_200>;
 100                         power-domains = <&CPU_PD2>;
 101                         power-domain-names = "psci";
 102                         qcom,freq-domain = <&cpufreq_hw 0>;
 103                         #cooling-cells = <2>;
 104                         clocks = <&cpufreq_hw 0>;
 105                         L2_200: l2-cache {
 106                                 compatible = "cache";
 107                                 cache-level = <2>;
 108                                 cache-unified;
 109                                 next-level-cache = <&L3_0>;
 110                         };
 111                 };
 112
 113                 CPU3: cpu@300 {
 114                         device_type = "cpu";
 115                         compatible = "qcom,kryo780";
 116                         reg = <0x0 0x300>;
 117                         enable-method = "psci";
 118                         next-level-cache = <&L2_300>;
 119                         power-domains = <&CPU_PD3>;
 120                         power-domain-names = "psci";
 121                         qcom,freq-domain = <&cpufreq_hw 0>;
 122                         #cooling-cells = <2>;
 123                         clocks = <&cpufreq_hw 0>;
 124                         L2_300: l2-cache {
 125                                 compatible = "cache";
 126                                 cache-level = <2>;
 127                                 cache-unified;
 128                                 next-level-cache = <&L3_0>;
 129                         };
 130                 };
 131
 132                 CPU4: cpu@400 {
 133                         device_type = "cpu";
 134                         compatible = "qcom,kryo780";
 135                         reg = <0x0 0x400>;
 136                         enable-method = "psci";
 137                         next-level-cache = <&L2_400>;
 138                         power-domains = <&CPU_PD4>;
 139                         power-domain-names = "psci";
 140                         qcom,freq-domain = <&cpufreq_hw 1>;
 141                         #cooling-cells = <2>;
 142                         clocks = <&cpufreq_hw 1>;
 143                         L2_400: l2-cache {
 144                                 compatible = "cache";
 145                                 cache-level = <2>;
 146                                 cache-unified;
 147                                 next-level-cache = <&L3_0>;
 148                         };
 149                 };
 150
 151                 CPU5: cpu@500 {
 152                         device_type = "cpu";
 153                         compatible = "qcom,kryo780";
 154                         reg = <0x0 0x500>;
 155                         enable-method = "psci";
 156                         next-level-cache = <&L2_500>;
 157                         power-domains = <&CPU_PD5>;
 158                         power-domain-names = "psci";
 159                         qcom,freq-domain = <&cpufreq_hw 1>;
 160                         #cooling-cells = <2>;
 161                         clocks = <&cpufreq_hw 1>;
 162                         L2_500: l2-cache {
 163                                 compatible = "cache";
 164                                 cache-level = <2>;
 165                                 cache-unified;
 166                                 next-level-cache = <&L3_0>;
 167                         };
 168                 };
 169
 170                 CPU6: cpu@600 {
 171                         device_type = "cpu";
 172                         compatible = "qcom,kryo780";
 173                         reg = <0x0 0x600>;
 174                         enable-method = "psci";
 175                         next-level-cache = <&L2_600>;
 176                         power-domains = <&CPU_PD6>;
 177                         power-domain-names = "psci";
 178                         qcom,freq-domain = <&cpufreq_hw 1>;
 179                         #cooling-cells = <2>;
 180                         clocks = <&cpufreq_hw 1>;
 181                         L2_600: l2-cache {
 182                                 compatible = "cache";
 183                                 cache-level = <2>;
 184                                 cache-unified;
 185                                 next-level-cache = <&L3_0>;
 186                         };
 187                 };
 188
 189                 CPU7: cpu@700 {
 190                         device_type = "cpu";
 191                         compatible = "qcom,kryo780";
 192                         reg = <0x0 0x700>;
 193                         enable-method = "psci";
 194                         next-level-cache = <&L2_700>;
 195                         power-domains = <&CPU_PD7>;
 196                         power-domain-names = "psci";
 197                         qcom,freq-domain = <&cpufreq_hw 2>;
 198                         #cooling-cells = <2>;
 199                         clocks = <&cpufreq_hw 2>;
 200                         L2_700: l2-cache {
 201                                 compatible = "cache";
 202                                 cache-level = <2>;
 203                                 cache-unified;
 204                                 next-level-cache = <&L3_0>;
 205                         };
 206                 };
 207
 208                 cpu-map {
 209                         cluster0 {
 210                                 core0 {
 211                                         cpu = <&CPU0>;
 212                                 };
 213
 214                                 core1 {
 215                                         cpu = <&CPU1>;
 216                                 };
 217
 218                                 core2 {
 219                                         cpu = <&CPU2>;
 220                                 };
 221
 222                                 core3 {
 223                                         cpu = <&CPU3>;
 224                                 };
 225
 226                                 core4 {
 227                                         cpu = <&CPU4>;
 228                                 };
 229
 230                                 core5 {
 231                                         cpu = <&CPU5>;
 232                                 };
 233
 234                                 core6 {
 235                                         cpu = <&CPU6>;
 236                                 };
 237
 238                                 core7 {
 239                                         cpu = <&CPU7>;
 240                                 };
 241                         };
 242                 };
 243
 244                 idle-states {
 245                         entry-method = "psci";
 246
 247                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 248                                 compatible = "arm,idle-state";
 249                                 idle-state-name = "silver-rail-power-collapse";
 250                                 arm,psci-suspend-param = <0x40000004>;
 251                                 entry-latency-us = <800>;
 252                                 exit-latency-us = <750>;
 253                                 min-residency-us = <4090>;
 254                                 local-timer-stop;
 255                         };
 256
 257                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 258                                 compatible = "arm,idle-state";
 259                                 idle-state-name = "gold-rail-power-collapse";
 260                                 arm,psci-suspend-param = <0x40000004>;
 261                                 entry-latency-us = <600>;
 262                                 exit-latency-us = <1550>;
 263                                 min-residency-us = <4791>;
 264                                 local-timer-stop;
 265                         };
 266                 };
 267
 268                 domain-idle-states {
 269                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 270                                 compatible = "domain-idle-state";
 271                                 arm,psci-suspend-param = <0x41000044>;
 272                                 entry-latency-us = <1050>;
 273                                 exit-latency-us = <2500>;
 274                                 min-residency-us = <5309>;
 275                         };
 276
 277                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 278                                 compatible = "domain-idle-state";
 279                                 arm,psci-suspend-param = <0x4100c344>;
 280                                 entry-latency-us = <2700>;
 281                                 exit-latency-us = <3500>;
 282                                 min-residency-us = <13959>;
 283                         };
 284                 };
 285         };
 286
 287         firmware {
 288                 scm: scm {
 289                         compatible = "qcom,scm-sm8450", "qcom,scm";
 290                         qcom,dload-mode = <&tcsr 0x13000>;
 291                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 292                         #reset-cells = <1>;
 293                 };
 294         };
 295
 296         clk_virt: interconnect-0 {
 297                 compatible = "qcom,sm8450-clk-virt";
 298                 #interconnect-cells = <2>;
 299                 qcom,bcm-voters = <&apps_bcm_voter>;
 300         };
 301
 302         mc_virt: interconnect-1 {
 303                 compatible = "qcom,sm8450-mc-virt";
 304                 #interconnect-cells = <2>;
 305                 qcom,bcm-voters = <&apps_bcm_voter>;
 306         };
 307
 308         memory@a0000000 {
 309                 device_type = "memory";
 310                 /* We expect the bootloader to fill in the size */
 311                 reg = <0x0 0xa0000000 0x0 0x0>;
 312         };
 313
 314         pmu {
 315                 compatible = "arm,armv8-pmuv3";
 316                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 317         };
 318
 319         psci {
 320                 compatible = "arm,psci-1.0";
 321                 method = "smc";
 322
 323                 CPU_PD0: power-domain-cpu0 {
 324                         #power-domain-cells = <0>;
 325                         power-domains = <&CLUSTER_PD>;
 326                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 327                 };
 328
 329                 CPU_PD1: power-domain-cpu1 {
 330                         #power-domain-cells = <0>;
 331                         power-domains = <&CLUSTER_PD>;
 332                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 333                 };
 334
 335                 CPU_PD2: power-domain-cpu2 {
 336                         #power-domain-cells = <0>;
 337                         power-domains = <&CLUSTER_PD>;
 338                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 339                 };
 340
 341                 CPU_PD3: power-domain-cpu3 {
 342                         #power-domain-cells = <0>;
 343                         power-domains = <&CLUSTER_PD>;
 344                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 345                 };
 346
 347                 CPU_PD4: power-domain-cpu4 {
 348                         #power-domain-cells = <0>;
 349                         power-domains = <&CLUSTER_PD>;
 350                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 351                 };
 352
 353                 CPU_PD5: power-domain-cpu5 {
 354                         #power-domain-cells = <0>;
 355                         power-domains = <&CLUSTER_PD>;
 356                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 357                 };
 358
 359                 CPU_PD6: power-domain-cpu6 {
 360                         #power-domain-cells = <0>;
 361                         power-domains = <&CLUSTER_PD>;
 362                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 363                 };
 364
 365                 CPU_PD7: power-domain-cpu7 {
 366                         #power-domain-cells = <0>;
 367                         power-domains = <&CLUSTER_PD>;
 368                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 369                 };
 370
 371                 CLUSTER_PD: power-domain-cpu-cluster0 {
 372                         #power-domain-cells = <0>;
 373                         domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
 374                 };
 375         };
 376
 377         qup_opp_table_100mhz: opp-table-qup {
 378                 compatible = "operating-points-v2";
 379
 380                 opp-50000000 {
 381                         opp-hz = /bits/ 64 <50000000>;
 382                         required-opps = <&rpmhpd_opp_min_svs>;
 383                 };
 384
 385                 opp-75000000 {
 386                         opp-hz = /bits/ 64 <75000000>;
 387                         required-opps = <&rpmhpd_opp_low_svs>;
 388                 };
 389
 390                 opp-100000000 {
 391                         opp-hz = /bits/ 64 <100000000>;
 392                         required-opps = <&rpmhpd_opp_svs>;
 393                 };
 394         };
 395
 396         reserved_memory: reserved-memory {
 397                 #address-cells = <2>;
 398                 #size-cells = <2>;
 399                 ranges;
 400
 401                 hyp_mem: memory@80000000 {
 402                         reg = <0x0 0x80000000 0x0 0x600000>;
 403                         no-map;
 404                 };
 405
 406                 xbl_dt_log_mem: memory@80600000 {
 407                         reg = <0x0 0x80600000 0x0 0x40000>;
 408                         no-map;
 409                 };
 410
 411                 xbl_ramdump_mem: memory@80640000 {
 412                         reg = <0x0 0x80640000 0x0 0x180000>;
 413                         no-map;
 414                 };
 415
 416                 xbl_sc_mem: memory@807c0000 {
 417                         reg = <0x0 0x807c0000 0x0 0x40000>;
 418                         no-map;
 419                 };
 420
 421                 aop_image_mem: memory@80800000 {
 422                         reg = <0x0 0x80800000 0x0 0x60000>;
 423                         no-map;
 424                 };
 425
 426                 aop_cmd_db_mem: memory@80860000 {
 427                         compatible = "qcom,cmd-db";
 428                         reg = <0x0 0x80860000 0x0 0x20000>;
 429                         no-map;
 430                 };
 431
 432                 aop_config_mem: memory@80880000 {
 433                         reg = <0x0 0x80880000 0x0 0x20000>;
 434                         no-map;
 435                 };
 436
 437                 tme_crash_dump_mem: memory@808a0000 {
 438                         reg = <0x0 0x808a0000 0x0 0x40000>;
 439                         no-map;
 440                 };
 441
 442                 tme_log_mem: memory@808e0000 {
 443                         reg = <0x0 0x808e0000 0x0 0x4000>;
 444                         no-map;
 445                 };
 446
 447                 uefi_log_mem: memory@808e4000 {
 448                         reg = <0x0 0x808e4000 0x0 0x10000>;
 449                         no-map;
 450                 };
 451
 452                 /* secdata region can be reused by apps */
 453                 smem: memory@80900000 {
 454                         compatible = "qcom,smem";
 455                         reg = <0x0 0x80900000 0x0 0x200000>;
 456                         hwlocks = <&tcsr_mutex 3>;
 457                         no-map;
 458                 };
 459
 460                 cpucp_fw_mem: memory@80b00000 {
 461                         reg = <0x0 0x80b00000 0x0 0x100000>;
 462                         no-map;
 463                 };
 464
 465                 cdsp_secure_heap: memory@80c00000 {
 466                         reg = <0x0 0x80c00000 0x0 0x4600000>;
 467                         no-map;
 468                 };
 469
 470                 video_mem: memory@85700000 {
 471                         reg = <0x0 0x85700000 0x0 0x700000>;
 472                         no-map;
 473                 };
 474
 475                 adsp_mem: memory@85e00000 {
 476                         reg = <0x0 0x85e00000 0x0 0x2100000>;
 477                         no-map;
 478                 };
 479
 480                 slpi_mem: memory@88000000 {
 481                         reg = <0x0 0x88000000 0x0 0x1900000>;
 482                         no-map;
 483                 };
 484
 485                 cdsp_mem: memory@89900000 {
 486                         reg = <0x0 0x89900000 0x0 0x2000000>;
 487                         no-map;
 488                 };
 489
 490                 ipa_fw_mem: memory@8b900000 {
 491                         reg = <0x0 0x8b900000 0x0 0x10000>;
 492                         no-map;
 493                 };
 494
 495                 ipa_gsi_mem: memory@8b910000 {
 496                         reg = <0x0 0x8b910000 0x0 0xa000>;
 497                         no-map;
 498                 };
 499
 500                 gpu_micro_code_mem: memory@8b91a000 {
 501                         reg = <0x0 0x8b91a000 0x0 0x2000>;
 502                         no-map;
 503                 };
 504
 505                 spss_region_mem: memory@8ba00000 {
 506                         reg = <0x0 0x8ba00000 0x0 0x180000>;
 507                         no-map;
 508                 };
 509
 510                 /* First part of the "SPU secure shared memory" region */
 511                 spu_tz_shared_mem: memory@8bb80000 {
 512                         reg = <0x0 0x8bb80000 0x0 0x60000>;
 513                         no-map;
 514                 };
 515
 516                 /* Second part of the "SPU secure shared memory" region */
 517                 spu_modem_shared_mem: memory@8bbe0000 {
 518                         reg = <0x0 0x8bbe0000 0x0 0x20000>;
 519                         no-map;
 520                 };
 521
 522                 mpss_mem: memory@8bc00000 {
 523                         reg = <0x0 0x8bc00000 0x0 0x13200000>;
 524                         no-map;
 525                 };
 526
 527                 cvp_mem: memory@9ee00000 {
 528                         reg = <0x0 0x9ee00000 0x0 0x700000>;
 529                         no-map;
 530                 };
 531
 532                 camera_mem: memory@9f500000 {
 533                         reg = <0x0 0x9f500000 0x0 0x800000>;
 534                         no-map;
 535                 };
 536
 537                 rmtfs_mem: memory@9fd00000 {
 538                         compatible = "qcom,rmtfs-mem";
 539                         reg = <0x0 0x9fd00000 0x0 0x280000>;
 540                         no-map;
 541
 542                         qcom,client-id = <1>;
 543                         qcom,vmid = <15>;
 544                 };
 545
 546                 xbl_sc_mem2: memory@a6e00000 {
 547                         reg = <0x0 0xa6e00000 0x0 0x40000>;
 548                         no-map;
 549                 };
 550
 551                 global_sync_mem: memory@a6f00000 {
 552                         reg = <0x0 0xa6f00000 0x0 0x100000>;
 553                         no-map;
 554                 };
 555
 556                 /* uefi region can be reused by APPS */
 557
 558                 /* Linux kernel image is loaded at 0xa0000000 */
 559
 560                 oem_vm_mem: memory@bb000000 {
 561                         reg = <0x0 0xbb000000 0x0 0x5000000>;
 562                         no-map;
 563                 };
 564
 565                 mte_mem: memory@c0000000 {
 566                         reg = <0x0 0xc0000000 0x0 0x20000000>;
 567                         no-map;
 568                 };
 569
 570                 qheebsp_reserved_mem: memory@e0000000 {
 571                         reg = <0x0 0xe0000000 0x0 0x600000>;
 572                         no-map;
 573                 };
 574
 575                 cpusys_vm_mem: memory@e0600000 {
 576                         reg = <0x0 0xe0600000 0x0 0x400000>;
 577                         no-map;
 578                 };
 579
 580                 hyp_reserved_mem: memory@e0a00000 {
 581                         reg = <0x0 0xe0a00000 0x0 0x100000>;
 582                         no-map;
 583                 };
 584
 585                 trust_ui_vm_mem: memory@e0b00000 {
 586                         reg = <0x0 0xe0b00000 0x0 0x4af3000>;
 587                         no-map;
 588                 };
 589
 590                 trust_ui_vm_qrtr: memory@e55f3000 {
 591                         reg = <0x0 0xe55f3000 0x0 0x9000>;
 592                         no-map;
 593                 };
 594
 595                 trust_ui_vm_vblk0_ring: memory@e55fc000 {
 596                         reg = <0x0 0xe55fc000 0x0 0x4000>;
 597                         no-map;
 598                 };
 599
 600                 trust_ui_vm_swiotlb: memory@e5600000 {
 601                         reg = <0x0 0xe5600000 0x0 0x100000>;
 602                         no-map;
 603                 };
 604
 605                 tz_stat_mem: memory@e8800000 {
 606                         reg = <0x0 0xe8800000 0x0 0x100000>;
 607                         no-map;
 608                 };
 609
 610                 tags_mem: memory@e8900000 {
 611                         reg = <0x0 0xe8900000 0x0 0x1200000>;
 612                         no-map;
 613                 };
 614
 615                 qtee_mem: memory@e9b00000 {
 616                         reg = <0x0 0xe9b00000 0x0 0x500000>;
 617                         no-map;
 618                 };
 619
 620                 trusted_apps_mem: memory@ea000000 {
 621                         reg = <0x0 0xea000000 0x0 0x3900000>;
 622                         no-map;
 623                 };
 624
 625                 trusted_apps_ext_mem: memory@ed900000 {
 626                         reg = <0x0 0xed900000 0x0 0x3b00000>;
 627                         no-map;
 628                 };
 629         };
 630
 631         smp2p-adsp {
 632                 compatible = "qcom,smp2p";
 633                 qcom,smem = <443>, <429>;
 634                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 635                                              IPCC_MPROC_SIGNAL_SMP2P
 636                                              IRQ_TYPE_EDGE_RISING>;
 637                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 638                                 IPCC_MPROC_SIGNAL_SMP2P>;
 639
 640                 qcom,local-pid = <0>;
 641                 qcom,remote-pid = <2>;
 642
 643                 smp2p_adsp_out: master-kernel {
 644                         qcom,entry-name = "master-kernel";
 645                         #qcom,smem-state-cells = <1>;
 646                 };
 647
 648                 smp2p_adsp_in: slave-kernel {
 649                         qcom,entry-name = "slave-kernel";
 650                         interrupt-controller;
 651                         #interrupt-cells = <2>;
 652                 };
 653         };
 654
 655         smp2p-cdsp {
 656                 compatible = "qcom,smp2p";
 657                 qcom,smem = <94>, <432>;
 658                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 659                                              IPCC_MPROC_SIGNAL_SMP2P
 660                                              IRQ_TYPE_EDGE_RISING>;
 661                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 662                                 IPCC_MPROC_SIGNAL_SMP2P>;
 663
 664                 qcom,local-pid = <0>;
 665                 qcom,remote-pid = <5>;
 666
 667                 smp2p_cdsp_out: master-kernel {
 668                         qcom,entry-name = "master-kernel";
 669                         #qcom,smem-state-cells = <1>;
 670                 };
 671
 672                 smp2p_cdsp_in: slave-kernel {
 673                         qcom,entry-name = "slave-kernel";
 674                         interrupt-controller;
 675                         #interrupt-cells = <2>;
 676                 };
 677         };
 678
 679         smp2p-modem {
 680                 compatible = "qcom,smp2p";
 681                 qcom,smem = <435>, <428>;
 682                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 683                                              IPCC_MPROC_SIGNAL_SMP2P
 684                                              IRQ_TYPE_EDGE_RISING>;
 685                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 686                                 IPCC_MPROC_SIGNAL_SMP2P>;
 687
 688                 qcom,local-pid = <0>;
 689                 qcom,remote-pid = <1>;
 690
 691                 smp2p_modem_out: master-kernel {
 692                         qcom,entry-name = "master-kernel";
 693                         #qcom,smem-state-cells = <1>;
 694                 };
 695
 696                 smp2p_modem_in: slave-kernel {
 697                         qcom,entry-name = "slave-kernel";
 698                         interrupt-controller;
 699                         #interrupt-cells = <2>;
 700                 };
 701
 702                 ipa_smp2p_out: ipa-ap-to-modem {
 703                         qcom,entry-name = "ipa";
 704                         #qcom,smem-state-cells = <1>;
 705                 };
 706
 707                 ipa_smp2p_in: ipa-modem-to-ap {
 708                         qcom,entry-name = "ipa";
 709                         interrupt-controller;
 710                         #interrupt-cells = <2>;
 711                 };
 712         };
 713
 714         smp2p-slpi {
 715                 compatible = "qcom,smp2p";
 716                 qcom,smem = <481>, <430>;
 717                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 718                                              IPCC_MPROC_SIGNAL_SMP2P
 719                                              IRQ_TYPE_EDGE_RISING>;
 720                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 721                                 IPCC_MPROC_SIGNAL_SMP2P>;
 722
 723                 qcom,local-pid = <0>;
 724                 qcom,remote-pid = <3>;
 725
 726                 smp2p_slpi_out: master-kernel {
 727                         qcom,entry-name = "master-kernel";
 728                         #qcom,smem-state-cells = <1>;
 729                 };
 730
 731                 smp2p_slpi_in: slave-kernel {
 732                         qcom,entry-name = "slave-kernel";
 733                         interrupt-controller;
 734                         #interrupt-cells = <2>;
 735                 };
 736         };
 737
 738         soc: soc@0 {
 739                 #address-cells = <2>;
 740                 #size-cells = <2>;
 741                 ranges = <0 0 0 0 0x10 0>;
 742                 dma-ranges = <0 0 0 0 0x10 0>;
 743                 compatible = "simple-bus";
 744
 745                 gcc: clock-controller@100000 {
 746                         compatible = "qcom,gcc-sm8450";
 747                         reg = <0x0 0x00100000 0x0 0x1f4200>;
 748                         #clock-cells = <1>;
 749                         #reset-cells = <1>;
 750                         #power-domain-cells = <1>;
 751                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 752                                  <&sleep_clk>,
 753                                  <&pcie0_lane>,
 754                                  <&pcie1_lane>,
 755                                  <0>,
 756                                  <&ufs_mem_phy_lanes 0>,
 757                                  <&ufs_mem_phy_lanes 1>,
 758                                  <&ufs_mem_phy_lanes 2>,
 759                                  <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 760                         clock-names = "bi_tcxo",
 761                                       "sleep_clk",
 762                                       "pcie_0_pipe_clk",
 763                                       "pcie_1_pipe_clk",
 764                                       "pcie_1_phy_aux_clk",
 765                                       "ufs_phy_rx_symbol_0_clk",
 766                                       "ufs_phy_rx_symbol_1_clk",
 767                                       "ufs_phy_tx_symbol_0_clk",
 768                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 769                 };
 770
 771                 gpi_dma2: dma-controller@800000 {
 772                         compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
 773                         #dma-cells = <3>;
 774                         reg = <0 0x00800000 0 0x60000>;
 775                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 776                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 777                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 778                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 779                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 780                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 781                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 782                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 783                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 784                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 785                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 786                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 787                         dma-channels = <12>;
 788                         dma-channel-mask = <0x7e>;
 789                         iommus = <&apps_smmu 0x496 0x0>;
 790                         status = "disabled";
 791                 };
 792
 793                 qupv3_id_2: geniqup@8c0000 {
 794                         compatible = "qcom,geni-se-qup";
 795                         reg = <0x0 0x008c0000 0x0 0x2000>;
 796                         clock-names = "m-ahb", "s-ahb";
 797                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 798                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 799                         iommus = <&apps_smmu 0x483 0x0>;
 800                         #address-cells = <2>;
 801                         #size-cells = <2>;
 802                         ranges;
 803                         status = "disabled";
 804
 805                         i2c15: i2c@880000 {
 806                                 compatible = "qcom,geni-i2c";
 807                                 reg = <0x0 0x00880000 0x0 0x4000>;
 808                                 clock-names = "se";
 809                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 810                                 pinctrl-names = "default";
 811                                 pinctrl-0 = <&qup_i2c15_data_clk>;
 812                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 813                                 #address-cells = <1>;
 814                                 #size-cells = <0>;
 815                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 816                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 817                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 818                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 819                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 820                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 821                                 dma-names = "tx", "rx";
 822                                 status = "disabled";
 823                         };
 824
 825                         spi15: spi@880000 {
 826                                 compatible = "qcom,geni-spi";
 827                                 reg = <0x0 0x00880000 0x0 0x4000>;
 828                                 clock-names = "se";
 829                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 830                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 831                                 pinctrl-names = "default";
 832                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
 833                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 834                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 835                                 interconnect-names = "qup-core", "qup-config";
 836                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 837                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 838                                 dma-names = "tx", "rx";
 839                                 #address-cells = <1>;
 840                                 #size-cells = <0>;
 841                                 status = "disabled";
 842                         };
 843
 844                         i2c16: i2c@884000 {
 845                                 compatible = "qcom,geni-i2c";
 846                                 reg = <0x0 0x00884000 0x0 0x4000>;
 847                                 clock-names = "se";
 848                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 849                                 pinctrl-names = "default";
 850                                 pinctrl-0 = <&qup_i2c16_data_clk>;
 851                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 852                                 #address-cells = <1>;
 853                                 #size-cells = <0>;
 854                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 855                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 856                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 857                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 858                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 859                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 860                                 dma-names = "tx", "rx";
 861                                 status = "disabled";
 862                         };
 863
 864                         spi16: spi@884000 {
 865                                 compatible = "qcom,geni-spi";
 866                                 reg = <0x0 0x00884000 0x0 0x4000>;
 867                                 clock-names = "se";
 868                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 869                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 870                                 pinctrl-names = "default";
 871                                 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
 872                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 873                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 874                                 interconnect-names = "qup-core", "qup-config";
 875                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 876                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 877                                 dma-names = "tx", "rx";
 878                                 #address-cells = <1>;
 879                                 #size-cells = <0>;
 880                                 status = "disabled";
 881                         };
 882
 883                         i2c17: i2c@888000 {
 884                                 compatible = "qcom,geni-i2c";
 885                                 reg = <0x0 0x00888000 0x0 0x4000>;
 886                                 clock-names = "se";
 887                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 888                                 pinctrl-names = "default";
 889                                 pinctrl-0 = <&qup_i2c17_data_clk>;
 890                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 891                                 #address-cells = <1>;
 892                                 #size-cells = <0>;
 893                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 894                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 895                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 896                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 897                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 898                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 899                                 dma-names = "tx", "rx";
 900                                 status = "disabled";
 901                         };
 902
 903                         spi17: spi@888000 {
 904                                 compatible = "qcom,geni-spi";
 905                                 reg = <0x0 0x00888000 0x0 0x4000>;
 906                                 clock-names = "se";
 907                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 908                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 909                                 pinctrl-names = "default";
 910                                 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
 911                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 912                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 913                                 interconnect-names = "qup-core", "qup-config";
 914                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 915                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 916                                 dma-names = "tx", "rx";
 917                                 #address-cells = <1>;
 918                                 #size-cells = <0>;
 919                                 status = "disabled";
 920                         };
 921
 922                         i2c18: i2c@88c000 {
 923                                 compatible = "qcom,geni-i2c";
 924                                 reg = <0x0 0x0088c000 0x0 0x4000>;
 925                                 clock-names = "se";
 926                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 927                                 pinctrl-names = "default";
 928                                 pinctrl-0 = <&qup_i2c18_data_clk>;
 929                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 930                                 #address-cells = <1>;
 931                                 #size-cells = <0>;
 932                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 933                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 934                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 935                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 936                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 937                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 938                                 dma-names = "tx", "rx";
 939                                 status = "disabled";
 940                         };
 941
 942                         spi18: spi@88c000 {
 943                                 compatible = "qcom,geni-spi";
 944                                 reg = <0 0x0088c000 0 0x4000>;
 945                                 clock-names = "se";
 946                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 947                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 948                                 pinctrl-names = "default";
 949                                 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
 950                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 951                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 952                                 interconnect-names = "qup-core", "qup-config";
 953                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 954                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 955                                 dma-names = "tx", "rx";
 956                                 #address-cells = <1>;
 957                                 #size-cells = <0>;
 958                                 status = "disabled";
 959                         };
 960
 961                         i2c19: i2c@890000 {
 962                                 compatible = "qcom,geni-i2c";
 963                                 reg = <0x0 0x00890000 0x0 0x4000>;
 964                                 clock-names = "se";
 965                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 966                                 pinctrl-names = "default";
 967                                 pinctrl-0 = <&qup_i2c19_data_clk>;
 968                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 969                                 #address-cells = <1>;
 970                                 #size-cells = <0>;
 971                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 972                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 973                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 974                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 975                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 976                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 977                                 dma-names = "tx", "rx";
 978                                 status = "disabled";
 979                         };
 980
 981                         spi19: spi@890000 {
 982                                 compatible = "qcom,geni-spi";
 983                                 reg = <0 0x00890000 0 0x4000>;
 984                                 clock-names = "se";
 985                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 986                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 987                                 pinctrl-names = "default";
 988                                 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
 989                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 990                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 991                                 interconnect-names = "qup-core", "qup-config";
 992                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 993                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 994                                 dma-names = "tx", "rx";
 995                                 #address-cells = <1>;
 996                                 #size-cells = <0>;
 997                                 status = "disabled";
 998                         };
 999
1000                         i2c20: i2c@894000 {
1001                                 compatible = "qcom,geni-i2c";
1002                                 reg = <0x0 0x00894000 0x0 0x4000>;
1003                                 clock-names = "se";
1004                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1005                                 pinctrl-names = "default";
1006                                 pinctrl-0 = <&qup_i2c20_data_clk>;
1007                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1008                                 #address-cells = <1>;
1009                                 #size-cells = <0>;
1010                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1011                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1012                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1013                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1014                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1015                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1016                                 dma-names = "tx", "rx";
1017                                 status = "disabled";
1018                         };
1019
1020                         uart20: serial@894000 {
1021                                 compatible = "qcom,geni-uart";
1022                                 reg = <0 0x00894000 0 0x4000>;
1023                                 clock-names = "se";
1024                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1025                                 pinctrl-names = "default";
1026                                 pinctrl-0 = <&qup_uart20_default>;
1027                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1028                                 status = "disabled";
1029                         };
1030
1031                         spi20: spi@894000 {
1032                                 compatible = "qcom,geni-spi";
1033                                 reg = <0 0x00894000 0 0x4000>;
1034                                 clock-names = "se";
1035                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1036                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1037                                 pinctrl-names = "default";
1038                                 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1039                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1040                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1041                                 interconnect-names = "qup-core", "qup-config";
1042                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1043                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1044                                 dma-names = "tx", "rx";
1045                                 #address-cells = <1>;
1046                                 #size-cells = <0>;
1047                                 status = "disabled";
1048                         };
1049
1050                         i2c21: i2c@898000 {
1051                                 compatible = "qcom,geni-i2c";
1052                                 reg = <0x0 0x00898000 0x0 0x4000>;
1053                                 clock-names = "se";
1054                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1055                                 pinctrl-names = "default";
1056                                 pinctrl-0 = <&qup_i2c21_data_clk>;
1057                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1058                                 #address-cells = <1>;
1059                                 #size-cells = <0>;
1060                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1061                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1062                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1063                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1064                                 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1065                                        <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1066                                 dma-names = "tx", "rx";
1067                                 status = "disabled";
1068                         };
1069
1070                         spi21: spi@898000 {
1071                                 compatible = "qcom,geni-spi";
1072                                 reg = <0 0x00898000 0 0x4000>;
1073                                 clock-names = "se";
1074                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1075                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1076                                 pinctrl-names = "default";
1077                                 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1078                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1079                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1080                                 interconnect-names = "qup-core", "qup-config";
1081                                 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1082                                        <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1083                                 dma-names = "tx", "rx";
1084                                 #address-cells = <1>;
1085                                 #size-cells = <0>;
1086                                 status = "disabled";
1087                         };
1088                 };
1089
1090                 gpi_dma0: dma-controller@900000 {
1091                         compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1092                         #dma-cells = <3>;
1093                         reg = <0 0x00900000 0 0x60000>;
1094                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1095                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1096                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1097                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1098                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1099                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1100                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1101                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1102                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1103                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1104                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1105                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1106                         dma-channels = <12>;
1107                         dma-channel-mask = <0x7e>;
1108                         iommus = <&apps_smmu 0x5b6 0x0>;
1109                         status = "disabled";
1110                 };
1111
1112                 qupv3_id_0: geniqup@9c0000 {
1113                         compatible = "qcom,geni-se-qup";
1114                         reg = <0x0 0x009c0000 0x0 0x2000>;
1115                         clock-names = "m-ahb", "s-ahb";
1116                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1117                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1118                         iommus = <&apps_smmu 0x5a3 0x0>;
1119                         interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1120                         interconnect-names = "qup-core";
1121                         #address-cells = <2>;
1122                         #size-cells = <2>;
1123                         ranges;
1124                         status = "disabled";
1125
1126                         i2c0: i2c@980000 {
1127                                 compatible = "qcom,geni-i2c";
1128                                 reg = <0x0 0x00980000 0x0 0x4000>;
1129                                 clock-names = "se";
1130                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1131                                 pinctrl-names = "default";
1132                                 pinctrl-0 = <&qup_i2c0_data_clk>;
1133                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1134                                 #address-cells = <1>;
1135                                 #size-cells = <0>;
1136                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1137                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1138                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1139                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1140                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1141                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1142                                 dma-names = "tx", "rx";
1143                                 status = "disabled";
1144                         };
1145
1146                         spi0: spi@980000 {
1147                                 compatible = "qcom,geni-spi";
1148                                 reg = <0x0 0x00980000 0x0 0x4000>;
1149                                 clock-names = "se";
1150                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1151                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1152                                 pinctrl-names = "default";
1153                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1154                                 power-domains = <&rpmhpd RPMHPD_CX>;
1155                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1156                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1157                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1158                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1159                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1160                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1161                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1162                                 dma-names = "tx", "rx";
1163                                 #address-cells = <1>;
1164                                 #size-cells = <0>;
1165                                 status = "disabled";
1166                         };
1167
1168                         i2c1: i2c@984000 {
1169                                 compatible = "qcom,geni-i2c";
1170                                 reg = <0x0 0x00984000 0x0 0x4000>;
1171                                 clock-names = "se";
1172                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1173                                 pinctrl-names = "default";
1174                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1175                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1176                                 #address-cells = <1>;
1177                                 #size-cells = <0>;
1178                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1179                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1180                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1181                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1182                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1183                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1184                                 dma-names = "tx", "rx";
1185                                 status = "disabled";
1186                         };
1187
1188                         spi1: spi@984000 {
1189                                 compatible = "qcom,geni-spi";
1190                                 reg = <0x0 0x00984000 0x0 0x4000>;
1191                                 clock-names = "se";
1192                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1193                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1194                                 pinctrl-names = "default";
1195                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1196                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1197                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1198                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1199                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1200                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1201                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1202                                 dma-names = "tx", "rx";
1203                                 #address-cells = <1>;
1204                                 #size-cells = <0>;
1205                                 status = "disabled";
1206                         };
1207
1208                         i2c2: i2c@988000 {
1209                                 compatible = "qcom,geni-i2c";
1210                                 reg = <0x0 0x00988000 0x0 0x4000>;
1211                                 clock-names = "se";
1212                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1213                                 pinctrl-names = "default";
1214                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1215                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1216                                 #address-cells = <1>;
1217                                 #size-cells = <0>;
1218                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1219                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1220                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1221                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1222                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1223                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1224                                 dma-names = "tx", "rx";
1225                                 status = "disabled";
1226                         };
1227
1228                         spi2: spi@988000 {
1229                                 compatible = "qcom,geni-spi";
1230                                 reg = <0x0 0x00988000 0x0 0x4000>;
1231                                 clock-names = "se";
1232                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1233                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1234                                 pinctrl-names = "default";
1235                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1236                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1237                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1238                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1239                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1240                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1241                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1242                                 dma-names = "tx", "rx";
1243                                 #address-cells = <1>;
1244                                 #size-cells = <0>;
1245                                 status = "disabled";
1246                         };
1247
1248
1249                         i2c3: i2c@98c000 {
1250                                 compatible = "qcom,geni-i2c";
1251                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1252                                 clock-names = "se";
1253                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1254                                 pinctrl-names = "default";
1255                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1256                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1257                                 #address-cells = <1>;
1258                                 #size-cells = <0>;
1259                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1260                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1261                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1262                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1263                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1264                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1265                                 dma-names = "tx", "rx";
1266                                 status = "disabled";
1267                         };
1268
1269                         spi3: spi@98c000 {
1270                                 compatible = "qcom,geni-spi";
1271                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1272                                 clock-names = "se";
1273                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1274                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1275                                 pinctrl-names = "default";
1276                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1277                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1278                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1279                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1280                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1281                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1282                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1283                                 dma-names = "tx", "rx";
1284                                 #address-cells = <1>;
1285                                 #size-cells = <0>;
1286                                 status = "disabled";
1287                         };
1288
1289                         i2c4: i2c@990000 {
1290                                 compatible = "qcom,geni-i2c";
1291                                 reg = <0x0 0x00990000 0x0 0x4000>;
1292                                 clock-names = "se";
1293                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1294                                 pinctrl-names = "default";
1295                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1296                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1297                                 #address-cells = <1>;
1298                                 #size-cells = <0>;
1299                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1300                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1301                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1302                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1303                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1304                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1305                                 dma-names = "tx", "rx";
1306                                 status = "disabled";
1307                         };
1308
1309                         spi4: spi@990000 {
1310                                 compatible = "qcom,geni-spi";
1311                                 reg = <0x0 0x00990000 0x0 0x4000>;
1312                                 clock-names = "se";
1313                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1314                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1315                                 pinctrl-names = "default";
1316                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1317                                 power-domains = <&rpmhpd RPMHPD_CX>;
1318                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1319                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1320                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1321                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1322                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1323                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1324                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1325                                 dma-names = "tx", "rx";
1326                                 #address-cells = <1>;
1327                                 #size-cells = <0>;
1328                                 status = "disabled";
1329                         };
1330
1331                         i2c5: i2c@994000 {
1332                                 compatible = "qcom,geni-i2c";
1333                                 reg = <0x0 0x00994000 0x0 0x4000>;
1334                                 clock-names = "se";
1335                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1336                                 pinctrl-names = "default";
1337                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1338                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1339                                 #address-cells = <1>;
1340                                 #size-cells = <0>;
1341                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1342                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1343                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1344                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1345                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1346                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1347                                 dma-names = "tx", "rx";
1348                                 status = "disabled";
1349                         };
1350
1351                         spi5: spi@994000 {
1352                                 compatible = "qcom,geni-spi";
1353                                 reg = <0x0 0x00994000 0x0 0x4000>;
1354                                 clock-names = "se";
1355                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1356                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1357                                 pinctrl-names = "default";
1358                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1359                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1360                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1361                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1362                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1363                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1364                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1365                                 dma-names = "tx", "rx";
1366                                 #address-cells = <1>;
1367                                 #size-cells = <0>;
1368                                 status = "disabled";
1369                         };
1370
1371
1372                         i2c6: i2c@998000 {
1373                                 compatible = "qcom,geni-i2c";
1374                                 reg = <0x0 0x00998000 0x0 0x4000>;
1375                                 clock-names = "se";
1376                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1377                                 pinctrl-names = "default";
1378                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1379                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1380                                 #address-cells = <1>;
1381                                 #size-cells = <0>;
1382                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1383                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1384                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1385                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1386                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1387                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1388                                 dma-names = "tx", "rx";
1389                                 status = "disabled";
1390                         };
1391
1392                         spi6: spi@998000 {
1393                                 compatible = "qcom,geni-spi";
1394                                 reg = <0x0 0x00998000 0x0 0x4000>;
1395                                 clock-names = "se";
1396                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1397                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1398                                 pinctrl-names = "default";
1399                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1400                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1401                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1402                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1403                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1404                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1405                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1406                                 dma-names = "tx", "rx";
1407                                 #address-cells = <1>;
1408                                 #size-cells = <0>;
1409                                 status = "disabled";
1410                         };
1411
1412                         uart7: serial@99c000 {
1413                                 compatible = "qcom,geni-debug-uart";
1414                                 reg = <0 0x0099c000 0 0x4000>;
1415                                 clock-names = "se";
1416                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1417                                 pinctrl-names = "default";
1418                                 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1419                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1420                                 status = "disabled";
1421                         };
1422                 };
1423
1424                 gpi_dma1: dma-controller@a00000 {
1425                         compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1426                         #dma-cells = <3>;
1427                         reg = <0 0x00a00000 0 0x60000>;
1428                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1429                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1430                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1431                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1432                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1433                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1434                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1435                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1436                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1437                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1438                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1439                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1440                         dma-channels = <12>;
1441                         dma-channel-mask = <0x7e>;
1442                         iommus = <&apps_smmu 0x56 0x0>;
1443                         status = "disabled";
1444                 };
1445
1446                 qupv3_id_1: geniqup@ac0000 {
1447                         compatible = "qcom,geni-se-qup";
1448                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1449                         clock-names = "m-ahb", "s-ahb";
1450                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1451                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1452                         iommus = <&apps_smmu 0x43 0x0>;
1453                         interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1454                         interconnect-names = "qup-core";
1455                         #address-cells = <2>;
1456                         #size-cells = <2>;
1457                         ranges;
1458                         status = "disabled";
1459
1460                         i2c8: i2c@a80000 {
1461                                 compatible = "qcom,geni-i2c";
1462                                 reg = <0x0 0x00a80000 0x0 0x4000>;
1463                                 clock-names = "se";
1464                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1465                                 pinctrl-names = "default";
1466                                 pinctrl-0 = <&qup_i2c8_data_clk>;
1467                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1468                                 #address-cells = <1>;
1469                                 #size-cells = <0>;
1470                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1471                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1472                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1473                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1474                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1475                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1476                                 dma-names = "tx", "rx";
1477                                 status = "disabled";
1478                         };
1479
1480                         spi8: spi@a80000 {
1481                                 compatible = "qcom,geni-spi";
1482                                 reg = <0x0 0x00a80000 0x0 0x4000>;
1483                                 clock-names = "se";
1484                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1485                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1486                                 pinctrl-names = "default";
1487                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1488                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1489                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1490                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1491                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1492                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1493                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1494                                 dma-names = "tx", "rx";
1495                                 #address-cells = <1>;
1496                                 #size-cells = <0>;
1497                                 status = "disabled";
1498                         };
1499
1500                         i2c9: i2c@a84000 {
1501                                 compatible = "qcom,geni-i2c";
1502                                 reg = <0x0 0x00a84000 0x0 0x4000>;
1503                                 clock-names = "se";
1504                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1505                                 pinctrl-names = "default";
1506                                 pinctrl-0 = <&qup_i2c9_data_clk>;
1507                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1508                                 #address-cells = <1>;
1509                                 #size-cells = <0>;
1510                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1511                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1512                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1513                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1514                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1515                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1516                                 dma-names = "tx", "rx";
1517                                 status = "disabled";
1518                         };
1519
1520                         spi9: spi@a84000 {
1521                                 compatible = "qcom,geni-spi";
1522                                 reg = <0x0 0x00a84000 0x0 0x4000>;
1523                                 clock-names = "se";
1524                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1525                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1526                                 pinctrl-names = "default";
1527                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1528                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1529                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1530                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1531                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1532                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1533                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1534                                 dma-names = "tx", "rx";
1535                                 #address-cells = <1>;
1536                                 #size-cells = <0>;
1537                                 status = "disabled";
1538                         };
1539
1540                         i2c10: i2c@a88000 {
1541                                 compatible = "qcom,geni-i2c";
1542                                 reg = <0x0 0x00a88000 0x0 0x4000>;
1543                                 clock-names = "se";
1544                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1545                                 pinctrl-names = "default";
1546                                 pinctrl-0 = <&qup_i2c10_data_clk>;
1547                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1548                                 #address-cells = <1>;
1549                                 #size-cells = <0>;
1550                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1551                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1552                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1553                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1554                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1555                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1556                                 dma-names = "tx", "rx";
1557                                 status = "disabled";
1558                         };
1559
1560                         spi10: spi@a88000 {
1561                                 compatible = "qcom,geni-spi";
1562                                 reg = <0x0 0x00a88000 0x0 0x4000>;
1563                                 clock-names = "se";
1564                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1565                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1566                                 pinctrl-names = "default";
1567                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1568                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1569                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1570                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1571                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1572                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1573                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1574                                 dma-names = "tx", "rx";
1575                                 #address-cells = <1>;
1576                                 #size-cells = <0>;
1577                                 status = "disabled";
1578                         };
1579
1580                         i2c11: i2c@a8c000 {
1581                                 compatible = "qcom,geni-i2c";
1582                                 reg = <0x0 0x00a8c000 0x0 0x4000>;
1583                                 clock-names = "se";
1584                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1585                                 pinctrl-names = "default";
1586                                 pinctrl-0 = <&qup_i2c11_data_clk>;
1587                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1588                                 #address-cells = <1>;
1589                                 #size-cells = <0>;
1590                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1591                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1592                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1593                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1594                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1595                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1596                                 dma-names = "tx", "rx";
1597                                 status = "disabled";
1598                         };
1599
1600                         spi11: spi@a8c000 {
1601                                 compatible = "qcom,geni-spi";
1602                                 reg = <0x0 0x00a8c000 0x0 0x4000>;
1603                                 clock-names = "se";
1604                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1605                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1606                                 pinctrl-names = "default";
1607                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1608                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1609                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1610                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1611                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1612                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1613                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1614                                 dma-names = "tx", "rx";
1615                                 #address-cells = <1>;
1616                                 #size-cells = <0>;
1617                                 status = "disabled";
1618                         };
1619
1620                         i2c12: i2c@a90000 {
1621                                 compatible = "qcom,geni-i2c";
1622                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1623                                 clock-names = "se";
1624                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1625                                 pinctrl-names = "default";
1626                                 pinctrl-0 = <&qup_i2c12_data_clk>;
1627                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1628                                 #address-cells = <1>;
1629                                 #size-cells = <0>;
1630                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1631                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1632                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1633                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1635                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1636                                 dma-names = "tx", "rx";
1637                                 status = "disabled";
1638                         };
1639
1640                         spi12: spi@a90000 {
1641                                 compatible = "qcom,geni-spi";
1642                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1643                                 clock-names = "se";
1644                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1645                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1646                                 pinctrl-names = "default";
1647                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1648                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1649                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1650                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1651                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1652                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1653                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1654                                 dma-names = "tx", "rx";
1655                                 #address-cells = <1>;
1656                                 #size-cells = <0>;
1657                                 status = "disabled";
1658                         };
1659
1660                         i2c13: i2c@a94000 {
1661                                 compatible = "qcom,geni-i2c";
1662                                 reg = <0 0x00a94000 0 0x4000>;
1663                                 clock-names = "se";
1664                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1665                                 pinctrl-names = "default";
1666                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1667                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1668                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1669                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1670                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1671                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1672                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1673                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1674                                 dma-names = "tx", "rx";
1675                                 #address-cells = <1>;
1676                                 #size-cells = <0>;
1677                                 status = "disabled";
1678                         };
1679
1680                         spi13: spi@a94000 {
1681                                 compatible = "qcom,geni-spi";
1682                                 reg = <0x0 0x00a94000 0x0 0x4000>;
1683                                 clock-names = "se";
1684                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1685                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1686                                 pinctrl-names = "default";
1687                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1688                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1689                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1690                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1691                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1692                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1693                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1694                                 dma-names = "tx", "rx";
1695                                 #address-cells = <1>;
1696                                 #size-cells = <0>;
1697                                 status = "disabled";
1698                         };
1699
1700                         i2c14: i2c@a98000 {
1701                                 compatible = "qcom,geni-i2c";
1702                                 reg = <0 0x00a98000 0 0x4000>;
1703                                 clock-names = "se";
1704                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1705                                 pinctrl-names = "default";
1706                                 pinctrl-0 = <&qup_i2c14_data_clk>;
1707                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1708                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1709                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1710                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1711                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1712                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1713                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1714                                 dma-names = "tx", "rx";
1715                                 #address-cells = <1>;
1716                                 #size-cells = <0>;
1717                                 status = "disabled";
1718                         };
1719
1720                         spi14: spi@a98000 {
1721                                 compatible = "qcom,geni-spi";
1722                                 reg = <0x0 0x00a98000 0x0 0x4000>;
1723                                 clock-names = "se";
1724                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1725                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1726                                 pinctrl-names = "default";
1727                                 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1728                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1729                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1730                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1731                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1732                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1733                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1734                                 dma-names = "tx", "rx";
1735                                 #address-cells = <1>;
1736                                 #size-cells = <0>;
1737                                 status = "disabled";
1738                         };
1739                 };
1740
1741                 rng: rng@10c3000 {
1742                         compatible = "qcom,sm8450-prng-ee", "qcom,prng-ee";
1743                         reg = <0 0x010c3000 0 0x1000>;
1744                 };
1745
1746                 pcie0: pci@1c00000 {
1747                         compatible = "qcom,pcie-sm8450-pcie0";
1748                         reg = <0 0x01c00000 0 0x3000>,
1749                               <0 0x60000000 0 0xf1d>,
1750                               <0 0x60000f20 0 0xa8>,
1751                               <0 0x60001000 0 0x1000>,
1752                               <0 0x60100000 0 0x100000>;
1753                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1754                         device_type = "pci";
1755                         linux,pci-domain = <0>;
1756                         bus-range = <0x00 0xff>;
1757                         num-lanes = <1>;
1758
1759                         #address-cells = <3>;
1760                         #size-cells = <2>;
1761
1762                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1763                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1764
1765                         /*
1766                          * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
1767                          * Hence, the IDs are swapped.
1768                          */
1769                         msi-map = <0x0 &gic_its 0x5981 0x1>,
1770                                   <0x100 &gic_its 0x5980 0x1>;
1771                         msi-map-mask = <0xff00>;
1772                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1773                         interrupt-names = "msi";
1774                         #interrupt-cells = <1>;
1775                         interrupt-map-mask = <0 0 0 0x7>;
1776                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1777                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1778                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1779                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1780
1781                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1782                                  <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1783                                  <&pcie0_lane>,
1784                                  <&rpmhcc RPMH_CXO_CLK>,
1785                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1786                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1787                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1788                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1789                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1790                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1791                                  <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1792                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1793                         clock-names = "pipe",
1794                                       "pipe_mux",
1795                                       "phy_pipe",
1796                                       "ref",
1797                                       "aux",
1798                                       "cfg",
1799                                       "bus_master",
1800                                       "bus_slave",
1801                                       "slave_q2a",
1802                                       "ddrss_sf_tbu",
1803                                       "aggre0",
1804                                       "aggre1";
1805
1806                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1807                                     <0x100 &apps_smmu 0x1c01 0x1>;
1808
1809                         resets = <&gcc GCC_PCIE_0_BCR>;
1810                         reset-names = "pci";
1811
1812                         power-domains = <&gcc PCIE_0_GDSC>;
1813
1814                         phys = <&pcie0_lane>;
1815                         phy-names = "pciephy";
1816
1817                         perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1818                         wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1819
1820                         pinctrl-names = "default";
1821                         pinctrl-0 = <&pcie0_default_state>;
1822
1823                         status = "disabled";
1824                 };
1825
1826                 pcie0_phy: phy@1c06000 {
1827                         compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1828                         reg = <0 0x01c06000 0 0x200>;
1829                         #address-cells = <2>;
1830                         #size-cells = <2>;
1831                         ranges;
1832                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1833                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1834                                  <&gcc GCC_PCIE_0_CLKREF_EN>,
1835                                  <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1836                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1837
1838                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1839                         reset-names = "phy";
1840
1841                         assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1842                         assigned-clock-rates = <100000000>;
1843
1844                         status = "disabled";
1845
1846                         pcie0_lane: phy@1c06200 {
1847                                 reg = <0 0x01c06e00 0 0x200>, /* tx */
1848                                       <0 0x01c07000 0 0x200>, /* rx */
1849                                       <0 0x01c06200 0 0x200>, /* pcs */
1850                                       <0 0x01c06600 0 0x200>; /* pcs_pcie */
1851                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1852                                 clock-names = "pipe0";
1853
1854                                 #clock-cells = <0>;
1855                                 #phy-cells = <0>;
1856                                 clock-output-names = "pcie_0_pipe_clk";
1857                         };
1858                 };
1859
1860                 pcie1: pci@1c08000 {
1861                         compatible = "qcom,pcie-sm8450-pcie1";
1862                         reg = <0 0x01c08000 0 0x3000>,
1863                               <0 0x40000000 0 0xf1d>,
1864                               <0 0x40000f20 0 0xa8>,
1865                               <0 0x40001000 0 0x1000>,
1866                               <0 0x40100000 0 0x100000>;
1867                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1868                         device_type = "pci";
1869                         linux,pci-domain = <1>;
1870                         bus-range = <0x00 0xff>;
1871                         num-lanes = <2>;
1872
1873                         #address-cells = <3>;
1874                         #size-cells = <2>;
1875
1876                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1877                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1878
1879                         /*
1880                          * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
1881                          * Hence, the IDs are swapped.
1882                          */
1883                         msi-map = <0x0 &gic_its 0x5a01 0x1>,
1884                                   <0x100 &gic_its 0x5a00 0x1>;
1885                         msi-map-mask = <0xff00>;
1886                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1887                         interrupt-names = "msi";
1888                         #interrupt-cells = <1>;
1889                         interrupt-map-mask = <0 0 0 0x7>;
1890                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1891                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1892                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1893                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1894
1895                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1896                                  <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1897                                  <&pcie1_lane>,
1898                                  <&rpmhcc RPMH_CXO_CLK>,
1899                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1900                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1901                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1902                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1903                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1904                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1905                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1906                         clock-names = "pipe",
1907                                       "pipe_mux",
1908                                       "phy_pipe",
1909                                       "ref",
1910                                       "aux",
1911                                       "cfg",
1912                                       "bus_master",
1913                                       "bus_slave",
1914                                       "slave_q2a",
1915                                       "ddrss_sf_tbu",
1916                                       "aggre1";
1917
1918                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1919                                     <0x100 &apps_smmu 0x1c81 0x1>;
1920
1921                         resets = <&gcc GCC_PCIE_1_BCR>;
1922                         reset-names = "pci";
1923
1924                         power-domains = <&gcc PCIE_1_GDSC>;
1925
1926                         phys = <&pcie1_lane>;
1927                         phy-names = "pciephy";
1928
1929                         perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1930                         wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1931
1932                         pinctrl-names = "default";
1933                         pinctrl-0 = <&pcie1_default_state>;
1934
1935                         status = "disabled";
1936                 };
1937
1938                 pcie1_phy: phy@1c0f000 {
1939                         compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1940                         reg = <0 0x01c0f000 0 0x200>;
1941                         #address-cells = <2>;
1942                         #size-cells = <2>;
1943                         ranges;
1944                         clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1945                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1946                                  <&gcc GCC_PCIE_1_CLKREF_EN>,
1947                                  <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1948                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1949
1950                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1951                         reset-names = "phy";
1952
1953                         assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1954                         assigned-clock-rates = <100000000>;
1955
1956                         status = "disabled";
1957
1958                         pcie1_lane: phy@1c0e000 {
1959                                 reg = <0 0x01c0e000 0 0x200>, /* tx */
1960                                       <0 0x01c0e200 0 0x300>, /* rx */
1961                                       <0 0x01c0f200 0 0x200>, /* pcs */
1962                                       <0 0x01c0e800 0 0x200>, /* tx */
1963                                       <0 0x01c0ea00 0 0x300>, /* rx */
1964                                       <0 0x01c0f400 0 0xc00>; /* pcs_pcie */
1965                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1966                                 clock-names = "pipe0";
1967
1968                                 #clock-cells = <0>;
1969                                 #phy-cells = <0>;
1970                                 clock-output-names = "pcie_1_pipe_clk";
1971                         };
1972                 };
1973
1974                 config_noc: interconnect@1500000 {
1975                         compatible = "qcom,sm8450-config-noc";
1976                         reg = <0 0x01500000 0 0x1c000>;
1977                         #interconnect-cells = <2>;
1978                         qcom,bcm-voters = <&apps_bcm_voter>;
1979                 };
1980
1981                 system_noc: interconnect@1680000 {
1982                         compatible = "qcom,sm8450-system-noc";
1983                         reg = <0 0x01680000 0 0x1e200>;
1984                         #interconnect-cells = <2>;
1985                         qcom,bcm-voters = <&apps_bcm_voter>;
1986                 };
1987
1988                 pcie_noc: interconnect@16c0000 {
1989                         compatible = "qcom,sm8450-pcie-anoc";
1990                         reg = <0 0x016c0000 0 0xe280>;
1991                         #interconnect-cells = <2>;
1992                         qcom,bcm-voters = <&apps_bcm_voter>;
1993                 };
1994
1995                 aggre1_noc: interconnect@16e0000 {
1996                         compatible = "qcom,sm8450-aggre1-noc";
1997                         reg = <0 0x016e0000 0 0x1c080>;
1998                         #interconnect-cells = <2>;
1999                         clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2000                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2001                         qcom,bcm-voters = <&apps_bcm_voter>;
2002                 };
2003
2004                 aggre2_noc: interconnect@1700000 {
2005                         compatible = "qcom,sm8450-aggre2-noc";
2006                         reg = <0 0x01700000 0 0x31080>;
2007                         #interconnect-cells = <2>;
2008                         qcom,bcm-voters = <&apps_bcm_voter>;
2009                         clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2010                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2011                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2012                                  <&rpmhcc RPMH_IPA_CLK>;
2013                 };
2014
2015                 mmss_noc: interconnect@1740000 {
2016                         compatible = "qcom,sm8450-mmss-noc";
2017                         reg = <0 0x01740000 0 0x1f080>;
2018                         #interconnect-cells = <2>;
2019                         qcom,bcm-voters = <&apps_bcm_voter>;
2020                 };
2021
2022                 tcsr_mutex: hwlock@1f40000 {
2023                         compatible = "qcom,tcsr-mutex";
2024                         reg = <0x0 0x01f40000 0x0 0x40000>;
2025                         #hwlock-cells = <1>;
2026                 };
2027
2028                 tcsr: syscon@1fc0000 {
2029                         compatible = "qcom,sm8450-tcsr", "syscon";
2030                         reg = <0x0 0x1fc0000 0x0 0x30000>;
2031                 };
2032
2033                 usb_1_hsphy: phy@88e3000 {
2034                         compatible = "qcom,sm8450-usb-hs-phy",
2035                                      "qcom,usb-snps-hs-7nm-phy";
2036                         reg = <0 0x088e3000 0 0x400>;
2037                         status = "disabled";
2038                         #phy-cells = <0>;
2039
2040                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2041                         clock-names = "ref";
2042
2043                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2044                 };
2045
2046                 usb_1_qmpphy: phy@88e8000 {
2047                         compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2048                         reg = <0 0x088e8000 0 0x3000>;
2049
2050                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2051                                  <&rpmhcc RPMH_CXO_CLK>,
2052                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2053                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2054                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2055
2056                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2057                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2058                         reset-names = "phy", "common";
2059
2060                         #clock-cells = <1>;
2061                         #phy-cells = <1>;
2062
2063                         status = "disabled";
2064
2065                         ports {
2066                                 #address-cells = <1>;
2067                                 #size-cells = <0>;
2068
2069                                 port@0 {
2070                                         reg = <0>;
2071
2072                                         usb_1_qmpphy_out: endpoint {
2073                                         };
2074                                 };
2075
2076                                 port@1 {
2077                                         reg = <1>;
2078
2079                                         usb_1_qmpphy_usb_ss_in: endpoint {
2080                                         };
2081                                 };
2082
2083                                 port@2 {
2084                                         reg = <2>;
2085
2086                                         usb_1_qmpphy_dp_in: endpoint {
2087                                         };
2088                                 };
2089                         };
2090                 };
2091
2092                 remoteproc_slpi: remoteproc@2400000 {
2093                         compatible = "qcom,sm8450-slpi-pas";
2094                         reg = <0 0x02400000 0 0x4000>;
2095
2096                         interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2097                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2098                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2099                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2100                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2101                         interrupt-names = "wdog", "fatal", "ready",
2102                                           "handover", "stop-ack";
2103
2104                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2105                         clock-names = "xo";
2106
2107                         power-domains = <&rpmhpd RPMHPD_LCX>,
2108                                         <&rpmhpd RPMHPD_LMX>;
2109                         power-domain-names = "lcx", "lmx";
2110
2111                         memory-region = <&slpi_mem>;
2112
2113                         qcom,qmp = <&aoss_qmp>;
2114
2115                         qcom,smem-states = <&smp2p_slpi_out 0>;
2116                         qcom,smem-state-names = "stop";
2117
2118                         status = "disabled";
2119
2120                         glink-edge {
2121                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2122                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2123                                                              IRQ_TYPE_EDGE_RISING>;
2124                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2125                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2126
2127                                 label = "slpi";
2128                                 qcom,remote-pid = <3>;
2129
2130                                 fastrpc {
2131                                         compatible = "qcom,fastrpc";
2132                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2133                                         label = "sdsp";
2134                                         #address-cells = <1>;
2135                                         #size-cells = <0>;
2136
2137                                         compute-cb@1 {
2138                                                 compatible = "qcom,fastrpc-compute-cb";
2139                                                 reg = <1>;
2140                                                 iommus = <&apps_smmu 0x0541 0x0>;
2141                                         };
2142
2143                                         compute-cb@2 {
2144                                                 compatible = "qcom,fastrpc-compute-cb";
2145                                                 reg = <2>;
2146                                                 iommus = <&apps_smmu 0x0542 0x0>;
2147                                         };
2148
2149                                         compute-cb@3 {
2150                                                 compatible = "qcom,fastrpc-compute-cb";
2151                                                 reg = <3>;
2152                                                 iommus = <&apps_smmu 0x0543 0x0>;
2153                                                 /* note: shared-cb = <4> in downstream */
2154                                         };
2155                                 };
2156                         };
2157                 };
2158
2159                 wsa2macro: codec@31e0000 {
2160                         compatible = "qcom,sm8450-lpass-wsa-macro";
2161                         reg = <0 0x031e0000 0 0x1000>;
2162                         clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2163                                  <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2164                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2165                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2166                                  <&vamacro>;
2167                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2168                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2169                                           <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2170                         assigned-clock-rates = <19200000>, <19200000>;
2171
2172                         #clock-cells = <0>;
2173                         clock-output-names = "wsa2-mclk";
2174                         pinctrl-names = "default";
2175                         pinctrl-0 = <&wsa2_swr_active>;
2176                         #sound-dai-cells = <1>;
2177                 };
2178
2179                 swr4: soundwire-controller@31f0000 {
2180                         compatible = "qcom,soundwire-v1.7.0";
2181                         reg = <0 0x031f0000 0 0x2000>;
2182                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2183                         clocks = <&wsa2macro>;
2184                         clock-names = "iface";
2185                         label = "WSA2";
2186
2187                         qcom,din-ports = <2>;
2188                         qcom,dout-ports = <6>;
2189
2190                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2191                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2192                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2193                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2194                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2195                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2196                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2197                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2198                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2199
2200                         #address-cells = <2>;
2201                         #size-cells = <0>;
2202                         #sound-dai-cells = <1>;
2203                         status = "disabled";
2204                 };
2205
2206                 rxmacro: codec@3200000 {
2207                         compatible = "qcom,sm8450-lpass-rx-macro";
2208                         reg = <0 0x03200000 0 0x1000>;
2209                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2210                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2211                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2212                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2213                                  <&vamacro>;
2214                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2215
2216                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2217                                           <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2218                         assigned-clock-rates = <19200000>, <19200000>;
2219
2220                         #clock-cells = <0>;
2221                         clock-output-names = "mclk";
2222                         pinctrl-names = "default";
2223                         pinctrl-0 = <&rx_swr_active>;
2224                         #sound-dai-cells = <1>;
2225                 };
2226
2227                 swr1: soundwire-controller@3210000 {
2228                         compatible = "qcom,soundwire-v1.7.0";
2229                         reg = <0 0x03210000 0 0x2000>;
2230                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2231                         clocks = <&rxmacro>;
2232                         clock-names = "iface";
2233                         label = "RX";
2234                         qcom,din-ports = <0>;
2235                         qcom,dout-ports = <5>;
2236
2237                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2238                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2239                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2240                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2241                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2242                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2243                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2244                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2245                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2246
2247                         #address-cells = <2>;
2248                         #size-cells = <0>;
2249                         #sound-dai-cells = <1>;
2250                         status = "disabled";
2251                 };
2252
2253                 txmacro: codec@3220000 {
2254                         compatible = "qcom,sm8450-lpass-tx-macro";
2255                         reg = <0 0x03220000 0 0x1000>;
2256                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2257                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2258                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2259                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2260                                  <&vamacro>;
2261                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2262                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2263                                           <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2264                         assigned-clock-rates = <19200000>, <19200000>;
2265
2266                         #clock-cells = <0>;
2267                         clock-output-names = "mclk";
2268                         pinctrl-names = "default";
2269                         pinctrl-0 = <&tx_swr_active>;
2270                         #sound-dai-cells = <1>;
2271                 };
2272
2273                 wsamacro: codec@3240000 {
2274                         compatible = "qcom,sm8450-lpass-wsa-macro";
2275                         reg = <0 0x03240000 0 0x1000>;
2276                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2277                                  <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2278                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2279                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2280                                  <&vamacro>;
2281                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2282
2283                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2284                                           <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2285                         assigned-clock-rates = <19200000>, <19200000>;
2286
2287                         #clock-cells = <0>;
2288                         clock-output-names = "mclk";
2289                         pinctrl-names = "default";
2290                         pinctrl-0 = <&wsa_swr_active>;
2291                         #sound-dai-cells = <1>;
2292                 };
2293
2294                 swr0: soundwire-controller@3250000 {
2295                         compatible = "qcom,soundwire-v1.7.0";
2296                         reg = <0 0x03250000 0 0x2000>;
2297                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2298                         clocks = <&wsamacro>;
2299                         clock-names = "iface";
2300                         label = "WSA";
2301
2302                         qcom,din-ports = <2>;
2303                         qcom,dout-ports = <6>;
2304
2305                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2306                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2307                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2308                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2309                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2310                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2311                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2312                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2313                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2314
2315                         #address-cells = <2>;
2316                         #size-cells = <0>;
2317                         #sound-dai-cells = <1>;
2318                         status = "disabled";
2319                 };
2320
2321                 swr2: soundwire-controller@33b0000 {
2322                         compatible = "qcom,soundwire-v1.7.0";
2323                         reg = <0 0x033b0000 0 0x2000>;
2324                         interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2325                                      <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2326                         interrupt-names = "core", "wakeup";
2327
2328                         clocks = <&txmacro>;
2329                         clock-names = "iface";
2330                         label = "TX";
2331
2332                         qcom,din-ports = <4>;
2333                         qcom,dout-ports = <0>;
2334                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x01 0x03 0x03>;
2335                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x01 0x01>;
2336                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
2337                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
2338                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
2339                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff>;
2340                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
2341                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
2342                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x02 0x00 0x00>;
2343
2344                         #address-cells = <2>;
2345                         #size-cells = <0>;
2346                         #sound-dai-cells = <1>;
2347                         status = "disabled";
2348                 };
2349
2350                 vamacro: codec@33f0000 {
2351                         compatible = "qcom,sm8450-lpass-va-macro";
2352                         reg = <0 0x033f0000 0 0x1000>;
2353                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2354                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2355                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2356                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2357                         clock-names = "mclk", "macro", "dcodec", "npl";
2358                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2359                         assigned-clock-rates = <19200000>;
2360
2361                         #clock-cells = <0>;
2362                         clock-output-names = "fsgen";
2363                         #sound-dai-cells = <1>;
2364                         status = "disabled";
2365                 };
2366
2367                 remoteproc_adsp: remoteproc@30000000 {
2368                         compatible = "qcom,sm8450-adsp-pas";
2369                         reg = <0 0x30000000 0 0x100>;
2370
2371                         interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2372                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2373                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2374                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2375                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2376                         interrupt-names = "wdog", "fatal", "ready",
2377                                           "handover", "stop-ack";
2378
2379                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2380                         clock-names = "xo";
2381
2382                         power-domains = <&rpmhpd RPMHPD_LCX>,
2383                                         <&rpmhpd RPMHPD_LMX>;
2384                         power-domain-names = "lcx", "lmx";
2385
2386                         memory-region = <&adsp_mem>;
2387
2388                         qcom,qmp = <&aoss_qmp>;
2389
2390                         qcom,smem-states = <&smp2p_adsp_out 0>;
2391                         qcom,smem-state-names = "stop";
2392
2393                         status = "disabled";
2394
2395                         remoteproc_adsp_glink: glink-edge {
2396                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2397                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2398                                                              IRQ_TYPE_EDGE_RISING>;
2399                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2400                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2401
2402                                 label = "lpass";
2403                                 qcom,remote-pid = <2>;
2404
2405                                 gpr {
2406                                         compatible = "qcom,gpr";
2407                                         qcom,glink-channels = "adsp_apps";
2408                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2409                                         qcom,intents = <512 20>;
2410                                         #address-cells = <1>;
2411                                         #size-cells = <0>;
2412
2413                                         q6apm: service@1 {
2414                                                 compatible = "qcom,q6apm";
2415                                                 reg = <GPR_APM_MODULE_IID>;
2416                                                 #sound-dai-cells = <0>;
2417                                                 qcom,protection-domain = "avs/audio",
2418                                                                          "msm/adsp/audio_pd";
2419
2420                                                 q6apmdai: dais {
2421                                                         compatible = "qcom,q6apm-dais";
2422                                                         iommus = <&apps_smmu 0x1801 0x0>;
2423                                                 };
2424
2425                                                 q6apmbedai: bedais {
2426                                                         compatible = "qcom,q6apm-lpass-dais";
2427                                                         #sound-dai-cells = <1>;
2428                                                 };
2429                                         };
2430
2431                                         q6prm: service@2 {
2432                                                 compatible = "qcom,q6prm";
2433                                                 reg = <GPR_PRM_MODULE_IID>;
2434                                                 qcom,protection-domain = "avs/audio",
2435                                                                          "msm/adsp/audio_pd";
2436
2437                                                 q6prmcc: clock-controller {
2438                                                         compatible = "qcom,q6prm-lpass-clocks";
2439                                                         #clock-cells = <2>;
2440                                                 };
2441                                         };
2442                                 };
2443
2444                                 fastrpc {
2445                                         compatible = "qcom,fastrpc";
2446                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2447                                         label = "adsp";
2448                                         #address-cells = <1>;
2449                                         #size-cells = <0>;
2450
2451                                         compute-cb@3 {
2452                                                 compatible = "qcom,fastrpc-compute-cb";
2453                                                 reg = <3>;
2454                                                 iommus = <&apps_smmu 0x1803 0x0>;
2455                                         };
2456
2457                                         compute-cb@4 {
2458                                                 compatible = "qcom,fastrpc-compute-cb";
2459                                                 reg = <4>;
2460                                                 iommus = <&apps_smmu 0x1804 0x0>;
2461                                         };
2462
2463                                         compute-cb@5 {
2464                                                 compatible = "qcom,fastrpc-compute-cb";
2465                                                 reg = <5>;
2466                                                 iommus = <&apps_smmu 0x1805 0x0>;
2467                                         };
2468                                 };
2469                         };
2470                 };
2471
2472                 remoteproc_cdsp: remoteproc@32300000 {
2473                         compatible = "qcom,sm8450-cdsp-pas";
2474                         reg = <0 0x32300000 0 0x1400000>;
2475
2476                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2477                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2478                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2479                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2480                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2481                         interrupt-names = "wdog", "fatal", "ready",
2482                                           "handover", "stop-ack";
2483
2484                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2485                         clock-names = "xo";
2486
2487                         power-domains = <&rpmhpd RPMHPD_CX>,
2488                                         <&rpmhpd RPMHPD_MXC>;
2489                         power-domain-names = "cx", "mxc";
2490
2491                         memory-region = <&cdsp_mem>;
2492
2493                         qcom,qmp = <&aoss_qmp>;
2494
2495                         qcom,smem-states = <&smp2p_cdsp_out 0>;
2496                         qcom,smem-state-names = "stop";
2497
2498                         status = "disabled";
2499
2500                         glink-edge {
2501                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2502                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2503                                                              IRQ_TYPE_EDGE_RISING>;
2504                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2505                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2506
2507                                 label = "cdsp";
2508                                 qcom,remote-pid = <5>;
2509
2510                                 fastrpc {
2511                                         compatible = "qcom,fastrpc";
2512                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2513                                         label = "cdsp";
2514                                         #address-cells = <1>;
2515                                         #size-cells = <0>;
2516
2517                                         compute-cb@1 {
2518                                                 compatible = "qcom,fastrpc-compute-cb";
2519                                                 reg = <1>;
2520                                                 iommus = <&apps_smmu 0x2161 0x0400>,
2521                                                          <&apps_smmu 0x1021 0x1420>;
2522                                         };
2523
2524                                         compute-cb@2 {
2525                                                 compatible = "qcom,fastrpc-compute-cb";
2526                                                 reg = <2>;
2527                                                 iommus = <&apps_smmu 0x2162 0x0400>,
2528                                                          <&apps_smmu 0x1022 0x1420>;
2529                                         };
2530
2531                                         compute-cb@3 {
2532                                                 compatible = "qcom,fastrpc-compute-cb";
2533                                                 reg = <3>;
2534                                                 iommus = <&apps_smmu 0x2163 0x0400>,
2535                                                          <&apps_smmu 0x1023 0x1420>;
2536                                         };
2537
2538                                         compute-cb@4 {
2539                                                 compatible = "qcom,fastrpc-compute-cb";
2540                                                 reg = <4>;
2541                                                 iommus = <&apps_smmu 0x2164 0x0400>,
2542                                                          <&apps_smmu 0x1024 0x1420>;
2543                                         };
2544
2545                                         compute-cb@5 {
2546                                                 compatible = "qcom,fastrpc-compute-cb";
2547                                                 reg = <5>;
2548                                                 iommus = <&apps_smmu 0x2165 0x0400>,
2549                                                          <&apps_smmu 0x1025 0x1420>;
2550                                         };
2551
2552                                         compute-cb@6 {
2553                                                 compatible = "qcom,fastrpc-compute-cb";
2554                                                 reg = <6>;
2555                                                 iommus = <&apps_smmu 0x2166 0x0400>,
2556                                                          <&apps_smmu 0x1026 0x1420>;
2557                                         };
2558
2559                                         compute-cb@7 {
2560                                                 compatible = "qcom,fastrpc-compute-cb";
2561                                                 reg = <7>;
2562                                                 iommus = <&apps_smmu 0x2167 0x0400>,
2563                                                          <&apps_smmu 0x1027 0x1420>;
2564                                         };
2565
2566                                         compute-cb@8 {
2567                                                 compatible = "qcom,fastrpc-compute-cb";
2568                                                 reg = <8>;
2569                                                 iommus = <&apps_smmu 0x2168 0x0400>,
2570                                                          <&apps_smmu 0x1028 0x1420>;
2571                                         };
2572
2573                                         /* note: secure cb9 in downstream */
2574                                 };
2575                         };
2576                 };
2577
2578                 remoteproc_mpss: remoteproc@4080000 {
2579                         compatible = "qcom,sm8450-mpss-pas";
2580                         reg = <0x0 0x04080000 0x0 0x4040>;
2581
2582                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2583                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2584                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2585                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2586                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2587                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2588                         interrupt-names = "wdog", "fatal", "ready", "handover",
2589                                           "stop-ack", "shutdown-ack";
2590
2591                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2592                         clock-names = "xo";
2593
2594                         power-domains = <&rpmhpd RPMHPD_CX>,
2595                                         <&rpmhpd RPMHPD_MSS>;
2596                         power-domain-names = "cx", "mss";
2597
2598                         memory-region = <&mpss_mem>;
2599
2600                         qcom,qmp = <&aoss_qmp>;
2601
2602                         qcom,smem-states = <&smp2p_modem_out 0>;
2603                         qcom,smem-state-names = "stop";
2604
2605                         status = "disabled";
2606
2607                         glink-edge {
2608                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2609                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2610                                                              IRQ_TYPE_EDGE_RISING>;
2611                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2612                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2613                                 label = "modem";
2614                                 qcom,remote-pid = <1>;
2615                         };
2616                 };
2617
2618                 videocc: clock-controller@aaf0000 {
2619                         compatible = "qcom,sm8450-videocc";
2620                         reg = <0 0x0aaf0000 0 0x10000>;
2621                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2622                                  <&gcc GCC_VIDEO_AHB_CLK>;
2623                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2624                         required-opps = <&rpmhpd_opp_low_svs>;
2625                         #clock-cells = <1>;
2626                         #reset-cells = <1>;
2627                         #power-domain-cells = <1>;
2628                 };
2629
2630                 cci0: cci@ac15000 {
2631                         compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2632                         reg = <0 0x0ac15000 0 0x1000>;
2633                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2634                         power-domains = <&camcc TITAN_TOP_GDSC>;
2635
2636                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2637                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2638                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
2639                                  <&camcc CAM_CC_CCI_0_CLK>,
2640                                  <&camcc CAM_CC_CCI_0_CLK_SRC>;
2641                         clock-names = "camnoc_axi",
2642                                       "slow_ahb_src",
2643                                       "cpas_ahb",
2644                                       "cci",
2645                                       "cci_src";
2646                         pinctrl-0 = <&cci0_default &cci1_default>;
2647                         pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2648                         pinctrl-names = "default", "sleep";
2649
2650                         status = "disabled";
2651                         #address-cells = <1>;
2652                         #size-cells = <0>;
2653
2654                         cci0_i2c0: i2c-bus@0 {
2655                                 reg = <0>;
2656                                 clock-frequency = <1000000>;
2657                                 #address-cells = <1>;
2658                                 #size-cells = <0>;
2659                         };
2660
2661                         cci0_i2c1: i2c-bus@1 {
2662                                 reg = <1>;
2663                                 clock-frequency = <1000000>;
2664                                 #address-cells = <1>;
2665                                 #size-cells = <0>;
2666                         };
2667                 };
2668
2669                 cci1: cci@ac16000 {
2670                         compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2671                         reg = <0 0x0ac16000 0 0x1000>;
2672                         interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2673                         power-domains = <&camcc TITAN_TOP_GDSC>;
2674
2675                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2676                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2677                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
2678                                  <&camcc CAM_CC_CCI_1_CLK>,
2679                                  <&camcc CAM_CC_CCI_1_CLK_SRC>;
2680                         clock-names = "camnoc_axi",
2681                                       "slow_ahb_src",
2682                                       "cpas_ahb",
2683                                       "cci",
2684                                       "cci_src";
2685                         pinctrl-0 = <&cci2_default &cci3_default>;
2686                         pinctrl-1 = <&cci2_sleep &cci3_sleep>;
2687                         pinctrl-names = "default", "sleep";
2688
2689                         status = "disabled";
2690                         #address-cells = <1>;
2691                         #size-cells = <0>;
2692
2693                         cci1_i2c0: i2c-bus@0 {
2694                                 reg = <0>;
2695                                 clock-frequency = <1000000>;
2696                                 #address-cells = <1>;
2697                                 #size-cells = <0>;
2698                         };
2699
2700                         cci1_i2c1: i2c-bus@1 {
2701                                 reg = <1>;
2702                                 clock-frequency = <1000000>;
2703                                 #address-cells = <1>;
2704                                 #size-cells = <0>;
2705                         };
2706                 };
2707
2708                 camcc: clock-controller@ade0000 {
2709                         compatible = "qcom,sm8450-camcc";
2710                         reg = <0 0x0ade0000 0 0x20000>;
2711                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2712                                  <&rpmhcc RPMH_CXO_CLK>,
2713                                  <&rpmhcc RPMH_CXO_CLK_A>,
2714                                  <&sleep_clk>;
2715                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2716                         required-opps = <&rpmhpd_opp_low_svs>;
2717                         #clock-cells = <1>;
2718                         #reset-cells = <1>;
2719                         #power-domain-cells = <1>;
2720                         status = "disabled";
2721                 };
2722
2723                 mdss: display-subsystem@ae00000 {
2724                         compatible = "qcom,sm8450-mdss";
2725                         reg = <0 0x0ae00000 0 0x1000>;
2726                         reg-names = "mdss";
2727
2728                         /* same path used twice */
2729                         interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2730                                         <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2731                                         <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2732                                          &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
2733                         interconnect-names = "mdp0-mem",
2734                                              "mdp1-mem",
2735                                              "cpu-cfg";
2736
2737                         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2738
2739                         power-domains = <&dispcc MDSS_GDSC>;
2740
2741                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2742                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2743                                  <&gcc GCC_DISP_SF_AXI_CLK>,
2744                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2745
2746                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2747                         interrupt-controller;
2748                         #interrupt-cells = <1>;
2749
2750                         iommus = <&apps_smmu 0x2800 0x402>;
2751
2752                         #address-cells = <2>;
2753                         #size-cells = <2>;
2754                         ranges;
2755
2756                         status = "disabled";
2757
2758                         mdss_mdp: display-controller@ae01000 {
2759                                 compatible = "qcom,sm8450-dpu";
2760                                 reg = <0 0x0ae01000 0 0x8f000>,
2761                                       <0 0x0aeb0000 0 0x2008>;
2762                                 reg-names = "mdp", "vbif";
2763
2764                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2765                                         <&gcc GCC_DISP_SF_AXI_CLK>,
2766                                         <&dispcc DISP_CC_MDSS_AHB_CLK>,
2767                                         <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2768                                         <&dispcc DISP_CC_MDSS_MDP_CLK>,
2769                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2770                                 clock-names = "bus",
2771                                               "nrt_bus",
2772                                               "iface",
2773                                               "lut",
2774                                               "core",
2775                                               "vsync";
2776
2777                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2778                                 assigned-clock-rates = <19200000>;
2779
2780                                 operating-points-v2 = <&mdp_opp_table>;
2781                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2782
2783                                 interrupt-parent = <&mdss>;
2784                                 interrupts = <0>;
2785
2786                                 ports {
2787                                         #address-cells = <1>;
2788                                         #size-cells = <0>;
2789
2790                                         port@0 {
2791                                                 reg = <0>;
2792                                                 dpu_intf1_out: endpoint {
2793                                                         remote-endpoint = <&mdss_dsi0_in>;
2794                                                 };
2795                                         };
2796
2797                                         port@1 {
2798                                                 reg = <1>;
2799                                                 dpu_intf2_out: endpoint {
2800                                                         remote-endpoint = <&mdss_dsi1_in>;
2801                                                 };
2802                                         };
2803
2804                                         port@2 {
2805                                                 reg = <2>;
2806                                                 dpu_intf0_out: endpoint {
2807                                                         remote-endpoint = <&mdss_dp0_in>;
2808                                                 };
2809                                         };
2810                                 };
2811
2812                                 mdp_opp_table: opp-table {
2813                                         compatible = "operating-points-v2";
2814
2815                                         opp-172000000 {
2816                                                 opp-hz = /bits/ 64 <172000000>;
2817                                                 required-opps = <&rpmhpd_opp_low_svs_d1>;
2818                                         };
2819
2820                                         opp-200000000 {
2821                                                 opp-hz = /bits/ 64 <200000000>;
2822                                                 required-opps = <&rpmhpd_opp_low_svs>;
2823                                         };
2824
2825                                         opp-325000000 {
2826                                                 opp-hz = /bits/ 64 <325000000>;
2827                                                 required-opps = <&rpmhpd_opp_svs>;
2828                                         };
2829
2830                                         opp-375000000 {
2831                                                 opp-hz = /bits/ 64 <375000000>;
2832                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2833                                         };
2834
2835                                         opp-500000000 {
2836                                                 opp-hz = /bits/ 64 <500000000>;
2837                                                 required-opps = <&rpmhpd_opp_nom>;
2838                                         };
2839                                 };
2840                         };
2841
2842                         mdss_dp0: displayport-controller@ae90000 {
2843                                 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
2844                                 reg = <0 0xae90000 0 0x200>,
2845                                       <0 0xae90200 0 0x200>,
2846                                       <0 0xae90400 0 0xc00>,
2847                                       <0 0xae91000 0 0x400>,
2848                                       <0 0xae91400 0 0x400>;
2849                                 interrupt-parent = <&mdss>;
2850                                 interrupts = <12>;
2851                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2852                                          <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
2853                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
2854                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
2855                                          <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
2856                                 clock-names = "core_iface",
2857                                               "core_aux",
2858                                               "ctrl_link",
2859                                               "ctrl_link_iface",
2860                                               "stream_pixel";
2861
2862                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2863                                                   <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
2864                                 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2865                                                          <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2866
2867                                 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
2868                                 phy-names = "dp";
2869
2870                                 #sound-dai-cells = <0>;
2871
2872                                 operating-points-v2 = <&dp_opp_table>;
2873                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2874
2875                                 status = "disabled";
2876
2877                                 ports {
2878                                         #address-cells = <1>;
2879                                         #size-cells = <0>;
2880
2881                                         port@0 {
2882                                                 reg = <0>;
2883                                                 mdss_dp0_in: endpoint {
2884                                                         remote-endpoint = <&dpu_intf0_out>;
2885                                                 };
2886                                         };
2887                                 };
2888
2889                                 dp_opp_table: opp-table {
2890                                         compatible = "operating-points-v2";
2891
2892                                         opp-160000000 {
2893                                                 opp-hz = /bits/ 64 <160000000>;
2894                                                 required-opps = <&rpmhpd_opp_low_svs>;
2895                                         };
2896
2897                                         opp-270000000 {
2898                                                 opp-hz = /bits/ 64 <270000000>;
2899                                                 required-opps = <&rpmhpd_opp_svs>;
2900                                         };
2901
2902                                         opp-540000000 {
2903                                                 opp-hz = /bits/ 64 <540000000>;
2904                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2905                                         };
2906
2907                                         opp-810000000 {
2908                                                 opp-hz = /bits/ 64 <810000000>;
2909                                                 required-opps = <&rpmhpd_opp_nom>;
2910                                         };
2911                                 };
2912                         };
2913
2914                         mdss_dsi0: dsi@ae94000 {
2915                                 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2916                                 reg = <0 0x0ae94000 0 0x400>;
2917                                 reg-names = "dsi_ctrl";
2918
2919                                 interrupt-parent = <&mdss>;
2920                                 interrupts = <4>;
2921
2922                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2923                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2924                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2925                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2926                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2927                                         <&gcc GCC_DISP_HF_AXI_CLK>;
2928                                 clock-names = "byte",
2929                                               "byte_intf",
2930                                               "pixel",
2931                                               "core",
2932                                               "iface",
2933                                               "bus";
2934
2935                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2936                                 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2937
2938                                 operating-points-v2 = <&mdss_dsi_opp_table>;
2939                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2940
2941                                 phys = <&mdss_dsi0_phy>;
2942                                 phy-names = "dsi";
2943
2944                                 #address-cells = <1>;
2945                                 #size-cells = <0>;
2946
2947                                 status = "disabled";
2948
2949                                 ports {
2950                                         #address-cells = <1>;
2951                                         #size-cells = <0>;
2952
2953                                         port@0 {
2954                                                 reg = <0>;
2955                                                 mdss_dsi0_in: endpoint {
2956                                                         remote-endpoint = <&dpu_intf1_out>;
2957                                                 };
2958                                         };
2959
2960                                         port@1 {
2961                                                 reg = <1>;
2962                                                 mdss_dsi0_out: endpoint {
2963                                                 };
2964                                         };
2965                                 };
2966
2967                                 mdss_dsi_opp_table: opp-table {
2968                                         compatible = "operating-points-v2";
2969
2970                                         opp-187500000 {
2971                                                 opp-hz = /bits/ 64 <187500000>;
2972                                                 required-opps = <&rpmhpd_opp_low_svs>;
2973                                         };
2974
2975                                         opp-300000000 {
2976                                                 opp-hz = /bits/ 64 <300000000>;
2977                                                 required-opps = <&rpmhpd_opp_svs>;
2978                                         };
2979
2980                                         opp-358000000 {
2981                                                 opp-hz = /bits/ 64 <358000000>;
2982                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2983                                         };
2984                                 };
2985                         };
2986
2987                         mdss_dsi0_phy: phy@ae94400 {
2988                                 compatible = "qcom,sm8450-dsi-phy-5nm";
2989                                 reg = <0 0x0ae94400 0 0x200>,
2990                                       <0 0x0ae94600 0 0x280>,
2991                                       <0 0x0ae94900 0 0x260>;
2992                                 reg-names = "dsi_phy",
2993                                             "dsi_phy_lane",
2994                                             "dsi_pll";
2995
2996                                 #clock-cells = <1>;
2997                                 #phy-cells = <0>;
2998
2999                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3000                                          <&rpmhcc RPMH_CXO_CLK>;
3001                                 clock-names = "iface", "ref";
3002
3003                                 status = "disabled";
3004                         };
3005
3006                         mdss_dsi1: dsi@ae96000 {
3007                                 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3008                                 reg = <0 0x0ae96000 0 0x400>;
3009                                 reg-names = "dsi_ctrl";
3010
3011                                 interrupt-parent = <&mdss>;
3012                                 interrupts = <5>;
3013
3014                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3015                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3016                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3017                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3018                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3019                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3020                                 clock-names = "byte",
3021                                               "byte_intf",
3022                                               "pixel",
3023                                               "core",
3024                                               "iface",
3025                                               "bus";
3026
3027                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3028                                 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3029
3030                                 operating-points-v2 = <&mdss_dsi_opp_table>;
3031                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
3032
3033                                 phys = <&mdss_dsi1_phy>;
3034                                 phy-names = "dsi";
3035
3036                                 #address-cells = <1>;
3037                                 #size-cells = <0>;
3038
3039                                 status = "disabled";
3040
3041                                 ports {
3042                                         #address-cells = <1>;
3043                                         #size-cells = <0>;
3044
3045                                         port@0 {
3046                                                 reg = <0>;
3047                                                 mdss_dsi1_in: endpoint {
3048                                                         remote-endpoint = <&dpu_intf2_out>;
3049                                                 };
3050                                         };
3051
3052                                         port@1 {
3053                                                 reg = <1>;
3054                                                 mdss_dsi1_out: endpoint {
3055                                                 };
3056                                         };
3057                                 };
3058                         };
3059
3060                         mdss_dsi1_phy: phy@ae96400 {
3061                                 compatible = "qcom,sm8450-dsi-phy-5nm";
3062                                 reg = <0 0x0ae96400 0 0x200>,
3063                                       <0 0x0ae96600 0 0x280>,
3064                                       <0 0x0ae96900 0 0x260>;
3065                                 reg-names = "dsi_phy",
3066                                             "dsi_phy_lane",
3067                                             "dsi_pll";
3068
3069                                 #clock-cells = <1>;
3070                                 #phy-cells = <0>;
3071
3072                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3073                                          <&rpmhcc RPMH_CXO_CLK>;
3074                                 clock-names = "iface", "ref";
3075
3076                                 status = "disabled";
3077                         };
3078                 };
3079
3080                 dispcc: clock-controller@af00000 {
3081                         compatible = "qcom,sm8450-dispcc";
3082                         reg = <0 0x0af00000 0 0x20000>;
3083                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3084                                  <&rpmhcc RPMH_CXO_CLK_A>,
3085                                  <&gcc GCC_DISP_AHB_CLK>,
3086                                  <&sleep_clk>,
3087                                  <&mdss_dsi0_phy 0>,
3088                                  <&mdss_dsi0_phy 1>,
3089                                  <&mdss_dsi1_phy 0>,
3090                                  <&mdss_dsi1_phy 1>,
3091                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3092                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3093                                  <0>, /* dp1 */
3094                                  <0>,
3095                                  <0>, /* dp2 */
3096                                  <0>,
3097                                  <0>, /* dp3 */
3098                                  <0>;
3099                         power-domains = <&rpmhpd RPMHPD_MMCX>;
3100                         required-opps = <&rpmhpd_opp_low_svs>;
3101                         #clock-cells = <1>;
3102                         #reset-cells = <1>;
3103                         #power-domain-cells = <1>;
3104                         status = "disabled";
3105                 };
3106
3107                 pdc: interrupt-controller@b220000 {
3108                         compatible = "qcom,sm8450-pdc", "qcom,pdc";
3109                         reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3110                         qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3111                                           <94 609 31>, <125 63 1>, <126 716 12>;
3112                         #interrupt-cells = <2>;
3113                         interrupt-parent = <&intc>;
3114                         interrupt-controller;
3115                 };
3116
3117                 tsens0: thermal-sensor@c263000 {
3118                         compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3119                         reg = <0 0x0c263000 0 0x1000>, /* TM */
3120                               <0 0x0c222000 0 0x1000>; /* SROT */
3121                         #qcom,sensors = <16>;
3122                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3123                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3124                         interrupt-names = "uplow", "critical";
3125                         #thermal-sensor-cells = <1>;
3126                 };
3127
3128                 tsens1: thermal-sensor@c265000 {
3129                         compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3130                         reg = <0 0x0c265000 0 0x1000>, /* TM */
3131                               <0 0x0c223000 0 0x1000>; /* SROT */
3132                         #qcom,sensors = <16>;
3133                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3134                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3135                         interrupt-names = "uplow", "critical";
3136                         #thermal-sensor-cells = <1>;
3137                 };
3138
3139                 aoss_qmp: power-management@c300000 {
3140                         compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3141                         reg = <0 0x0c300000 0 0x400>;
3142                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3143                                                      IRQ_TYPE_EDGE_RISING>;
3144                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3145
3146                         #clock-cells = <0>;
3147                 };
3148
3149                 sram@c3f0000 {
3150                         compatible = "qcom,rpmh-stats";
3151                         reg = <0 0x0c3f0000 0 0x400>;
3152                 };
3153
3154                 spmi_bus: spmi@c400000 {
3155                         compatible = "qcom,spmi-pmic-arb";
3156                         reg = <0 0x0c400000 0 0x00003000>,
3157                               <0 0x0c500000 0 0x00400000>,
3158                               <0 0x0c440000 0 0x00080000>,
3159                               <0 0x0c4c0000 0 0x00010000>,
3160                               <0 0x0c42d000 0 0x00010000>;
3161                         reg-names = "core",
3162                                     "chnls",
3163                                     "obsrvr",
3164                                     "intr",
3165                                     "cnfg";
3166                         interrupt-names = "periph_irq";
3167                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3168                         qcom,ee = <0>;
3169                         qcom,channel = <0>;
3170                         interrupt-controller;
3171                         #interrupt-cells = <4>;
3172                         #address-cells = <2>;
3173                         #size-cells = <0>;
3174                 };
3175
3176                 ipcc: mailbox@ed18000 {
3177                         compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3178                         reg = <0 0x0ed18000 0 0x1000>;
3179                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3180                         interrupt-controller;
3181                         #interrupt-cells = <3>;
3182                         #mbox-cells = <2>;
3183                 };
3184
3185                 tlmm: pinctrl@f100000 {
3186                         compatible = "qcom,sm8450-tlmm";
3187                         reg = <0 0x0f100000 0 0x300000>;
3188                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3189                         gpio-controller;
3190                         #gpio-cells = <2>;
3191                         interrupt-controller;
3192                         #interrupt-cells = <2>;
3193                         gpio-ranges = <&tlmm 0 0 211>;
3194                         wakeup-parent = <&pdc>;
3195
3196                         sdc2_default_state: sdc2-default-state {
3197                                 clk-pins {
3198                                         pins = "sdc2_clk";
3199                                         drive-strength = <16>;
3200                                         bias-disable;
3201                                 };
3202
3203                                 cmd-pins {
3204                                         pins = "sdc2_cmd";
3205                                         drive-strength = <16>;
3206                                         bias-pull-up;
3207                                 };
3208
3209                                 data-pins {
3210                                         pins = "sdc2_data";
3211                                         drive-strength = <16>;
3212                                         bias-pull-up;
3213                                 };
3214                         };
3215
3216                         sdc2_sleep_state: sdc2-sleep-state {
3217                                 clk-pins {
3218                                         pins = "sdc2_clk";
3219                                         drive-strength = <2>;
3220                                         bias-disable;
3221                                 };
3222
3223                                 cmd-pins {
3224                                         pins = "sdc2_cmd";
3225                                         drive-strength = <2>;
3226                                         bias-pull-up;
3227                                 };
3228
3229                                 data-pins {
3230                                         pins = "sdc2_data";
3231                                         drive-strength = <2>;
3232                                         bias-pull-up;
3233                                 };
3234                         };
3235
3236                         cci0_default: cci0-default-state {
3237                                 /* SDA, SCL */
3238                                 pins = "gpio110", "gpio111";
3239                                 function = "cci_i2c";
3240                                 drive-strength = <2>;
3241                                 bias-pull-up;
3242                         };
3243
3244                         cci0_sleep: cci0-sleep-state {
3245                                 /* SDA, SCL */
3246                                 pins = "gpio110", "gpio111";
3247                                 function = "cci_i2c";
3248                                 drive-strength = <2>;
3249                                 bias-pull-down;
3250                         };
3251
3252                         cci1_default: cci1-default-state {
3253                                 /* SDA, SCL */
3254                                 pins = "gpio112", "gpio113";
3255                                 function = "cci_i2c";
3256                                 drive-strength = <2>;
3257                                 bias-pull-up;
3258                         };
3259
3260                         cci1_sleep: cci1-sleep-state {
3261                                 /* SDA, SCL */
3262                                 pins = "gpio112", "gpio113";
3263                                 function = "cci_i2c";
3264                                 drive-strength = <2>;
3265                                 bias-pull-down;
3266                         };
3267
3268                         cci2_default: cci2-default-state {
3269                                 /* SDA, SCL */
3270                                 pins = "gpio114", "gpio115";
3271                                 function = "cci_i2c";
3272                                 drive-strength = <2>;
3273                                 bias-pull-up;
3274                         };
3275
3276                         cci2_sleep: cci2-sleep-state {
3277                                 /* SDA, SCL */
3278                                 pins = "gpio114", "gpio115";
3279                                 function = "cci_i2c";
3280                                 drive-strength = <2>;
3281                                 bias-pull-down;
3282                         };
3283
3284                         cci3_default: cci3-default-state {
3285                                 /* SDA, SCL */
3286                                 pins = "gpio208", "gpio209";
3287                                 function = "cci_i2c";
3288                                 drive-strength = <2>;
3289                                 bias-pull-up;
3290                         };
3291
3292                         cci3_sleep: cci3-sleep-state {
3293                                 /* SDA, SCL */
3294                                 pins = "gpio208", "gpio209";
3295                                 function = "cci_i2c";
3296                                 drive-strength = <2>;
3297                                 bias-pull-down;
3298                         };
3299
3300                         pcie0_default_state: pcie0-default-state {
3301                                 perst-pins {
3302                                         pins = "gpio94";
3303                                         function = "gpio";
3304                                         drive-strength = <2>;
3305                                         bias-pull-down;
3306                                 };
3307
3308                                 clkreq-pins {
3309                                         pins = "gpio95";
3310                                         function = "pcie0_clkreqn";
3311                                         drive-strength = <2>;
3312                                         bias-pull-up;
3313                                 };
3314
3315                                 wake-pins {
3316                                         pins = "gpio96";
3317                                         function = "gpio";
3318                                         drive-strength = <2>;
3319                                         bias-pull-up;
3320                                 };
3321                         };
3322
3323                         pcie1_default_state: pcie1-default-state {
3324                                 perst-pins {
3325                                         pins = "gpio97";
3326                                         function = "gpio";
3327                                         drive-strength = <2>;
3328                                         bias-pull-down;
3329                                 };
3330
3331                                 clkreq-pins {
3332                                         pins = "gpio98";
3333                                         function = "pcie1_clkreqn";
3334                                         drive-strength = <2>;
3335                                         bias-pull-up;
3336                                 };
3337
3338                                 wake-pins {
3339                                         pins = "gpio99";
3340                                         function = "gpio";
3341                                         drive-strength = <2>;
3342                                         bias-pull-up;
3343                                 };
3344                         };
3345
3346                         qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3347                                 pins = "gpio0", "gpio1";
3348                                 function = "qup0";
3349                         };
3350
3351                         qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3352                                 pins = "gpio4", "gpio5";
3353                                 function = "qup1";
3354                         };
3355
3356                         qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3357                                 pins = "gpio8", "gpio9";
3358                                 function = "qup2";
3359                         };
3360
3361                         qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3362                                 pins = "gpio12", "gpio13";
3363                                 function = "qup3";
3364                         };
3365
3366                         qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3367                                 pins = "gpio16", "gpio17";
3368                                 function = "qup4";
3369                         };
3370
3371                         qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3372                                 pins = "gpio206", "gpio207";
3373                                 function = "qup5";
3374                         };
3375
3376                         qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3377                                 pins = "gpio20", "gpio21";
3378                                 function = "qup6";
3379                         };
3380
3381                         qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3382                                 pins = "gpio28", "gpio29";
3383                                 function = "qup8";
3384                         };
3385
3386                         qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3387                                 pins = "gpio32", "gpio33";
3388                                 function = "qup9";
3389                         };
3390
3391                         qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3392                                 pins = "gpio36", "gpio37";
3393                                 function = "qup10";
3394                         };
3395
3396                         qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3397                                 pins = "gpio40", "gpio41";
3398                                 function = "qup11";
3399                         };
3400
3401                         qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3402                                 pins = "gpio44", "gpio45";
3403                                 function = "qup12";
3404                         };
3405
3406                         qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3407                                 pins = "gpio48", "gpio49";
3408                                 function = "qup13";
3409                                 drive-strength = <2>;
3410                                 bias-pull-up;
3411                         };
3412
3413                         qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3414                                 pins = "gpio52", "gpio53";
3415                                 function = "qup14";
3416                                 drive-strength = <2>;
3417                                 bias-pull-up;
3418                         };
3419
3420                         qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3421                                 pins = "gpio56", "gpio57";
3422                                 function = "qup15";
3423                         };
3424
3425                         qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3426                                 pins = "gpio60", "gpio61";
3427                                 function = "qup16";
3428                         };
3429
3430                         qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3431                                 pins = "gpio64", "gpio65";
3432                                 function = "qup17";
3433                         };
3434
3435                         qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3436                                 pins = "gpio68", "gpio69";
3437                                 function = "qup18";
3438                         };
3439
3440                         qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3441                                 pins = "gpio72", "gpio73";
3442                                 function = "qup19";
3443                         };
3444
3445                         qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3446                                 pins = "gpio76", "gpio77";
3447                                 function = "qup20";
3448                         };
3449
3450                         qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3451                                 pins = "gpio80", "gpio81";
3452                                 function = "qup21";
3453                         };
3454
3455                         qup_spi0_cs: qup-spi0-cs-state {
3456                                 pins = "gpio3";
3457                                 function = "qup0";
3458                         };
3459
3460                         qup_spi0_data_clk: qup-spi0-data-clk-state {
3461                                 pins = "gpio0", "gpio1", "gpio2";
3462                                 function = "qup0";
3463                         };
3464
3465                         qup_spi1_cs: qup-spi1-cs-state {
3466                                 pins = "gpio7";
3467                                 function = "qup1";
3468                         };
3469
3470                         qup_spi1_data_clk: qup-spi1-data-clk-state {
3471                                 pins = "gpio4", "gpio5", "gpio6";
3472                                 function = "qup1";
3473                         };
3474
3475                         qup_spi2_cs: qup-spi2-cs-state {
3476                                 pins = "gpio11";
3477                                 function = "qup2";
3478                         };
3479
3480                         qup_spi2_data_clk: qup-spi2-data-clk-state {
3481                                 pins = "gpio8", "gpio9", "gpio10";
3482                                 function = "qup2";
3483                         };
3484
3485                         qup_spi3_cs: qup-spi3-cs-state {
3486                                 pins = "gpio15";
3487                                 function = "qup3";
3488                         };
3489
3490                         qup_spi3_data_clk: qup-spi3-data-clk-state {
3491                                 pins = "gpio12", "gpio13", "gpio14";
3492                                 function = "qup3";
3493                         };
3494
3495                         qup_spi4_cs: qup-spi4-cs-state {
3496                                 pins = "gpio19";
3497                                 function = "qup4";
3498                                 drive-strength = <6>;
3499                                 bias-disable;
3500                         };
3501
3502                         qup_spi4_data_clk: qup-spi4-data-clk-state {
3503                                 pins = "gpio16", "gpio17", "gpio18";
3504                                 function = "qup4";
3505                         };
3506
3507                         qup_spi5_cs: qup-spi5-cs-state {
3508                                 pins = "gpio85";
3509                                 function = "qup5";
3510                         };
3511
3512                         qup_spi5_data_clk: qup-spi5-data-clk-state {
3513                                 pins = "gpio206", "gpio207", "gpio84";
3514                                 function = "qup5";
3515                         };
3516
3517                         qup_spi6_cs: qup-spi6-cs-state {
3518                                 pins = "gpio23";
3519                                 function = "qup6";
3520                         };
3521
3522                         qup_spi6_data_clk: qup-spi6-data-clk-state {
3523                                 pins = "gpio20", "gpio21", "gpio22";
3524                                 function = "qup6";
3525                         };
3526
3527                         qup_spi8_cs: qup-spi8-cs-state {
3528                                 pins = "gpio31";
3529                                 function = "qup8";
3530                         };
3531
3532                         qup_spi8_data_clk: qup-spi8-data-clk-state {
3533                                 pins = "gpio28", "gpio29", "gpio30";
3534                                 function = "qup8";
3535                         };
3536
3537                         qup_spi9_cs: qup-spi9-cs-state {
3538                                 pins = "gpio35";
3539                                 function = "qup9";
3540                         };
3541
3542                         qup_spi9_data_clk: qup-spi9-data-clk-state {
3543                                 pins = "gpio32", "gpio33", "gpio34";
3544                                 function = "qup9";
3545                         };
3546
3547                         qup_spi10_cs: qup-spi10-cs-state {
3548                                 pins = "gpio39";
3549                                 function = "qup10";
3550                         };
3551
3552                         qup_spi10_data_clk: qup-spi10-data-clk-state {
3553                                 pins = "gpio36", "gpio37", "gpio38";
3554                                 function = "qup10";
3555                         };
3556
3557                         qup_spi11_cs: qup-spi11-cs-state {
3558                                 pins = "gpio43";
3559                                 function = "qup11";
3560                         };
3561
3562                         qup_spi11_data_clk: qup-spi11-data-clk-state {
3563                                 pins = "gpio40", "gpio41", "gpio42";
3564                                 function = "qup11";
3565                         };
3566
3567                         qup_spi12_cs: qup-spi12-cs-state {
3568                                 pins = "gpio47";
3569                                 function = "qup12";
3570                         };
3571
3572                         qup_spi12_data_clk: qup-spi12-data-clk-state {
3573                                 pins = "gpio44", "gpio45", "gpio46";
3574                                 function = "qup12";
3575                         };
3576
3577                         qup_spi13_cs: qup-spi13-cs-state {
3578                                 pins = "gpio51";
3579                                 function = "qup13";
3580                         };
3581
3582                         qup_spi13_data_clk: qup-spi13-data-clk-state {
3583                                 pins = "gpio48", "gpio49", "gpio50";
3584                                 function = "qup13";
3585                         };
3586
3587                         qup_spi14_cs: qup-spi14-cs-state {
3588                                 pins = "gpio55";
3589                                 function = "qup14";
3590                         };
3591
3592                         qup_spi14_data_clk: qup-spi14-data-clk-state {
3593                                 pins = "gpio52", "gpio53", "gpio54";
3594                                 function = "qup14";
3595                         };
3596
3597                         qup_spi15_cs: qup-spi15-cs-state {
3598                                 pins = "gpio59";
3599                                 function = "qup15";
3600                         };
3601
3602                         qup_spi15_data_clk: qup-spi15-data-clk-state {
3603                                 pins = "gpio56", "gpio57", "gpio58";
3604                                 function = "qup15";
3605                         };
3606
3607                         qup_spi16_cs: qup-spi16-cs-state {
3608                                 pins = "gpio63";
3609                                 function = "qup16";
3610                         };
3611
3612                         qup_spi16_data_clk: qup-spi16-data-clk-state {
3613                                 pins = "gpio60", "gpio61", "gpio62";
3614                                 function = "qup16";
3615                         };
3616
3617                         qup_spi17_cs: qup-spi17-cs-state {
3618                                 pins = "gpio67";
3619                                 function = "qup17";
3620                         };
3621
3622                         qup_spi17_data_clk: qup-spi17-data-clk-state {
3623                                 pins = "gpio64", "gpio65", "gpio66";
3624                                 function = "qup17";
3625                         };
3626
3627                         qup_spi18_cs: qup-spi18-cs-state {
3628                                 pins = "gpio71";
3629                                 function = "qup18";
3630                                 drive-strength = <6>;
3631                                 bias-disable;
3632                         };
3633
3634                         qup_spi18_data_clk: qup-spi18-data-clk-state {
3635                                 pins = "gpio68", "gpio69", "gpio70";
3636                                 function = "qup18";
3637                                 drive-strength = <6>;
3638                                 bias-disable;
3639                         };
3640
3641                         qup_spi19_cs: qup-spi19-cs-state {
3642                                 pins = "gpio75";
3643                                 function = "qup19";
3644                                 drive-strength = <6>;
3645                                 bias-disable;
3646                         };
3647
3648                         qup_spi19_data_clk: qup-spi19-data-clk-state {
3649                                 pins = "gpio72", "gpio73", "gpio74";
3650                                 function = "qup19";
3651                                 drive-strength = <6>;
3652                                 bias-disable;
3653                         };
3654
3655                         qup_spi20_cs: qup-spi20-cs-state {
3656                                 pins = "gpio79";
3657                                 function = "qup20";
3658                         };
3659
3660                         qup_spi20_data_clk: qup-spi20-data-clk-state {
3661                                 pins = "gpio76", "gpio77", "gpio78";
3662                                 function = "qup20";
3663                         };
3664
3665                         qup_spi21_cs: qup-spi21-cs-state {
3666                                 pins = "gpio83";
3667                                 function = "qup21";
3668                         };
3669
3670                         qup_spi21_data_clk: qup-spi21-data-clk-state {
3671                                 pins = "gpio80", "gpio81", "gpio82";
3672                                 function = "qup21";
3673                         };
3674
3675                         qup_uart7_rx: qup-uart7-rx-state {
3676                                 pins = "gpio26";
3677                                 function = "qup7";
3678                                 drive-strength = <2>;
3679                                 bias-disable;
3680                         };
3681
3682                         qup_uart7_tx: qup-uart7-tx-state {
3683                                 pins = "gpio27";
3684                                 function = "qup7";
3685                                 drive-strength = <2>;
3686                                 bias-disable;
3687                         };
3688
3689                         qup_uart20_default: qup-uart20-default-state {
3690                                 pins = "gpio76", "gpio77", "gpio78", "gpio79";
3691                                 function = "qup20";
3692                         };
3693                 };
3694
3695                 lpass_tlmm: pinctrl@3440000 {
3696                         compatible = "qcom,sm8450-lpass-lpi-pinctrl";
3697                         reg = <0 0x03440000 0x0 0x20000>,
3698                               <0 0x034d0000 0x0 0x10000>;
3699                         gpio-controller;
3700                         #gpio-cells = <2>;
3701                         gpio-ranges = <&lpass_tlmm 0 0 23>;
3702
3703                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3704                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3705                         clock-names = "core", "audio";
3706
3707                         tx_swr_active: tx-swr-active-state {
3708                                 clk-pins {
3709                                         pins = "gpio0";
3710                                         function = "swr_tx_clk";
3711                                         drive-strength = <2>;
3712                                         slew-rate = <1>;
3713                                         bias-disable;
3714                                 };
3715
3716                                 data-pins {
3717                                         pins = "gpio1", "gpio2", "gpio14";
3718                                         function = "swr_tx_data";
3719                                         drive-strength = <2>;
3720                                         slew-rate = <1>;
3721                                         bias-bus-hold;
3722                                 };
3723                         };
3724
3725                         rx_swr_active: rx-swr-active-state {
3726                                 clk-pins {
3727                                         pins = "gpio3";
3728                                         function = "swr_rx_clk";
3729                                         drive-strength = <2>;
3730                                         slew-rate = <1>;
3731                                         bias-disable;
3732                                 };
3733
3734                                 data-pins {
3735                                         pins = "gpio4", "gpio5";
3736                                         function = "swr_rx_data";
3737                                         drive-strength = <2>;
3738                                         slew-rate = <1>;
3739                                         bias-bus-hold;
3740                                 };
3741                         };
3742
3743                         dmic01_default: dmic01-default-state {
3744                                 clk-pins {
3745                                         pins = "gpio6";
3746                                         function = "dmic1_clk";
3747                                         drive-strength = <8>;
3748                                         output-high;
3749                                 };
3750
3751                                 data-pins {
3752                                         pins = "gpio7";
3753                                         function = "dmic1_data";
3754                                         drive-strength = <8>;
3755                                 };
3756                         };
3757
3758                         dmic02_default: dmic02-default-state {
3759                                 clk-pins {
3760                                         pins = "gpio8";
3761                                         function = "dmic2_clk";
3762                                         drive-strength = <8>;
3763                                         output-high;
3764                                 };
3765
3766                                 data-pins {
3767                                         pins = "gpio9";
3768                                         function = "dmic2_data";
3769                                         drive-strength = <8>;
3770                                 };
3771                         };
3772
3773                         wsa_swr_active: wsa-swr-active-state {
3774                                 clk-pins {
3775                                         pins = "gpio10";
3776                                         function = "wsa_swr_clk";
3777                                         drive-strength = <2>;
3778                                         slew-rate = <1>;
3779                                         bias-disable;
3780                                 };
3781
3782                                 data-pins {
3783                                         pins = "gpio11";
3784                                         function = "wsa_swr_data";
3785                                         drive-strength = <2>;
3786                                         slew-rate = <1>;
3787                                         bias-bus-hold;
3788                                 };
3789                         };
3790
3791                         wsa2_swr_active: wsa2-swr-active-state {
3792                                 clk-pins {
3793                                         pins = "gpio15";
3794                                         function = "wsa2_swr_clk";
3795                                         drive-strength = <2>;
3796                                         slew-rate = <1>;
3797                                         bias-disable;
3798                                 };
3799
3800                                 data-pins {
3801                                         pins = "gpio16";
3802                                         function = "wsa2_swr_data";
3803                                         drive-strength = <2>;
3804                                         slew-rate = <1>;
3805                                         bias-bus-hold;
3806                                 };
3807                         };
3808                 };
3809
3810                 sram@146aa000 {
3811                         compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
3812                         reg = <0 0x146aa000 0 0x1000>;
3813                         ranges = <0 0 0x146aa000 0x1000>;
3814
3815                         #address-cells = <1>;
3816                         #size-cells = <1>;
3817
3818                         pil-reloc@94c {
3819                                 compatible = "qcom,pil-reloc-info";
3820                                 reg = <0x94c 0xc8>;
3821                         };
3822                 };
3823
3824                 apps_smmu: iommu@15000000 {
3825                         compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
3826                         reg = <0 0x15000000 0 0x100000>;
3827                         #iommu-cells = <2>;
3828                         #global-interrupts = <1>;
3829                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3830                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3831                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3832                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3833                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3834                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3835                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3836                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3837                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3838                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3839                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3840                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3841                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3842                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3843                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3844                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3845                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3846                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3847                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3848                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3849                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3850                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3851                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3852                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3853                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3854                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3855                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3856                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3857                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3858                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3859                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3860                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3861                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3862                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3863                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3864                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3865                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3866                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3867                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3868                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3869                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3870                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3871                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3872                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3873                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3874                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3875                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3876                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3877                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3878                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3879                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3880                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3881                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3882                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3883                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3884                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3885                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3886                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3887                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3888                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3889                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3890                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3891                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3892                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3893                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3894                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3895                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3896                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3897                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3898                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3899                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3900                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3901                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3902                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3903                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3904                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3905                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3906                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3907                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3908                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3909                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3910                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3911                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3912                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3913                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3914                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3915                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3916                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3917                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3918                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3919                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3920                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3921                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3922                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3923                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3924                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3925                                      <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
3926                 };
3927
3928                 intc: interrupt-controller@17100000 {
3929                         compatible = "arm,gic-v3";
3930                         #interrupt-cells = <3>;
3931                         interrupt-controller;
3932                         #redistributor-regions = <1>;
3933                         redistributor-stride = <0x0 0x40000>;
3934                         reg = <0x0 0x17100000 0x0 0x10000>,     /* GICD */
3935                               <0x0 0x17180000 0x0 0x200000>;    /* GICR * 8 */
3936                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3937                         #address-cells = <2>;
3938                         #size-cells = <2>;
3939                         ranges;
3940
3941                         gic_its: msi-controller@17140000 {
3942                                 compatible = "arm,gic-v3-its";
3943                                 reg = <0x0 0x17140000 0x0 0x20000>;
3944                                 msi-controller;
3945                                 #msi-cells = <1>;
3946                         };
3947                 };
3948
3949                 timer@17420000 {
3950                         compatible = "arm,armv7-timer-mem";
3951                         #address-cells = <1>;
3952                         #size-cells = <1>;
3953                         ranges = <0 0 0 0x20000000>;
3954                         reg = <0x0 0x17420000 0x0 0x1000>;
3955                         clock-frequency = <19200000>;
3956
3957                         frame@17421000 {
3958                                 frame-number = <0>;
3959                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3960                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3961                                 reg = <0x17421000 0x1000>,
3962                                       <0x17422000 0x1000>;
3963                         };
3964
3965                         frame@17423000 {
3966                                 frame-number = <1>;
3967                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3968                                 reg = <0x17423000 0x1000>;
3969                                 status = "disabled";
3970                         };
3971
3972                         frame@17425000 {
3973                                 frame-number = <2>;
3974                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3975                                 reg = <0x17425000 0x1000>;
3976                                 status = "disabled";
3977                         };
3978
3979                         frame@17427000 {
3980                                 frame-number = <3>;
3981                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3982                                 reg = <0x17427000 0x1000>;
3983                                 status = "disabled";
3984                         };
3985
3986                         frame@17429000 {
3987                                 frame-number = <4>;
3988                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3989                                 reg = <0x17429000 0x1000>;
3990                                 status = "disabled";
3991                         };
3992
3993                         frame@1742b000 {
3994                                 frame-number = <5>;
3995                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3996                                 reg = <0x1742b000 0x1000>;
3997                                 status = "disabled";
3998                         };
3999
4000                         frame@1742d000 {
4001                                 frame-number = <6>;
4002                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4003                                 reg = <0x1742d000 0x1000>;
4004                                 status = "disabled";
4005                         };
4006                 };
4007
4008                 apps_rsc: rsc@17a00000 {
4009                         label = "apps_rsc";
4010                         compatible = "qcom,rpmh-rsc";
4011                         reg = <0x0 0x17a00000 0x0 0x10000>,
4012                               <0x0 0x17a10000 0x0 0x10000>,
4013                               <0x0 0x17a20000 0x0 0x10000>,
4014                               <0x0 0x17a30000 0x0 0x10000>;
4015                         reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4016                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4017                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4018                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4019                         qcom,tcs-offset = <0xd00>;
4020                         qcom,drv-id = <2>;
4021                         qcom,tcs-config = <ACTIVE_TCS  3>, <SLEEP_TCS   2>,
4022                                           <WAKE_TCS    2>, <CONTROL_TCS 0>;
4023                         power-domains = <&CLUSTER_PD>;
4024
4025                         apps_bcm_voter: bcm-voter {
4026                                 compatible = "qcom,bcm-voter";
4027                         };
4028
4029                         rpmhcc: clock-controller {
4030                                 compatible = "qcom,sm8450-rpmh-clk";
4031                                 #clock-cells = <1>;
4032                                 clock-names = "xo";
4033                                 clocks = <&xo_board>;
4034                         };
4035
4036                         rpmhpd: power-controller {
4037                                 compatible = "qcom,sm8450-rpmhpd";
4038                                 #power-domain-cells = <1>;
4039                                 operating-points-v2 = <&rpmhpd_opp_table>;
4040
4041                                 rpmhpd_opp_table: opp-table {
4042                                         compatible = "operating-points-v2";
4043
4044                                         rpmhpd_opp_ret: opp1 {
4045                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4046                                         };
4047
4048                                         rpmhpd_opp_min_svs: opp2 {
4049                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4050                                         };
4051
4052                                         rpmhpd_opp_low_svs_d1: opp3 {
4053                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4054                                         };
4055
4056                                         rpmhpd_opp_low_svs: opp4 {
4057                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4058                                         };
4059
4060                                         rpmhpd_opp_low_svs_l1: opp5 {
4061                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4062                                         };
4063
4064                                         rpmhpd_opp_svs: opp6 {
4065                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4066                                         };
4067
4068                                         rpmhpd_opp_svs_l0: opp7 {
4069                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4070                                         };
4071
4072                                         rpmhpd_opp_svs_l1: opp8 {
4073                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4074                                         };
4075
4076                                         rpmhpd_opp_svs_l2: opp9 {
4077                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4078                                         };
4079
4080                                         rpmhpd_opp_nom: opp10 {
4081                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4082                                         };
4083
4084                                         rpmhpd_opp_nom_l1: opp11 {
4085                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4086                                         };
4087
4088                                         rpmhpd_opp_nom_l2: opp12 {
4089                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4090                                         };
4091
4092                                         rpmhpd_opp_turbo: opp13 {
4093                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4094                                         };
4095
4096                                         rpmhpd_opp_turbo_l1: opp14 {
4097                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4098                                         };
4099                                 };
4100                         };
4101                 };
4102
4103                 cpufreq_hw: cpufreq@17d91000 {
4104                         compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4105                         reg = <0 0x17d91000 0 0x1000>,
4106                               <0 0x17d92000 0 0x1000>,
4107                               <0 0x17d93000 0 0x1000>;
4108                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4109                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4110                         clock-names = "xo", "alternate";
4111                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4112                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4113                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4114                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4115                         #freq-domain-cells = <1>;
4116                         #clock-cells = <1>;
4117                 };
4118
4119                 gem_noc: interconnect@19100000 {
4120                         compatible = "qcom,sm8450-gem-noc";
4121                         reg = <0 0x19100000 0 0xbb800>;
4122                         #interconnect-cells = <2>;
4123                         qcom,bcm-voters = <&apps_bcm_voter>;
4124                 };
4125
4126                 system-cache-controller@19200000 {
4127                         compatible = "qcom,sm8450-llcc";
4128                         reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4129                               <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4130                               <0 0x19a00000 0 0x80000>;
4131                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4132                                     "llcc3_base", "llcc_broadcast_base";
4133                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4134                 };
4135
4136                 ufs_mem_hc: ufshc@1d84000 {
4137                         compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4138                                      "jedec,ufs-2.0";
4139                         reg = <0 0x01d84000 0 0x3000>;
4140                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4141                         phys = <&ufs_mem_phy_lanes>;
4142                         phy-names = "ufsphy";
4143                         lanes-per-direction = <2>;
4144                         #reset-cells = <1>;
4145                         resets = <&gcc GCC_UFS_PHY_BCR>;
4146                         reset-names = "rst";
4147
4148                         power-domains = <&gcc UFS_PHY_GDSC>;
4149
4150                         iommus = <&apps_smmu 0xe0 0x0>;
4151                         dma-coherent;
4152
4153                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4154                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4155                         interconnect-names = "ufs-ddr", "cpu-ufs";
4156                         clock-names =
4157                                 "core_clk",
4158                                 "bus_aggr_clk",
4159                                 "iface_clk",
4160                                 "core_clk_unipro",
4161                                 "ref_clk",
4162                                 "tx_lane0_sync_clk",
4163                                 "rx_lane0_sync_clk",
4164                                 "rx_lane1_sync_clk";
4165                         clocks =
4166                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
4167                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4168                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
4169                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4170                                 <&rpmhcc RPMH_CXO_CLK>,
4171                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4172                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4173                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4174                         freq-table-hz =
4175                                 <75000000 300000000>,
4176                                 <0 0>,
4177                                 <0 0>,
4178                                 <75000000 300000000>,
4179                                 <75000000 300000000>,
4180                                 <0 0>,
4181                                 <0 0>,
4182                                 <0 0>;
4183                         qcom,ice = <&ice>;
4184
4185                         status = "disabled";
4186                 };
4187
4188                 ufs_mem_phy: phy@1d87000 {
4189                         compatible = "qcom,sm8450-qmp-ufs-phy";
4190                         reg = <0 0x01d87000 0 0x1c4>;
4191                         #address-cells = <2>;
4192                         #size-cells = <2>;
4193                         ranges;
4194                         clock-names = "ref", "ref_aux", "qref";
4195                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4196                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4197                                  <&gcc GCC_UFS_0_CLKREF_EN>;
4198
4199                         resets = <&ufs_mem_hc 0>;
4200                         reset-names = "ufsphy";
4201                         status = "disabled";
4202
4203                         ufs_mem_phy_lanes: phy@1d87400 {
4204                                 reg = <0 0x01d87400 0 0x188>,
4205                                       <0 0x01d87600 0 0x200>,
4206                                       <0 0x01d87c00 0 0x200>,
4207                                       <0 0x01d87800 0 0x188>,
4208                                       <0 0x01d87a00 0 0x200>;
4209                                 #clock-cells = <1>;
4210                                 #phy-cells = <0>;
4211                         };
4212                 };
4213
4214                 ice: crypto@1d88000 {
4215                         compatible = "qcom,sm8450-inline-crypto-engine",
4216                                      "qcom,inline-crypto-engine";
4217                         reg = <0 0x01d88000 0 0x8000>;
4218                         clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4219                 };
4220
4221                 cryptobam: dma-controller@1dc4000 {
4222                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4223                         reg = <0 0x01dc4000 0 0x28000>;
4224                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4225                         #dma-cells = <1>;
4226                         qcom,ee = <0>;
4227                         qcom,controlled-remotely;
4228                         iommus = <&apps_smmu 0x584 0x11>,
4229                                  <&apps_smmu 0x588 0x0>,
4230                                  <&apps_smmu 0x598 0x5>,
4231                                  <&apps_smmu 0x59a 0x0>,
4232                                  <&apps_smmu 0x59f 0x0>;
4233                 };
4234
4235                 crypto: crypto@1dfa000 {
4236                         compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4237                         reg = <0 0x01dfa000 0 0x6000>;
4238                         dmas = <&cryptobam 4>, <&cryptobam 5>;
4239                         dma-names = "rx", "tx";
4240                         iommus = <&apps_smmu 0x584 0x11>,
4241                                  <&apps_smmu 0x588 0x0>,
4242                                  <&apps_smmu 0x598 0x5>,
4243                                  <&apps_smmu 0x59a 0x0>,
4244                                  <&apps_smmu 0x59f 0x0>;
4245                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4246                         interconnect-names = "memory";
4247                 };
4248
4249                 sdhc_2: mmc@8804000 {
4250                         compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4251                         reg = <0 0x08804000 0 0x1000>;
4252
4253                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4254                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4255                         interrupt-names = "hc_irq", "pwr_irq";
4256
4257                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4258                                  <&gcc GCC_SDCC2_APPS_CLK>,
4259                                  <&rpmhcc RPMH_CXO_CLK>;
4260                         clock-names = "iface", "core", "xo";
4261                         resets = <&gcc GCC_SDCC2_BCR>;
4262                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4263                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4264                         interconnect-names = "sdhc-ddr","cpu-sdhc";
4265                         iommus = <&apps_smmu 0x4a0 0x0>;
4266                         power-domains = <&rpmhpd RPMHPD_CX>;
4267                         operating-points-v2 = <&sdhc2_opp_table>;
4268                         bus-width = <4>;
4269                         dma-coherent;
4270
4271                         /* Forbid SDR104/SDR50 - broken hw! */
4272                         sdhci-caps-mask = <0x3 0x0>;
4273
4274                         status = "disabled";
4275
4276                         sdhc2_opp_table: opp-table {
4277                                 compatible = "operating-points-v2";
4278
4279                                 opp-100000000 {
4280                                         opp-hz = /bits/ 64 <100000000>;
4281                                         required-opps = <&rpmhpd_opp_low_svs>;
4282                                 };
4283
4284                                 opp-202000000 {
4285                                         opp-hz = /bits/ 64 <202000000>;
4286                                         required-opps = <&rpmhpd_opp_svs_l1>;
4287                                 };
4288                         };
4289                 };
4290
4291                 usb_1: usb@a6f8800 {
4292                         compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4293                         reg = <0 0x0a6f8800 0 0x400>;
4294                         status = "disabled";
4295                         #address-cells = <2>;
4296                         #size-cells = <2>;
4297                         ranges;
4298
4299                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4300                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4301                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4302                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4303                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4304                                  <&gcc GCC_USB3_0_CLKREF_EN>;
4305                         clock-names = "cfg_noc",
4306                                       "core",
4307                                       "iface",
4308                                       "sleep",
4309                                       "mock_utmi",
4310                                       "xo";
4311
4312                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4313                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4314                         assigned-clock-rates = <19200000>, <200000000>;
4315
4316                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4317                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4318                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4319                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4320                         interrupt-names = "hs_phy_irq",
4321                                           "ss_phy_irq",
4322                                           "dm_hs_phy_irq",
4323                                           "dp_hs_phy_irq";
4324
4325                         power-domains = <&gcc USB30_PRIM_GDSC>;
4326
4327                         resets = <&gcc GCC_USB30_PRIM_BCR>;
4328
4329                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4330                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4331                         interconnect-names = "usb-ddr", "apps-usb";
4332
4333                         usb_1_dwc3: usb@a600000 {
4334                                 compatible = "snps,dwc3";
4335                                 reg = <0 0x0a600000 0 0xcd00>;
4336                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4337                                 iommus = <&apps_smmu 0x0 0x0>;
4338                                 snps,dis_u2_susphy_quirk;
4339                                 snps,dis_enblslpm_quirk;
4340                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4341                                 phy-names = "usb2-phy", "usb3-phy";
4342
4343                                 ports {
4344                                         #address-cells = <1>;
4345                                         #size-cells = <0>;
4346
4347                                         port@0 {
4348                                                 reg = <0>;
4349
4350                                                 usb_1_dwc3_hs: endpoint {
4351                                                 };
4352                                         };
4353
4354                                         port@1 {
4355                                                 reg = <1>;
4356
4357                                                 usb_1_dwc3_ss: endpoint {
4358                                                 };
4359                                         };
4360                                 };
4361                         };
4362                 };
4363
4364                 nsp_noc: interconnect@320c0000 {
4365                         compatible = "qcom,sm8450-nsp-noc";
4366                         reg = <0 0x320c0000 0 0x10000>;
4367                         #interconnect-cells = <2>;
4368                         qcom,bcm-voters = <&apps_bcm_voter>;
4369                 };
4370
4371                 lpass_ag_noc: interconnect@3c40000 {
4372                         compatible = "qcom,sm8450-lpass-ag-noc";
4373                         reg = <0 0x03c40000 0 0x17200>;
4374                         #interconnect-cells = <2>;
4375                         qcom,bcm-voters = <&apps_bcm_voter>;
4376                 };
4377         };
4378
4379         sound: sound {
4380         };
4381
4382         thermal-zones {
4383                 aoss0-thermal {
4384                         polling-delay-passive = <0>;
4385                         polling-delay = <0>;
4386                         thermal-sensors = <&tsens0 0>;
4387
4388                         trips {
4389                                 thermal-engine-config {
4390                                         temperature = <125000>;
4391                                         hysteresis = <1000>;
4392                                         type = "passive";
4393                                 };
4394
4395                                 reset-mon-cfg {
4396                                         temperature = <115000>;
4397                                         hysteresis = <5000>;
4398                                         type = "passive";
4399                                 };
4400                         };
4401                 };
4402
4403                 cpuss0-thermal {
4404                         polling-delay-passive = <0>;
4405                         polling-delay = <0>;
4406                         thermal-sensors = <&tsens0 1>;
4407
4408                         trips {
4409                                 thermal-engine-config {
4410                                         temperature = <125000>;
4411                                         hysteresis = <1000>;
4412                                         type = "passive";
4413                                 };
4414
4415                                 reset-mon-cfg {
4416                                         temperature = <115000>;
4417                                         hysteresis = <5000>;
4418                                         type = "passive";
4419                                 };
4420                         };
4421                 };
4422
4423                 cpuss1-thermal {
4424                         polling-delay-passive = <0>;
4425                         polling-delay = <0>;
4426                         thermal-sensors = <&tsens0 2>;
4427
4428                         trips {
4429                                 thermal-engine-config {
4430                                         temperature = <125000>;
4431                                         hysteresis = <1000>;
4432                                         type = "passive";
4433                                 };
4434
4435                                 reset-mon-cfg {
4436                                         temperature = <115000>;
4437                                         hysteresis = <5000>;
4438                                         type = "passive";
4439                                 };
4440                         };
4441                 };
4442
4443                 cpuss3-thermal {
4444                         polling-delay-passive = <0>;
4445                         polling-delay = <0>;
4446                         thermal-sensors = <&tsens0 3>;
4447
4448                         trips {
4449                                 thermal-engine-config {
4450                                         temperature = <125000>;
4451                                         hysteresis = <1000>;
4452                                         type = "passive";
4453                                 };
4454
4455                                 reset-mon-cfg {
4456                                         temperature = <115000>;
4457                                         hysteresis = <5000>;
4458                                         type = "passive";
4459                                 };
4460                         };
4461                 };
4462
4463                 cpuss4-thermal {
4464                         polling-delay-passive = <0>;
4465                         polling-delay = <0>;
4466                         thermal-sensors = <&tsens0 4>;
4467
4468                         trips {
4469                                 thermal-engine-config {
4470                                         temperature = <125000>;
4471                                         hysteresis = <1000>;
4472                                         type = "passive";
4473                                 };
4474
4475                                 reset-mon-cfg {
4476                                         temperature = <115000>;
4477                                         hysteresis = <5000>;
4478                                         type = "passive";
4479                                 };
4480                         };
4481                 };
4482
4483                 cpu4-top-thermal {
4484                         polling-delay-passive = <0>;
4485                         polling-delay = <0>;
4486                         thermal-sensors = <&tsens0 5>;
4487
4488                         trips {
4489                                 cpu4_top_alert0: trip-point0 {
4490                                         temperature = <90000>;
4491                                         hysteresis = <2000>;
4492                                         type = "passive";
4493                                 };
4494
4495                                 cpu4_top_alert1: trip-point1 {
4496                                         temperature = <95000>;
4497                                         hysteresis = <2000>;
4498                                         type = "passive";
4499                                 };
4500
4501                                 cpu4_top_crit: cpu-crit {
4502                                         temperature = <110000>;
4503                                         hysteresis = <1000>;
4504                                         type = "critical";
4505                                 };
4506                         };
4507                 };
4508
4509                 cpu4-bottom-thermal {
4510                         polling-delay-passive = <0>;
4511                         polling-delay = <0>;
4512                         thermal-sensors = <&tsens0 6>;
4513
4514                         trips {
4515                                 cpu4_bottom_alert0: trip-point0 {
4516                                         temperature = <90000>;
4517                                         hysteresis = <2000>;
4518                                         type = "passive";
4519                                 };
4520
4521                                 cpu4_bottom_alert1: trip-point1 {
4522                                         temperature = <95000>;
4523                                         hysteresis = <2000>;
4524                                         type = "passive";
4525                                 };
4526
4527                                 cpu4_bottom_crit: cpu-crit {
4528                                         temperature = <110000>;
4529                                         hysteresis = <1000>;
4530                                         type = "critical";
4531                                 };
4532                         };
4533                 };
4534
4535                 cpu5-top-thermal {
4536                         polling-delay-passive = <0>;
4537                         polling-delay = <0>;
4538                         thermal-sensors = <&tsens0 7>;
4539
4540                         trips {
4541                                 cpu5_top_alert0: trip-point0 {
4542                                         temperature = <90000>;
4543                                         hysteresis = <2000>;
4544                                         type = "passive";
4545                                 };
4546
4547                                 cpu5_top_alert1: trip-point1 {
4548                                         temperature = <95000>;
4549                                         hysteresis = <2000>;
4550                                         type = "passive";
4551                                 };
4552
4553                                 cpu5_top_crit: cpu-crit {
4554                                         temperature = <110000>;
4555                                         hysteresis = <1000>;
4556                                         type = "critical";
4557                                 };
4558                         };
4559                 };
4560
4561                 cpu5-bottom-thermal {
4562                         polling-delay-passive = <0>;
4563                         polling-delay = <0>;
4564                         thermal-sensors = <&tsens0 8>;
4565
4566                         trips {
4567                                 cpu5_bottom_alert0: trip-point0 {
4568                                         temperature = <90000>;
4569                                         hysteresis = <2000>;
4570                                         type = "passive";
4571                                 };
4572
4573                                 cpu5_bottom_alert1: trip-point1 {
4574                                         temperature = <95000>;
4575                                         hysteresis = <2000>;
4576                                         type = "passive";
4577                                 };
4578
4579                                 cpu5_bottom_crit: cpu-crit {
4580                                         temperature = <110000>;
4581                                         hysteresis = <1000>;
4582                                         type = "critical";
4583                                 };
4584                         };
4585                 };
4586
4587                 cpu6-top-thermal {
4588                         polling-delay-passive = <0>;
4589                         polling-delay = <0>;
4590                         thermal-sensors = <&tsens0 9>;
4591
4592                         trips {
4593                                 cpu6_top_alert0: trip-point0 {
4594                                         temperature = <90000>;
4595                                         hysteresis = <2000>;
4596                                         type = "passive";
4597                                 };
4598
4599                                 cpu6_top_alert1: trip-point1 {
4600                                         temperature = <95000>;
4601                                         hysteresis = <2000>;
4602                                         type = "passive";
4603                                 };
4604
4605                                 cpu6_top_crit: cpu-crit {
4606                                         temperature = <110000>;
4607                                         hysteresis = <1000>;
4608                                         type = "critical";
4609                                 };
4610                         };
4611                 };
4612
4613                 cpu6-bottom-thermal {
4614                         polling-delay-passive = <0>;
4615                         polling-delay = <0>;
4616                         thermal-sensors = <&tsens0 10>;
4617
4618                         trips {
4619                                 cpu6_bottom_alert0: trip-point0 {
4620                                         temperature = <90000>;
4621                                         hysteresis = <2000>;
4622                                         type = "passive";
4623                                 };
4624
4625                                 cpu6_bottom_alert1: trip-point1 {
4626                                         temperature = <95000>;
4627                                         hysteresis = <2000>;
4628                                         type = "passive";
4629                                 };
4630
4631                                 cpu6_bottom_crit: cpu-crit {
4632                                         temperature = <110000>;
4633                                         hysteresis = <1000>;
4634                                         type = "critical";
4635                                 };
4636                         };
4637                 };
4638
4639                 cpu7-top-thermal {
4640                         polling-delay-passive = <0>;
4641                         polling-delay = <0>;
4642                         thermal-sensors = <&tsens0 11>;
4643
4644                         trips {
4645                                 cpu7_top_alert0: trip-point0 {
4646                                         temperature = <90000>;
4647                                         hysteresis = <2000>;
4648                                         type = "passive";
4649                                 };
4650
4651                                 cpu7_top_alert1: trip-point1 {
4652                                         temperature = <95000>;
4653                                         hysteresis = <2000>;
4654                                         type = "passive";
4655                                 };
4656
4657                                 cpu7_top_crit: cpu-crit {
4658                                         temperature = <110000>;
4659                                         hysteresis = <1000>;
4660                                         type = "critical";
4661                                 };
4662                         };
4663                 };
4664
4665                 cpu7-middle-thermal {
4666                         polling-delay-passive = <0>;
4667                         polling-delay = <0>;
4668                         thermal-sensors = <&tsens0 12>;
4669
4670                         trips {
4671                                 cpu7_middle_alert0: trip-point0 {
4672                                         temperature = <90000>;
4673                                         hysteresis = <2000>;
4674                                         type = "passive";
4675                                 };
4676
4677                                 cpu7_middle_alert1: trip-point1 {
4678                                         temperature = <95000>;
4679                                         hysteresis = <2000>;
4680                                         type = "passive";
4681                                 };
4682
4683                                 cpu7_middle_crit: cpu-crit {
4684                                         temperature = <110000>;
4685                                         hysteresis = <1000>;
4686                                         type = "critical";
4687                                 };
4688                         };
4689                 };
4690
4691                 cpu7-bottom-thermal {
4692                         polling-delay-passive = <0>;
4693                         polling-delay = <0>;
4694                         thermal-sensors = <&tsens0 13>;
4695
4696                         trips {
4697                                 cpu7_bottom_alert0: trip-point0 {
4698                                         temperature = <90000>;
4699                                         hysteresis = <2000>;
4700                                         type = "passive";
4701                                 };
4702
4703                                 cpu7_bottom_alert1: trip-point1 {
4704                                         temperature = <95000>;
4705                                         hysteresis = <2000>;
4706                                         type = "passive";
4707                                 };
4708
4709                                 cpu7_bottom_crit: cpu-crit {
4710                                         temperature = <110000>;
4711                                         hysteresis = <1000>;
4712                                         type = "critical";
4713                                 };
4714                         };
4715                 };
4716
4717                 gpu-top-thermal {
4718                         polling-delay-passive = <10>;
4719                         polling-delay = <0>;
4720                         thermal-sensors = <&tsens0 14>;
4721
4722                         trips {
4723                                 thermal-engine-config {
4724                                         temperature = <125000>;
4725                                         hysteresis = <1000>;
4726                                         type = "passive";
4727                                 };
4728
4729                                 thermal-hal-config {
4730                                         temperature = <125000>;
4731                                         hysteresis = <1000>;
4732                                         type = "passive";
4733                                 };
4734
4735                                 reset-mon-cfg {
4736                                         temperature = <115000>;
4737                                         hysteresis = <5000>;
4738                                         type = "passive";
4739                                 };
4740
4741                                 gpu0_tj_cfg: tj-cfg {
4742                                         temperature = <95000>;
4743                                         hysteresis = <5000>;
4744                                         type = "passive";
4745                                 };
4746                         };
4747                 };
4748
4749                 gpu-bottom-thermal {
4750                         polling-delay-passive = <10>;
4751                         polling-delay = <0>;
4752                         thermal-sensors = <&tsens0 15>;
4753
4754                         trips {
4755                                 thermal-engine-config {
4756                                         temperature = <125000>;
4757                                         hysteresis = <1000>;
4758                                         type = "passive";
4759                                 };
4760
4761                                 thermal-hal-config {
4762                                         temperature = <125000>;
4763                                         hysteresis = <1000>;
4764                                         type = "passive";
4765                                 };
4766
4767                                 reset-mon-cfg {
4768                                         temperature = <115000>;
4769                                         hysteresis = <5000>;
4770                                         type = "passive";
4771                                 };
4772
4773                                 gpu1_tj_cfg: tj-cfg {
4774                                         temperature = <95000>;
4775                                         hysteresis = <5000>;
4776                                         type = "passive";
4777                                 };
4778                         };
4779                 };
4780
4781                 aoss1-thermal {
4782                         polling-delay-passive = <0>;
4783                         polling-delay = <0>;
4784                         thermal-sensors = <&tsens1 0>;
4785
4786                         trips {
4787                                 thermal-engine-config {
4788                                         temperature = <125000>;
4789                                         hysteresis = <1000>;
4790                                         type = "passive";
4791                                 };
4792
4793                                 reset-mon-cfg {
4794                                         temperature = <115000>;
4795                                         hysteresis = <5000>;
4796                                         type = "passive";
4797                                 };
4798                         };
4799                 };
4800
4801                 cpu0-thermal {
4802                         polling-delay-passive = <0>;
4803                         polling-delay = <0>;
4804                         thermal-sensors = <&tsens1 1>;
4805
4806                         trips {
4807                                 cpu0_alert0: trip-point0 {
4808                                         temperature = <90000>;
4809                                         hysteresis = <2000>;
4810                                         type = "passive";
4811                                 };
4812
4813                                 cpu0_alert1: trip-point1 {
4814                                         temperature = <95000>;
4815                                         hysteresis = <2000>;
4816                                         type = "passive";
4817                                 };
4818
4819                                 cpu0_crit: cpu-crit {
4820                                         temperature = <110000>;
4821                                         hysteresis = <1000>;
4822                                         type = "critical";
4823                                 };
4824                         };
4825                 };
4826
4827                 cpu1-thermal {
4828                         polling-delay-passive = <0>;
4829                         polling-delay = <0>;
4830                         thermal-sensors = <&tsens1 2>;
4831
4832                         trips {
4833                                 cpu1_alert0: trip-point0 {
4834                                         temperature = <90000>;
4835                                         hysteresis = <2000>;
4836                                         type = "passive";
4837                                 };
4838
4839                                 cpu1_alert1: trip-point1 {
4840                                         temperature = <95000>;
4841                                         hysteresis = <2000>;
4842                                         type = "passive";
4843                                 };
4844
4845                                 cpu1_crit: cpu-crit {
4846                                         temperature = <110000>;
4847                                         hysteresis = <1000>;
4848                                         type = "critical";
4849                                 };
4850                         };
4851                 };
4852
4853                 cpu2-thermal {
4854                         polling-delay-passive = <0>;
4855                         polling-delay = <0>;
4856                         thermal-sensors = <&tsens1 3>;
4857
4858                         trips {
4859                                 cpu2_alert0: trip-point0 {
4860                                         temperature = <90000>;
4861                                         hysteresis = <2000>;
4862                                         type = "passive";
4863                                 };
4864
4865                                 cpu2_alert1: trip-point1 {
4866                                         temperature = <95000>;
4867                                         hysteresis = <2000>;
4868                                         type = "passive";
4869                                 };
4870
4871                                 cpu2_crit: cpu-crit {
4872                                         temperature = <110000>;
4873                                         hysteresis = <1000>;
4874                                         type = "critical";
4875                                 };
4876                         };
4877                 };
4878
4879                 cpu3-thermal {
4880                         polling-delay-passive = <0>;
4881                         polling-delay = <0>;
4882                         thermal-sensors = <&tsens1 4>;
4883
4884                         trips {
4885                                 cpu3_alert0: trip-point0 {
4886                                         temperature = <90000>;
4887                                         hysteresis = <2000>;
4888                                         type = "passive";
4889                                 };
4890
4891                                 cpu3_alert1: trip-point1 {
4892                                         temperature = <95000>;
4893                                         hysteresis = <2000>;
4894                                         type = "passive";
4895                                 };
4896
4897                                 cpu3_crit: cpu-crit {
4898                                         temperature = <110000>;
4899                                         hysteresis = <1000>;
4900                                         type = "critical";
4901                                 };
4902                         };
4903                 };
4904
4905                 cdsp0-thermal {
4906                         polling-delay-passive = <10>;
4907                         polling-delay = <0>;
4908                         thermal-sensors = <&tsens1 5>;
4909
4910                         trips {
4911                                 thermal-engine-config {
4912                                         temperature = <125000>;
4913                                         hysteresis = <1000>;
4914                                         type = "passive";
4915                                 };
4916
4917                                 thermal-hal-config {
4918                                         temperature = <125000>;
4919                                         hysteresis = <1000>;
4920                                         type = "passive";
4921                                 };
4922
4923                                 reset-mon-cfg {
4924                                         temperature = <115000>;
4925                                         hysteresis = <5000>;
4926                                         type = "passive";
4927                                 };
4928
4929                                 cdsp_0_config: junction-config {
4930                                         temperature = <95000>;
4931                                         hysteresis = <5000>;
4932                                         type = "passive";
4933                                 };
4934                         };
4935                 };
4936
4937                 cdsp1-thermal {
4938                         polling-delay-passive = <10>;
4939                         polling-delay = <0>;
4940                         thermal-sensors = <&tsens1 6>;
4941
4942                         trips {
4943                                 thermal-engine-config {
4944                                         temperature = <125000>;
4945                                         hysteresis = <1000>;
4946                                         type = "passive";
4947                                 };
4948
4949                                 thermal-hal-config {
4950                                         temperature = <125000>;
4951                                         hysteresis = <1000>;
4952                                         type = "passive";
4953                                 };
4954
4955                                 reset-mon-cfg {
4956                                         temperature = <115000>;
4957                                         hysteresis = <5000>;
4958                                         type = "passive";
4959                                 };
4960
4961                                 cdsp_1_config: junction-config {
4962                                         temperature = <95000>;
4963                                         hysteresis = <5000>;
4964                                         type = "passive";
4965                                 };
4966                         };
4967                 };
4968
4969                 cdsp2-thermal {
4970                         polling-delay-passive = <10>;
4971                         polling-delay = <0>;
4972                         thermal-sensors = <&tsens1 7>;
4973
4974                         trips {
4975                                 thermal-engine-config {
4976                                         temperature = <125000>;
4977                                         hysteresis = <1000>;
4978                                         type = "passive";
4979                                 };
4980
4981                                 thermal-hal-config {
4982                                         temperature = <125000>;
4983                                         hysteresis = <1000>;
4984                                         type = "passive";
4985                                 };
4986
4987                                 reset-mon-cfg {
4988                                         temperature = <115000>;
4989                                         hysteresis = <5000>;
4990                                         type = "passive";
4991                                 };
4992
4993                                 cdsp_2_config: junction-config {
4994                                         temperature = <95000>;
4995                                         hysteresis = <5000>;
4996                                         type = "passive";
4997                                 };
4998                         };
4999                 };
5000
5001                 video-thermal {
5002                         polling-delay-passive = <0>;
5003                         polling-delay = <0>;
5004                         thermal-sensors = <&tsens1 8>;
5005
5006                         trips {
5007                                 thermal-engine-config {
5008                                         temperature = <125000>;
5009                                         hysteresis = <1000>;
5010                                         type = "passive";
5011                                 };
5012
5013                                 reset-mon-cfg {
5014                                         temperature = <115000>;
5015                                         hysteresis = <5000>;
5016                                         type = "passive";
5017                                 };
5018                         };
5019                 };
5020
5021                 mem-thermal {
5022                         polling-delay-passive = <10>;
5023                         polling-delay = <0>;
5024                         thermal-sensors = <&tsens1 9>;
5025
5026                         trips {
5027                                 thermal-engine-config {
5028                                         temperature = <125000>;
5029                                         hysteresis = <1000>;
5030                                         type = "passive";
5031                                 };
5032
5033                                 ddr_config0: ddr0-config {
5034                                         temperature = <90000>;
5035                                         hysteresis = <5000>;
5036                                         type = "passive";
5037                                 };
5038
5039                                 reset-mon-cfg {
5040                                         temperature = <115000>;
5041                                         hysteresis = <5000>;
5042                                         type = "passive";
5043                                 };
5044                         };
5045                 };
5046
5047                 modem0-thermal {
5048                         polling-delay-passive = <0>;
5049                         polling-delay = <0>;
5050                         thermal-sensors = <&tsens1 10>;
5051
5052                         trips {
5053                                 thermal-engine-config {
5054                                         temperature = <125000>;
5055                                         hysteresis = <1000>;
5056                                         type = "passive";
5057                                 };
5058
5059                                 mdmss0_config0: mdmss0-config0 {
5060                                         temperature = <102000>;
5061                                         hysteresis = <3000>;
5062                                         type = "passive";
5063                                 };
5064
5065                                 mdmss0_config1: mdmss0-config1 {
5066                                         temperature = <105000>;
5067                                         hysteresis = <3000>;
5068                                         type = "passive";
5069                                 };
5070
5071                                 reset-mon-cfg {
5072                                         temperature = <115000>;
5073                                         hysteresis = <5000>;
5074                                         type = "passive";
5075                                 };
5076                         };
5077                 };
5078
5079                 modem1-thermal {
5080                         polling-delay-passive = <0>;
5081                         polling-delay = <0>;
5082                         thermal-sensors = <&tsens1 11>;
5083
5084                         trips {
5085                                 thermal-engine-config {
5086                                         temperature = <125000>;
5087                                         hysteresis = <1000>;
5088                                         type = "passive";
5089                                 };
5090
5091                                 mdmss1_config0: mdmss1-config0 {
5092                                         temperature = <102000>;
5093                                         hysteresis = <3000>;
5094                                         type = "passive";
5095                                 };
5096
5097                                 mdmss1_config1: mdmss1-config1 {
5098                                         temperature = <105000>;
5099                                         hysteresis = <3000>;
5100                                         type = "passive";
5101                                 };
5102
5103                                 reset-mon-cfg {
5104                                         temperature = <115000>;
5105                                         hysteresis = <5000>;
5106                                         type = "passive";
5107                                 };
5108                         };
5109                 };
5110
5111                 modem2-thermal {
5112                         polling-delay-passive = <0>;
5113                         polling-delay = <0>;
5114                         thermal-sensors = <&tsens1 12>;
5115
5116                         trips {
5117                                 thermal-engine-config {
5118                                         temperature = <125000>;
5119                                         hysteresis = <1000>;
5120                                         type = "passive";
5121                                 };
5122
5123                                 mdmss2_config0: mdmss2-config0 {
5124                                         temperature = <102000>;
5125                                         hysteresis = <3000>;
5126                                         type = "passive";
5127                                 };
5128
5129                                 mdmss2_config1: mdmss2-config1 {
5130                                         temperature = <105000>;
5131                                         hysteresis = <3000>;
5132                                         type = "passive";
5133                                 };
5134
5135                                 reset-mon-cfg {
5136                                         temperature = <115000>;
5137                                         hysteresis = <5000>;
5138                                         type = "passive";
5139                                 };
5140                         };
5141                 };
5142
5143                 modem3-thermal {
5144                         polling-delay-passive = <0>;
5145                         polling-delay = <0>;
5146                         thermal-sensors = <&tsens1 13>;
5147
5148                         trips {
5149                                 thermal-engine-config {
5150                                         temperature = <125000>;
5151                                         hysteresis = <1000>;
5152                                         type = "passive";
5153                                 };
5154
5155                                 mdmss3_config0: mdmss3-config0 {
5156                                         temperature = <102000>;
5157                                         hysteresis = <3000>;
5158                                         type = "passive";
5159                                 };
5160
5161                                 mdmss3_config1: mdmss3-config1 {
5162                                         temperature = <105000>;
5163                                         hysteresis = <3000>;
5164                                         type = "passive";
5165                                 };
5166
5167                                 reset-mon-cfg {
5168                                         temperature = <115000>;
5169                                         hysteresis = <5000>;
5170                                         type = "passive";
5171                                 };
5172                         };
5173                 };
5174
5175                 camera0-thermal {
5176                         polling-delay-passive = <0>;
5177                         polling-delay = <0>;
5178                         thermal-sensors = <&tsens1 14>;
5179
5180                         trips {
5181                                 thermal-engine-config {
5182                                         temperature = <125000>;
5183                                         hysteresis = <1000>;
5184                                         type = "passive";
5185                                 };
5186
5187                                 reset-mon-cfg {
5188                                         temperature = <115000>;
5189                                         hysteresis = <5000>;
5190                                         type = "passive";
5191                                 };
5192                         };
5193                 };
5194
5195                 camera1-thermal {
5196                         polling-delay-passive = <0>;
5197                         polling-delay = <0>;
5198                         thermal-sensors = <&tsens1 15>;
5199
5200                         trips {
5201                                 thermal-engine-config {
5202                                         temperature = <125000>;
5203                                         hysteresis = <1000>;
5204                                         type = "passive";
5205                                 };
5206
5207                                 reset-mon-cfg {
5208                                         temperature = <115000>;
5209                                         hysteresis = <5000>;
5210                                         type = "passive";
5211                                 };
5212                         };
5213                 };
5214         };
5215
5216         timer {
5217                 compatible = "arm,armv8-timer";
5218                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5219                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5220                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5221                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5222                 clock-frequency = <19200000>;
5223         };
5224 };