1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, Linaro Limited
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interconnect/qcom,sm8350.h>
13 #include <dt-bindings/mailbox/qcom-ipcc.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/interconnect/qcom,sm8350.h>
20 interrupt-parent = <&intc>;
29 compatible = "fixed-clock";
31 clock-frequency = <38400000>;
32 clock-output-names = "xo_board";
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 clock-frequency = <32000>;
41 ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
42 compatible = "fixed-clock";
43 clock-frequency = <1000>;
47 ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
48 compatible = "fixed-clock";
49 clock-frequency = <1000>;
53 ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
54 compatible = "fixed-clock";
55 clock-frequency = <1000>;
66 compatible = "qcom,kryo685";
68 enable-method = "psci";
69 next-level-cache = <&L2_0>;
70 qcom,freq-domain = <&cpufreq_hw 0>;
71 power-domains = <&CPU_PD0>;
72 power-domain-names = "psci";
76 next-level-cache = <&L3_0>;
85 compatible = "qcom,kryo685";
87 enable-method = "psci";
88 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&cpufreq_hw 0>;
90 power-domains = <&CPU_PD1>;
91 power-domain-names = "psci";
95 next-level-cache = <&L3_0>;
101 compatible = "qcom,kryo685";
103 enable-method = "psci";
104 next-level-cache = <&L2_200>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 power-domains = <&CPU_PD2>;
107 power-domain-names = "psci";
108 #cooling-cells = <2>;
110 compatible = "cache";
111 next-level-cache = <&L3_0>;
117 compatible = "qcom,kryo685";
119 enable-method = "psci";
120 next-level-cache = <&L2_300>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 power-domains = <&CPU_PD3>;
123 power-domain-names = "psci";
124 #cooling-cells = <2>;
126 compatible = "cache";
127 next-level-cache = <&L3_0>;
133 compatible = "qcom,kryo685";
135 enable-method = "psci";
136 next-level-cache = <&L2_400>;
137 qcom,freq-domain = <&cpufreq_hw 1>;
138 power-domains = <&CPU_PD4>;
139 power-domain-names = "psci";
140 #cooling-cells = <2>;
142 compatible = "cache";
143 next-level-cache = <&L3_0>;
149 compatible = "qcom,kryo685";
151 enable-method = "psci";
152 next-level-cache = <&L2_500>;
153 qcom,freq-domain = <&cpufreq_hw 1>;
154 power-domains = <&CPU_PD5>;
155 power-domain-names = "psci";
156 #cooling-cells = <2>;
158 compatible = "cache";
159 next-level-cache = <&L3_0>;
166 compatible = "qcom,kryo685";
168 enable-method = "psci";
169 next-level-cache = <&L2_600>;
170 qcom,freq-domain = <&cpufreq_hw 1>;
171 power-domains = <&CPU_PD6>;
172 power-domain-names = "psci";
173 #cooling-cells = <2>;
175 compatible = "cache";
176 next-level-cache = <&L3_0>;
182 compatible = "qcom,kryo685";
184 enable-method = "psci";
185 next-level-cache = <&L2_700>;
186 qcom,freq-domain = <&cpufreq_hw 2>;
187 power-domains = <&CPU_PD7>;
188 power-domain-names = "psci";
189 #cooling-cells = <2>;
191 compatible = "cache";
192 next-level-cache = <&L3_0>;
233 entry-method = "psci";
235 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
236 compatible = "arm,idle-state";
237 idle-state-name = "silver-rail-power-collapse";
238 arm,psci-suspend-param = <0x40000004>;
239 entry-latency-us = <355>;
240 exit-latency-us = <909>;
241 min-residency-us = <3934>;
245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
246 compatible = "arm,idle-state";
247 idle-state-name = "gold-rail-power-collapse";
248 arm,psci-suspend-param = <0x40000004>;
249 entry-latency-us = <241>;
250 exit-latency-us = <1461>;
251 min-residency-us = <4488>;
257 CLUSTER_SLEEP_0: cluster-sleep-0 {
258 compatible = "domain-idle-state";
259 idle-state-name = "cluster-power-collapse";
260 arm,psci-suspend-param = <0x4100c344>;
261 entry-latency-us = <3263>;
262 exit-latency-us = <6562>;
263 min-residency-us = <9987>;
271 compatible = "qcom,scm-sm8350", "qcom,scm";
277 device_type = "memory";
278 /* We expect the bootloader to fill in the size */
279 reg = <0x0 0x80000000 0x0 0x0>;
283 compatible = "arm,armv8-pmuv3";
284 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
288 compatible = "arm,psci-1.0";
292 #power-domain-cells = <0>;
293 power-domains = <&CLUSTER_PD>;
294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
298 #power-domain-cells = <0>;
299 power-domains = <&CLUSTER_PD>;
300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
304 #power-domain-cells = <0>;
305 power-domains = <&CLUSTER_PD>;
306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
310 #power-domain-cells = <0>;
311 power-domains = <&CLUSTER_PD>;
312 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
316 #power-domain-cells = <0>;
317 power-domains = <&CLUSTER_PD>;
318 domain-idle-states = <&BIG_CPU_SLEEP_0>;
322 #power-domain-cells = <0>;
323 power-domains = <&CLUSTER_PD>;
324 domain-idle-states = <&BIG_CPU_SLEEP_0>;
328 #power-domain-cells = <0>;
329 power-domains = <&CLUSTER_PD>;
330 domain-idle-states = <&BIG_CPU_SLEEP_0>;
334 #power-domain-cells = <0>;
335 power-domains = <&CLUSTER_PD>;
336 domain-idle-states = <&BIG_CPU_SLEEP_0>;
339 CLUSTER_PD: cpu-cluster0 {
340 #power-domain-cells = <0>;
341 domain-idle-states = <&CLUSTER_SLEEP_0>;
345 qup_opp_table_100mhz: opp-table-qup100mhz {
346 compatible = "operating-points-v2";
349 opp-hz = /bits/ 64 <50000000>;
350 required-opps = <&rpmhpd_opp_min_svs>;
354 opp-hz = /bits/ 64 <75000000>;
355 required-opps = <&rpmhpd_opp_low_svs>;
359 opp-hz = /bits/ 64 <100000000>;
360 required-opps = <&rpmhpd_opp_svs>;
364 qup_opp_table_120mhz: opp-table-qup120mhz {
365 compatible = "operating-points-v2";
368 opp-hz = /bits/ 64 <50000000>;
369 required-opps = <&rpmhpd_opp_min_svs>;
373 opp-hz = /bits/ 64 <75000000>;
374 required-opps = <&rpmhpd_opp_low_svs>;
378 opp-hz = /bits/ 64 <120000000>;
379 required-opps = <&rpmhpd_opp_svs>;
383 reserved_memory: reserved-memory {
384 #address-cells = <2>;
388 hyp_mem: memory@80000000 {
389 reg = <0x0 0x80000000 0x0 0x600000>;
393 xbl_aop_mem: memory@80700000 {
395 reg = <0x0 0x80700000 0x0 0x160000>;
398 cmd_db: memory@80860000 {
399 compatible = "qcom,cmd-db";
400 reg = <0x0 0x80860000 0x0 0x20000>;
404 reserved_xbl_uefi_log: memory@80880000 {
405 reg = <0x0 0x80880000 0x0 0x14000>;
409 smem_mem: memory@80900000 {
410 reg = <0x0 0x80900000 0x0 0x200000>;
414 cpucp_fw_mem: memory@80b00000 {
415 reg = <0x0 0x80b00000 0x0 0x100000>;
419 cdsp_secure_heap: memory@80c00000 {
420 reg = <0x0 0x80c00000 0x0 0x4600000>;
424 pil_camera_mem: mmeory@85200000 {
425 reg = <0x0 0x85200000 0x0 0x500000>;
429 pil_video_mem: memory@85700000 {
430 reg = <0x0 0x85700000 0x0 0x500000>;
434 pil_cvp_mem: memory@85c00000 {
435 reg = <0x0 0x85c00000 0x0 0x500000>;
439 pil_adsp_mem: memory@86100000 {
440 reg = <0x0 0x86100000 0x0 0x2100000>;
444 pil_slpi_mem: memory@88200000 {
445 reg = <0x0 0x88200000 0x0 0x1500000>;
449 pil_cdsp_mem: memory@89700000 {
450 reg = <0x0 0x89700000 0x0 0x1e00000>;
454 pil_ipa_fw_mem: memory@8b500000 {
455 reg = <0x0 0x8b500000 0x0 0x10000>;
459 pil_ipa_gsi_mem: memory@8b510000 {
460 reg = <0x0 0x8b510000 0x0 0xa000>;
464 pil_gpu_mem: memory@8b51a000 {
465 reg = <0x0 0x8b51a000 0x0 0x2000>;
469 pil_spss_mem: memory@8b600000 {
470 reg = <0x0 0x8b600000 0x0 0x100000>;
474 pil_modem_mem: memory@8b800000 {
475 reg = <0x0 0x8b800000 0x0 0x10000000>;
479 rmtfs_mem: memory@9b800000 {
480 compatible = "qcom,rmtfs-mem";
481 reg = <0x0 0x9b800000 0x0 0x280000>;
484 qcom,client-id = <1>;
488 hyp_reserved_mem: memory@d0000000 {
489 reg = <0x0 0xd0000000 0x0 0x800000>;
493 pil_trustedvm_mem: memory@d0800000 {
494 reg = <0x0 0xd0800000 0x0 0x76f7000>;
498 qrtr_shbuf: memory@d7ef7000 {
499 reg = <0x0 0xd7ef7000 0x0 0x9000>;
503 chan0_shbuf: memory@d7f00000 {
504 reg = <0x0 0xd7f00000 0x0 0x80000>;
508 chan1_shbuf: memory@d7f80000 {
509 reg = <0x0 0xd7f80000 0x0 0x80000>;
513 removed_mem: memory@d8800000 {
514 reg = <0x0 0xd8800000 0x0 0x6800000>;
520 compatible = "qcom,smem";
521 memory-region = <&smem_mem>;
522 hwlocks = <&tcsr_mutex 3>;
526 compatible = "qcom,smp2p";
527 qcom,smem = <443>, <429>;
528 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
529 IPCC_MPROC_SIGNAL_SMP2P
530 IRQ_TYPE_EDGE_RISING>;
531 mboxes = <&ipcc IPCC_CLIENT_LPASS
532 IPCC_MPROC_SIGNAL_SMP2P>;
534 qcom,local-pid = <0>;
535 qcom,remote-pid = <2>;
537 smp2p_adsp_out: master-kernel {
538 qcom,entry-name = "master-kernel";
539 #qcom,smem-state-cells = <1>;
542 smp2p_adsp_in: slave-kernel {
543 qcom,entry-name = "slave-kernel";
544 interrupt-controller;
545 #interrupt-cells = <2>;
550 compatible = "qcom,smp2p";
551 qcom,smem = <94>, <432>;
552 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
553 IPCC_MPROC_SIGNAL_SMP2P
554 IRQ_TYPE_EDGE_RISING>;
555 mboxes = <&ipcc IPCC_CLIENT_CDSP
556 IPCC_MPROC_SIGNAL_SMP2P>;
558 qcom,local-pid = <0>;
559 qcom,remote-pid = <5>;
561 smp2p_cdsp_out: master-kernel {
562 qcom,entry-name = "master-kernel";
563 #qcom,smem-state-cells = <1>;
566 smp2p_cdsp_in: slave-kernel {
567 qcom,entry-name = "slave-kernel";
568 interrupt-controller;
569 #interrupt-cells = <2>;
574 compatible = "qcom,smp2p";
575 qcom,smem = <435>, <428>;
576 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
577 IPCC_MPROC_SIGNAL_SMP2P
578 IRQ_TYPE_EDGE_RISING>;
579 mboxes = <&ipcc IPCC_CLIENT_MPSS
580 IPCC_MPROC_SIGNAL_SMP2P>;
582 qcom,local-pid = <0>;
583 qcom,remote-pid = <1>;
585 smp2p_modem_out: master-kernel {
586 qcom,entry-name = "master-kernel";
587 #qcom,smem-state-cells = <1>;
590 smp2p_modem_in: slave-kernel {
591 qcom,entry-name = "slave-kernel";
592 interrupt-controller;
593 #interrupt-cells = <2>;
596 ipa_smp2p_out: ipa-ap-to-modem {
597 qcom,entry-name = "ipa";
598 #qcom,smem-state-cells = <1>;
601 ipa_smp2p_in: ipa-modem-to-ap {
602 qcom,entry-name = "ipa";
603 interrupt-controller;
604 #interrupt-cells = <2>;
609 compatible = "qcom,smp2p";
610 qcom,smem = <481>, <430>;
611 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
612 IPCC_MPROC_SIGNAL_SMP2P
613 IRQ_TYPE_EDGE_RISING>;
614 mboxes = <&ipcc IPCC_CLIENT_SLPI
615 IPCC_MPROC_SIGNAL_SMP2P>;
617 qcom,local-pid = <0>;
618 qcom,remote-pid = <3>;
620 smp2p_slpi_out: master-kernel {
621 qcom,entry-name = "master-kernel";
622 #qcom,smem-state-cells = <1>;
625 smp2p_slpi_in: slave-kernel {
626 qcom,entry-name = "slave-kernel";
627 interrupt-controller;
628 #interrupt-cells = <2>;
633 #address-cells = <2>;
635 ranges = <0 0 0 0 0x10 0>;
636 dma-ranges = <0 0 0 0 0x10 0>;
637 compatible = "simple-bus";
639 gcc: clock-controller@100000 {
640 compatible = "qcom,gcc-sm8350";
641 reg = <0x0 0x00100000 0x0 0x1f0000>;
644 #power-domain-cells = <1>;
645 clock-names = "bi_tcxo",
649 "ufs_card_rx_symbol_0_clk",
650 "ufs_card_rx_symbol_1_clk",
651 "ufs_card_tx_symbol_0_clk",
652 "ufs_phy_rx_symbol_0_clk",
653 "ufs_phy_rx_symbol_1_clk",
654 "ufs_phy_tx_symbol_0_clk",
655 "usb3_phy_wrapper_gcc_usb30_pipe_clk",
656 "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
657 clocks = <&rpmhcc RPMH_CXO_CLK>,
664 <&ufs_phy_rx_symbol_0_clk>,
665 <&ufs_phy_rx_symbol_1_clk>,
666 <&ufs_phy_tx_symbol_0_clk>,
671 ipcc: mailbox@408000 {
672 compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
673 reg = <0 0x00408000 0 0x1000>;
674 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
675 interrupt-controller;
676 #interrupt-cells = <3>;
680 gpi_dma2: dma-controller@800000 {
681 compatible = "qcom,sm8350-gpi-dma";
682 reg = <0 0x00800000 0 0x60000>;
683 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
696 dma-channel-mask = <0xff>;
697 iommus = <&apps_smmu 0x5f6 0x0>;
702 qupv3_id_2: geniqup@8c0000 {
703 compatible = "qcom,geni-se-qup";
704 reg = <0x0 0x008c0000 0x0 0x6000>;
705 clock-names = "m-ahb", "s-ahb";
706 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
707 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
708 iommus = <&apps_smmu 0x5e3 0x0>;
709 #address-cells = <2>;
715 compatible = "qcom,geni-i2c";
716 reg = <0 0x00880000 0 0x4000>;
718 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
719 pinctrl-names = "default";
720 pinctrl-0 = <&qup_i2c14_default>;
721 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
722 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
723 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
724 dma-names = "tx", "rx";
725 #address-cells = <1>;
731 compatible = "qcom,geni-spi";
732 reg = <0 0x00880000 0 0x4000>;
734 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
735 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
736 power-domains = <&rpmhpd SM8350_CX>;
737 operating-points-v2 = <&qup_opp_table_120mhz>;
738 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
739 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
740 dma-names = "tx", "rx";
741 #address-cells = <1>;
747 compatible = "qcom,geni-i2c";
748 reg = <0 0x00884000 0 0x4000>;
750 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
751 pinctrl-names = "default";
752 pinctrl-0 = <&qup_i2c15_default>;
753 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
754 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
755 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
756 dma-names = "tx", "rx";
757 #address-cells = <1>;
763 compatible = "qcom,geni-spi";
764 reg = <0 0x00884000 0 0x4000>;
766 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
767 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
768 power-domains = <&rpmhpd SM8350_CX>;
769 operating-points-v2 = <&qup_opp_table_120mhz>;
770 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
771 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
772 dma-names = "tx", "rx";
773 #address-cells = <1>;
779 compatible = "qcom,geni-i2c";
780 reg = <0 0x00888000 0 0x4000>;
782 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
783 pinctrl-names = "default";
784 pinctrl-0 = <&qup_i2c16_default>;
785 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
786 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
787 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
788 dma-names = "tx", "rx";
789 #address-cells = <1>;
795 compatible = "qcom,geni-spi";
796 reg = <0 0x00888000 0 0x4000>;
798 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
799 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
800 power-domains = <&rpmhpd SM8350_CX>;
801 operating-points-v2 = <&qup_opp_table_100mhz>;
802 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
803 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
804 dma-names = "tx", "rx";
805 #address-cells = <1>;
811 compatible = "qcom,geni-i2c";
812 reg = <0 0x0088c000 0 0x4000>;
814 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
815 pinctrl-names = "default";
816 pinctrl-0 = <&qup_i2c17_default>;
817 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
818 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
819 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
820 dma-names = "tx", "rx";
821 #address-cells = <1>;
827 compatible = "qcom,geni-spi";
828 reg = <0 0x0088c000 0 0x4000>;
830 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
831 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
832 power-domains = <&rpmhpd SM8350_CX>;
833 operating-points-v2 = <&qup_opp_table_100mhz>;
834 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
835 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
836 dma-names = "tx", "rx";
837 #address-cells = <1>;
842 /* QUP no. 18 seems to be strictly SPI/UART-only */
845 compatible = "qcom,geni-spi";
846 reg = <0 0x00890000 0 0x4000>;
848 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
849 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
850 power-domains = <&rpmhpd SM8350_CX>;
851 operating-points-v2 = <&qup_opp_table_100mhz>;
852 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
853 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
854 dma-names = "tx", "rx";
855 #address-cells = <1>;
860 uart18: serial@890000 {
861 compatible = "qcom,geni-uart";
862 reg = <0 0x00890000 0 0x4000>;
864 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
865 pinctrl-names = "default";
866 pinctrl-0 = <&qup_uart18_default>;
867 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
868 power-domains = <&rpmhpd SM8350_CX>;
869 operating-points-v2 = <&qup_opp_table_100mhz>;
874 compatible = "qcom,geni-i2c";
875 reg = <0 0x00894000 0 0x4000>;
877 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
878 pinctrl-names = "default";
879 pinctrl-0 = <&qup_i2c19_default>;
880 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
881 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
882 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
883 dma-names = "tx", "rx";
884 #address-cells = <1>;
890 compatible = "qcom,geni-spi";
891 reg = <0 0x00894000 0 0x4000>;
893 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
894 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
895 power-domains = <&rpmhpd SM8350_CX>;
896 operating-points-v2 = <&qup_opp_table_100mhz>;
897 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
898 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
899 dma-names = "tx", "rx";
900 #address-cells = <1>;
906 gpi_dma0: dma-controller@900000 {
907 compatible = "qcom,sm8350-gpi-dma";
908 reg = <0 0x09800000 0 0x60000>;
909 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
911 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
912 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
913 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
914 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
922 dma-channel-mask = <0x7e>;
923 iommus = <&apps_smmu 0x5b6 0x0>;
928 qupv3_id_0: geniqup@9c0000 {
929 compatible = "qcom,geni-se-qup";
930 reg = <0x0 0x009c0000 0x0 0x6000>;
931 clock-names = "m-ahb", "s-ahb";
932 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
933 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
934 iommus = <&apps_smmu 0x5a3 0>;
935 #address-cells = <2>;
941 compatible = "qcom,geni-i2c";
942 reg = <0 0x00980000 0 0x4000>;
944 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
945 pinctrl-names = "default";
946 pinctrl-0 = <&qup_i2c0_default>;
947 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
948 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
949 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
950 dma-names = "tx", "rx";
951 #address-cells = <1>;
957 compatible = "qcom,geni-spi";
958 reg = <0 0x00980000 0 0x4000>;
960 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
961 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
962 power-domains = <&rpmhpd SM8350_CX>;
963 operating-points-v2 = <&qup_opp_table_100mhz>;
964 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
965 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
966 dma-names = "tx", "rx";
967 #address-cells = <1>;
973 compatible = "qcom,geni-i2c";
974 reg = <0 0x00984000 0 0x4000>;
976 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
977 pinctrl-names = "default";
978 pinctrl-0 = <&qup_i2c1_default>;
979 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
980 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
981 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
982 dma-names = "tx", "rx";
983 #address-cells = <1>;
989 compatible = "qcom,geni-spi";
990 reg = <0 0x00984000 0 0x4000>;
992 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
993 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
994 power-domains = <&rpmhpd SM8350_CX>;
995 operating-points-v2 = <&qup_opp_table_100mhz>;
996 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
997 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
998 dma-names = "tx", "rx";
999 #address-cells = <1>;
1001 status = "disabled";
1005 compatible = "qcom,geni-i2c";
1006 reg = <0 0x00988000 0 0x4000>;
1008 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1009 pinctrl-names = "default";
1010 pinctrl-0 = <&qup_i2c2_default>;
1011 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1012 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1013 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1014 dma-names = "tx", "rx";
1015 #address-cells = <1>;
1017 status = "disabled";
1021 compatible = "qcom,geni-spi";
1022 reg = <0 0x00988000 0 0x4000>;
1024 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1025 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1026 power-domains = <&rpmhpd SM8350_CX>;
1027 operating-points-v2 = <&qup_opp_table_100mhz>;
1028 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1029 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1030 dma-names = "tx", "rx";
1031 #address-cells = <1>;
1033 status = "disabled";
1036 uart2: serial@98c000 {
1037 compatible = "qcom,geni-debug-uart";
1038 reg = <0 0x0098c000 0 0x4000>;
1040 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1041 pinctrl-names = "default";
1042 pinctrl-0 = <&qup_uart3_default_state>;
1043 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1044 power-domains = <&rpmhpd SM8350_CX>;
1045 operating-points-v2 = <&qup_opp_table_100mhz>;
1046 #address-cells = <1>;
1048 status = "disabled";
1051 /* QUP no. 3 seems to be strictly SPI-only */
1054 compatible = "qcom,geni-spi";
1055 reg = <0 0x0098c000 0 0x4000>;
1057 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1059 power-domains = <&rpmhpd SM8350_CX>;
1060 operating-points-v2 = <&qup_opp_table_100mhz>;
1061 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1062 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1063 dma-names = "tx", "rx";
1064 #address-cells = <1>;
1066 status = "disabled";
1070 compatible = "qcom,geni-i2c";
1071 reg = <0 0x00990000 0 0x4000>;
1073 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1074 pinctrl-names = "default";
1075 pinctrl-0 = <&qup_i2c4_default>;
1076 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1077 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1078 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1079 dma-names = "tx", "rx";
1080 #address-cells = <1>;
1082 status = "disabled";
1086 compatible = "qcom,geni-spi";
1087 reg = <0 0x00990000 0 0x4000>;
1089 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1090 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1091 power-domains = <&rpmhpd SM8350_CX>;
1092 operating-points-v2 = <&qup_opp_table_100mhz>;
1093 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1094 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1095 dma-names = "tx", "rx";
1096 #address-cells = <1>;
1098 status = "disabled";
1102 compatible = "qcom,geni-i2c";
1103 reg = <0 0x00994000 0 0x4000>;
1105 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1106 pinctrl-names = "default";
1107 pinctrl-0 = <&qup_i2c5_default>;
1108 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1109 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1110 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1111 dma-names = "tx", "rx";
1112 #address-cells = <1>;
1114 status = "disabled";
1118 compatible = "qcom,geni-spi";
1119 reg = <0 0x00994000 0 0x4000>;
1121 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1122 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1123 power-domains = <&rpmhpd SM8350_CX>;
1124 operating-points-v2 = <&qup_opp_table_100mhz>;
1125 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1126 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1127 dma-names = "tx", "rx";
1128 #address-cells = <1>;
1130 status = "disabled";
1134 compatible = "qcom,geni-i2c";
1135 reg = <0 0x00998000 0 0x4000>;
1137 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1138 pinctrl-names = "default";
1139 pinctrl-0 = <&qup_i2c6_default>;
1140 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1141 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1142 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1143 dma-names = "tx", "rx";
1144 #address-cells = <1>;
1146 status = "disabled";
1150 compatible = "qcom,geni-spi";
1151 reg = <0 0x00998000 0 0x4000>;
1153 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1154 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1155 power-domains = <&rpmhpd SM8350_CX>;
1156 operating-points-v2 = <&qup_opp_table_100mhz>;
1157 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1158 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1159 dma-names = "tx", "rx";
1160 #address-cells = <1>;
1162 status = "disabled";
1165 uart6: serial@998000 {
1166 compatible = "qcom,geni-uart";
1167 reg = <0 0x00998000 0 0x4000>;
1169 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&qup_uart6_default>;
1172 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1173 power-domains = <&rpmhpd SM8350_CX>;
1174 operating-points-v2 = <&qup_opp_table_100mhz>;
1175 status = "disabled";
1179 compatible = "qcom,geni-i2c";
1180 reg = <0 0x0099c000 0 0x4000>;
1182 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1183 pinctrl-names = "default";
1184 pinctrl-0 = <&qup_i2c7_default>;
1185 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1186 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1187 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1188 dma-names = "tx", "rx";
1189 #address-cells = <1>;
1191 status = "disabled";
1195 compatible = "qcom,geni-spi";
1196 reg = <0 0x0099c000 0 0x4000>;
1198 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1199 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1200 power-domains = <&rpmhpd SM8350_CX>;
1201 operating-points-v2 = <&qup_opp_table_100mhz>;
1202 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1203 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1204 dma-names = "tx", "rx";
1205 #address-cells = <1>;
1207 status = "disabled";
1211 gpi_dma1: dma-controller@a00000 {
1212 compatible = "qcom,sm8350-gpi-dma";
1213 reg = <0 0x00a00000 0 0x60000>;
1214 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1216 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1226 dma-channels = <12>;
1227 dma-channel-mask = <0xff>;
1228 iommus = <&apps_smmu 0x56 0x0>;
1230 status = "disabled";
1233 qupv3_id_1: geniqup@ac0000 {
1234 compatible = "qcom,geni-se-qup";
1235 reg = <0x0 0x00ac0000 0x0 0x6000>;
1236 clock-names = "m-ahb", "s-ahb";
1237 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1238 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1239 iommus = <&apps_smmu 0x43 0>;
1240 #address-cells = <2>;
1243 status = "disabled";
1246 compatible = "qcom,geni-i2c";
1247 reg = <0 0x00a80000 0 0x4000>;
1249 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1250 pinctrl-names = "default";
1251 pinctrl-0 = <&qup_i2c8_default>;
1252 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1253 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1254 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1255 dma-names = "tx", "rx";
1256 #address-cells = <1>;
1258 status = "disabled";
1262 compatible = "qcom,geni-spi";
1263 reg = <0 0x00a80000 0 0x4000>;
1265 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1266 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1267 power-domains = <&rpmhpd SM8350_CX>;
1268 operating-points-v2 = <&qup_opp_table_120mhz>;
1269 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1270 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1271 dma-names = "tx", "rx";
1272 #address-cells = <1>;
1274 status = "disabled";
1278 compatible = "qcom,geni-i2c";
1279 reg = <0 0x00a84000 0 0x4000>;
1281 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1282 pinctrl-names = "default";
1283 pinctrl-0 = <&qup_i2c9_default>;
1284 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1285 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1286 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1287 dma-names = "tx", "rx";
1288 #address-cells = <1>;
1290 status = "disabled";
1294 compatible = "qcom,geni-spi";
1295 reg = <0 0x00a84000 0 0x4000>;
1297 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1298 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1299 power-domains = <&rpmhpd SM8350_CX>;
1300 operating-points-v2 = <&qup_opp_table_100mhz>;
1301 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1302 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1303 dma-names = "tx", "rx";
1304 #address-cells = <1>;
1306 status = "disabled";
1310 compatible = "qcom,geni-i2c";
1311 reg = <0 0x00a88000 0 0x4000>;
1313 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1314 pinctrl-names = "default";
1315 pinctrl-0 = <&qup_i2c10_default>;
1316 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1317 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1318 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1319 dma-names = "tx", "rx";
1320 #address-cells = <1>;
1322 status = "disabled";
1326 compatible = "qcom,geni-spi";
1327 reg = <0 0x00a88000 0 0x4000>;
1329 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1330 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1331 power-domains = <&rpmhpd SM8350_CX>;
1332 operating-points-v2 = <&qup_opp_table_100mhz>;
1333 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1334 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1335 dma-names = "tx", "rx";
1336 #address-cells = <1>;
1338 status = "disabled";
1342 compatible = "qcom,geni-i2c";
1343 reg = <0 0x00a8c000 0 0x4000>;
1345 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1346 pinctrl-names = "default";
1347 pinctrl-0 = <&qup_i2c11_default>;
1348 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1349 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1350 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1351 dma-names = "tx", "rx";
1352 #address-cells = <1>;
1354 status = "disabled";
1358 compatible = "qcom,geni-spi";
1359 reg = <0 0x00a8c000 0 0x4000>;
1361 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1362 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1363 power-domains = <&rpmhpd SM8350_CX>;
1364 operating-points-v2 = <&qup_opp_table_100mhz>;
1365 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1366 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1367 dma-names = "tx", "rx";
1368 #address-cells = <1>;
1370 status = "disabled";
1374 compatible = "qcom,geni-i2c";
1375 reg = <0 0x00a90000 0 0x4000>;
1377 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1378 pinctrl-names = "default";
1379 pinctrl-0 = <&qup_i2c12_default>;
1380 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1381 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1382 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1383 dma-names = "tx", "rx";
1384 #address-cells = <1>;
1386 status = "disabled";
1390 compatible = "qcom,geni-spi";
1391 reg = <0 0x00a90000 0 0x4000>;
1393 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1394 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1395 power-domains = <&rpmhpd SM8350_CX>;
1396 operating-points-v2 = <&qup_opp_table_100mhz>;
1397 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1398 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1399 dma-names = "tx", "rx";
1400 #address-cells = <1>;
1402 status = "disabled";
1406 compatible = "qcom,geni-i2c";
1407 reg = <0 0x00a94000 0 0x4000>;
1409 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&qup_i2c13_default>;
1412 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1413 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1414 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1415 dma-names = "tx", "rx";
1416 #address-cells = <1>;
1418 status = "disabled";
1422 compatible = "qcom,geni-spi";
1423 reg = <0 0x00a94000 0 0x4000>;
1425 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1426 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1427 power-domains = <&rpmhpd SM8350_CX>;
1428 operating-points-v2 = <&qup_opp_table_100mhz>;
1429 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1430 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1431 dma-names = "tx", "rx";
1432 #address-cells = <1>;
1434 status = "disabled";
1438 apps_smmu: iommu@15000000 {
1439 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
1440 reg = <0 0x15000000 0 0x100000>;
1442 #global-interrupts = <2>;
1443 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1455 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1457 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1459 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1460 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1461 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1463 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1464 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1465 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1466 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1467 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1468 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1473 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1474 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1482 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1486 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1487 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1488 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1497 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1498 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1499 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1500 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1501 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1502 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1507 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1508 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1509 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1510 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1511 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1512 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1513 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1514 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1515 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1516 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1517 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1518 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1519 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1520 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1521 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1522 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1523 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1524 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1525 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1526 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
1543 config_noc: interconnect@1500000 {
1544 compatible = "qcom,sm8350-config-noc";
1545 reg = <0 0x01500000 0 0xa580>;
1546 #interconnect-cells = <1>;
1547 qcom,bcm-voters = <&apps_bcm_voter>;
1550 mc_virt: interconnect@1580000 {
1551 compatible = "qcom,sm8350-mc-virt";
1552 reg = <0 0x01580000 0 0x1000>;
1553 #interconnect-cells = <1>;
1554 qcom,bcm-voters = <&apps_bcm_voter>;
1557 system_noc: interconnect@1680000 {
1558 compatible = "qcom,sm8350-system-noc";
1559 reg = <0 0x01680000 0 0x1c200>;
1560 #interconnect-cells = <1>;
1561 qcom,bcm-voters = <&apps_bcm_voter>;
1564 aggre1_noc: interconnect@16e0000 {
1565 compatible = "qcom,sm8350-aggre1-noc";
1566 reg = <0 0x016e0000 0 0x1f180>;
1567 #interconnect-cells = <1>;
1568 qcom,bcm-voters = <&apps_bcm_voter>;
1571 aggre2_noc: interconnect@1700000 {
1572 compatible = "qcom,sm8350-aggre2-noc";
1573 reg = <0 0x01700000 0 0x33000>;
1574 #interconnect-cells = <1>;
1575 qcom,bcm-voters = <&apps_bcm_voter>;
1578 mmss_noc: interconnect@1740000 {
1579 compatible = "qcom,sm8350-mmss-noc";
1580 reg = <0 0x01740000 0 0x1f080>;
1581 #interconnect-cells = <1>;
1582 qcom,bcm-voters = <&apps_bcm_voter>;
1585 lpass_ag_noc: interconnect@3c40000 {
1586 compatible = "qcom,sm8350-lpass-ag-noc";
1587 reg = <0 0x03c40000 0 0xf080>;
1588 #interconnect-cells = <1>;
1589 qcom,bcm-voters = <&apps_bcm_voter>;
1592 compute_noc: interconnect@a0c0000{
1593 compatible = "qcom,sm8350-compute-noc";
1594 reg = <0 0x0a0c0000 0 0xa180>;
1595 #interconnect-cells = <1>;
1596 qcom,bcm-voters = <&apps_bcm_voter>;
1600 compatible = "qcom,sm8350-ipa";
1602 iommus = <&apps_smmu 0x5c0 0x0>,
1603 <&apps_smmu 0x5c2 0x0>;
1604 reg = <0 0x1e40000 0 0x8000>,
1605 <0 0x1e50000 0 0x4b20>,
1606 <0 0x1e04000 0 0x23000>;
1607 reg-names = "ipa-reg",
1611 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1612 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1613 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1614 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1615 interrupt-names = "ipa",
1620 clocks = <&rpmhcc RPMH_IPA_CLK>;
1621 clock-names = "core";
1623 interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
1624 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
1625 interconnect-names = "memory",
1628 qcom,qmp = <&aoss_qmp>;
1630 qcom,smem-states = <&ipa_smp2p_out 0>,
1632 qcom,smem-state-names = "ipa-clock-enabled-valid",
1633 "ipa-clock-enabled";
1635 status = "disabled";
1638 tcsr_mutex: hwlock@1f40000 {
1639 compatible = "qcom,tcsr-mutex";
1640 reg = <0x0 0x01f40000 0x0 0x40000>;
1641 #hwlock-cells = <1>;
1644 mpss: remoteproc@4080000 {
1645 compatible = "qcom,sm8350-mpss-pas";
1646 reg = <0x0 0x04080000 0x0 0x4040>;
1648 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1649 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1650 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1651 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1652 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1653 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1654 interrupt-names = "wdog", "fatal", "ready", "handover",
1655 "stop-ack", "shutdown-ack";
1657 clocks = <&rpmhcc RPMH_CXO_CLK>;
1660 power-domains = <&rpmhpd SM8350_CX>,
1661 <&rpmhpd SM8350_MSS>;
1662 power-domain-names = "cx", "mss";
1664 interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
1666 memory-region = <&pil_modem_mem>;
1668 qcom,qmp = <&aoss_qmp>;
1670 qcom,smem-states = <&smp2p_modem_out 0>;
1671 qcom,smem-state-names = "stop";
1673 status = "disabled";
1676 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1677 IPCC_MPROC_SIGNAL_GLINK_QMP
1678 IRQ_TYPE_EDGE_RISING>;
1679 mboxes = <&ipcc IPCC_CLIENT_MPSS
1680 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1682 qcom,remote-pid = <1>;
1686 pdc: interrupt-controller@b220000 {
1687 compatible = "qcom,sm8350-pdc", "qcom,pdc";
1688 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1689 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
1690 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
1691 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
1693 #interrupt-cells = <2>;
1694 interrupt-parent = <&intc>;
1695 interrupt-controller;
1698 tsens0: thermal-sensor@c263000 {
1699 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1700 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1701 <0 0x0c222000 0 0x8>; /* SROT */
1702 #qcom,sensors = <15>;
1703 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1704 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
1705 interrupt-names = "uplow", "critical";
1706 #thermal-sensor-cells = <1>;
1709 tsens1: thermal-sensor@c265000 {
1710 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1711 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1712 <0 0x0c223000 0 0x8>; /* SROT */
1713 #qcom,sensors = <14>;
1714 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1715 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
1716 interrupt-names = "uplow", "critical";
1717 #thermal-sensor-cells = <1>;
1720 aoss_qmp: power-controller@c300000 {
1721 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
1722 reg = <0 0x0c300000 0 0x400>;
1723 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1724 IRQ_TYPE_EDGE_RISING>;
1725 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1731 compatible = "qcom,rpmh-stats";
1732 reg = <0 0x0c3f0000 0 0x400>;
1735 spmi_bus: spmi@c440000 {
1736 compatible = "qcom,spmi-pmic-arb";
1737 reg = <0x0 0xc440000 0x0 0x1100>,
1738 <0x0 0xc600000 0x0 0x2000000>,
1739 <0x0 0xe600000 0x0 0x100000>,
1740 <0x0 0xe700000 0x0 0xa0000>,
1741 <0x0 0xc40a000 0x0 0x26000>;
1742 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1743 interrupt-names = "periph_irq";
1744 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1747 #address-cells = <2>;
1749 interrupt-controller;
1750 #interrupt-cells = <4>;
1753 tlmm: pinctrl@f100000 {
1754 compatible = "qcom,sm8350-tlmm";
1755 reg = <0 0x0f100000 0 0x300000>;
1756 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1759 interrupt-controller;
1760 #interrupt-cells = <2>;
1761 gpio-ranges = <&tlmm 0 0 204>;
1762 wakeup-parent = <&pdc>;
1764 qup_uart3_default_state: qup-uart3-default-state {
1775 qup_uart6_default: qup-uart6-default-state {
1776 pins = "gpio30", "gpio31";
1778 drive-strength = <2>;
1782 qup_uart18_default: qup-uart18-default-state {
1783 pins = "gpio58", "gpio59";
1785 drive-strength = <2>;
1789 qup_i2c0_default: qup-i2c0-default-state {
1790 pins = "gpio4", "gpio5";
1792 drive-strength = <2>;
1796 qup_i2c1_default: qup-i2c1-default-state {
1797 pins = "gpio8", "gpio9";
1799 drive-strength = <2>;
1803 qup_i2c2_default: qup-i2c2-default-state {
1804 pins = "gpio12", "gpio13";
1806 drive-strength = <2>;
1810 qup_i2c4_default: qup-i2c4-default-state {
1811 pins = "gpio20", "gpio21";
1813 drive-strength = <2>;
1817 qup_i2c5_default: qup-i2c5-default-state {
1818 pins = "gpio24", "gpio25";
1820 drive-strength = <2>;
1824 qup_i2c6_default: qup-i2c6-default-state {
1825 pins = "gpio28", "gpio29";
1827 drive-strength = <2>;
1831 qup_i2c7_default: qup-i2c7-default-state {
1832 pins = "gpio32", "gpio33";
1834 drive-strength = <2>;
1838 qup_i2c8_default: qup-i2c8-default-state {
1839 pins = "gpio36", "gpio37";
1841 drive-strength = <2>;
1845 qup_i2c9_default: qup-i2c9-default-state {
1846 pins = "gpio40", "gpio41";
1848 drive-strength = <2>;
1852 qup_i2c10_default: qup-i2c10-default-state {
1853 pins = "gpio44", "gpio45";
1855 drive-strength = <2>;
1859 qup_i2c11_default: qup-i2c11-default-state {
1860 pins = "gpio48", "gpio49";
1862 drive-strength = <2>;
1866 qup_i2c12_default: qup-i2c12-default-state {
1867 pins = "gpio52", "gpio53";
1869 drive-strength = <2>;
1873 qup_i2c13_default: qup-i2c13-default-state {
1874 pins = "gpio0", "gpio1";
1876 drive-strength = <2>;
1880 qup_i2c14_default: qup-i2c14-default-state {
1881 pins = "gpio56", "gpio57";
1883 drive-strength = <2>;
1887 qup_i2c15_default: qup-i2c15-default-state {
1888 pins = "gpio60", "gpio61";
1890 drive-strength = <2>;
1894 qup_i2c16_default: qup-i2c16-default-state {
1895 pins = "gpio64", "gpio65";
1897 drive-strength = <2>;
1901 qup_i2c17_default: qup-i2c17-default-state {
1902 pins = "gpio72", "gpio73";
1904 drive-strength = <2>;
1908 qup_i2c19_default: qup-i2c19-default-state {
1909 pins = "gpio76", "gpio77";
1911 drive-strength = <2>;
1917 compatible = "qcom,prng-ee";
1918 reg = <0 0x010d3000 0 0x1000>;
1919 clocks = <&rpmhcc RPMH_HWKM_CLK>;
1920 clock-names = "core";
1923 intc: interrupt-controller@17a00000 {
1924 compatible = "arm,gic-v3";
1925 #interrupt-cells = <3>;
1926 interrupt-controller;
1927 #redistributor-regions = <1>;
1928 redistributor-stride = <0 0x20000>;
1929 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
1930 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
1931 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1935 compatible = "arm,armv7-timer-mem";
1936 #address-cells = <1>;
1938 ranges = <0 0 0 0x20000000>;
1939 reg = <0x0 0x17c20000 0x0 0x1000>;
1940 clock-frequency = <19200000>;
1944 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1946 reg = <0x17c21000 0x1000>,
1947 <0x17c22000 0x1000>;
1952 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1953 reg = <0x17c23000 0x1000>;
1954 status = "disabled";
1959 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1960 reg = <0x17c25000 0x1000>;
1961 status = "disabled";
1966 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1967 reg = <0x17c27000 0x1000>;
1968 status = "disabled";
1973 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1974 reg = <0x17c29000 0x1000>;
1975 status = "disabled";
1980 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1981 reg = <0x17c2b000 0x1000>;
1982 status = "disabled";
1987 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1988 reg = <0x17c2d000 0x1000>;
1989 status = "disabled";
1993 apps_rsc: rsc@18200000 {
1995 compatible = "qcom,rpmh-rsc";
1996 reg = <0x0 0x18200000 0x0 0x10000>,
1997 <0x0 0x18210000 0x0 0x10000>,
1998 <0x0 0x18220000 0x0 0x10000>;
1999 reg-names = "drv-0", "drv-1", "drv-2";
2000 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2001 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2002 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2003 qcom,tcs-offset = <0xd00>;
2005 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2006 <WAKE_TCS 3>, <CONTROL_TCS 0>;
2008 rpmhcc: clock-controller {
2009 compatible = "qcom,sm8350-rpmh-clk";
2012 clocks = <&xo_board>;
2015 rpmhpd: power-controller {
2016 compatible = "qcom,sm8350-rpmhpd";
2017 #power-domain-cells = <1>;
2018 operating-points-v2 = <&rpmhpd_opp_table>;
2020 rpmhpd_opp_table: opp-table {
2021 compatible = "operating-points-v2";
2023 rpmhpd_opp_ret: opp1 {
2024 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2027 rpmhpd_opp_min_svs: opp2 {
2028 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2031 rpmhpd_opp_low_svs: opp3 {
2032 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2035 rpmhpd_opp_svs: opp4 {
2036 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2039 rpmhpd_opp_svs_l1: opp5 {
2040 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2043 rpmhpd_opp_nom: opp6 {
2044 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2047 rpmhpd_opp_nom_l1: opp7 {
2048 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2051 rpmhpd_opp_nom_l2: opp8 {
2052 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2055 rpmhpd_opp_turbo: opp9 {
2056 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2059 rpmhpd_opp_turbo_l1: opp10 {
2060 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2065 apps_bcm_voter: bcm-voter {
2066 compatible = "qcom,bcm-voter";
2070 cpufreq_hw: cpufreq@18591000 {
2071 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
2072 reg = <0 0x18591000 0 0x1000>,
2073 <0 0x18592000 0 0x1000>,
2074 <0 0x18593000 0 0x1000>;
2075 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
2077 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2078 clock-names = "xo", "alternate";
2080 #freq-domain-cells = <1>;
2083 ufs_mem_hc: ufshc@1d84000 {
2084 compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
2086 reg = <0 0x01d84000 0 0x3000>;
2087 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2088 phys = <&ufs_mem_phy_lanes>;
2089 phy-names = "ufsphy";
2090 lanes-per-direction = <2>;
2092 resets = <&gcc GCC_UFS_PHY_BCR>;
2093 reset-names = "rst";
2095 power-domains = <&gcc UFS_PHY_GDSC>;
2097 iommus = <&apps_smmu 0xe0 0x0>;
2105 "tx_lane0_sync_clk",
2106 "rx_lane0_sync_clk",
2107 "rx_lane1_sync_clk";
2109 <&gcc GCC_UFS_PHY_AXI_CLK>,
2110 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2111 <&gcc GCC_UFS_PHY_AHB_CLK>,
2112 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2113 <&rpmhcc RPMH_CXO_CLK>,
2114 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2115 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2116 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2118 <75000000 300000000>,
2121 <75000000 300000000>,
2126 status = "disabled";
2129 ufs_mem_phy: phy@1d87000 {
2130 compatible = "qcom,sm8350-qmp-ufs-phy";
2131 reg = <0 0x01d87000 0 0x1c4>;
2132 #address-cells = <2>;
2135 clock-names = "ref",
2137 clocks = <&rpmhcc RPMH_CXO_CLK>,
2138 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2140 resets = <&ufs_mem_hc 0>;
2141 reset-names = "ufsphy";
2142 status = "disabled";
2144 ufs_mem_phy_lanes: phy@1d87400 {
2145 reg = <0 0x01d87400 0 0x108>,
2146 <0 0x01d87600 0 0x1e0>,
2147 <0 0x01d87c00 0 0x1dc>,
2148 <0 0x01d87800 0 0x108>,
2149 <0 0x01d87a00 0 0x1e0>;
2154 slpi: remoteproc@5c00000 {
2155 compatible = "qcom,sm8350-slpi-pas";
2156 reg = <0 0x05c00000 0 0x4000>;
2158 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2159 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2160 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2161 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2162 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2163 interrupt-names = "wdog", "fatal", "ready",
2164 "handover", "stop-ack";
2166 clocks = <&rpmhcc RPMH_CXO_CLK>;
2169 power-domains = <&rpmhpd SM8350_LCX>,
2170 <&rpmhpd SM8350_LMX>;
2171 power-domain-names = "lcx", "lmx";
2173 memory-region = <&pil_slpi_mem>;
2175 qcom,qmp = <&aoss_qmp>;
2177 qcom,smem-states = <&smp2p_slpi_out 0>;
2178 qcom,smem-state-names = "stop";
2180 status = "disabled";
2183 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2184 IPCC_MPROC_SIGNAL_GLINK_QMP
2185 IRQ_TYPE_EDGE_RISING>;
2186 mboxes = <&ipcc IPCC_CLIENT_SLPI
2187 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2190 qcom,remote-pid = <3>;
2193 compatible = "qcom,fastrpc";
2194 qcom,glink-channels = "fastrpcglink-apps-dsp";
2196 qcom,non-secure-domain;
2197 #address-cells = <1>;
2201 compatible = "qcom,fastrpc-compute-cb";
2203 iommus = <&apps_smmu 0x0541 0x0>;
2207 compatible = "qcom,fastrpc-compute-cb";
2209 iommus = <&apps_smmu 0x0542 0x0>;
2213 compatible = "qcom,fastrpc-compute-cb";
2215 iommus = <&apps_smmu 0x0543 0x0>;
2216 /* note: shared-cb = <4> in downstream */
2222 cdsp: remoteproc@98900000 {
2223 compatible = "qcom,sm8350-cdsp-pas";
2224 reg = <0 0x098900000 0 0x1400000>;
2226 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2227 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2228 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2229 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2230 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2231 interrupt-names = "wdog", "fatal", "ready",
2232 "handover", "stop-ack";
2234 clocks = <&rpmhcc RPMH_CXO_CLK>;
2237 power-domains = <&rpmhpd SM8350_CX>,
2238 <&rpmhpd SM8350_MXC>;
2239 power-domain-names = "cx", "mxc";
2241 interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
2243 memory-region = <&pil_cdsp_mem>;
2245 qcom,qmp = <&aoss_qmp>;
2247 qcom,smem-states = <&smp2p_cdsp_out 0>;
2248 qcom,smem-state-names = "stop";
2250 status = "disabled";
2253 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2254 IPCC_MPROC_SIGNAL_GLINK_QMP
2255 IRQ_TYPE_EDGE_RISING>;
2256 mboxes = <&ipcc IPCC_CLIENT_CDSP
2257 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2260 qcom,remote-pid = <5>;
2263 compatible = "qcom,fastrpc";
2264 qcom,glink-channels = "fastrpcglink-apps-dsp";
2266 qcom,non-secure-domain;
2267 #address-cells = <1>;
2271 compatible = "qcom,fastrpc-compute-cb";
2273 iommus = <&apps_smmu 0x2161 0x0400>,
2274 <&apps_smmu 0x1181 0x0420>;
2278 compatible = "qcom,fastrpc-compute-cb";
2280 iommus = <&apps_smmu 0x2162 0x0400>,
2281 <&apps_smmu 0x1182 0x0420>;
2285 compatible = "qcom,fastrpc-compute-cb";
2287 iommus = <&apps_smmu 0x2163 0x0400>,
2288 <&apps_smmu 0x1183 0x0420>;
2292 compatible = "qcom,fastrpc-compute-cb";
2294 iommus = <&apps_smmu 0x2164 0x0400>,
2295 <&apps_smmu 0x1184 0x0420>;
2299 compatible = "qcom,fastrpc-compute-cb";
2301 iommus = <&apps_smmu 0x2165 0x0400>,
2302 <&apps_smmu 0x1185 0x0420>;
2306 compatible = "qcom,fastrpc-compute-cb";
2308 iommus = <&apps_smmu 0x2166 0x0400>,
2309 <&apps_smmu 0x1186 0x0420>;
2313 compatible = "qcom,fastrpc-compute-cb";
2315 iommus = <&apps_smmu 0x2167 0x0400>,
2316 <&apps_smmu 0x1187 0x0420>;
2320 compatible = "qcom,fastrpc-compute-cb";
2322 iommus = <&apps_smmu 0x2168 0x0400>,
2323 <&apps_smmu 0x1188 0x0420>;
2326 /* note: secure cb9 in downstream */
2331 usb_1_hsphy: phy@88e3000 {
2332 compatible = "qcom,sm8350-usb-hs-phy",
2333 "qcom,usb-snps-hs-7nm-phy";
2334 reg = <0 0x088e3000 0 0x400>;
2335 status = "disabled";
2338 clocks = <&rpmhcc RPMH_CXO_CLK>;
2339 clock-names = "ref";
2341 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2344 usb_2_hsphy: phy@88e4000 {
2345 compatible = "qcom,sm8250-usb-hs-phy",
2346 "qcom,usb-snps-hs-7nm-phy";
2347 reg = <0 0x088e4000 0 0x400>;
2348 status = "disabled";
2351 clocks = <&rpmhcc RPMH_CXO_CLK>;
2352 clock-names = "ref";
2354 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2357 usb_1_qmpphy: phy-wrapper@88e9000 {
2358 compatible = "qcom,sm8350-qmp-usb3-phy";
2359 reg = <0 0x088e9000 0 0x200>,
2360 <0 0x088e8000 0 0x20>;
2361 status = "disabled";
2362 #address-cells = <2>;
2366 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2367 <&rpmhcc RPMH_CXO_CLK>,
2368 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2369 clock-names = "aux", "ref_clk_src", "com_aux";
2371 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2372 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2373 reset-names = "phy", "common";
2375 usb_1_ssphy: phy@88e9200 {
2376 reg = <0 0x088e9200 0 0x200>,
2377 <0 0x088e9400 0 0x200>,
2378 <0 0x088e9c00 0 0x400>,
2379 <0 0x088e9600 0 0x200>,
2380 <0 0x088e9800 0 0x200>,
2381 <0 0x088e9a00 0 0x100>;
2384 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2385 clock-names = "pipe0";
2386 clock-output-names = "usb3_phy_pipe_clk_src";
2390 usb_2_qmpphy: phy-wrapper@88eb000 {
2391 compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2392 reg = <0 0x088eb000 0 0x200>;
2393 status = "disabled";
2394 #address-cells = <2>;
2398 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2399 <&rpmhcc RPMH_CXO_CLK>,
2400 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2401 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2402 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2404 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2405 <&gcc GCC_USB3_PHY_SEC_BCR>;
2406 reset-names = "phy", "common";
2408 usb_2_ssphy: phy@88ebe00 {
2409 reg = <0 0x088ebe00 0 0x200>,
2410 <0 0x088ec000 0 0x200>,
2411 <0 0x088eb200 0 0x1100>;
2414 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2415 clock-names = "pipe0";
2416 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2420 dc_noc: interconnect@90c0000 {
2421 compatible = "qcom,sm8350-dc-noc";
2422 reg = <0 0x090c0000 0 0x4200>;
2423 #interconnect-cells = <1>;
2424 qcom,bcm-voters = <&apps_bcm_voter>;
2427 gem_noc: interconnect@9100000 {
2428 compatible = "qcom,sm8350-gem-noc";
2429 reg = <0 0x09100000 0 0xb4000>;
2430 #interconnect-cells = <1>;
2431 qcom,bcm-voters = <&apps_bcm_voter>;
2434 system-cache-controller@9200000 {
2435 compatible = "qcom,sm8350-llcc";
2436 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2437 reg-names = "llcc_base", "llcc_broadcast_base";
2440 usb_1: usb@a6f8800 {
2441 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2442 reg = <0 0x0a6f8800 0 0x400>;
2443 status = "disabled";
2444 #address-cells = <2>;
2448 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2449 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2450 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2451 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2452 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2453 clock-names = "cfg_noc",
2459 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2460 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2461 assigned-clock-rates = <19200000>, <200000000>;
2463 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2464 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
2465 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2466 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
2467 interrupt-names = "hs_phy_irq",
2472 power-domains = <&gcc USB30_PRIM_GDSC>;
2474 resets = <&gcc GCC_USB30_PRIM_BCR>;
2476 usb_1_dwc3: usb@a600000 {
2477 compatible = "snps,dwc3";
2478 reg = <0 0x0a600000 0 0xcd00>;
2479 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2480 iommus = <&apps_smmu 0x0 0x0>;
2481 snps,dis_u2_susphy_quirk;
2482 snps,dis_enblslpm_quirk;
2483 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2484 phy-names = "usb2-phy", "usb3-phy";
2488 usb_2: usb@a8f8800 {
2489 compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2490 reg = <0 0x0a8f8800 0 0x400>;
2491 status = "disabled";
2492 #address-cells = <2>;
2496 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2497 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2498 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2499 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2500 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2501 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2502 clock-names = "cfg_noc",
2509 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2510 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2511 assigned-clock-rates = <19200000>, <200000000>;
2513 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2514 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
2515 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2516 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
2517 interrupt-names = "hs_phy_irq",
2522 power-domains = <&gcc USB30_SEC_GDSC>;
2524 resets = <&gcc GCC_USB30_SEC_BCR>;
2526 usb_2_dwc3: usb@a800000 {
2527 compatible = "snps,dwc3";
2528 reg = <0 0x0a800000 0 0xcd00>;
2529 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2530 iommus = <&apps_smmu 0x20 0x0>;
2531 snps,dis_u2_susphy_quirk;
2532 snps,dis_enblslpm_quirk;
2533 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2534 phy-names = "usb2-phy", "usb3-phy";
2538 dispcc: clock-controller@af00000 {
2539 compatible = "qcom,sm8350-dispcc";
2540 reg = <0 0x0af00000 0 0x10000>;
2541 clocks = <&rpmhcc RPMH_CXO_CLK>,
2548 clock-names = "bi_tcxo",
2549 "dsi0_phy_pll_out_byteclk",
2550 "dsi0_phy_pll_out_dsiclk",
2551 "dsi1_phy_pll_out_byteclk",
2552 "dsi1_phy_pll_out_dsiclk",
2553 "dp_phy_pll_link_clk",
2554 "dp_phy_pll_vco_div_clk";
2557 #power-domain-cells = <1>;
2559 power-domains = <&rpmhpd SM8350_MMCX>;
2560 power-domain-names = "mmcx";
2563 adsp: remoteproc@17300000 {
2564 compatible = "qcom,sm8350-adsp-pas";
2565 reg = <0 0x17300000 0 0x100>;
2567 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2568 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2569 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2570 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2571 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2572 interrupt-names = "wdog", "fatal", "ready",
2573 "handover", "stop-ack";
2575 clocks = <&rpmhcc RPMH_CXO_CLK>;
2578 power-domains = <&rpmhpd SM8350_LCX>,
2579 <&rpmhpd SM8350_LMX>;
2580 power-domain-names = "lcx", "lmx";
2582 memory-region = <&pil_adsp_mem>;
2584 qcom,qmp = <&aoss_qmp>;
2586 qcom,smem-states = <&smp2p_adsp_out 0>;
2587 qcom,smem-state-names = "stop";
2589 status = "disabled";
2592 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2593 IPCC_MPROC_SIGNAL_GLINK_QMP
2594 IRQ_TYPE_EDGE_RISING>;
2595 mboxes = <&ipcc IPCC_CLIENT_LPASS
2596 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2599 qcom,remote-pid = <2>;
2602 compatible = "qcom,fastrpc";
2603 qcom,glink-channels = "fastrpcglink-apps-dsp";
2605 qcom,non-secure-domain;
2606 #address-cells = <1>;
2610 compatible = "qcom,fastrpc-compute-cb";
2612 iommus = <&apps_smmu 0x1803 0x0>;
2616 compatible = "qcom,fastrpc-compute-cb";
2618 iommus = <&apps_smmu 0x1804 0x0>;
2622 compatible = "qcom,fastrpc-compute-cb";
2624 iommus = <&apps_smmu 0x1805 0x0>;
2631 thermal_zones: thermal-zones {
2633 polling-delay-passive = <250>;
2634 polling-delay = <1000>;
2636 thermal-sensors = <&tsens0 1>;
2639 cpu0_alert0: trip-point0 {
2640 temperature = <90000>;
2641 hysteresis = <2000>;
2645 cpu0_alert1: trip-point1 {
2646 temperature = <95000>;
2647 hysteresis = <2000>;
2651 cpu0_crit: cpu_crit {
2652 temperature = <110000>;
2653 hysteresis = <1000>;
2660 trip = <&cpu0_alert0>;
2661 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2662 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2663 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2664 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2667 trip = <&cpu0_alert1>;
2668 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2669 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2670 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2671 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2677 polling-delay-passive = <250>;
2678 polling-delay = <1000>;
2680 thermal-sensors = <&tsens0 2>;
2683 cpu1_alert0: trip-point0 {
2684 temperature = <90000>;
2685 hysteresis = <2000>;
2689 cpu1_alert1: trip-point1 {
2690 temperature = <95000>;
2691 hysteresis = <2000>;
2695 cpu1_crit: cpu_crit {
2696 temperature = <110000>;
2697 hysteresis = <1000>;
2704 trip = <&cpu1_alert0>;
2705 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2706 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2707 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2708 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2711 trip = <&cpu1_alert1>;
2712 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2713 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2714 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2715 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2721 polling-delay-passive = <250>;
2722 polling-delay = <1000>;
2724 thermal-sensors = <&tsens0 3>;
2727 cpu2_alert0: trip-point0 {
2728 temperature = <90000>;
2729 hysteresis = <2000>;
2733 cpu2_alert1: trip-point1 {
2734 temperature = <95000>;
2735 hysteresis = <2000>;
2739 cpu2_crit: cpu_crit {
2740 temperature = <110000>;
2741 hysteresis = <1000>;
2748 trip = <&cpu2_alert0>;
2749 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2750 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2751 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2752 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2755 trip = <&cpu2_alert1>;
2756 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2757 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2758 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2759 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2765 polling-delay-passive = <250>;
2766 polling-delay = <1000>;
2768 thermal-sensors = <&tsens0 4>;
2771 cpu3_alert0: trip-point0 {
2772 temperature = <90000>;
2773 hysteresis = <2000>;
2777 cpu3_alert1: trip-point1 {
2778 temperature = <95000>;
2779 hysteresis = <2000>;
2783 cpu3_crit: cpu_crit {
2784 temperature = <110000>;
2785 hysteresis = <1000>;
2792 trip = <&cpu3_alert0>;
2793 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2794 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2795 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2796 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2799 trip = <&cpu3_alert1>;
2800 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2801 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2802 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2803 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2809 polling-delay-passive = <250>;
2810 polling-delay = <1000>;
2812 thermal-sensors = <&tsens0 7>;
2815 cpu4_top_alert0: trip-point0 {
2816 temperature = <90000>;
2817 hysteresis = <2000>;
2821 cpu4_top_alert1: trip-point1 {
2822 temperature = <95000>;
2823 hysteresis = <2000>;
2827 cpu4_top_crit: cpu_crit {
2828 temperature = <110000>;
2829 hysteresis = <1000>;
2836 trip = <&cpu4_top_alert0>;
2837 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2838 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2839 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2840 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2843 trip = <&cpu4_top_alert1>;
2844 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2845 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2846 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2847 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2853 polling-delay-passive = <250>;
2854 polling-delay = <1000>;
2856 thermal-sensors = <&tsens0 8>;
2859 cpu5_top_alert0: trip-point0 {
2860 temperature = <90000>;
2861 hysteresis = <2000>;
2865 cpu5_top_alert1: trip-point1 {
2866 temperature = <95000>;
2867 hysteresis = <2000>;
2871 cpu5_top_crit: cpu_crit {
2872 temperature = <110000>;
2873 hysteresis = <1000>;
2880 trip = <&cpu5_top_alert0>;
2881 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2882 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2883 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2884 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2887 trip = <&cpu5_top_alert1>;
2888 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2889 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2890 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2891 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2897 polling-delay-passive = <250>;
2898 polling-delay = <1000>;
2900 thermal-sensors = <&tsens0 9>;
2903 cpu6_top_alert0: trip-point0 {
2904 temperature = <90000>;
2905 hysteresis = <2000>;
2909 cpu6_top_alert1: trip-point1 {
2910 temperature = <95000>;
2911 hysteresis = <2000>;
2915 cpu6_top_crit: cpu_crit {
2916 temperature = <110000>;
2917 hysteresis = <1000>;
2924 trip = <&cpu6_top_alert0>;
2925 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2926 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2927 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2928 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2931 trip = <&cpu6_top_alert1>;
2932 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2933 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2934 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2935 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2941 polling-delay-passive = <250>;
2942 polling-delay = <1000>;
2944 thermal-sensors = <&tsens0 10>;
2947 cpu7_top_alert0: trip-point0 {
2948 temperature = <90000>;
2949 hysteresis = <2000>;
2953 cpu7_top_alert1: trip-point1 {
2954 temperature = <95000>;
2955 hysteresis = <2000>;
2959 cpu7_top_crit: cpu_crit {
2960 temperature = <110000>;
2961 hysteresis = <1000>;
2968 trip = <&cpu7_top_alert0>;
2969 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2970 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2971 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2972 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2975 trip = <&cpu7_top_alert1>;
2976 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2977 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2978 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2979 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2984 cpu4-bottom-thermal {
2985 polling-delay-passive = <250>;
2986 polling-delay = <1000>;
2988 thermal-sensors = <&tsens0 11>;
2991 cpu4_bottom_alert0: trip-point0 {
2992 temperature = <90000>;
2993 hysteresis = <2000>;
2997 cpu4_bottom_alert1: trip-point1 {
2998 temperature = <95000>;
2999 hysteresis = <2000>;
3003 cpu4_bottom_crit: cpu_crit {
3004 temperature = <110000>;
3005 hysteresis = <1000>;
3012 trip = <&cpu4_bottom_alert0>;
3013 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3014 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3015 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3016 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3019 trip = <&cpu4_bottom_alert1>;
3020 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3021 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3022 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3023 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3028 cpu5-bottom-thermal {
3029 polling-delay-passive = <250>;
3030 polling-delay = <1000>;
3032 thermal-sensors = <&tsens0 12>;
3035 cpu5_bottom_alert0: trip-point0 {
3036 temperature = <90000>;
3037 hysteresis = <2000>;
3041 cpu5_bottom_alert1: trip-point1 {
3042 temperature = <95000>;
3043 hysteresis = <2000>;
3047 cpu5_bottom_crit: cpu_crit {
3048 temperature = <110000>;
3049 hysteresis = <1000>;
3056 trip = <&cpu5_bottom_alert0>;
3057 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3058 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3059 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3060 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3063 trip = <&cpu5_bottom_alert1>;
3064 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3065 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3066 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3067 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3072 cpu6-bottom-thermal {
3073 polling-delay-passive = <250>;
3074 polling-delay = <1000>;
3076 thermal-sensors = <&tsens0 13>;
3079 cpu6_bottom_alert0: trip-point0 {
3080 temperature = <90000>;
3081 hysteresis = <2000>;
3085 cpu6_bottom_alert1: trip-point1 {
3086 temperature = <95000>;
3087 hysteresis = <2000>;
3091 cpu6_bottom_crit: cpu_crit {
3092 temperature = <110000>;
3093 hysteresis = <1000>;
3100 trip = <&cpu6_bottom_alert0>;
3101 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3102 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3103 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3104 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3107 trip = <&cpu6_bottom_alert1>;
3108 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3109 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3110 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3111 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3116 cpu7-bottom-thermal {
3117 polling-delay-passive = <250>;
3118 polling-delay = <1000>;
3120 thermal-sensors = <&tsens0 14>;
3123 cpu7_bottom_alert0: trip-point0 {
3124 temperature = <90000>;
3125 hysteresis = <2000>;
3129 cpu7_bottom_alert1: trip-point1 {
3130 temperature = <95000>;
3131 hysteresis = <2000>;
3135 cpu7_bottom_crit: cpu_crit {
3136 temperature = <110000>;
3137 hysteresis = <1000>;
3144 trip = <&cpu7_bottom_alert0>;
3145 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3146 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3147 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3148 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3151 trip = <&cpu7_bottom_alert1>;
3152 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3153 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3154 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3155 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3161 polling-delay-passive = <250>;
3162 polling-delay = <1000>;
3164 thermal-sensors = <&tsens0 0>;
3167 aoss0_alert0: trip-point0 {
3168 temperature = <90000>;
3169 hysteresis = <2000>;
3176 polling-delay-passive = <250>;
3177 polling-delay = <1000>;
3179 thermal-sensors = <&tsens0 5>;
3182 cluster0_alert0: trip-point0 {
3183 temperature = <90000>;
3184 hysteresis = <2000>;
3187 cluster0_crit: cluster0_crit {
3188 temperature = <110000>;
3189 hysteresis = <2000>;
3196 polling-delay-passive = <250>;
3197 polling-delay = <1000>;
3199 thermal-sensors = <&tsens0 6>;
3202 cluster1_alert0: trip-point0 {
3203 temperature = <90000>;
3204 hysteresis = <2000>;
3207 cluster1_crit: cluster1_crit {
3208 temperature = <110000>;
3209 hysteresis = <2000>;
3216 polling-delay-passive = <250>;
3217 polling-delay = <1000>;
3219 thermal-sensors = <&tsens1 0>;
3222 aoss1_alert0: trip-point0 {
3223 temperature = <90000>;
3224 hysteresis = <2000>;
3231 polling-delay-passive = <250>;
3232 polling-delay = <1000>;
3234 thermal-sensors = <&tsens1 1>;
3237 gpu1_alert0: trip-point0 {
3238 temperature = <90000>;
3239 hysteresis = <1000>;
3245 gpu-bottom-thermal {
3246 polling-delay-passive = <250>;
3247 polling-delay = <1000>;
3249 thermal-sensors = <&tsens1 2>;
3252 gpu2_alert0: trip-point0 {
3253 temperature = <90000>;
3254 hysteresis = <1000>;
3261 polling-delay-passive = <250>;
3262 polling-delay = <1000>;
3264 thermal-sensors = <&tsens1 3>;
3267 nspss1_alert0: trip-point0 {
3268 temperature = <90000>;
3269 hysteresis = <1000>;
3276 polling-delay-passive = <250>;
3277 polling-delay = <1000>;
3279 thermal-sensors = <&tsens1 4>;
3282 nspss2_alert0: trip-point0 {
3283 temperature = <90000>;
3284 hysteresis = <1000>;
3291 polling-delay-passive = <250>;
3292 polling-delay = <1000>;
3294 thermal-sensors = <&tsens1 5>;
3297 nspss3_alert0: trip-point0 {
3298 temperature = <90000>;
3299 hysteresis = <1000>;
3306 polling-delay-passive = <250>;
3307 polling-delay = <1000>;
3309 thermal-sensors = <&tsens1 6>;
3312 video_alert0: trip-point0 {
3313 temperature = <90000>;
3314 hysteresis = <2000>;
3321 polling-delay-passive = <250>;
3322 polling-delay = <1000>;
3324 thermal-sensors = <&tsens1 7>;
3327 mem_alert0: trip-point0 {
3328 temperature = <90000>;
3329 hysteresis = <2000>;
3335 modem1-top-thermal {
3336 polling-delay-passive = <250>;
3337 polling-delay = <1000>;
3339 thermal-sensors = <&tsens1 8>;
3342 modem1_alert0: trip-point0 {
3343 temperature = <90000>;
3344 hysteresis = <2000>;
3350 modem2-top-thermal {
3351 polling-delay-passive = <250>;
3352 polling-delay = <1000>;
3354 thermal-sensors = <&tsens1 9>;
3357 modem2_alert0: trip-point0 {
3358 temperature = <90000>;
3359 hysteresis = <2000>;
3365 modem3-top-thermal {
3366 polling-delay-passive = <250>;
3367 polling-delay = <1000>;
3369 thermal-sensors = <&tsens1 10>;
3372 modem3_alert0: trip-point0 {
3373 temperature = <90000>;
3374 hysteresis = <2000>;
3380 modem4-top-thermal {
3381 polling-delay-passive = <250>;
3382 polling-delay = <1000>;
3384 thermal-sensors = <&tsens1 11>;
3387 modem4_alert0: trip-point0 {
3388 temperature = <90000>;
3389 hysteresis = <2000>;
3395 camera-top-thermal {
3396 polling-delay-passive = <250>;
3397 polling-delay = <1000>;
3399 thermal-sensors = <&tsens1 12>;
3402 camera1_alert0: trip-point0 {
3403 temperature = <90000>;
3404 hysteresis = <2000>;
3410 cam-bottom-thermal {
3411 polling-delay-passive = <250>;
3412 polling-delay = <1000>;
3414 thermal-sensors = <&tsens1 13>;
3417 camera2_alert0: trip-point0 {
3418 temperature = <90000>;
3419 hysteresis = <2000>;
3427 compatible = "arm,armv8-timer";
3428 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3429 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3430 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3431 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;