arch/arm64/boot/dts/qcom/sm8350.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interconnect/qcom,sm8350.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
   9 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sm8350.h>
  11 #include <dt-bindings/clock/qcom,rpmh.h>
  12 #include <dt-bindings/dma/qcom-gpi.h>
  13 #include <dt-bindings/gpio/gpio.h>
  14 #include <dt-bindings/interconnect/qcom,sm8350.h>
  15 #include <dt-bindings/mailbox/qcom-ipcc.h>
  16 #include <dt-bindings/phy/phy-qcom-qmp.h>
  17 #include <dt-bindings/power/qcom-rpmpd.h>
  18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  19 #include <dt-bindings/thermal/thermal.h>
  20 #include <dt-bindings/interconnect/qcom,sm8350.h>
  21
  22 / {
  23         interrupt-parent = <&intc>;
  24
  25         #address-cells = <2>;
  26         #size-cells = <2>;
  27
  28         chosen { };
  29
  30         clocks {
  31                 xo_board: xo-board {
  32                         compatible = "fixed-clock";
  33                         #clock-cells = <0>;
  34                         clock-frequency = <38400000>;
  35                         clock-output-names = "xo_board";
  36                 };
  37
  38                 sleep_clk: sleep-clk {
  39                         compatible = "fixed-clock";
  40                         clock-frequency = <32000>;
  41                         #clock-cells = <0>;
  42                 };
  43         };
  44
  45         cpus {
  46                 #address-cells = <2>;
  47                 #size-cells = <0>;
  48
  49                 CPU0: cpu@0 {
  50                         device_type = "cpu";
  51                         compatible = "qcom,kryo685";
  52                         reg = <0x0 0x0>;
  53                         clocks = <&cpufreq_hw 0>;
  54                         enable-method = "psci";
  55                         next-level-cache = <&L2_0>;
  56                         qcom,freq-domain = <&cpufreq_hw 0>;
  57                         power-domains = <&CPU_PD0>;
  58                         power-domain-names = "psci";
  59                         #cooling-cells = <2>;
  60                         L2_0: l2-cache {
  61                                 compatible = "cache";
  62                                 cache-level = <2>;
  63                                 cache-unified;
  64                                 next-level-cache = <&L3_0>;
  65                                 L3_0: l3-cache {
  66                                         compatible = "cache";
  67                                         cache-level = <3>;
  68                                         cache-unified;
  69                                 };
  70                         };
  71                 };
  72
  73                 CPU1: cpu@100 {
  74                         device_type = "cpu";
  75                         compatible = "qcom,kryo685";
  76                         reg = <0x0 0x100>;
  77                         clocks = <&cpufreq_hw 0>;
  78                         enable-method = "psci";
  79                         next-level-cache = <&L2_100>;
  80                         qcom,freq-domain = <&cpufreq_hw 0>;
  81                         power-domains = <&CPU_PD1>;
  82                         power-domain-names = "psci";
  83                         #cooling-cells = <2>;
  84                         L2_100: l2-cache {
  85                                 compatible = "cache";
  86                                 cache-level = <2>;
  87                                 cache-unified;
  88                                 next-level-cache = <&L3_0>;
  89                         };
  90                 };
  91
  92                 CPU2: cpu@200 {
  93                         device_type = "cpu";
  94                         compatible = "qcom,kryo685";
  95                         reg = <0x0 0x200>;
  96                         clocks = <&cpufreq_hw 0>;
  97                         enable-method = "psci";
  98                         next-level-cache = <&L2_200>;
  99                         qcom,freq-domain = <&cpufreq_hw 0>;
 100                         power-domains = <&CPU_PD2>;
 101                         power-domain-names = "psci";
 102                         #cooling-cells = <2>;
 103                         L2_200: l2-cache {
 104                                 compatible = "cache";
 105                                 cache-level = <2>;
 106                                 cache-unified;
 107                                 next-level-cache = <&L3_0>;
 108                         };
 109                 };
 110
 111                 CPU3: cpu@300 {
 112                         device_type = "cpu";
 113                         compatible = "qcom,kryo685";
 114                         reg = <0x0 0x300>;
 115                         clocks = <&cpufreq_hw 0>;
 116                         enable-method = "psci";
 117                         next-level-cache = <&L2_300>;
 118                         qcom,freq-domain = <&cpufreq_hw 0>;
 119                         power-domains = <&CPU_PD3>;
 120                         power-domain-names = "psci";
 121                         #cooling-cells = <2>;
 122                         L2_300: l2-cache {
 123                                 compatible = "cache";
 124                                 cache-level = <2>;
 125                                 cache-unified;
 126                                 next-level-cache = <&L3_0>;
 127                         };
 128                 };
 129
 130                 CPU4: cpu@400 {
 131                         device_type = "cpu";
 132                         compatible = "qcom,kryo685";
 133                         reg = <0x0 0x400>;
 134                         clocks = <&cpufreq_hw 1>;
 135                         enable-method = "psci";
 136                         next-level-cache = <&L2_400>;
 137                         qcom,freq-domain = <&cpufreq_hw 1>;
 138                         power-domains = <&CPU_PD4>;
 139                         power-domain-names = "psci";
 140                         #cooling-cells = <2>;
 141                         L2_400: l2-cache {
 142                                 compatible = "cache";
 143                                 cache-level = <2>;
 144                                 cache-unified;
 145                                 next-level-cache = <&L3_0>;
 146                         };
 147                 };
 148
 149                 CPU5: cpu@500 {
 150                         device_type = "cpu";
 151                         compatible = "qcom,kryo685";
 152                         reg = <0x0 0x500>;
 153                         clocks = <&cpufreq_hw 1>;
 154                         enable-method = "psci";
 155                         next-level-cache = <&L2_500>;
 156                         qcom,freq-domain = <&cpufreq_hw 1>;
 157                         power-domains = <&CPU_PD5>;
 158                         power-domain-names = "psci";
 159                         #cooling-cells = <2>;
 160                         L2_500: l2-cache {
 161                                 compatible = "cache";
 162                                 cache-level = <2>;
 163                                 cache-unified;
 164                                 next-level-cache = <&L3_0>;
 165                         };
 166                 };
 167
 168                 CPU6: cpu@600 {
 169                         device_type = "cpu";
 170                         compatible = "qcom,kryo685";
 171                         reg = <0x0 0x600>;
 172                         clocks = <&cpufreq_hw 1>;
 173                         enable-method = "psci";
 174                         next-level-cache = <&L2_600>;
 175                         qcom,freq-domain = <&cpufreq_hw 1>;
 176                         power-domains = <&CPU_PD6>;
 177                         power-domain-names = "psci";
 178                         #cooling-cells = <2>;
 179                         L2_600: l2-cache {
 180                                 compatible = "cache";
 181                                 cache-level = <2>;
 182                                 cache-unified;
 183                                 next-level-cache = <&L3_0>;
 184                         };
 185                 };
 186
 187                 CPU7: cpu@700 {
 188                         device_type = "cpu";
 189                         compatible = "qcom,kryo685";
 190                         reg = <0x0 0x700>;
 191                         clocks = <&cpufreq_hw 2>;
 192                         enable-method = "psci";
 193                         next-level-cache = <&L2_700>;
 194                         qcom,freq-domain = <&cpufreq_hw 2>;
 195                         power-domains = <&CPU_PD7>;
 196                         power-domain-names = "psci";
 197                         #cooling-cells = <2>;
 198                         L2_700: l2-cache {
 199                                 compatible = "cache";
 200                                 cache-level = <2>;
 201                                 cache-unified;
 202                                 next-level-cache = <&L3_0>;
 203                         };
 204                 };
 205
 206                 cpu-map {
 207                         cluster0 {
 208                                 core0 {
 209                                         cpu = <&CPU0>;
 210                                 };
 211
 212                                 core1 {
 213                                         cpu = <&CPU1>;
 214                                 };
 215
 216                                 core2 {
 217                                         cpu = <&CPU2>;
 218                                 };
 219
 220                                 core3 {
 221                                         cpu = <&CPU3>;
 222                                 };
 223
 224                                 core4 {
 225                                         cpu = <&CPU4>;
 226                                 };
 227
 228                                 core5 {
 229                                         cpu = <&CPU5>;
 230                                 };
 231
 232                                 core6 {
 233                                         cpu = <&CPU6>;
 234                                 };
 235
 236                                 core7 {
 237                                         cpu = <&CPU7>;
 238                                 };
 239                         };
 240                 };
 241
 242                 idle-states {
 243                         entry-method = "psci";
 244
 245                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 246                                 compatible = "arm,idle-state";
 247                                 idle-state-name = "silver-rail-power-collapse";
 248                                 arm,psci-suspend-param = <0x40000004>;
 249                                 entry-latency-us = <355>;
 250                                 exit-latency-us = <909>;
 251                                 min-residency-us = <3934>;
 252                                 local-timer-stop;
 253                         };
 254
 255                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 256                                 compatible = "arm,idle-state";
 257                                 idle-state-name = "gold-rail-power-collapse";
 258                                 arm,psci-suspend-param = <0x40000004>;
 259                                 entry-latency-us = <241>;
 260                                 exit-latency-us = <1461>;
 261                                 min-residency-us = <4488>;
 262                                 local-timer-stop;
 263                         };
 264                 };
 265
 266                 domain-idle-states {
 267                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 268                                 compatible = "domain-idle-state";
 269                                 arm,psci-suspend-param = <0x4100c344>;
 270                                 entry-latency-us = <3263>;
 271                                 exit-latency-us = <6562>;
 272                                 min-residency-us = <9987>;
 273                         };
 274                 };
 275         };
 276
 277         firmware {
 278                 scm: scm {
 279                         compatible = "qcom,scm-sm8350", "qcom,scm";
 280                         #reset-cells = <1>;
 281                 };
 282         };
 283
 284         memory@80000000 {
 285                 device_type = "memory";
 286                 /* We expect the bootloader to fill in the size */
 287                 reg = <0x0 0x80000000 0x0 0x0>;
 288         };
 289
 290         pmu {
 291                 compatible = "arm,armv8-pmuv3";
 292                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 293         };
 294
 295         psci {
 296                 compatible = "arm,psci-1.0";
 297                 method = "smc";
 298
 299                 CPU_PD0: power-domain-cpu0 {
 300                         #power-domain-cells = <0>;
 301                         power-domains = <&CLUSTER_PD>;
 302                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 303                 };
 304
 305                 CPU_PD1: power-domain-cpu1 {
 306                         #power-domain-cells = <0>;
 307                         power-domains = <&CLUSTER_PD>;
 308                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 309                 };
 310
 311                 CPU_PD2: power-domain-cpu2 {
 312                         #power-domain-cells = <0>;
 313                         power-domains = <&CLUSTER_PD>;
 314                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 315                 };
 316
 317                 CPU_PD3: power-domain-cpu3 {
 318                         #power-domain-cells = <0>;
 319                         power-domains = <&CLUSTER_PD>;
 320                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 321                 };
 322
 323                 CPU_PD4: power-domain-cpu4 {
 324                         #power-domain-cells = <0>;
 325                         power-domains = <&CLUSTER_PD>;
 326                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 327                 };
 328
 329                 CPU_PD5: power-domain-cpu5 {
 330                         #power-domain-cells = <0>;
 331                         power-domains = <&CLUSTER_PD>;
 332                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 333                 };
 334
 335                 CPU_PD6: power-domain-cpu6 {
 336                         #power-domain-cells = <0>;
 337                         power-domains = <&CLUSTER_PD>;
 338                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 339                 };
 340
 341                 CPU_PD7: power-domain-cpu7 {
 342                         #power-domain-cells = <0>;
 343                         power-domains = <&CLUSTER_PD>;
 344                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 345                 };
 346
 347                 CLUSTER_PD: power-domain-cpu-cluster0 {
 348                         #power-domain-cells = <0>;
 349                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 350                 };
 351         };
 352
 353         qup_opp_table_100mhz: opp-table-qup100mhz {
 354                 compatible = "operating-points-v2";
 355
 356                 opp-50000000 {
 357                         opp-hz = /bits/ 64 <50000000>;
 358                         required-opps = <&rpmhpd_opp_min_svs>;
 359                 };
 360
 361                 opp-75000000 {
 362                         opp-hz = /bits/ 64 <75000000>;
 363                         required-opps = <&rpmhpd_opp_low_svs>;
 364                 };
 365
 366                 opp-100000000 {
 367                         opp-hz = /bits/ 64 <100000000>;
 368                         required-opps = <&rpmhpd_opp_svs>;
 369                 };
 370         };
 371
 372         qup_opp_table_120mhz: opp-table-qup120mhz {
 373                 compatible = "operating-points-v2";
 374
 375                 opp-50000000 {
 376                         opp-hz = /bits/ 64 <50000000>;
 377                         required-opps = <&rpmhpd_opp_min_svs>;
 378                 };
 379
 380                 opp-75000000 {
 381                         opp-hz = /bits/ 64 <75000000>;
 382                         required-opps = <&rpmhpd_opp_low_svs>;
 383                 };
 384
 385                 opp-120000000 {
 386                         opp-hz = /bits/ 64 <120000000>;
 387                         required-opps = <&rpmhpd_opp_svs>;
 388                 };
 389         };
 390
 391         reserved_memory: reserved-memory {
 392                 #address-cells = <2>;
 393                 #size-cells = <2>;
 394                 ranges;
 395
 396                 hyp_mem: memory@80000000 {
 397                         reg = <0x0 0x80000000 0x0 0x600000>;
 398                         no-map;
 399                 };
 400
 401                 xbl_aop_mem: memory@80700000 {
 402                         no-map;
 403                         reg = <0x0 0x80700000 0x0 0x160000>;
 404                 };
 405
 406                 cmd_db: memory@80860000 {
 407                         compatible = "qcom,cmd-db";
 408                         reg = <0x0 0x80860000 0x0 0x20000>;
 409                         no-map;
 410                 };
 411
 412                 reserved_xbl_uefi_log: memory@80880000 {
 413                         reg = <0x0 0x80880000 0x0 0x14000>;
 414                         no-map;
 415                 };
 416
 417                 smem@80900000 {
 418                         compatible = "qcom,smem";
 419                         reg = <0x0 0x80900000 0x0 0x200000>;
 420                         hwlocks = <&tcsr_mutex 3>;
 421                         no-map;
 422                 };
 423
 424                 cpucp_fw_mem: memory@80b00000 {
 425                         reg = <0x0 0x80b00000 0x0 0x100000>;
 426                         no-map;
 427                 };
 428
 429                 cdsp_secure_heap: memory@80c00000 {
 430                         reg = <0x0 0x80c00000 0x0 0x4600000>;
 431                         no-map;
 432                 };
 433
 434                 pil_camera_mem: mmeory@85200000 {
 435                         reg = <0x0 0x85200000 0x0 0x500000>;
 436                         no-map;
 437                 };
 438
 439                 pil_video_mem: memory@85700000 {
 440                         reg = <0x0 0x85700000 0x0 0x500000>;
 441                         no-map;
 442                 };
 443
 444                 pil_cvp_mem: memory@85c00000 {
 445                         reg = <0x0 0x85c00000 0x0 0x500000>;
 446                         no-map;
 447                 };
 448
 449                 pil_adsp_mem: memory@86100000 {
 450                         reg = <0x0 0x86100000 0x0 0x2100000>;
 451                         no-map;
 452                 };
 453
 454                 pil_slpi_mem: memory@88200000 {
 455                         reg = <0x0 0x88200000 0x0 0x1500000>;
 456                         no-map;
 457                 };
 458
 459                 pil_cdsp_mem: memory@89700000 {
 460                         reg = <0x0 0x89700000 0x0 0x1e00000>;
 461                         no-map;
 462                 };
 463
 464                 pil_ipa_fw_mem: memory@8b500000 {
 465                         reg = <0x0 0x8b500000 0x0 0x10000>;
 466                         no-map;
 467                 };
 468
 469                 pil_ipa_gsi_mem: memory@8b510000 {
 470                         reg = <0x0 0x8b510000 0x0 0xa000>;
 471                         no-map;
 472                 };
 473
 474                 pil_gpu_mem: memory@8b51a000 {
 475                         reg = <0x0 0x8b51a000 0x0 0x2000>;
 476                         no-map;
 477                 };
 478
 479                 pil_spss_mem: memory@8b600000 {
 480                         reg = <0x0 0x8b600000 0x0 0x100000>;
 481                         no-map;
 482                 };
 483
 484                 pil_modem_mem: memory@8b800000 {
 485                         reg = <0x0 0x8b800000 0x0 0x10000000>;
 486                         no-map;
 487                 };
 488
 489                 rmtfs_mem: memory@9b800000 {
 490                         compatible = "qcom,rmtfs-mem";
 491                         reg = <0x0 0x9b800000 0x0 0x280000>;
 492                         no-map;
 493
 494                         qcom,client-id = <1>;
 495                         qcom,vmid = <15>;
 496                 };
 497
 498                 hyp_reserved_mem: memory@d0000000 {
 499                         reg = <0x0 0xd0000000 0x0 0x800000>;
 500                         no-map;
 501                 };
 502
 503                 pil_trustedvm_mem: memory@d0800000 {
 504                         reg = <0x0 0xd0800000 0x0 0x76f7000>;
 505                         no-map;
 506                 };
 507
 508                 qrtr_shbuf: memory@d7ef7000 {
 509                         reg = <0x0 0xd7ef7000 0x0 0x9000>;
 510                         no-map;
 511                 };
 512
 513                 chan0_shbuf: memory@d7f00000 {
 514                         reg = <0x0 0xd7f00000 0x0 0x80000>;
 515                         no-map;
 516                 };
 517
 518                 chan1_shbuf: memory@d7f80000 {
 519                         reg = <0x0 0xd7f80000 0x0 0x80000>;
 520                         no-map;
 521                 };
 522
 523                 removed_mem: memory@d8800000 {
 524                         reg = <0x0 0xd8800000 0x0 0x6800000>;
 525                         no-map;
 526                 };
 527         };
 528
 529         smp2p-adsp {
 530                 compatible = "qcom,smp2p";
 531                 qcom,smem = <443>, <429>;
 532                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 533                                              IPCC_MPROC_SIGNAL_SMP2P
 534                                              IRQ_TYPE_EDGE_RISING>;
 535                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 536                                 IPCC_MPROC_SIGNAL_SMP2P>;
 537
 538                 qcom,local-pid = <0>;
 539                 qcom,remote-pid = <2>;
 540
 541                 smp2p_adsp_out: master-kernel {
 542                         qcom,entry-name = "master-kernel";
 543                         #qcom,smem-state-cells = <1>;
 544                 };
 545
 546                 smp2p_adsp_in: slave-kernel {
 547                         qcom,entry-name = "slave-kernel";
 548                         interrupt-controller;
 549                         #interrupt-cells = <2>;
 550                 };
 551         };
 552
 553         smp2p-cdsp {
 554                 compatible = "qcom,smp2p";
 555                 qcom,smem = <94>, <432>;
 556                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 557                                              IPCC_MPROC_SIGNAL_SMP2P
 558                                              IRQ_TYPE_EDGE_RISING>;
 559                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 560                                 IPCC_MPROC_SIGNAL_SMP2P>;
 561
 562                 qcom,local-pid = <0>;
 563                 qcom,remote-pid = <5>;
 564
 565                 smp2p_cdsp_out: master-kernel {
 566                         qcom,entry-name = "master-kernel";
 567                         #qcom,smem-state-cells = <1>;
 568                 };
 569
 570                 smp2p_cdsp_in: slave-kernel {
 571                         qcom,entry-name = "slave-kernel";
 572                         interrupt-controller;
 573                         #interrupt-cells = <2>;
 574                 };
 575         };
 576
 577         smp2p-modem {
 578                 compatible = "qcom,smp2p";
 579                 qcom,smem = <435>, <428>;
 580                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 581                                              IPCC_MPROC_SIGNAL_SMP2P
 582                                              IRQ_TYPE_EDGE_RISING>;
 583                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 584                                 IPCC_MPROC_SIGNAL_SMP2P>;
 585
 586                 qcom,local-pid = <0>;
 587                 qcom,remote-pid = <1>;
 588
 589                 smp2p_modem_out: master-kernel {
 590                         qcom,entry-name = "master-kernel";
 591                         #qcom,smem-state-cells = <1>;
 592                 };
 593
 594                 smp2p_modem_in: slave-kernel {
 595                         qcom,entry-name = "slave-kernel";
 596                         interrupt-controller;
 597                         #interrupt-cells = <2>;
 598                 };
 599
 600                 ipa_smp2p_out: ipa-ap-to-modem {
 601                         qcom,entry-name = "ipa";
 602                         #qcom,smem-state-cells = <1>;
 603                 };
 604
 605                 ipa_smp2p_in: ipa-modem-to-ap {
 606                         qcom,entry-name = "ipa";
 607                         interrupt-controller;
 608                         #interrupt-cells = <2>;
 609                 };
 610         };
 611
 612         smp2p-slpi {
 613                 compatible = "qcom,smp2p";
 614                 qcom,smem = <481>, <430>;
 615                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 616                                              IPCC_MPROC_SIGNAL_SMP2P
 617                                              IRQ_TYPE_EDGE_RISING>;
 618                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 619                                 IPCC_MPROC_SIGNAL_SMP2P>;
 620
 621                 qcom,local-pid = <0>;
 622                 qcom,remote-pid = <3>;
 623
 624                 smp2p_slpi_out: master-kernel {
 625                         qcom,entry-name = "master-kernel";
 626                         #qcom,smem-state-cells = <1>;
 627                 };
 628
 629                 smp2p_slpi_in: slave-kernel {
 630                         qcom,entry-name = "slave-kernel";
 631                         interrupt-controller;
 632                         #interrupt-cells = <2>;
 633                 };
 634         };
 635
 636         soc: soc@0 {
 637                 #address-cells = <2>;
 638                 #size-cells = <2>;
 639                 ranges = <0 0 0 0 0x10 0>;
 640                 dma-ranges = <0 0 0 0 0x10 0>;
 641                 compatible = "simple-bus";
 642
 643                 gcc: clock-controller@100000 {
 644                         compatible = "qcom,gcc-sm8350";
 645                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 646                         #clock-cells = <1>;
 647                         #reset-cells = <1>;
 648                         #power-domain-cells = <1>;
 649                         clock-names = "bi_tcxo",
 650                                       "sleep_clk",
 651                                       "pcie_0_pipe_clk",
 652                                       "pcie_1_pipe_clk",
 653                                       "ufs_card_rx_symbol_0_clk",
 654                                       "ufs_card_rx_symbol_1_clk",
 655                                       "ufs_card_tx_symbol_0_clk",
 656                                       "ufs_phy_rx_symbol_0_clk",
 657                                       "ufs_phy_rx_symbol_1_clk",
 658                                       "ufs_phy_tx_symbol_0_clk",
 659                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk",
 660                                       "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
 661                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 662                                  <&sleep_clk>,
 663                                  <&pcie0_phy>,
 664                                  <&pcie1_phy>,
 665                                  <0>,
 666                                  <0>,
 667                                  <0>,
 668                                  <&ufs_mem_phy_lanes 0>,
 669                                  <&ufs_mem_phy_lanes 1>,
 670                                  <&ufs_mem_phy_lanes 2>,
 671                                  <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 672                                  <0>;
 673                 };
 674
 675                 ipcc: mailbox@408000 {
 676                         compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
 677                         reg = <0 0x00408000 0 0x1000>;
 678                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 679                         interrupt-controller;
 680                         #interrupt-cells = <3>;
 681                         #mbox-cells = <2>;
 682                 };
 683
 684                 gpi_dma2: dma-controller@800000 {
 685                         compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
 686                         reg = <0 0x00800000 0 0x60000>;
 687                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 688                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 689                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 690                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 693                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 695                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 696                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 697                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 698                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 699                         dma-channels = <12>;
 700                         dma-channel-mask = <0xff>;
 701                         iommus = <&apps_smmu 0x5f6 0x0>;
 702                         #dma-cells = <3>;
 703                         status = "disabled";
 704                 };
 705
 706                 qupv3_id_2: geniqup@8c0000 {
 707                         compatible = "qcom,geni-se-qup";
 708                         reg = <0x0 0x008c0000 0x0 0x6000>;
 709                         clock-names = "m-ahb", "s-ahb";
 710                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 711                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 712                         iommus = <&apps_smmu 0x5e3 0x0>;
 713                         #address-cells = <2>;
 714                         #size-cells = <2>;
 715                         ranges;
 716                         status = "disabled";
 717
 718                         i2c14: i2c@880000 {
 719                                 compatible = "qcom,geni-i2c";
 720                                 reg = <0 0x00880000 0 0x4000>;
 721                                 clock-names = "se";
 722                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 723                                 pinctrl-names = "default";
 724                                 pinctrl-0 = <&qup_i2c14_default>;
 725                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 726                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 727                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 728                                 dma-names = "tx", "rx";
 729                                 #address-cells = <1>;
 730                                 #size-cells = <0>;
 731                                 status = "disabled";
 732                         };
 733
 734                         spi14: spi@880000 {
 735                                 compatible = "qcom,geni-spi";
 736                                 reg = <0 0x00880000 0 0x4000>;
 737                                 clock-names = "se";
 738                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 739                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 740                                 power-domains = <&rpmhpd SM8350_CX>;
 741                                 operating-points-v2 = <&qup_opp_table_120mhz>;
 742                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 743                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 744                                 dma-names = "tx", "rx";
 745                                 #address-cells = <1>;
 746                                 #size-cells = <0>;
 747                                 status = "disabled";
 748                         };
 749
 750                         i2c15: i2c@884000 {
 751                                 compatible = "qcom,geni-i2c";
 752                                 reg = <0 0x00884000 0 0x4000>;
 753                                 clock-names = "se";
 754                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 755                                 pinctrl-names = "default";
 756                                 pinctrl-0 = <&qup_i2c15_default>;
 757                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 758                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 759                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 760                                 dma-names = "tx", "rx";
 761                                 #address-cells = <1>;
 762                                 #size-cells = <0>;
 763                                 status = "disabled";
 764                         };
 765
 766                         spi15: spi@884000 {
 767                                 compatible = "qcom,geni-spi";
 768                                 reg = <0 0x00884000 0 0x4000>;
 769                                 clock-names = "se";
 770                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 771                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 772                                 power-domains = <&rpmhpd SM8350_CX>;
 773                                 operating-points-v2 = <&qup_opp_table_120mhz>;
 774                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 775                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 776                                 dma-names = "tx", "rx";
 777                                 #address-cells = <1>;
 778                                 #size-cells = <0>;
 779                                 status = "disabled";
 780                         };
 781
 782                         i2c16: i2c@888000 {
 783                                 compatible = "qcom,geni-i2c";
 784                                 reg = <0 0x00888000 0 0x4000>;
 785                                 clock-names = "se";
 786                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 787                                 pinctrl-names = "default";
 788                                 pinctrl-0 = <&qup_i2c16_default>;
 789                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 790                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 791                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 792                                 dma-names = "tx", "rx";
 793                                 #address-cells = <1>;
 794                                 #size-cells = <0>;
 795                                 status = "disabled";
 796                         };
 797
 798                         spi16: spi@888000 {
 799                                 compatible = "qcom,geni-spi";
 800                                 reg = <0 0x00888000 0 0x4000>;
 801                                 clock-names = "se";
 802                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 803                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 804                                 power-domains = <&rpmhpd SM8350_CX>;
 805                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 806                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 807                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 808                                 dma-names = "tx", "rx";
 809                                 #address-cells = <1>;
 810                                 #size-cells = <0>;
 811                                 status = "disabled";
 812                         };
 813
 814                         i2c17: i2c@88c000 {
 815                                 compatible = "qcom,geni-i2c";
 816                                 reg = <0 0x0088c000 0 0x4000>;
 817                                 clock-names = "se";
 818                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 819                                 pinctrl-names = "default";
 820                                 pinctrl-0 = <&qup_i2c17_default>;
 821                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 822                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 823                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 824                                 dma-names = "tx", "rx";
 825                                 #address-cells = <1>;
 826                                 #size-cells = <0>;
 827                                 status = "disabled";
 828                         };
 829
 830                         spi17: spi@88c000 {
 831                                 compatible = "qcom,geni-spi";
 832                                 reg = <0 0x0088c000 0 0x4000>;
 833                                 clock-names = "se";
 834                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 835                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 836                                 power-domains = <&rpmhpd SM8350_CX>;
 837                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 838                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
 839                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
 840                                 dma-names = "tx", "rx";
 841                                 #address-cells = <1>;
 842                                 #size-cells = <0>;
 843                                 status = "disabled";
 844                         };
 845
 846                         /* QUP no. 18 seems to be strictly SPI/UART-only */
 847
 848                         spi18: spi@890000 {
 849                                 compatible = "qcom,geni-spi";
 850                                 reg = <0 0x00890000 0 0x4000>;
 851                                 clock-names = "se";
 852                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 853                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 854                                 power-domains = <&rpmhpd SM8350_CX>;
 855                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 856                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
 857                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
 858                                 dma-names = "tx", "rx";
 859                                 #address-cells = <1>;
 860                                 #size-cells = <0>;
 861                                 status = "disabled";
 862                         };
 863
 864                         uart18: serial@890000 {
 865                                 compatible = "qcom,geni-uart";
 866                                 reg = <0 0x00890000 0 0x4000>;
 867                                 clock-names = "se";
 868                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 869                                 pinctrl-names = "default";
 870                                 pinctrl-0 = <&qup_uart18_default>;
 871                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 872                                 power-domains = <&rpmhpd SM8350_CX>;
 873                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 874                                 status = "disabled";
 875                         };
 876
 877                         i2c19: i2c@894000 {
 878                                 compatible = "qcom,geni-i2c";
 879                                 reg = <0 0x00894000 0 0x4000>;
 880                                 clock-names = "se";
 881                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 882                                 pinctrl-names = "default";
 883                                 pinctrl-0 = <&qup_i2c19_default>;
 884                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 885                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
 886                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
 887                                 dma-names = "tx", "rx";
 888                                 #address-cells = <1>;
 889                                 #size-cells = <0>;
 890                                 status = "disabled";
 891                         };
 892
 893                         spi19: spi@894000 {
 894                                 compatible = "qcom,geni-spi";
 895                                 reg = <0 0x00894000 0 0x4000>;
 896                                 clock-names = "se";
 897                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 898                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 899                                 power-domains = <&rpmhpd SM8350_CX>;
 900                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 901                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
 902                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
 903                                 dma-names = "tx", "rx";
 904                                 #address-cells = <1>;
 905                                 #size-cells = <0>;
 906                                 status = "disabled";
 907                         };
 908                 };
 909
 910                 gpi_dma0: dma-controller@9800000 {
 911                         compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
 912                         reg = <0 0x09800000 0 0x60000>;
 913                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 914                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 915                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 916                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 917                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 918                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 919                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 920                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 921                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 922                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 923                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 924                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 925                         dma-channels = <12>;
 926                         dma-channel-mask = <0x7e>;
 927                         iommus = <&apps_smmu 0x5b6 0x0>;
 928                         #dma-cells = <3>;
 929                         status = "disabled";
 930                 };
 931
 932                 qupv3_id_0: geniqup@9c0000 {
 933                         compatible = "qcom,geni-se-qup";
 934                         reg = <0x0 0x009c0000 0x0 0x6000>;
 935                         clock-names = "m-ahb", "s-ahb";
 936                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 937                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 938                         iommus = <&apps_smmu 0x5a3 0>;
 939                         #address-cells = <2>;
 940                         #size-cells = <2>;
 941                         ranges;
 942                         status = "disabled";
 943
 944                         i2c0: i2c@980000 {
 945                                 compatible = "qcom,geni-i2c";
 946                                 reg = <0 0x00980000 0 0x4000>;
 947                                 clock-names = "se";
 948                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 949                                 pinctrl-names = "default";
 950                                 pinctrl-0 = <&qup_i2c0_default>;
 951                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 952                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 953                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 954                                 dma-names = "tx", "rx";
 955                                 #address-cells = <1>;
 956                                 #size-cells = <0>;
 957                                 status = "disabled";
 958                         };
 959
 960                         spi0: spi@980000 {
 961                                 compatible = "qcom,geni-spi";
 962                                 reg = <0 0x00980000 0 0x4000>;
 963                                 clock-names = "se";
 964                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 965                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 966                                 power-domains = <&rpmhpd SM8350_CX>;
 967                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 968                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 969                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 970                                 dma-names = "tx", "rx";
 971                                 #address-cells = <1>;
 972                                 #size-cells = <0>;
 973                                 status = "disabled";
 974                         };
 975
 976                         i2c1: i2c@984000 {
 977                                 compatible = "qcom,geni-i2c";
 978                                 reg = <0 0x00984000 0 0x4000>;
 979                                 clock-names = "se";
 980                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 981                                 pinctrl-names = "default";
 982                                 pinctrl-0 = <&qup_i2c1_default>;
 983                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 984                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 985                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 986                                 dma-names = "tx", "rx";
 987                                 #address-cells = <1>;
 988                                 #size-cells = <0>;
 989                                 status = "disabled";
 990                         };
 991
 992                         spi1: spi@984000 {
 993                                 compatible = "qcom,geni-spi";
 994                                 reg = <0 0x00984000 0 0x4000>;
 995                                 clock-names = "se";
 996                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 997                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 998                                 power-domains = <&rpmhpd SM8350_CX>;
 999                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1000                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1001                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1002                                 dma-names = "tx", "rx";
1003                                 #address-cells = <1>;
1004                                 #size-cells = <0>;
1005                                 status = "disabled";
1006                         };
1007
1008                         i2c2: i2c@988000 {
1009                                 compatible = "qcom,geni-i2c";
1010                                 reg = <0 0x00988000 0 0x4000>;
1011                                 clock-names = "se";
1012                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1013                                 pinctrl-names = "default";
1014                                 pinctrl-0 = <&qup_i2c2_default>;
1015                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1016                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1017                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1018                                 dma-names = "tx", "rx";
1019                                 #address-cells = <1>;
1020                                 #size-cells = <0>;
1021                                 status = "disabled";
1022                         };
1023
1024                         spi2: spi@988000 {
1025                                 compatible = "qcom,geni-spi";
1026                                 reg = <0 0x00988000 0 0x4000>;
1027                                 clock-names = "se";
1028                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1029                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1030                                 power-domains = <&rpmhpd SM8350_CX>;
1031                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1032                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1033                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1034                                 dma-names = "tx", "rx";
1035                                 #address-cells = <1>;
1036                                 #size-cells = <0>;
1037                                 status = "disabled";
1038                         };
1039
1040                         uart2: serial@98c000 {
1041                                 compatible = "qcom,geni-debug-uart";
1042                                 reg = <0 0x0098c000 0 0x4000>;
1043                                 clock-names = "se";
1044                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1045                                 pinctrl-names = "default";
1046                                 pinctrl-0 = <&qup_uart3_default_state>;
1047                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1048                                 power-domains = <&rpmhpd SM8350_CX>;
1049                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1050                                 status = "disabled";
1051                         };
1052
1053                         /* QUP no. 3 seems to be strictly SPI-only */
1054
1055                         spi3: spi@98c000 {
1056                                 compatible = "qcom,geni-spi";
1057                                 reg = <0 0x0098c000 0 0x4000>;
1058                                 clock-names = "se";
1059                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1060                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061                                 power-domains = <&rpmhpd SM8350_CX>;
1062                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1063                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1064                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1065                                 dma-names = "tx", "rx";
1066                                 #address-cells = <1>;
1067                                 #size-cells = <0>;
1068                                 status = "disabled";
1069                         };
1070
1071                         i2c4: i2c@990000 {
1072                                 compatible = "qcom,geni-i2c";
1073                                 reg = <0 0x00990000 0 0x4000>;
1074                                 clock-names = "se";
1075                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1076                                 pinctrl-names = "default";
1077                                 pinctrl-0 = <&qup_i2c4_default>;
1078                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1079                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1080                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1081                                 dma-names = "tx", "rx";
1082                                 #address-cells = <1>;
1083                                 #size-cells = <0>;
1084                                 status = "disabled";
1085                         };
1086
1087                         spi4: spi@990000 {
1088                                 compatible = "qcom,geni-spi";
1089                                 reg = <0 0x00990000 0 0x4000>;
1090                                 clock-names = "se";
1091                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1093                                 power-domains = <&rpmhpd SM8350_CX>;
1094                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1095                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1096                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1097                                 dma-names = "tx", "rx";
1098                                 #address-cells = <1>;
1099                                 #size-cells = <0>;
1100                                 status = "disabled";
1101                         };
1102
1103                         i2c5: i2c@994000 {
1104                                 compatible = "qcom,geni-i2c";
1105                                 reg = <0 0x00994000 0 0x4000>;
1106                                 clock-names = "se";
1107                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1108                                 pinctrl-names = "default";
1109                                 pinctrl-0 = <&qup_i2c5_default>;
1110                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1111                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1112                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1113                                 dma-names = "tx", "rx";
1114                                 #address-cells = <1>;
1115                                 #size-cells = <0>;
1116                                 status = "disabled";
1117                         };
1118
1119                         spi5: spi@994000 {
1120                                 compatible = "qcom,geni-spi";
1121                                 reg = <0 0x00994000 0 0x4000>;
1122                                 clock-names = "se";
1123                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1124                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1125                                 power-domains = <&rpmhpd SM8350_CX>;
1126                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1127                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1128                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1129                                 dma-names = "tx", "rx";
1130                                 #address-cells = <1>;
1131                                 #size-cells = <0>;
1132                                 status = "disabled";
1133                         };
1134
1135                         i2c6: i2c@998000 {
1136                                 compatible = "qcom,geni-i2c";
1137                                 reg = <0 0x00998000 0 0x4000>;
1138                                 clock-names = "se";
1139                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1140                                 pinctrl-names = "default";
1141                                 pinctrl-0 = <&qup_i2c6_default>;
1142                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1143                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1144                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1145                                 dma-names = "tx", "rx";
1146                                 #address-cells = <1>;
1147                                 #size-cells = <0>;
1148                                 status = "disabled";
1149                         };
1150
1151                         spi6: spi@998000 {
1152                                 compatible = "qcom,geni-spi";
1153                                 reg = <0 0x00998000 0 0x4000>;
1154                                 clock-names = "se";
1155                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1156                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1157                                 power-domains = <&rpmhpd SM8350_CX>;
1158                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1159                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1160                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1161                                 dma-names = "tx", "rx";
1162                                 #address-cells = <1>;
1163                                 #size-cells = <0>;
1164                                 status = "disabled";
1165                         };
1166
1167                         uart6: serial@998000 {
1168                                 compatible = "qcom,geni-uart";
1169                                 reg = <0 0x00998000 0 0x4000>;
1170                                 clock-names = "se";
1171                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1172                                 pinctrl-names = "default";
1173                                 pinctrl-0 = <&qup_uart6_default>;
1174                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1175                                 power-domains = <&rpmhpd SM8350_CX>;
1176                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1177                                 status = "disabled";
1178                         };
1179
1180                         i2c7: i2c@99c000 {
1181                                 compatible = "qcom,geni-i2c";
1182                                 reg = <0 0x0099c000 0 0x4000>;
1183                                 clock-names = "se";
1184                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1185                                 pinctrl-names = "default";
1186                                 pinctrl-0 = <&qup_i2c7_default>;
1187                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1188                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1189                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1190                                 dma-names = "tx", "rx";
1191                                 #address-cells = <1>;
1192                                 #size-cells = <0>;
1193                                 status = "disabled";
1194                         };
1195
1196                         spi7: spi@99c000 {
1197                                 compatible = "qcom,geni-spi";
1198                                 reg = <0 0x0099c000 0 0x4000>;
1199                                 clock-names = "se";
1200                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1201                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1202                                 power-domains = <&rpmhpd SM8350_CX>;
1203                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1204                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1205                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1206                                 dma-names = "tx", "rx";
1207                                 #address-cells = <1>;
1208                                 #size-cells = <0>;
1209                                 status = "disabled";
1210                         };
1211                 };
1212
1213                 gpi_dma1: dma-controller@a00000 {
1214                         compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
1215                         reg = <0 0x00a00000 0 0x60000>;
1216                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1217                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1218                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1219                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1220                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1221                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1222                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1223                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1224                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1225                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1226                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1227                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1228                         dma-channels = <12>;
1229                         dma-channel-mask = <0xff>;
1230                         iommus = <&apps_smmu 0x56 0x0>;
1231                         #dma-cells = <3>;
1232                         status = "disabled";
1233                 };
1234
1235                 qupv3_id_1: geniqup@ac0000 {
1236                         compatible = "qcom,geni-se-qup";
1237                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1238                         clock-names = "m-ahb", "s-ahb";
1239                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1240                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1241                         iommus = <&apps_smmu 0x43 0>;
1242                         #address-cells = <2>;
1243                         #size-cells = <2>;
1244                         ranges;
1245                         status = "disabled";
1246
1247                         i2c8: i2c@a80000 {
1248                                 compatible = "qcom,geni-i2c";
1249                                 reg = <0 0x00a80000 0 0x4000>;
1250                                 clock-names = "se";
1251                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1252                                 pinctrl-names = "default";
1253                                 pinctrl-0 = <&qup_i2c8_default>;
1254                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1255                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1256                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1257                                 dma-names = "tx", "rx";
1258                                 #address-cells = <1>;
1259                                 #size-cells = <0>;
1260                                 status = "disabled";
1261                         };
1262
1263                         spi8: spi@a80000 {
1264                                 compatible = "qcom,geni-spi";
1265                                 reg = <0 0x00a80000 0 0x4000>;
1266                                 clock-names = "se";
1267                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1268                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1269                                 power-domains = <&rpmhpd SM8350_CX>;
1270                                 operating-points-v2 = <&qup_opp_table_120mhz>;
1271                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1272                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1273                                 dma-names = "tx", "rx";
1274                                 #address-cells = <1>;
1275                                 #size-cells = <0>;
1276                                 status = "disabled";
1277                         };
1278
1279                         i2c9: i2c@a84000 {
1280                                 compatible = "qcom,geni-i2c";
1281                                 reg = <0 0x00a84000 0 0x4000>;
1282                                 clock-names = "se";
1283                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1284                                 pinctrl-names = "default";
1285                                 pinctrl-0 = <&qup_i2c9_default>;
1286                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1287                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1288                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1289                                 dma-names = "tx", "rx";
1290                                 #address-cells = <1>;
1291                                 #size-cells = <0>;
1292                                 status = "disabled";
1293                         };
1294
1295                         spi9: spi@a84000 {
1296                                 compatible = "qcom,geni-spi";
1297                                 reg = <0 0x00a84000 0 0x4000>;
1298                                 clock-names = "se";
1299                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1300                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1301                                 power-domains = <&rpmhpd SM8350_CX>;
1302                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1303                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1304                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1305                                 dma-names = "tx", "rx";
1306                                 #address-cells = <1>;
1307                                 #size-cells = <0>;
1308                                 status = "disabled";
1309                         };
1310
1311                         i2c10: i2c@a88000 {
1312                                 compatible = "qcom,geni-i2c";
1313                                 reg = <0 0x00a88000 0 0x4000>;
1314                                 clock-names = "se";
1315                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1316                                 pinctrl-names = "default";
1317                                 pinctrl-0 = <&qup_i2c10_default>;
1318                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1319                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1320                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1321                                 dma-names = "tx", "rx";
1322                                 #address-cells = <1>;
1323                                 #size-cells = <0>;
1324                                 status = "disabled";
1325                         };
1326
1327                         spi10: spi@a88000 {
1328                                 compatible = "qcom,geni-spi";
1329                                 reg = <0 0x00a88000 0 0x4000>;
1330                                 clock-names = "se";
1331                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1332                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1333                                 power-domains = <&rpmhpd SM8350_CX>;
1334                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1335                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1336                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1337                                 dma-names = "tx", "rx";
1338                                 #address-cells = <1>;
1339                                 #size-cells = <0>;
1340                                 status = "disabled";
1341                         };
1342
1343                         i2c11: i2c@a8c000 {
1344                                 compatible = "qcom,geni-i2c";
1345                                 reg = <0 0x00a8c000 0 0x4000>;
1346                                 clock-names = "se";
1347                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1348                                 pinctrl-names = "default";
1349                                 pinctrl-0 = <&qup_i2c11_default>;
1350                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1351                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1352                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1353                                 dma-names = "tx", "rx";
1354                                 #address-cells = <1>;
1355                                 #size-cells = <0>;
1356                                 status = "disabled";
1357                         };
1358
1359                         spi11: spi@a8c000 {
1360                                 compatible = "qcom,geni-spi";
1361                                 reg = <0 0x00a8c000 0 0x4000>;
1362                                 clock-names = "se";
1363                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1364                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1365                                 power-domains = <&rpmhpd SM8350_CX>;
1366                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1367                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1368                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1369                                 dma-names = "tx", "rx";
1370                                 #address-cells = <1>;
1371                                 #size-cells = <0>;
1372                                 status = "disabled";
1373                         };
1374
1375                         i2c12: i2c@a90000 {
1376                                 compatible = "qcom,geni-i2c";
1377                                 reg = <0 0x00a90000 0 0x4000>;
1378                                 clock-names = "se";
1379                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1380                                 pinctrl-names = "default";
1381                                 pinctrl-0 = <&qup_i2c12_default>;
1382                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1383                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1384                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1385                                 dma-names = "tx", "rx";
1386                                 #address-cells = <1>;
1387                                 #size-cells = <0>;
1388                                 status = "disabled";
1389                         };
1390
1391                         spi12: spi@a90000 {
1392                                 compatible = "qcom,geni-spi";
1393                                 reg = <0 0x00a90000 0 0x4000>;
1394                                 clock-names = "se";
1395                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1396                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1397                                 power-domains = <&rpmhpd SM8350_CX>;
1398                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1399                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1400                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1401                                 dma-names = "tx", "rx";
1402                                 #address-cells = <1>;
1403                                 #size-cells = <0>;
1404                                 status = "disabled";
1405                         };
1406
1407                         i2c13: i2c@a94000 {
1408                                 compatible = "qcom,geni-i2c";
1409                                 reg = <0 0x00a94000 0 0x4000>;
1410                                 clock-names = "se";
1411                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1412                                 pinctrl-names = "default";
1413                                 pinctrl-0 = <&qup_i2c13_default>;
1414                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1415                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1416                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1417                                 dma-names = "tx", "rx";
1418                                 #address-cells = <1>;
1419                                 #size-cells = <0>;
1420                                 status = "disabled";
1421                         };
1422
1423                         spi13: spi@a94000 {
1424                                 compatible = "qcom,geni-spi";
1425                                 reg = <0 0x00a94000 0 0x4000>;
1426                                 clock-names = "se";
1427                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1428                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1429                                 power-domains = <&rpmhpd SM8350_CX>;
1430                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1431                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1432                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1433                                 dma-names = "tx", "rx";
1434                                 #address-cells = <1>;
1435                                 #size-cells = <0>;
1436                                 status = "disabled";
1437                         };
1438                 };
1439
1440                 rng: rng@10d3000 {
1441                         compatible = "qcom,prng-ee";
1442                         reg = <0 0x010d3000 0 0x1000>;
1443                         clocks = <&rpmhcc RPMH_HWKM_CLK>;
1444                         clock-names = "core";
1445                 };
1446
1447                 config_noc: interconnect@1500000 {
1448                         compatible = "qcom,sm8350-config-noc";
1449                         reg = <0 0x01500000 0 0xa580>;
1450                         #interconnect-cells = <2>;
1451                         qcom,bcm-voters = <&apps_bcm_voter>;
1452                 };
1453
1454                 mc_virt: interconnect@1580000 {
1455                         compatible = "qcom,sm8350-mc-virt";
1456                         reg = <0 0x01580000 0 0x1000>;
1457                         #interconnect-cells = <2>;
1458                         qcom,bcm-voters = <&apps_bcm_voter>;
1459                 };
1460
1461                 system_noc: interconnect@1680000 {
1462                         compatible = "qcom,sm8350-system-noc";
1463                         reg = <0 0x01680000 0 0x1c200>;
1464                         #interconnect-cells = <2>;
1465                         qcom,bcm-voters = <&apps_bcm_voter>;
1466                 };
1467
1468                 aggre1_noc: interconnect@16e0000 {
1469                         compatible = "qcom,sm8350-aggre1-noc";
1470                         reg = <0 0x016e0000 0 0x1f180>;
1471                         #interconnect-cells = <2>;
1472                         qcom,bcm-voters = <&apps_bcm_voter>;
1473                 };
1474
1475                 aggre2_noc: interconnect@1700000 {
1476                         compatible = "qcom,sm8350-aggre2-noc";
1477                         reg = <0 0x01700000 0 0x33000>;
1478                         #interconnect-cells = <2>;
1479                         qcom,bcm-voters = <&apps_bcm_voter>;
1480                 };
1481
1482                 mmss_noc: interconnect@1740000 {
1483                         compatible = "qcom,sm8350-mmss-noc";
1484                         reg = <0 0x01740000 0 0x1f080>;
1485                         #interconnect-cells = <2>;
1486                         qcom,bcm-voters = <&apps_bcm_voter>;
1487                 };
1488
1489                 pcie0: pci@1c00000 {
1490                         compatible = "qcom,pcie-sm8350";
1491                         reg = <0 0x01c00000 0 0x3000>,
1492                               <0 0x60000000 0 0xf1d>,
1493                               <0 0x60000f20 0 0xa8>,
1494                               <0 0x60001000 0 0x1000>,
1495                               <0 0x60100000 0 0x100000>;
1496                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1497                         device_type = "pci";
1498                         linux,pci-domain = <0>;
1499                         bus-range = <0x00 0xff>;
1500                         num-lanes = <1>;
1501
1502                         #address-cells = <3>;
1503                         #size-cells = <2>;
1504
1505                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1506                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1507
1508                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1509                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1510                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1511                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1512                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1513                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1514                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1515                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1516                         interrupt-names = "msi0", "msi1", "msi2", "msi3",
1517                                           "msi4", "msi5", "msi6", "msi7";
1518                         #interrupt-cells = <1>;
1519                         interrupt-map-mask = <0 0 0 0x7>;
1520                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1521                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1522                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1523                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1524
1525                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1526                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1527                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1528                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1529                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1530                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1531                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1532                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1533                                  <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
1534                         clock-names = "aux",
1535                                       "cfg",
1536                                       "bus_master",
1537                                       "bus_slave",
1538                                       "slave_q2a",
1539                                       "tbu",
1540                                       "ddrss_sf_tbu",
1541                                       "aggre1",
1542                                       "aggre0";
1543
1544                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1545                                     <0x100 &apps_smmu 0x1c01 0x1>;
1546
1547                         resets = <&gcc GCC_PCIE_0_BCR>;
1548                         reset-names = "pci";
1549
1550                         power-domains = <&gcc PCIE_0_GDSC>;
1551
1552                         phys = <&pcie0_phy>;
1553                         phy-names = "pciephy";
1554
1555                         status = "disabled";
1556                 };
1557
1558                 pcie0_phy: phy@1c06000 {
1559                         compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
1560                         reg = <0 0x01c06000 0 0x2000>;
1561                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1562                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1563                                  <&gcc GCC_PCIE_0_CLKREF_EN>,
1564                                  <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
1565                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
1566                         clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1567
1568                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1569                         reset-names = "phy";
1570
1571                         assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
1572                         assigned-clock-rates = <100000000>;
1573
1574                         #clock-cells = <0>;
1575                         clock-output-names = "pcie_0_pipe_clk";
1576
1577                         #phy-cells = <0>;
1578
1579                         status = "disabled";
1580                 };
1581
1582                 pcie1: pci@1c08000 {
1583                         compatible = "qcom,pcie-sm8350";
1584                         reg = <0 0x01c08000 0 0x3000>,
1585                               <0 0x40000000 0 0xf1d>,
1586                               <0 0x40000f20 0 0xa8>,
1587                               <0 0x40001000 0 0x1000>,
1588                               <0 0x40100000 0 0x100000>;
1589                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1590                         device_type = "pci";
1591                         linux,pci-domain = <1>;
1592                         bus-range = <0x00 0xff>;
1593                         num-lanes = <2>;
1594
1595                         #address-cells = <3>;
1596                         #size-cells = <2>;
1597
1598                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1599                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1600
1601                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1602                         interrupt-names = "msi";
1603                         #interrupt-cells = <1>;
1604                         interrupt-map-mask = <0 0 0 0x7>;
1605                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1606                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1607                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1608                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1609
1610                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1611                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1612                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1613                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1614                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1615                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1616                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1617                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1618                         clock-names = "aux",
1619                                       "cfg",
1620                                       "bus_master",
1621                                       "bus_slave",
1622                                       "slave_q2a",
1623                                       "tbu",
1624                                       "ddrss_sf_tbu",
1625                                       "aggre1";
1626
1627                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1628                                     <0x100 &apps_smmu 0x1c81 0x1>;
1629
1630                         resets = <&gcc GCC_PCIE_1_BCR>;
1631                         reset-names = "pci";
1632
1633                         power-domains = <&gcc PCIE_1_GDSC>;
1634
1635                         phys = <&pcie1_phy>;
1636                         phy-names = "pciephy";
1637
1638                         status = "disabled";
1639                 };
1640
1641                 pcie1_phy: phy@1c0e000 {
1642                         compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
1643                         reg = <0 0x01c0e000 0 0x2000>;
1644                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1645                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1646                                  <&gcc GCC_PCIE_1_CLKREF_EN>,
1647                                  <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
1648                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
1649                         clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
1650
1651                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1652                         reset-names = "phy";
1653
1654                         assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
1655                         assigned-clock-rates = <100000000>;
1656
1657                         #clock-cells = <0>;
1658                         clock-output-names = "pcie_1_pipe_clk";
1659
1660                         #phy-cells = <0>;
1661
1662                         status = "disabled";
1663                 };
1664
1665                 ufs_mem_hc: ufshc@1d84000 {
1666                         compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1667                                      "jedec,ufs-2.0";
1668                         reg = <0 0x01d84000 0 0x3000>;
1669                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1670                         phys = <&ufs_mem_phy_lanes>;
1671                         phy-names = "ufsphy";
1672                         lanes-per-direction = <2>;
1673                         #reset-cells = <1>;
1674                         resets = <&gcc GCC_UFS_PHY_BCR>;
1675                         reset-names = "rst";
1676
1677                         power-domains = <&gcc UFS_PHY_GDSC>;
1678
1679                         iommus = <&apps_smmu 0xe0 0x0>;
1680                         dma-coherent;
1681
1682                         clock-names =
1683                                 "core_clk",
1684                                 "bus_aggr_clk",
1685                                 "iface_clk",
1686                                 "core_clk_unipro",
1687                                 "ref_clk",
1688                                 "tx_lane0_sync_clk",
1689                                 "rx_lane0_sync_clk",
1690                                 "rx_lane1_sync_clk";
1691                         clocks =
1692                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1693                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1694                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1695                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1696                                 <&rpmhcc RPMH_CXO_CLK>,
1697                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1698                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1699                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1700                         freq-table-hz =
1701                                 <75000000 300000000>,
1702                                 <0 0>,
1703                                 <0 0>,
1704                                 <75000000 300000000>,
1705                                 <0 0>,
1706                                 <0 0>,
1707                                 <0 0>,
1708                                 <0 0>;
1709                         status = "disabled";
1710                 };
1711
1712                 ufs_mem_phy: phy@1d87000 {
1713                         compatible = "qcom,sm8350-qmp-ufs-phy";
1714                         reg = <0 0x01d87000 0 0x1c4>;
1715                         #address-cells = <2>;
1716                         #size-cells = <2>;
1717                         ranges;
1718                         clock-names = "ref",
1719                                       "ref_aux";
1720                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1721                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1722
1723                         resets = <&ufs_mem_hc 0>;
1724                         reset-names = "ufsphy";
1725                         status = "disabled";
1726
1727                         ufs_mem_phy_lanes: phy@1d87400 {
1728                                 reg = <0 0x01d87400 0 0x188>,
1729                                       <0 0x01d87600 0 0x200>,
1730                                       <0 0x01d87c00 0 0x200>,
1731                                       <0 0x01d87800 0 0x188>,
1732                                       <0 0x01d87a00 0 0x200>;
1733                                 #clock-cells = <1>;
1734                                 #phy-cells = <0>;
1735                         };
1736                 };
1737
1738                 cryptobam: dma-controller@1dc4000 {
1739                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1740                         reg = <0 0x01dc4000 0 0x24000>;
1741                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1742                         #dma-cells = <1>;
1743                         qcom,ee = <0>;
1744                         qcom,controlled-remotely;
1745                         iommus = <&apps_smmu 0x594 0x0011>,
1746                                  <&apps_smmu 0x596 0x0011>;
1747                 };
1748
1749                 crypto: crypto@1dfa000 {
1750                         compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce";
1751                         reg = <0 0x01dfa000 0 0x6000>;
1752                         dmas = <&cryptobam 4>, <&cryptobam 5>;
1753                         dma-names = "rx", "tx";
1754                         iommus = <&apps_smmu 0x594 0x0011>,
1755                                  <&apps_smmu 0x596 0x0011>;
1756                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1757                         interconnect-names = "memory";
1758                 };
1759
1760                 ipa: ipa@1e40000 {
1761                         compatible = "qcom,sm8350-ipa";
1762
1763                         iommus = <&apps_smmu 0x5c0 0x0>,
1764                                  <&apps_smmu 0x5c2 0x0>;
1765                         reg = <0 0x01e40000 0 0x8000>,
1766                               <0 0x01e50000 0 0x4b20>,
1767                               <0 0x01e04000 0 0x23000>;
1768                         reg-names = "ipa-reg",
1769                                     "ipa-shared",
1770                                     "gsi";
1771
1772                         interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1773                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1774                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1775                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1776                         interrupt-names = "ipa",
1777                                           "gsi",
1778                                           "ipa-clock-query",
1779                                           "ipa-setup-ready";
1780
1781                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1782                         clock-names = "core";
1783
1784                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1785                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1786                         interconnect-names = "memory",
1787                                              "config";
1788
1789                         qcom,qmp = <&aoss_qmp>;
1790
1791                         qcom,smem-states = <&ipa_smp2p_out 0>,
1792                                            <&ipa_smp2p_out 1>;
1793                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1794                                                 "ipa-clock-enabled";
1795
1796                         status = "disabled";
1797                 };
1798
1799                 tcsr_mutex: hwlock@1f40000 {
1800                         compatible = "qcom,tcsr-mutex";
1801                         reg = <0x0 0x01f40000 0x0 0x40000>;
1802                         #hwlock-cells = <1>;
1803                 };
1804
1805                 gpu: gpu@3d00000 {
1806                         compatible = "qcom,adreno-660.1", "qcom,adreno";
1807
1808                         reg = <0 0x03d00000 0 0x40000>,
1809                               <0 0x03d9e000 0 0x1000>,
1810                               <0 0x03d61000 0 0x800>;
1811                         reg-names = "kgsl_3d0_reg_memory",
1812                                     "cx_mem",
1813                                     "cx_dbgc";
1814
1815                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1816
1817                         iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
1818
1819                         operating-points-v2 = <&gpu_opp_table>;
1820
1821                         qcom,gmu = <&gmu>;
1822
1823                         status = "disabled";
1824
1825                         zap-shader {
1826                                 memory-region = <&pil_gpu_mem>;
1827                         };
1828
1829                         /* note: downstream checks gpu binning for 670 Mhz */
1830                         gpu_opp_table: opp-table {
1831                                 compatible = "operating-points-v2";
1832
1833                                 opp-840000000 {
1834                                         opp-hz = /bits/ 64 <840000000>;
1835                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1836                                 };
1837
1838                                 opp-778000000 {
1839                                         opp-hz = /bits/ 64 <778000000>;
1840                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1841                                 };
1842
1843                                 opp-738000000 {
1844                                         opp-hz = /bits/ 64 <738000000>;
1845                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1846                                 };
1847
1848                                 opp-676000000 {
1849                                         opp-hz = /bits/ 64 <676000000>;
1850                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1851                                 };
1852
1853                                 opp-608000000 {
1854                                         opp-hz = /bits/ 64 <608000000>;
1855                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1856                                 };
1857
1858                                 opp-540000000 {
1859                                         opp-hz = /bits/ 64 <540000000>;
1860                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1861                                 };
1862
1863                                 opp-491000000 {
1864                                         opp-hz = /bits/ 64 <491000000>;
1865                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1866                                 };
1867
1868                                 opp-443000000 {
1869                                         opp-hz = /bits/ 64 <443000000>;
1870                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1871                                 };
1872
1873                                 opp-379000000 {
1874                                         opp-hz = /bits/ 64 <379000000>;
1875                                         opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>;
1876                                 };
1877
1878                                 opp-315000000 {
1879                                         opp-hz = /bits/ 64 <315000000>;
1880                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1881                                 };
1882                         };
1883                 };
1884
1885                 gmu: gmu@3d6a000 {
1886                         compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1887
1888                         reg = <0 0x03d6a000 0 0x34000>,
1889                               <0 0x03de0000 0 0x10000>,
1890                               <0 0x0b290000 0 0x10000>;
1891                         reg-names = "gmu", "rscc", "gmu_pdc";
1892
1893                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1894                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1895                         interrupt-names = "hfi", "gmu";
1896
1897                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
1898                                  <&gpucc GPU_CC_CXO_CLK>,
1899                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1900                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1901                                  <&gpucc GPU_CC_AHB_CLK>,
1902                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1903                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
1904                         clock-names = "gmu",
1905                                       "cxo",
1906                                       "axi",
1907                                       "memnoc",
1908                                       "ahb",
1909                                       "hub",
1910                                       "smmu_vote";
1911
1912                         power-domains = <&gpucc GPU_CX_GDSC>,
1913                                         <&gpucc GPU_GX_GDSC>;
1914                         power-domain-names = "cx",
1915                                              "gx";
1916
1917                         iommus = <&adreno_smmu 5 0x400>;
1918
1919                         operating-points-v2 = <&gmu_opp_table>;
1920
1921                         gmu_opp_table: opp-table {
1922                                 compatible = "operating-points-v2";
1923
1924                                 opp-200000000 {
1925                                         opp-hz = /bits/ 64 <200000000>;
1926                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1927                                 };
1928                         };
1929                 };
1930
1931                 gpucc: clock-controller@3d90000 {
1932                         compatible = "qcom,sm8350-gpucc";
1933                         reg = <0 0x03d90000 0 0x9000>;
1934                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1935                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1936                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1937                         clock-names = "bi_tcxo",
1938                                       "gcc_gpu_gpll0_clk_src",
1939                                       "gcc_gpu_gpll0_div_clk_src";
1940                         #clock-cells = <1>;
1941                         #reset-cells = <1>;
1942                         #power-domain-cells = <1>;
1943                 };
1944
1945                 adreno_smmu: iommu@3da0000 {
1946                         compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu",
1947                                      "qcom,smmu-500", "arm,mmu-500";
1948                         reg = <0 0x03da0000 0 0x20000>;
1949                         #iommu-cells = <2>;
1950                         #global-interrupts = <2>;
1951                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1952                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1953                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1954                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1955                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1956                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1957                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1958                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1959                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1960                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
1961                                      <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
1962                                      <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
1963
1964                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1965                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
1966                                  <&gpucc GPU_CC_AHB_CLK>,
1967                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1968                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1969                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1970                                  <&gpucc GPU_CC_HUB_AON_CLK>;
1971                         clock-names = "bus",
1972                                       "iface",
1973                                       "ahb",
1974                                       "hlos1_vote_gpu_smmu",
1975                                       "cx_gmu",
1976                                       "hub_cx_int",
1977                                       "hub_aon";
1978
1979                         power-domains = <&gpucc GPU_CX_GDSC>;
1980                         dma-coherent;
1981                 };
1982
1983                 lpass_ag_noc: interconnect@3c40000 {
1984                         compatible = "qcom,sm8350-lpass-ag-noc";
1985                         reg = <0 0x03c40000 0 0xf080>;
1986                         #interconnect-cells = <2>;
1987                         qcom,bcm-voters = <&apps_bcm_voter>;
1988                 };
1989
1990                 mpss: remoteproc@4080000 {
1991                         compatible = "qcom,sm8350-mpss-pas";
1992                         reg = <0x0 0x04080000 0x0 0x4040>;
1993
1994                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1995                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1996                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1997                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1998                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1999                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2000                         interrupt-names = "wdog", "fatal", "ready", "handover",
2001                                           "stop-ack", "shutdown-ack";
2002
2003                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2004                         clock-names = "xo";
2005
2006                         power-domains = <&rpmhpd SM8350_CX>,
2007                                         <&rpmhpd SM8350_MSS>;
2008                         power-domain-names = "cx", "mss";
2009
2010                         interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2011
2012                         memory-region = <&pil_modem_mem>;
2013
2014                         qcom,qmp = <&aoss_qmp>;
2015
2016                         qcom,smem-states = <&smp2p_modem_out 0>;
2017                         qcom,smem-state-names = "stop";
2018
2019                         status = "disabled";
2020
2021                         glink-edge {
2022                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2023                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2024                                                              IRQ_TYPE_EDGE_RISING>;
2025                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2026                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2027                                 label = "modem";
2028                                 qcom,remote-pid = <1>;
2029                         };
2030                 };
2031
2032                 slpi: remoteproc@5c00000 {
2033                         compatible = "qcom,sm8350-slpi-pas";
2034                         reg = <0 0x05c00000 0 0x4000>;
2035
2036                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2037                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2038                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2039                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2040                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2041                         interrupt-names = "wdog", "fatal", "ready",
2042                                           "handover", "stop-ack";
2043
2044                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2045                         clock-names = "xo";
2046
2047                         power-domains = <&rpmhpd SM8350_LCX>,
2048                                         <&rpmhpd SM8350_LMX>;
2049                         power-domain-names = "lcx", "lmx";
2050
2051                         memory-region = <&pil_slpi_mem>;
2052
2053                         qcom,qmp = <&aoss_qmp>;
2054
2055                         qcom,smem-states = <&smp2p_slpi_out 0>;
2056                         qcom,smem-state-names = "stop";
2057
2058                         status = "disabled";
2059
2060                         glink-edge {
2061                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2062                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2063                                                              IRQ_TYPE_EDGE_RISING>;
2064                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2065                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2066
2067                                 label = "slpi";
2068                                 qcom,remote-pid = <3>;
2069
2070                                 fastrpc {
2071                                         compatible = "qcom,fastrpc";
2072                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2073                                         label = "sdsp";
2074                                         qcom,non-secure-domain;
2075                                         #address-cells = <1>;
2076                                         #size-cells = <0>;
2077
2078                                         compute-cb@1 {
2079                                                 compatible = "qcom,fastrpc-compute-cb";
2080                                                 reg = <1>;
2081                                                 iommus = <&apps_smmu 0x0541 0x0>;
2082                                         };
2083
2084                                         compute-cb@2 {
2085                                                 compatible = "qcom,fastrpc-compute-cb";
2086                                                 reg = <2>;
2087                                                 iommus = <&apps_smmu 0x0542 0x0>;
2088                                         };
2089
2090                                         compute-cb@3 {
2091                                                 compatible = "qcom,fastrpc-compute-cb";
2092                                                 reg = <3>;
2093                                                 iommus = <&apps_smmu 0x0543 0x0>;
2094                                                 /* note: shared-cb = <4> in downstream */
2095                                         };
2096                                 };
2097                         };
2098                 };
2099
2100                 sdhc_2: mmc@8804000 {
2101                         compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5";
2102                         reg = <0 0x08804000 0 0x1000>;
2103
2104                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2105                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2106                         interrupt-names = "hc_irq", "pwr_irq";
2107
2108                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2109                                  <&gcc GCC_SDCC2_APPS_CLK>,
2110                                  <&rpmhcc RPMH_CXO_CLK>;
2111                         clock-names = "iface", "core", "xo";
2112                         resets = <&gcc GCC_SDCC2_BCR>;
2113                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2114                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2115                         interconnect-names = "sdhc-ddr","cpu-sdhc";
2116                         iommus = <&apps_smmu 0x4a0 0x0>;
2117                         power-domains = <&rpmhpd SM8350_CX>;
2118                         operating-points-v2 = <&sdhc2_opp_table>;
2119                         bus-width = <4>;
2120                         dma-coherent;
2121
2122                         status = "disabled";
2123
2124                         sdhc2_opp_table: opp-table {
2125                                 compatible = "operating-points-v2";
2126
2127                                 opp-100000000 {
2128                                         opp-hz = /bits/ 64 <100000000>;
2129                                         required-opps = <&rpmhpd_opp_low_svs>;
2130                                 };
2131
2132                                 opp-202000000 {
2133                                         opp-hz = /bits/ 64 <202000000>;
2134                                         required-opps = <&rpmhpd_opp_svs_l1>;
2135                                 };
2136                         };
2137                 };
2138
2139                 usb_1_hsphy: phy@88e3000 {
2140                         compatible = "qcom,sm8350-usb-hs-phy",
2141                                      "qcom,usb-snps-hs-7nm-phy";
2142                         reg = <0 0x088e3000 0 0x400>;
2143                         status = "disabled";
2144                         #phy-cells = <0>;
2145
2146                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2147                         clock-names = "ref";
2148
2149                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2150                 };
2151
2152                 usb_2_hsphy: phy@88e4000 {
2153                         compatible = "qcom,sm8250-usb-hs-phy",
2154                                      "qcom,usb-snps-hs-7nm-phy";
2155                         reg = <0 0x088e4000 0 0x400>;
2156                         status = "disabled";
2157                         #phy-cells = <0>;
2158
2159                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2160                         clock-names = "ref";
2161
2162                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2163                 };
2164
2165                 usb_1_qmpphy: phy@88e8000 {
2166                         compatible = "qcom,sm8350-qmp-usb3-dp-phy";
2167                         reg = <0 0x088e8000 0 0x3000>;
2168
2169                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2170                                  <&rpmhcc RPMH_CXO_CLK>,
2171                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2172                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2173                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2174
2175                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2176                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2177                         reset-names = "phy", "common";
2178
2179                         #clock-cells = <1>;
2180                         #phy-cells = <1>;
2181
2182                         status = "disabled";
2183
2184                         ports {
2185                                 #address-cells = <1>;
2186                                 #size-cells = <0>;
2187
2188                                 port@0 {
2189                                         reg = <0>;
2190
2191                                         usb_1_qmpphy_out: endpoint {
2192                                         };
2193                                 };
2194
2195                                 port@1 {
2196                                         reg = <1>;
2197
2198                                         usb_1_qmpphy_usb_ss_in: endpoint {
2199                                         };
2200                                 };
2201
2202                                 port@2 {
2203                                         reg = <2>;
2204
2205                                         usb_1_qmpphy_dp_in: endpoint {
2206                                         };
2207                                 };
2208                         };
2209                 };
2210
2211                 usb_2_qmpphy: phy-wrapper@88eb000 {
2212                         compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2213                         reg = <0 0x088eb000 0 0x200>;
2214                         status = "disabled";
2215                         #address-cells = <2>;
2216                         #size-cells = <2>;
2217                         ranges;
2218
2219                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2220                                  <&rpmhcc RPMH_CXO_CLK>,
2221                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
2222                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2223                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2224
2225                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2226                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2227                         reset-names = "phy", "common";
2228
2229                         usb_2_ssphy: phy@88ebe00 {
2230                                 reg = <0 0x088ebe00 0 0x200>,
2231                                       <0 0x088ec000 0 0x200>,
2232                                       <0 0x088eb200 0 0x1100>;
2233                                 #phy-cells = <0>;
2234                                 #clock-cells = <0>;
2235                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2236                                 clock-names = "pipe0";
2237                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2238                         };
2239                 };
2240
2241                 dc_noc: interconnect@90c0000 {
2242                         compatible = "qcom,sm8350-dc-noc";
2243                         reg = <0 0x090c0000 0 0x4200>;
2244                         #interconnect-cells = <2>;
2245                         qcom,bcm-voters = <&apps_bcm_voter>;
2246                 };
2247
2248                 gem_noc: interconnect@9100000 {
2249                         compatible = "qcom,sm8350-gem-noc";
2250                         reg = <0 0x09100000 0 0xb4000>;
2251                         #interconnect-cells = <2>;
2252                         qcom,bcm-voters = <&apps_bcm_voter>;
2253                 };
2254
2255                 system-cache-controller@9200000 {
2256                         compatible = "qcom,sm8350-llcc";
2257                         reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2258                               <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2259                               <0 0x09600000 0 0x58000>;
2260                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2261                                     "llcc3_base", "llcc_broadcast_base";
2262                 };
2263
2264                 compute_noc: interconnect@a0c0000 {
2265                         compatible = "qcom,sm8350-compute-noc";
2266                         reg = <0 0x0a0c0000 0 0xa180>;
2267                         #interconnect-cells = <2>;
2268                         qcom,bcm-voters = <&apps_bcm_voter>;
2269                 };
2270
2271                 usb_1: usb@a6f8800 {
2272                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2273                         reg = <0 0x0a6f8800 0 0x400>;
2274                         status = "disabled";
2275                         #address-cells = <2>;
2276                         #size-cells = <2>;
2277                         ranges;
2278
2279                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2280                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2281                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2282                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2283                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2284                         clock-names = "cfg_noc",
2285                                       "core",
2286                                       "iface",
2287                                       "sleep",
2288                                       "mock_utmi";
2289
2290                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2291                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2292                         assigned-clock-rates = <19200000>, <200000000>;
2293
2294                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2295                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
2296                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2297                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
2298                         interrupt-names = "hs_phy_irq",
2299                                           "ss_phy_irq",
2300                                           "dm_hs_phy_irq",
2301                                           "dp_hs_phy_irq";
2302
2303                         power-domains = <&gcc USB30_PRIM_GDSC>;
2304
2305                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2306
2307                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2308                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2309                         interconnect-names = "usb-ddr", "apps-usb";
2310
2311                         usb_1_dwc3: usb@a600000 {
2312                                 compatible = "snps,dwc3";
2313                                 reg = <0 0x0a600000 0 0xcd00>;
2314                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2315                                 iommus = <&apps_smmu 0x0 0x0>;
2316                                 snps,dis_u2_susphy_quirk;
2317                                 snps,dis_enblslpm_quirk;
2318                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
2319                                 phy-names = "usb2-phy", "usb3-phy";
2320
2321                                 ports {
2322                                         #address-cells = <1>;
2323                                         #size-cells = <0>;
2324
2325                                         port@0 {
2326                                                 reg = <0>;
2327
2328                                                 usb_1_dwc3_hs: endpoint {
2329                                                 };
2330                                         };
2331
2332                                         port@1 {
2333                                                 reg = <1>;
2334
2335                                                 usb_1_dwc3_ss: endpoint {
2336                                                 };
2337                                         };
2338                                 };
2339                         };
2340                 };
2341
2342                 usb_2: usb@a8f8800 {
2343                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2344                         reg = <0 0x0a8f8800 0 0x400>;
2345                         status = "disabled";
2346                         #address-cells = <2>;
2347                         #size-cells = <2>;
2348                         ranges;
2349
2350                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2351                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2352                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2353                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2354                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2355                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
2356                         clock-names = "cfg_noc",
2357                                       "core",
2358                                       "iface",
2359                                       "sleep",
2360                                       "mock_utmi",
2361                                       "xo";
2362
2363                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2364                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2365                         assigned-clock-rates = <19200000>, <200000000>;
2366
2367                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2368                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
2369                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2370                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
2371                         interrupt-names = "hs_phy_irq",
2372                                           "ss_phy_irq",
2373                                           "dm_hs_phy_irq",
2374                                           "dp_hs_phy_irq";
2375
2376                         power-domains = <&gcc USB30_SEC_GDSC>;
2377
2378                         resets = <&gcc GCC_USB30_SEC_BCR>;
2379
2380                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2381                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2382                         interconnect-names = "usb-ddr", "apps-usb";
2383
2384                         usb_2_dwc3: usb@a800000 {
2385                                 compatible = "snps,dwc3";
2386                                 reg = <0 0x0a800000 0 0xcd00>;
2387                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2388                                 iommus = <&apps_smmu 0x20 0x0>;
2389                                 snps,dis_u2_susphy_quirk;
2390                                 snps,dis_enblslpm_quirk;
2391                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2392                                 phy-names = "usb2-phy", "usb3-phy";
2393                         };
2394                 };
2395
2396                 mdss: display-subsystem@ae00000 {
2397                         compatible = "qcom,sm8350-mdss";
2398                         reg = <0 0x0ae00000 0 0x1000>;
2399                         reg-names = "mdss";
2400
2401                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
2402                                         <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
2403                         interconnect-names = "mdp0-mem", "mdp1-mem";
2404
2405                         power-domains = <&dispcc MDSS_GDSC>;
2406                         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2407
2408                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2409                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2410                                  <&gcc GCC_DISP_SF_AXI_CLK>,
2411                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2412                         clock-names = "iface", "bus", "nrt_bus", "core";
2413
2414                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2415                         interrupt-controller;
2416                         #interrupt-cells = <1>;
2417
2418                         iommus = <&apps_smmu 0x820 0x402>;
2419
2420                         status = "disabled";
2421
2422                         #address-cells = <2>;
2423                         #size-cells = <2>;
2424                         ranges;
2425
2426                         dpu_opp_table: opp-table {
2427                                 compatible = "operating-points-v2";
2428
2429                                 /* TODO: opp-200000000 should work with
2430                                  * &rpmhpd_opp_low_svs, but one some of
2431                                  * sm8350_hdk boards reboot using this
2432                                  * opp.
2433                                  */
2434                                 opp-200000000 {
2435                                         opp-hz = /bits/ 64 <200000000>;
2436                                         required-opps = <&rpmhpd_opp_svs>;
2437                                 };
2438
2439                                 opp-300000000 {
2440                                         opp-hz = /bits/ 64 <300000000>;
2441                                         required-opps = <&rpmhpd_opp_svs>;
2442                                 };
2443
2444                                 opp-345000000 {
2445                                         opp-hz = /bits/ 64 <345000000>;
2446                                         required-opps = <&rpmhpd_opp_svs_l1>;
2447                                 };
2448
2449                                 opp-460000000 {
2450                                         opp-hz = /bits/ 64 <460000000>;
2451                                         required-opps = <&rpmhpd_opp_nom>;
2452                                 };
2453                         };
2454
2455                         mdss_mdp: display-controller@ae01000 {
2456                                 compatible = "qcom,sm8350-dpu";
2457                                 reg = <0 0x0ae01000 0 0x8f000>,
2458                                       <0 0x0aeb0000 0 0x2008>;
2459                                 reg-names = "mdp", "vbif";
2460
2461                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2462                                         <&gcc GCC_DISP_SF_AXI_CLK>,
2463                                         <&dispcc DISP_CC_MDSS_AHB_CLK>,
2464                                         <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2465                                         <&dispcc DISP_CC_MDSS_MDP_CLK>,
2466                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2467                                 clock-names = "bus",
2468                                               "nrt_bus",
2469                                               "iface",
2470                                               "lut",
2471                                               "core",
2472                                               "vsync";
2473
2474                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2475                                 assigned-clock-rates = <19200000>;
2476
2477                                 operating-points-v2 = <&dpu_opp_table>;
2478                                 power-domains = <&rpmhpd SM8350_MMCX>;
2479
2480                                 interrupt-parent = <&mdss>;
2481                                 interrupts = <0>;
2482
2483                                 ports {
2484                                         #address-cells = <1>;
2485                                         #size-cells = <0>;
2486
2487                                         port@0 {
2488                                                 reg = <0>;
2489                                                 dpu_intf1_out: endpoint {
2490                                                         remote-endpoint = <&mdss_dsi0_in>;
2491                                                 };
2492                                         };
2493
2494                                         port@1 {
2495                                                 reg = <1>;
2496                                                 dpu_intf2_out: endpoint {
2497                                                         remote-endpoint = <&mdss_dsi1_in>;
2498                                                 };
2499                                         };
2500
2501                                         port@2 {
2502                                                 reg = <2>;
2503                                                 dpu_intf0_out: endpoint {
2504                                                         remote-endpoint = <&mdss_dp_in>;
2505                                                 };
2506                                         };
2507                                 };
2508                         };
2509
2510                         mdss_dp: displayport-controller@ae90000 {
2511                                 compatible = "qcom,sm8350-dp";
2512                                 reg = <0 0xae90000 0 0x200>,
2513                                       <0 0xae90200 0 0x200>,
2514                                       <0 0xae90400 0 0x600>,
2515                                       <0 0xae91000 0 0x400>,
2516                                       <0 0xae91400 0 0x400>;
2517                                 interrupt-parent = <&mdss>;
2518                                 interrupts = <12>;
2519                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2520                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
2521                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
2522                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
2523                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
2524                                 clock-names = "core_iface",
2525                                               "core_aux",
2526                                               "ctrl_link",
2527                                               "ctrl_link_iface",
2528                                               "stream_pixel";
2529
2530                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2531                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
2532                                 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2533                                                          <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2534
2535                                 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
2536                                 phy-names = "dp";
2537
2538                                 #sound-dai-cells = <0>;
2539
2540                                 operating-points-v2 = <&dp_opp_table>;
2541                                 power-domains = <&rpmhpd SM8350_MMCX>;
2542
2543                                 status = "disabled";
2544
2545                                 ports {
2546                                         #address-cells = <1>;
2547                                         #size-cells = <0>;
2548
2549                                         port@0 {
2550                                                 reg = <0>;
2551                                                 mdss_dp_in: endpoint {
2552                                                         remote-endpoint = <&dpu_intf0_out>;
2553                                                 };
2554                                         };
2555                                 };
2556
2557                                 dp_opp_table: opp-table {
2558                                         compatible = "operating-points-v2";
2559
2560                                         opp-160000000 {
2561                                                 opp-hz = /bits/ 64 <160000000>;
2562                                                 required-opps = <&rpmhpd_opp_low_svs>;
2563                                         };
2564
2565                                         opp-270000000 {
2566                                                 opp-hz = /bits/ 64 <270000000>;
2567                                                 required-opps = <&rpmhpd_opp_svs>;
2568                                         };
2569
2570                                         opp-540000000 {
2571                                                 opp-hz = /bits/ 64 <540000000>;
2572                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2573                                         };
2574
2575                                         opp-810000000 {
2576                                                 opp-hz = /bits/ 64 <810000000>;
2577                                                 required-opps = <&rpmhpd_opp_nom>;
2578                                         };
2579                                 };
2580                         };
2581
2582                         mdss_dsi0: dsi@ae94000 {
2583                                 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2584                                 reg = <0 0x0ae94000 0 0x400>;
2585                                 reg-names = "dsi_ctrl";
2586
2587                                 interrupt-parent = <&mdss>;
2588                                 interrupts = <4>;
2589
2590                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2591                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2592                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2593                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2594                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2595                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2596                                 clock-names = "byte",
2597                                               "byte_intf",
2598                                               "pixel",
2599                                               "core",
2600                                               "iface",
2601                                               "bus";
2602
2603                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2604                                                   <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2605                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2606                                                          <&mdss_dsi0_phy 1>;
2607
2608                                 operating-points-v2 = <&dsi0_opp_table>;
2609                                 power-domains = <&rpmhpd SM8350_MMCX>;
2610
2611                                 phys = <&mdss_dsi0_phy>;
2612
2613                                 #address-cells = <1>;
2614                                 #size-cells = <0>;
2615
2616                                 status = "disabled";
2617
2618                                 dsi0_opp_table: opp-table {
2619                                         compatible = "operating-points-v2";
2620
2621                                         /* TODO: opp-187500000 should work with
2622                                          * &rpmhpd_opp_low_svs, but one some of
2623                                          * sm8350_hdk boards reboot using this
2624                                          * opp.
2625                                          */
2626                                         opp-187500000 {
2627                                                 opp-hz = /bits/ 64 <187500000>;
2628                                                 required-opps = <&rpmhpd_opp_svs>;
2629                                         };
2630
2631                                         opp-300000000 {
2632                                                 opp-hz = /bits/ 64 <300000000>;
2633                                                 required-opps = <&rpmhpd_opp_svs>;
2634                                         };
2635
2636                                         opp-358000000 {
2637                                                 opp-hz = /bits/ 64 <358000000>;
2638                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2639                                         };
2640                                 };
2641
2642                                 ports {
2643                                         #address-cells = <1>;
2644                                         #size-cells = <0>;
2645
2646                                         port@0 {
2647                                                 reg = <0>;
2648                                                 mdss_dsi0_in: endpoint {
2649                                                         remote-endpoint = <&dpu_intf1_out>;
2650                                                 };
2651                                         };
2652
2653                                         port@1 {
2654                                                 reg = <1>;
2655                                                 mdss_dsi0_out: endpoint {
2656                                                 };
2657                                         };
2658                                 };
2659                         };
2660
2661                         mdss_dsi0_phy: phy@ae94400 {
2662                                 compatible = "qcom,sm8350-dsi-phy-5nm";
2663                                 reg = <0 0x0ae94400 0 0x200>,
2664                                       <0 0x0ae94600 0 0x280>,
2665                                       <0 0x0ae94900 0 0x27c>;
2666                                 reg-names = "dsi_phy",
2667                                             "dsi_phy_lane",
2668                                             "dsi_pll";
2669
2670                                 #clock-cells = <1>;
2671                                 #phy-cells = <0>;
2672
2673                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2674                                          <&rpmhcc RPMH_CXO_CLK>;
2675                                 clock-names = "iface", "ref";
2676
2677                                 status = "disabled";
2678                         };
2679
2680                         mdss_dsi1: dsi@ae96000 {
2681                                 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2682                                 reg = <0 0x0ae96000 0 0x400>;
2683                                 reg-names = "dsi_ctrl";
2684
2685                                 interrupt-parent = <&mdss>;
2686                                 interrupts = <5>;
2687
2688                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2689                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2690                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2691                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2692                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2693                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2694                                 clock-names = "byte",
2695                                               "byte_intf",
2696                                               "pixel",
2697                                               "core",
2698                                               "iface",
2699                                               "bus";
2700
2701                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2702                                                   <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2703                                 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2704                                                          <&mdss_dsi1_phy 1>;
2705
2706                                 operating-points-v2 = <&dsi1_opp_table>;
2707                                 power-domains = <&rpmhpd SM8350_MMCX>;
2708
2709                                 phys = <&mdss_dsi1_phy>;
2710
2711                                 #address-cells = <1>;
2712                                 #size-cells = <0>;
2713
2714                                 status = "disabled";
2715
2716                                 dsi1_opp_table: opp-table {
2717                                         compatible = "operating-points-v2";
2718
2719                                         /* TODO: opp-187500000 should work with
2720                                          * &rpmhpd_opp_low_svs, but one some of
2721                                          * sm8350_hdk boards reboot using this
2722                                          * opp.
2723                                          */
2724                                         opp-187500000 {
2725                                                 opp-hz = /bits/ 64 <187500000>;
2726                                                 required-opps = <&rpmhpd_opp_svs>;
2727                                         };
2728
2729                                         opp-300000000 {
2730                                                 opp-hz = /bits/ 64 <300000000>;
2731                                                 required-opps = <&rpmhpd_opp_svs>;
2732                                         };
2733
2734                                         opp-358000000 {
2735                                                 opp-hz = /bits/ 64 <358000000>;
2736                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2737                                         };
2738                                 };
2739
2740                                 ports {
2741                                         #address-cells = <1>;
2742                                         #size-cells = <0>;
2743
2744                                         port@0 {
2745                                                 reg = <0>;
2746                                                 mdss_dsi1_in: endpoint {
2747                                                         remote-endpoint = <&dpu_intf2_out>;
2748                                                 };
2749                                         };
2750
2751                                         port@1 {
2752                                                 reg = <1>;
2753                                                 mdss_dsi1_out: endpoint {
2754                                                 };
2755                                         };
2756                                 };
2757                         };
2758
2759                         mdss_dsi1_phy: phy@ae96400 {
2760                                 compatible = "qcom,sm8350-dsi-phy-5nm";
2761                                 reg = <0 0x0ae96400 0 0x200>,
2762                                       <0 0x0ae96600 0 0x280>,
2763                                       <0 0x0ae96900 0 0x27c>;
2764                                 reg-names = "dsi_phy",
2765                                             "dsi_phy_lane",
2766                                             "dsi_pll";
2767
2768                                 #clock-cells = <1>;
2769                                 #phy-cells = <0>;
2770
2771                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2772                                          <&rpmhcc RPMH_CXO_CLK>;
2773                                 clock-names = "iface", "ref";
2774
2775                                 status = "disabled";
2776                         };
2777                 };
2778
2779                 dispcc: clock-controller@af00000 {
2780                         compatible = "qcom,sm8350-dispcc";
2781                         reg = <0 0x0af00000 0 0x10000>;
2782                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2783                                  <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2784                                  <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2785                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2786                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2787                         clock-names = "bi_tcxo",
2788                                       "dsi0_phy_pll_out_byteclk",
2789                                       "dsi0_phy_pll_out_dsiclk",
2790                                       "dsi1_phy_pll_out_byteclk",
2791                                       "dsi1_phy_pll_out_dsiclk",
2792                                       "dp_phy_pll_link_clk",
2793                                       "dp_phy_pll_vco_div_clk";
2794                         #clock-cells = <1>;
2795                         #reset-cells = <1>;
2796                         #power-domain-cells = <1>;
2797
2798                         power-domains = <&rpmhpd SM8350_MMCX>;
2799                 };
2800
2801                 pdc: interrupt-controller@b220000 {
2802                         compatible = "qcom,sm8350-pdc", "qcom,pdc";
2803                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2804                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,   <55 306 4>,
2805                                           <59 312 3>, <62 374 2>,  <64 434 2>,   <66 438 3>,
2806                                           <69 86 1>,  <70 520 54>, <124 609 31>, <155 63 1>,
2807                                           <156 716 12>;
2808                         #interrupt-cells = <2>;
2809                         interrupt-parent = <&intc>;
2810                         interrupt-controller;
2811                 };
2812
2813                 tsens0: thermal-sensor@c263000 {
2814                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2815                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
2816                               <0 0x0c222000 0 0x8>; /* SROT */
2817                         #qcom,sensors = <15>;
2818                         interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2819                                      <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2820                         interrupt-names = "uplow", "critical";
2821                         #thermal-sensor-cells = <1>;
2822                 };
2823
2824                 tsens1: thermal-sensor@c265000 {
2825                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
2826                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
2827                               <0 0x0c223000 0 0x8>; /* SROT */
2828                         #qcom,sensors = <14>;
2829                         interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2830                                      <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2831                         interrupt-names = "uplow", "critical";
2832                         #thermal-sensor-cells = <1>;
2833                 };
2834
2835                 aoss_qmp: power-management@c300000 {
2836                         compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
2837                         reg = <0 0x0c300000 0 0x400>;
2838                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2839                                                      IRQ_TYPE_EDGE_RISING>;
2840                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2841
2842                         #clock-cells = <0>;
2843                 };
2844
2845                 sram@c3f0000 {
2846                         compatible = "qcom,rpmh-stats";
2847                         reg = <0 0x0c3f0000 0 0x400>;
2848                 };
2849
2850                 spmi_bus: spmi@c440000 {
2851                         compatible = "qcom,spmi-pmic-arb";
2852                         reg = <0x0 0x0c440000 0x0 0x1100>,
2853                               <0x0 0x0c600000 0x0 0x2000000>,
2854                               <0x0 0x0e600000 0x0 0x100000>,
2855                               <0x0 0x0e700000 0x0 0xa0000>,
2856                               <0x0 0x0c40a000 0x0 0x26000>;
2857                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2858                         interrupt-names = "periph_irq";
2859                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2860                         qcom,ee = <0>;
2861                         qcom,channel = <0>;
2862                         #address-cells = <2>;
2863                         #size-cells = <0>;
2864                         interrupt-controller;
2865                         #interrupt-cells = <4>;
2866                 };
2867
2868                 tlmm: pinctrl@f100000 {
2869                         compatible = "qcom,sm8350-tlmm";
2870                         reg = <0 0x0f100000 0 0x300000>;
2871                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2872                         gpio-controller;
2873                         #gpio-cells = <2>;
2874                         interrupt-controller;
2875                         #interrupt-cells = <2>;
2876                         gpio-ranges = <&tlmm 0 0 204>;
2877                         wakeup-parent = <&pdc>;
2878
2879                         sdc2_default_state: sdc2-default-state {
2880                                 clk-pins {
2881                                         pins = "sdc2_clk";
2882                                         drive-strength = <16>;
2883                                         bias-disable;
2884                                 };
2885
2886                                 cmd-pins {
2887                                         pins = "sdc2_cmd";
2888                                         drive-strength = <16>;
2889                                         bias-pull-up;
2890                                 };
2891
2892                                 data-pins {
2893                                         pins = "sdc2_data";
2894                                         drive-strength = <16>;
2895                                         bias-pull-up;
2896                                 };
2897                         };
2898
2899                         sdc2_sleep_state: sdc2-sleep-state {
2900                                 clk-pins {
2901                                         pins = "sdc2_clk";
2902                                         drive-strength = <2>;
2903                                         bias-disable;
2904                                 };
2905
2906                                 cmd-pins {
2907                                         pins = "sdc2_cmd";
2908                                         drive-strength = <2>;
2909                                         bias-pull-up;
2910                                 };
2911
2912                                 data-pins {
2913                                         pins = "sdc2_data";
2914                                         drive-strength = <2>;
2915                                         bias-pull-up;
2916                                 };
2917                         };
2918
2919                         qup_uart3_default_state: qup-uart3-default-state {
2920                                 rx-pins {
2921                                         pins = "gpio18";
2922                                         function = "qup3";
2923                                 };
2924                                 tx-pins {
2925                                         pins = "gpio19";
2926                                         function = "qup3";
2927                                 };
2928                         };
2929
2930                         qup_uart6_default: qup-uart6-default-state {
2931                                 pins = "gpio30", "gpio31";
2932                                 function = "qup6";
2933                                 drive-strength = <2>;
2934                                 bias-disable;
2935                         };
2936
2937                         qup_uart18_default: qup-uart18-default-state {
2938                                 pins = "gpio58", "gpio59";
2939                                 function = "qup18";
2940                                 drive-strength = <2>;
2941                                 bias-disable;
2942                         };
2943
2944                         qup_i2c0_default: qup-i2c0-default-state {
2945                                 pins = "gpio4", "gpio5";
2946                                 function = "qup0";
2947                                 drive-strength = <2>;
2948                                 bias-pull-up;
2949                         };
2950
2951                         qup_i2c1_default: qup-i2c1-default-state {
2952                                 pins = "gpio8", "gpio9";
2953                                 function = "qup1";
2954                                 drive-strength = <2>;
2955                                 bias-pull-up;
2956                         };
2957
2958                         qup_i2c2_default: qup-i2c2-default-state {
2959                                 pins = "gpio12", "gpio13";
2960                                 function = "qup2";
2961                                 drive-strength = <2>;
2962                                 bias-pull-up;
2963                         };
2964
2965                         qup_i2c4_default: qup-i2c4-default-state {
2966                                 pins = "gpio20", "gpio21";
2967                                 function = "qup4";
2968                                 drive-strength = <2>;
2969                                 bias-pull-up;
2970                         };
2971
2972                         qup_i2c5_default: qup-i2c5-default-state {
2973                                 pins = "gpio24", "gpio25";
2974                                 function = "qup5";
2975                                 drive-strength = <2>;
2976                                 bias-pull-up;
2977                         };
2978
2979                         qup_i2c6_default: qup-i2c6-default-state {
2980                                 pins = "gpio28", "gpio29";
2981                                 function = "qup6";
2982                                 drive-strength = <2>;
2983                                 bias-pull-up;
2984                         };
2985
2986                         qup_i2c7_default: qup-i2c7-default-state {
2987                                 pins = "gpio32", "gpio33";
2988                                 function = "qup7";
2989                                 drive-strength = <2>;
2990                                 bias-disable;
2991                         };
2992
2993                         qup_i2c8_default: qup-i2c8-default-state {
2994                                 pins = "gpio36", "gpio37";
2995                                 function = "qup8";
2996                                 drive-strength = <2>;
2997                                 bias-pull-up;
2998                         };
2999
3000                         qup_i2c9_default: qup-i2c9-default-state {
3001                                 pins = "gpio40", "gpio41";
3002                                 function = "qup9";
3003                                 drive-strength = <2>;
3004                                 bias-pull-up;
3005                         };
3006
3007                         qup_i2c10_default: qup-i2c10-default-state {
3008                                 pins = "gpio44", "gpio45";
3009                                 function = "qup10";
3010                                 drive-strength = <2>;
3011                                 bias-pull-up;
3012                         };
3013
3014                         qup_i2c11_default: qup-i2c11-default-state {
3015                                 pins = "gpio48", "gpio49";
3016                                 function = "qup11";
3017                                 drive-strength = <2>;
3018                                 bias-pull-up;
3019                         };
3020
3021                         qup_i2c12_default: qup-i2c12-default-state {
3022                                 pins = "gpio52", "gpio53";
3023                                 function = "qup12";
3024                                 drive-strength = <2>;
3025                                 bias-pull-up;
3026                         };
3027
3028                         qup_i2c13_default: qup-i2c13-default-state {
3029                                 pins = "gpio0", "gpio1";
3030                                 function = "qup13";
3031                                 drive-strength = <2>;
3032                                 bias-pull-up;
3033                         };
3034
3035                         qup_i2c14_default: qup-i2c14-default-state {
3036                                 pins = "gpio56", "gpio57";
3037                                 function = "qup14";
3038                                 drive-strength = <2>;
3039                                 bias-disable;
3040                         };
3041
3042                         qup_i2c15_default: qup-i2c15-default-state {
3043                                 pins = "gpio60", "gpio61";
3044                                 function = "qup15";
3045                                 drive-strength = <2>;
3046                                 bias-disable;
3047                         };
3048
3049                         qup_i2c16_default: qup-i2c16-default-state {
3050                                 pins = "gpio64", "gpio65";
3051                                 function = "qup16";
3052                                 drive-strength = <2>;
3053                                 bias-disable;
3054                         };
3055
3056                         qup_i2c17_default: qup-i2c17-default-state {
3057                                 pins = "gpio72", "gpio73";
3058                                 function = "qup17";
3059                                 drive-strength = <2>;
3060                                 bias-disable;
3061                         };
3062
3063                         qup_i2c19_default: qup-i2c19-default-state {
3064                                 pins = "gpio76", "gpio77";
3065                                 function = "qup19";
3066                                 drive-strength = <2>;
3067                                 bias-disable;
3068                         };
3069                 };
3070
3071                 apps_smmu: iommu@15000000 {
3072                         compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
3073                         reg = <0 0x15000000 0 0x100000>;
3074                         #iommu-cells = <2>;
3075                         #global-interrupts = <2>;
3076                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3077                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3078                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3079                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3080                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3081                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3082                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3083                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3084                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3085                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3086                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3087                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3088                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3089                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3090                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3091                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3092                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3093                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3094                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3095                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3096                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3097                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3098                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3099                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3100                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3101                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3102                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3103                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3104                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3105                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3106                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3107                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3108                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3109                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3110                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3111                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3112                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3113                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3114                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3115                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3116                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3117                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3118                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3119                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3120                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3121                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3122                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3123                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3124                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3125                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3126                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3127                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3128                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3129                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3130                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3131                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3132                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3133                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3134                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3135                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3136                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3137                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3138                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3139                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3140                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3141                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3142                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3143                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3144                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3145                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3146                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3147                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3148                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3149                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3150                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3151                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3152                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3153                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3154                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3155                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3156                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3157                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3158                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3159                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3160                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3161                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3162                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3163                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3164                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3165                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3166                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3167                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3168                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3169                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3170                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3171                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3172                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3173                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3174                 };
3175
3176                 adsp: remoteproc@17300000 {
3177                         compatible = "qcom,sm8350-adsp-pas";
3178                         reg = <0 0x17300000 0 0x100>;
3179
3180                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3181                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3182                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3183                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3184                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3185                         interrupt-names = "wdog", "fatal", "ready",
3186                                           "handover", "stop-ack";
3187
3188                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3189                         clock-names = "xo";
3190
3191                         power-domains = <&rpmhpd SM8350_LCX>,
3192                                         <&rpmhpd SM8350_LMX>;
3193                         power-domain-names = "lcx", "lmx";
3194
3195                         memory-region = <&pil_adsp_mem>;
3196
3197                         qcom,qmp = <&aoss_qmp>;
3198
3199                         qcom,smem-states = <&smp2p_adsp_out 0>;
3200                         qcom,smem-state-names = "stop";
3201
3202                         status = "disabled";
3203
3204                         glink-edge {
3205                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3206                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3207                                                              IRQ_TYPE_EDGE_RISING>;
3208                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
3209                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3210
3211                                 label = "lpass";
3212                                 qcom,remote-pid = <2>;
3213
3214                                 fastrpc {
3215                                         compatible = "qcom,fastrpc";
3216                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3217                                         label = "adsp";
3218                                         qcom,non-secure-domain;
3219                                         #address-cells = <1>;
3220                                         #size-cells = <0>;
3221
3222                                         compute-cb@3 {
3223                                                 compatible = "qcom,fastrpc-compute-cb";
3224                                                 reg = <3>;
3225                                                 iommus = <&apps_smmu 0x1803 0x0>;
3226                                         };
3227
3228                                         compute-cb@4 {
3229                                                 compatible = "qcom,fastrpc-compute-cb";
3230                                                 reg = <4>;
3231                                                 iommus = <&apps_smmu 0x1804 0x0>;
3232                                         };
3233
3234                                         compute-cb@5 {
3235                                                 compatible = "qcom,fastrpc-compute-cb";
3236                                                 reg = <5>;
3237                                                 iommus = <&apps_smmu 0x1805 0x0>;
3238                                         };
3239                                 };
3240                         };
3241                 };
3242
3243                 intc: interrupt-controller@17a00000 {
3244                         compatible = "arm,gic-v3";
3245                         #interrupt-cells = <3>;
3246                         interrupt-controller;
3247                         #redistributor-regions = <1>;
3248                         redistributor-stride = <0 0x20000>;
3249                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
3250                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
3251                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3252                 };
3253
3254                 timer@17c20000 {
3255                         compatible = "arm,armv7-timer-mem";
3256                         #address-cells = <1>;
3257                         #size-cells = <1>;
3258                         ranges = <0 0 0 0x20000000>;
3259                         reg = <0x0 0x17c20000 0x0 0x1000>;
3260                         clock-frequency = <19200000>;
3261
3262                         frame@17c21000 {
3263                                 frame-number = <0>;
3264                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3265                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3266                                 reg = <0x17c21000 0x1000>,
3267                                       <0x17c22000 0x1000>;
3268                         };
3269
3270                         frame@17c23000 {
3271                                 frame-number = <1>;
3272                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3273                                 reg = <0x17c23000 0x1000>;
3274                                 status = "disabled";
3275                         };
3276
3277                         frame@17c25000 {
3278                                 frame-number = <2>;
3279                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3280                                 reg = <0x17c25000 0x1000>;
3281                                 status = "disabled";
3282                         };
3283
3284                         frame@17c27000 {
3285                                 frame-number = <3>;
3286                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3287                                 reg = <0x17c27000 0x1000>;
3288                                 status = "disabled";
3289                         };
3290
3291                         frame@17c29000 {
3292                                 frame-number = <4>;
3293                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3294                                 reg = <0x17c29000 0x1000>;
3295                                 status = "disabled";
3296                         };
3297
3298                         frame@17c2b000 {
3299                                 frame-number = <5>;
3300                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3301                                 reg = <0x17c2b000 0x1000>;
3302                                 status = "disabled";
3303                         };
3304
3305                         frame@17c2d000 {
3306                                 frame-number = <6>;
3307                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3308                                 reg = <0x17c2d000 0x1000>;
3309                                 status = "disabled";
3310                         };
3311                 };
3312
3313                 apps_rsc: rsc@18200000 {
3314                         label = "apps_rsc";
3315                         compatible = "qcom,rpmh-rsc";
3316                         reg = <0x0 0x18200000 0x0 0x10000>,
3317                                 <0x0 0x18210000 0x0 0x10000>,
3318                                 <0x0 0x18220000 0x0 0x10000>;
3319                         reg-names = "drv-0", "drv-1", "drv-2";
3320                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3321                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3322                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3323                         qcom,tcs-offset = <0xd00>;
3324                         qcom,drv-id = <2>;
3325                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
3326                                           <WAKE_TCS    3>, <CONTROL_TCS 0>;
3327                         power-domains = <&CLUSTER_PD>;
3328
3329                         rpmhcc: clock-controller {
3330                                 compatible = "qcom,sm8350-rpmh-clk";
3331                                 #clock-cells = <1>;
3332                                 clock-names = "xo";
3333                                 clocks = <&xo_board>;
3334                         };
3335
3336                         rpmhpd: power-controller {
3337                                 compatible = "qcom,sm8350-rpmhpd";
3338                                 #power-domain-cells = <1>;
3339                                 operating-points-v2 = <&rpmhpd_opp_table>;
3340
3341                                 rpmhpd_opp_table: opp-table {
3342                                         compatible = "operating-points-v2";
3343
3344                                         rpmhpd_opp_ret: opp1 {
3345                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3346                                         };
3347
3348                                         rpmhpd_opp_min_svs: opp2 {
3349                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3350                                         };
3351
3352                                         rpmhpd_opp_low_svs: opp3 {
3353                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3354                                         };
3355
3356                                         rpmhpd_opp_svs: opp4 {
3357                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3358                                         };
3359
3360                                         rpmhpd_opp_svs_l1: opp5 {
3361                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3362                                         };
3363
3364                                         rpmhpd_opp_nom: opp6 {
3365                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3366                                         };
3367
3368                                         rpmhpd_opp_nom_l1: opp7 {
3369                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3370                                         };
3371
3372                                         rpmhpd_opp_nom_l2: opp8 {
3373                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3374                                         };
3375
3376                                         rpmhpd_opp_turbo: opp9 {
3377                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3378                                         };
3379
3380                                         rpmhpd_opp_turbo_l1: opp10 {
3381                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3382                                         };
3383                                 };
3384                         };
3385
3386                         apps_bcm_voter: bcm-voter {
3387                                 compatible = "qcom,bcm-voter";
3388                         };
3389                 };
3390
3391                 cpufreq_hw: cpufreq@18591000 {
3392                         compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
3393                         reg = <0 0x18591000 0 0x1000>,
3394                               <0 0x18592000 0 0x1000>,
3395                               <0 0x18593000 0 0x1000>;
3396                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3397
3398                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3399                         clock-names = "xo", "alternate";
3400
3401                         #freq-domain-cells = <1>;
3402                         #clock-cells = <1>;
3403                 };
3404
3405                 cdsp: remoteproc@98900000 {
3406                         compatible = "qcom,sm8350-cdsp-pas";
3407                         reg = <0 0x98900000 0 0x1400000>;
3408
3409                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3410                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3411                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3412                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3413                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3414                         interrupt-names = "wdog", "fatal", "ready",
3415                                           "handover", "stop-ack";
3416
3417                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3418                         clock-names = "xo";
3419
3420                         power-domains = <&rpmhpd SM8350_CX>,
3421                                         <&rpmhpd SM8350_MXC>;
3422                         power-domain-names = "cx", "mxc";
3423
3424                         interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3425
3426                         memory-region = <&pil_cdsp_mem>;
3427
3428                         qcom,qmp = <&aoss_qmp>;
3429
3430                         qcom,smem-states = <&smp2p_cdsp_out 0>;
3431                         qcom,smem-state-names = "stop";
3432
3433                         status = "disabled";
3434
3435                         glink-edge {
3436                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3437                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3438                                                              IRQ_TYPE_EDGE_RISING>;
3439                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
3440                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3441
3442                                 label = "cdsp";
3443                                 qcom,remote-pid = <5>;
3444
3445                                 fastrpc {
3446                                         compatible = "qcom,fastrpc";
3447                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3448                                         label = "cdsp";
3449                                         qcom,non-secure-domain;
3450                                         #address-cells = <1>;
3451                                         #size-cells = <0>;
3452
3453                                         compute-cb@1 {
3454                                                 compatible = "qcom,fastrpc-compute-cb";
3455                                                 reg = <1>;
3456                                                 iommus = <&apps_smmu 0x2161 0x0400>,
3457                                                          <&apps_smmu 0x1181 0x0420>;
3458                                         };
3459
3460                                         compute-cb@2 {
3461                                                 compatible = "qcom,fastrpc-compute-cb";
3462                                                 reg = <2>;
3463                                                 iommus = <&apps_smmu 0x2162 0x0400>,
3464                                                          <&apps_smmu 0x1182 0x0420>;
3465                                         };
3466
3467                                         compute-cb@3 {
3468                                                 compatible = "qcom,fastrpc-compute-cb";
3469                                                 reg = <3>;
3470                                                 iommus = <&apps_smmu 0x2163 0x0400>,
3471                                                          <&apps_smmu 0x1183 0x0420>;
3472                                         };
3473
3474                                         compute-cb@4 {
3475                                                 compatible = "qcom,fastrpc-compute-cb";
3476                                                 reg = <4>;
3477                                                 iommus = <&apps_smmu 0x2164 0x0400>,
3478                                                          <&apps_smmu 0x1184 0x0420>;
3479                                         };
3480
3481                                         compute-cb@5 {
3482                                                 compatible = "qcom,fastrpc-compute-cb";
3483                                                 reg = <5>;
3484                                                 iommus = <&apps_smmu 0x2165 0x0400>,
3485                                                          <&apps_smmu 0x1185 0x0420>;
3486                                         };
3487
3488                                         compute-cb@6 {
3489                                                 compatible = "qcom,fastrpc-compute-cb";
3490                                                 reg = <6>;
3491                                                 iommus = <&apps_smmu 0x2166 0x0400>,
3492                                                          <&apps_smmu 0x1186 0x0420>;
3493                                         };
3494
3495                                         compute-cb@7 {
3496                                                 compatible = "qcom,fastrpc-compute-cb";
3497                                                 reg = <7>;
3498                                                 iommus = <&apps_smmu 0x2167 0x0400>,
3499                                                          <&apps_smmu 0x1187 0x0420>;
3500                                         };
3501
3502                                         compute-cb@8 {
3503                                                 compatible = "qcom,fastrpc-compute-cb";
3504                                                 reg = <8>;
3505                                                 iommus = <&apps_smmu 0x2168 0x0400>,
3506                                                          <&apps_smmu 0x1188 0x0420>;
3507                                         };
3508
3509                                         /* note: secure cb9 in downstream */
3510                                 };
3511                         };
3512                 };
3513         };
3514
3515         thermal_zones: thermal-zones {
3516                 cpu0-thermal {
3517                         polling-delay-passive = <250>;
3518                         polling-delay = <1000>;
3519
3520                         thermal-sensors = <&tsens0 1>;
3521
3522                         trips {
3523                                 cpu0_alert0: trip-point0 {
3524                                         temperature = <90000>;
3525                                         hysteresis = <2000>;
3526                                         type = "passive";
3527                                 };
3528
3529                                 cpu0_alert1: trip-point1 {
3530                                         temperature = <95000>;
3531                                         hysteresis = <2000>;
3532                                         type = "passive";
3533                                 };
3534
3535                                 cpu0_crit: cpu-crit {
3536                                         temperature = <110000>;
3537                                         hysteresis = <1000>;
3538                                         type = "critical";
3539                                 };
3540                         };
3541
3542                         cooling-maps {
3543                                 map0 {
3544                                         trip = <&cpu0_alert0>;
3545                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3546                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3547                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3548                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3549                                 };
3550                                 map1 {
3551                                         trip = <&cpu0_alert1>;
3552                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3553                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3554                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3555                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3556                                 };
3557                         };
3558                 };
3559
3560                 cpu1-thermal {
3561                         polling-delay-passive = <250>;
3562                         polling-delay = <1000>;
3563
3564                         thermal-sensors = <&tsens0 2>;
3565
3566                         trips {
3567                                 cpu1_alert0: trip-point0 {
3568                                         temperature = <90000>;
3569                                         hysteresis = <2000>;
3570                                         type = "passive";
3571                                 };
3572
3573                                 cpu1_alert1: trip-point1 {
3574                                         temperature = <95000>;
3575                                         hysteresis = <2000>;
3576                                         type = "passive";
3577                                 };
3578
3579                                 cpu1_crit: cpu-crit {
3580                                         temperature = <110000>;
3581                                         hysteresis = <1000>;
3582                                         type = "critical";
3583                                 };
3584                         };
3585
3586                         cooling-maps {
3587                                 map0 {
3588                                         trip = <&cpu1_alert0>;
3589                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3590                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3591                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3592                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3593                                 };
3594                                 map1 {
3595                                         trip = <&cpu1_alert1>;
3596                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3597                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3598                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3599                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3600                                 };
3601                         };
3602                 };
3603
3604                 cpu2-thermal {
3605                         polling-delay-passive = <250>;
3606                         polling-delay = <1000>;
3607
3608                         thermal-sensors = <&tsens0 3>;
3609
3610                         trips {
3611                                 cpu2_alert0: trip-point0 {
3612                                         temperature = <90000>;
3613                                         hysteresis = <2000>;
3614                                         type = "passive";
3615                                 };
3616
3617                                 cpu2_alert1: trip-point1 {
3618                                         temperature = <95000>;
3619                                         hysteresis = <2000>;
3620                                         type = "passive";
3621                                 };
3622
3623                                 cpu2_crit: cpu-crit {
3624                                         temperature = <110000>;
3625                                         hysteresis = <1000>;
3626                                         type = "critical";
3627                                 };
3628                         };
3629
3630                         cooling-maps {
3631                                 map0 {
3632                                         trip = <&cpu2_alert0>;
3633                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3634                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3635                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3636                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3637                                 };
3638                                 map1 {
3639                                         trip = <&cpu2_alert1>;
3640                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3641                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3642                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3643                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3644                                 };
3645                         };
3646                 };
3647
3648                 cpu3-thermal {
3649                         polling-delay-passive = <250>;
3650                         polling-delay = <1000>;
3651
3652                         thermal-sensors = <&tsens0 4>;
3653
3654                         trips {
3655                                 cpu3_alert0: trip-point0 {
3656                                         temperature = <90000>;
3657                                         hysteresis = <2000>;
3658                                         type = "passive";
3659                                 };
3660
3661                                 cpu3_alert1: trip-point1 {
3662                                         temperature = <95000>;
3663                                         hysteresis = <2000>;
3664                                         type = "passive";
3665                                 };
3666
3667                                 cpu3_crit: cpu-crit {
3668                                         temperature = <110000>;
3669                                         hysteresis = <1000>;
3670                                         type = "critical";
3671                                 };
3672                         };
3673
3674                         cooling-maps {
3675                                 map0 {
3676                                         trip = <&cpu3_alert0>;
3677                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3678                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3679                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3680                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3681                                 };
3682                                 map1 {
3683                                         trip = <&cpu3_alert1>;
3684                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3685                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3686                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3687                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3688                                 };
3689                         };
3690                 };
3691
3692                 cpu4-top-thermal {
3693                         polling-delay-passive = <250>;
3694                         polling-delay = <1000>;
3695
3696                         thermal-sensors = <&tsens0 7>;
3697
3698                         trips {
3699                                 cpu4_top_alert0: trip-point0 {
3700                                         temperature = <90000>;
3701                                         hysteresis = <2000>;
3702                                         type = "passive";
3703                                 };
3704
3705                                 cpu4_top_alert1: trip-point1 {
3706                                         temperature = <95000>;
3707                                         hysteresis = <2000>;
3708                                         type = "passive";
3709                                 };
3710
3711                                 cpu4_top_crit: cpu-crit {
3712                                         temperature = <110000>;
3713                                         hysteresis = <1000>;
3714                                         type = "critical";
3715                                 };
3716                         };
3717
3718                         cooling-maps {
3719                                 map0 {
3720                                         trip = <&cpu4_top_alert0>;
3721                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3722                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3723                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3724                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3725                                 };
3726                                 map1 {
3727                                         trip = <&cpu4_top_alert1>;
3728                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3729                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3730                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3731                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3732                                 };
3733                         };
3734                 };
3735
3736                 cpu5-top-thermal {
3737                         polling-delay-passive = <250>;
3738                         polling-delay = <1000>;
3739
3740                         thermal-sensors = <&tsens0 8>;
3741
3742                         trips {
3743                                 cpu5_top_alert0: trip-point0 {
3744                                         temperature = <90000>;
3745                                         hysteresis = <2000>;
3746                                         type = "passive";
3747                                 };
3748
3749                                 cpu5_top_alert1: trip-point1 {
3750                                         temperature = <95000>;
3751                                         hysteresis = <2000>;
3752                                         type = "passive";
3753                                 };
3754
3755                                 cpu5_top_crit: cpu-crit {
3756                                         temperature = <110000>;
3757                                         hysteresis = <1000>;
3758                                         type = "critical";
3759                                 };
3760                         };
3761
3762                         cooling-maps {
3763                                 map0 {
3764                                         trip = <&cpu5_top_alert0>;
3765                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3766                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3767                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3768                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3769                                 };
3770                                 map1 {
3771                                         trip = <&cpu5_top_alert1>;
3772                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3773                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3774                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3775                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3776                                 };
3777                         };
3778                 };
3779
3780                 cpu6-top-thermal {
3781                         polling-delay-passive = <250>;
3782                         polling-delay = <1000>;
3783
3784                         thermal-sensors = <&tsens0 9>;
3785
3786                         trips {
3787                                 cpu6_top_alert0: trip-point0 {
3788                                         temperature = <90000>;
3789                                         hysteresis = <2000>;
3790                                         type = "passive";
3791                                 };
3792
3793                                 cpu6_top_alert1: trip-point1 {
3794                                         temperature = <95000>;
3795                                         hysteresis = <2000>;
3796                                         type = "passive";
3797                                 };
3798
3799                                 cpu6_top_crit: cpu-crit {
3800                                         temperature = <110000>;
3801                                         hysteresis = <1000>;
3802                                         type = "critical";
3803                                 };
3804                         };
3805
3806                         cooling-maps {
3807                                 map0 {
3808                                         trip = <&cpu6_top_alert0>;
3809                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3810                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3811                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3812                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3813                                 };
3814                                 map1 {
3815                                         trip = <&cpu6_top_alert1>;
3816                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3817                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3818                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3819                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3820                                 };
3821                         };
3822                 };
3823
3824                 cpu7-top-thermal {
3825                         polling-delay-passive = <250>;
3826                         polling-delay = <1000>;
3827
3828                         thermal-sensors = <&tsens0 10>;
3829
3830                         trips {
3831                                 cpu7_top_alert0: trip-point0 {
3832                                         temperature = <90000>;
3833                                         hysteresis = <2000>;
3834                                         type = "passive";
3835                                 };
3836
3837                                 cpu7_top_alert1: trip-point1 {
3838                                         temperature = <95000>;
3839                                         hysteresis = <2000>;
3840                                         type = "passive";
3841                                 };
3842
3843                                 cpu7_top_crit: cpu-crit {
3844                                         temperature = <110000>;
3845                                         hysteresis = <1000>;
3846                                         type = "critical";
3847                                 };
3848                         };
3849
3850                         cooling-maps {
3851                                 map0 {
3852                                         trip = <&cpu7_top_alert0>;
3853                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3854                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3855                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3856                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3857                                 };
3858                                 map1 {
3859                                         trip = <&cpu7_top_alert1>;
3860                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3861                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3862                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3863                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3864                                 };
3865                         };
3866                 };
3867
3868                 cpu4-bottom-thermal {
3869                         polling-delay-passive = <250>;
3870                         polling-delay = <1000>;
3871
3872                         thermal-sensors = <&tsens0 11>;
3873
3874                         trips {
3875                                 cpu4_bottom_alert0: trip-point0 {
3876                                         temperature = <90000>;
3877                                         hysteresis = <2000>;
3878                                         type = "passive";
3879                                 };
3880
3881                                 cpu4_bottom_alert1: trip-point1 {
3882                                         temperature = <95000>;
3883                                         hysteresis = <2000>;
3884                                         type = "passive";
3885                                 };
3886
3887                                 cpu4_bottom_crit: cpu-crit {
3888                                         temperature = <110000>;
3889                                         hysteresis = <1000>;
3890                                         type = "critical";
3891                                 };
3892                         };
3893
3894                         cooling-maps {
3895                                 map0 {
3896                                         trip = <&cpu4_bottom_alert0>;
3897                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3898                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3899                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3900                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3901                                 };
3902                                 map1 {
3903                                         trip = <&cpu4_bottom_alert1>;
3904                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3905                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3906                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3907                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3908                                 };
3909                         };
3910                 };
3911
3912                 cpu5-bottom-thermal {
3913                         polling-delay-passive = <250>;
3914                         polling-delay = <1000>;
3915
3916                         thermal-sensors = <&tsens0 12>;
3917
3918                         trips {
3919                                 cpu5_bottom_alert0: trip-point0 {
3920                                         temperature = <90000>;
3921                                         hysteresis = <2000>;
3922                                         type = "passive";
3923                                 };
3924
3925                                 cpu5_bottom_alert1: trip-point1 {
3926                                         temperature = <95000>;
3927                                         hysteresis = <2000>;
3928                                         type = "passive";
3929                                 };
3930
3931                                 cpu5_bottom_crit: cpu-crit {
3932                                         temperature = <110000>;
3933                                         hysteresis = <1000>;
3934                                         type = "critical";
3935                                 };
3936                         };
3937
3938                         cooling-maps {
3939                                 map0 {
3940                                         trip = <&cpu5_bottom_alert0>;
3941                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3942                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3943                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3944                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3945                                 };
3946                                 map1 {
3947                                         trip = <&cpu5_bottom_alert1>;
3948                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3949                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3950                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3951                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3952                                 };
3953                         };
3954                 };
3955
3956                 cpu6-bottom-thermal {
3957                         polling-delay-passive = <250>;
3958                         polling-delay = <1000>;
3959
3960                         thermal-sensors = <&tsens0 13>;
3961
3962                         trips {
3963                                 cpu6_bottom_alert0: trip-point0 {
3964                                         temperature = <90000>;
3965                                         hysteresis = <2000>;
3966                                         type = "passive";
3967                                 };
3968
3969                                 cpu6_bottom_alert1: trip-point1 {
3970                                         temperature = <95000>;
3971                                         hysteresis = <2000>;
3972                                         type = "passive";
3973                                 };
3974
3975                                 cpu6_bottom_crit: cpu-crit {
3976                                         temperature = <110000>;
3977                                         hysteresis = <1000>;
3978                                         type = "critical";
3979                                 };
3980                         };
3981
3982                         cooling-maps {
3983                                 map0 {
3984                                         trip = <&cpu6_bottom_alert0>;
3985                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3986                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3987                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3988                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3989                                 };
3990                                 map1 {
3991                                         trip = <&cpu6_bottom_alert1>;
3992                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3993                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3994                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3995                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3996                                 };
3997                         };
3998                 };
3999
4000                 cpu7-bottom-thermal {
4001                         polling-delay-passive = <250>;
4002                         polling-delay = <1000>;
4003
4004                         thermal-sensors = <&tsens0 14>;
4005
4006                         trips {
4007                                 cpu7_bottom_alert0: trip-point0 {
4008                                         temperature = <90000>;
4009                                         hysteresis = <2000>;
4010                                         type = "passive";
4011                                 };
4012
4013                                 cpu7_bottom_alert1: trip-point1 {
4014                                         temperature = <95000>;
4015                                         hysteresis = <2000>;
4016                                         type = "passive";
4017                                 };
4018
4019                                 cpu7_bottom_crit: cpu-crit {
4020                                         temperature = <110000>;
4021                                         hysteresis = <1000>;
4022                                         type = "critical";
4023                                 };
4024                         };
4025
4026                         cooling-maps {
4027                                 map0 {
4028                                         trip = <&cpu7_bottom_alert0>;
4029                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4030                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4031                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4032                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4033                                 };
4034                                 map1 {
4035                                         trip = <&cpu7_bottom_alert1>;
4036                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4037                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4038                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4039                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4040                                 };
4041                         };
4042                 };
4043
4044                 aoss0-thermal {
4045                         polling-delay-passive = <250>;
4046                         polling-delay = <1000>;
4047
4048                         thermal-sensors = <&tsens0 0>;
4049
4050                         trips {
4051                                 aoss0_alert0: trip-point0 {
4052                                         temperature = <90000>;
4053                                         hysteresis = <2000>;
4054                                         type = "hot";
4055                                 };
4056                         };
4057                 };
4058
4059                 cluster0-thermal {
4060                         polling-delay-passive = <250>;
4061                         polling-delay = <1000>;
4062
4063                         thermal-sensors = <&tsens0 5>;
4064
4065                         trips {
4066                                 cluster0_alert0: trip-point0 {
4067                                         temperature = <90000>;
4068                                         hysteresis = <2000>;
4069                                         type = "hot";
4070                                 };
4071                                 cluster0_crit: cluster0_crit {
4072                                         temperature = <110000>;
4073                                         hysteresis = <2000>;
4074                                         type = "critical";
4075                                 };
4076                         };
4077                 };
4078
4079                 cluster1-thermal {
4080                         polling-delay-passive = <250>;
4081                         polling-delay = <1000>;
4082
4083                         thermal-sensors = <&tsens0 6>;
4084
4085                         trips {
4086                                 cluster1_alert0: trip-point0 {
4087                                         temperature = <90000>;
4088                                         hysteresis = <2000>;
4089                                         type = "hot";
4090                                 };
4091                                 cluster1_crit: cluster1_crit {
4092                                         temperature = <110000>;
4093                                         hysteresis = <2000>;
4094                                         type = "critical";
4095                                 };
4096                         };
4097                 };
4098
4099                 aoss1-thermal {
4100                         polling-delay-passive = <250>;
4101                         polling-delay = <1000>;
4102
4103                         thermal-sensors = <&tsens1 0>;
4104
4105                         trips {
4106                                 aoss1_alert0: trip-point0 {
4107                                         temperature = <90000>;
4108                                         hysteresis = <2000>;
4109                                         type = "hot";
4110                                 };
4111                         };
4112                 };
4113
4114                 gpu-top-thermal {
4115                         polling-delay-passive = <250>;
4116                         polling-delay = <1000>;
4117
4118                         thermal-sensors = <&tsens1 1>;
4119
4120                         trips {
4121                                 gpu1_alert0: trip-point0 {
4122                                         temperature = <90000>;
4123                                         hysteresis = <1000>;
4124                                         type = "hot";
4125                                 };
4126                         };
4127                 };
4128
4129                 gpu-bottom-thermal {
4130                         polling-delay-passive = <250>;
4131                         polling-delay = <1000>;
4132
4133                         thermal-sensors = <&tsens1 2>;
4134
4135                         trips {
4136                                 gpu2_alert0: trip-point0 {
4137                                         temperature = <90000>;
4138                                         hysteresis = <1000>;
4139                                         type = "hot";
4140                                 };
4141                         };
4142                 };
4143
4144                 nspss1-thermal {
4145                         polling-delay-passive = <250>;
4146                         polling-delay = <1000>;
4147
4148                         thermal-sensors = <&tsens1 3>;
4149
4150                         trips {
4151                                 nspss1_alert0: trip-point0 {
4152                                         temperature = <90000>;
4153                                         hysteresis = <1000>;
4154                                         type = "hot";
4155                                 };
4156                         };
4157                 };
4158
4159                 nspss2-thermal {
4160                         polling-delay-passive = <250>;
4161                         polling-delay = <1000>;
4162
4163                         thermal-sensors = <&tsens1 4>;
4164
4165                         trips {
4166                                 nspss2_alert0: trip-point0 {
4167                                         temperature = <90000>;
4168                                         hysteresis = <1000>;
4169                                         type = "hot";
4170                                 };
4171                         };
4172                 };
4173
4174                 nspss3-thermal {
4175                         polling-delay-passive = <250>;
4176                         polling-delay = <1000>;
4177
4178                         thermal-sensors = <&tsens1 5>;
4179
4180                         trips {
4181                                 nspss3_alert0: trip-point0 {
4182                                         temperature = <90000>;
4183                                         hysteresis = <1000>;
4184                                         type = "hot";
4185                                 };
4186                         };
4187                 };
4188
4189                 video-thermal {
4190                         polling-delay-passive = <250>;
4191                         polling-delay = <1000>;
4192
4193                         thermal-sensors = <&tsens1 6>;
4194
4195                         trips {
4196                                 video_alert0: trip-point0 {
4197                                         temperature = <90000>;
4198                                         hysteresis = <2000>;
4199                                         type = "hot";
4200                                 };
4201                         };
4202                 };
4203
4204                 mem-thermal {
4205                         polling-delay-passive = <250>;
4206                         polling-delay = <1000>;
4207
4208                         thermal-sensors = <&tsens1 7>;
4209
4210                         trips {
4211                                 mem_alert0: trip-point0 {
4212                                         temperature = <90000>;
4213                                         hysteresis = <2000>;
4214                                         type = "hot";
4215                                 };
4216                         };
4217                 };
4218
4219                 modem1-top-thermal {
4220                         polling-delay-passive = <250>;
4221                         polling-delay = <1000>;
4222
4223                         thermal-sensors = <&tsens1 8>;
4224
4225                         trips {
4226                                 modem1_alert0: trip-point0 {
4227                                         temperature = <90000>;
4228                                         hysteresis = <2000>;
4229                                         type = "hot";
4230                                 };
4231                         };
4232                 };
4233
4234                 modem2-top-thermal {
4235                         polling-delay-passive = <250>;
4236                         polling-delay = <1000>;
4237
4238                         thermal-sensors = <&tsens1 9>;
4239
4240                         trips {
4241                                 modem2_alert0: trip-point0 {
4242                                         temperature = <90000>;
4243                                         hysteresis = <2000>;
4244                                         type = "hot";
4245                                 };
4246                         };
4247                 };
4248
4249                 modem3-top-thermal {
4250                         polling-delay-passive = <250>;
4251                         polling-delay = <1000>;
4252
4253                         thermal-sensors = <&tsens1 10>;
4254
4255                         trips {
4256                                 modem3_alert0: trip-point0 {
4257                                         temperature = <90000>;
4258                                         hysteresis = <2000>;
4259                                         type = "hot";
4260                                 };
4261                         };
4262                 };
4263
4264                 modem4-top-thermal {
4265                         polling-delay-passive = <250>;
4266                         polling-delay = <1000>;
4267
4268                         thermal-sensors = <&tsens1 11>;
4269
4270                         trips {
4271                                 modem4_alert0: trip-point0 {
4272                                         temperature = <90000>;
4273                                         hysteresis = <2000>;
4274                                         type = "hot";
4275                                 };
4276                         };
4277                 };
4278
4279                 camera-top-thermal {
4280                         polling-delay-passive = <250>;
4281                         polling-delay = <1000>;
4282
4283                         thermal-sensors = <&tsens1 12>;
4284
4285                         trips {
4286                                 camera1_alert0: trip-point0 {
4287                                         temperature = <90000>;
4288                                         hysteresis = <2000>;
4289                                         type = "hot";
4290                                 };
4291                         };
4292                 };
4293
4294                 cam-bottom-thermal {
4295                         polling-delay-passive = <250>;
4296                         polling-delay = <1000>;
4297
4298                         thermal-sensors = <&tsens1 13>;
4299
4300                         trips {
4301                                 camera2_alert0: trip-point0 {
4302                                         temperature = <90000>;
4303                                         hysteresis = <2000>;
4304                                         type = "hot";
4305                                 };
4306                         };
4307                 };
4308         };
4309
4310         timer {
4311                 compatible = "arm,armv8-timer";
4312                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4313                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4314                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4315                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
4316         };
4317 };