arch/arm64/boot/dts/qcom/sm8350.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interconnect/qcom,sm8350.h>
  11 #include <dt-bindings/mailbox/qcom-ipcc.h>
  12 #include <dt-bindings/power/qcom-rpmpd.h>
  13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  14 #include <dt-bindings/thermal/thermal.h>
  15 #include <dt-bindings/interconnect/qcom,sm8350.h>
  16
  17 / {
  18         interrupt-parent = <&intc>;
  19
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         chosen { };
  24
  25         clocks {
  26                 xo_board: xo-board {
  27                         compatible = "fixed-clock";
  28                         #clock-cells = <0>;
  29                         clock-frequency = <38400000>;
  30                         clock-output-names = "xo_board";
  31                 };
  32
  33                 sleep_clk: sleep-clk {
  34                         compatible = "fixed-clock";
  35                         clock-frequency = <32000>;
  36                         #clock-cells = <0>;
  37                 };
  38
  39                 ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
  40                         compatible = "fixed-clock";
  41                         clock-frequency = <1000>;
  42                         #clock-cells = <0>;
  43                 };
  44
  45                 ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
  46                         compatible = "fixed-clock";
  47                         clock-frequency = <1000>;
  48                         #clock-cells = <0>;
  49                 };
  50
  51                 ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
  52                         compatible = "fixed-clock";
  53                         clock-frequency = <1000>;
  54                         #clock-cells = <0>;
  55                 };
  56         };
  57
  58         cpus {
  59                 #address-cells = <2>;
  60                 #size-cells = <0>;
  61
  62                 CPU0: cpu@0 {
  63                         device_type = "cpu";
  64                         compatible = "qcom,kryo685";
  65                         reg = <0x0 0x0>;
  66                         enable-method = "psci";
  67                         next-level-cache = <&L2_0>;
  68                         qcom,freq-domain = <&cpufreq_hw 0>;
  69                         power-domains = <&CPU_PD0>;
  70                         power-domain-names = "psci";
  71                         #cooling-cells = <2>;
  72                         L2_0: l2-cache {
  73                               compatible = "cache";
  74                               next-level-cache = <&L3_0>;
  75                                 L3_0: l3-cache {
  76                                       compatible = "cache";
  77                                 };
  78                         };
  79                 };
  80
  81                 CPU1: cpu@100 {
  82                         device_type = "cpu";
  83                         compatible = "qcom,kryo685";
  84                         reg = <0x0 0x100>;
  85                         enable-method = "psci";
  86                         next-level-cache = <&L2_100>;
  87                         qcom,freq-domain = <&cpufreq_hw 0>;
  88                         power-domains = <&CPU_PD1>;
  89                         power-domain-names = "psci";
  90                         #cooling-cells = <2>;
  91                         L2_100: l2-cache {
  92                               compatible = "cache";
  93                               next-level-cache = <&L3_0>;
  94                         };
  95                 };
  96
  97                 CPU2: cpu@200 {
  98                         device_type = "cpu";
  99                         compatible = "qcom,kryo685";
 100                         reg = <0x0 0x200>;
 101                         enable-method = "psci";
 102                         next-level-cache = <&L2_200>;
 103                         qcom,freq-domain = <&cpufreq_hw 0>;
 104                         power-domains = <&CPU_PD2>;
 105                         power-domain-names = "psci";
 106                         #cooling-cells = <2>;
 107                         L2_200: l2-cache {
 108                               compatible = "cache";
 109                               next-level-cache = <&L3_0>;
 110                         };
 111                 };
 112
 113                 CPU3: cpu@300 {
 114                         device_type = "cpu";
 115                         compatible = "qcom,kryo685";
 116                         reg = <0x0 0x300>;
 117                         enable-method = "psci";
 118                         next-level-cache = <&L2_300>;
 119                         qcom,freq-domain = <&cpufreq_hw 0>;
 120                         power-domains = <&CPU_PD3>;
 121                         power-domain-names = "psci";
 122                         #cooling-cells = <2>;
 123                         L2_300: l2-cache {
 124                               compatible = "cache";
 125                               next-level-cache = <&L3_0>;
 126                         };
 127                 };
 128
 129                 CPU4: cpu@400 {
 130                         device_type = "cpu";
 131                         compatible = "qcom,kryo685";
 132                         reg = <0x0 0x400>;
 133                         enable-method = "psci";
 134                         next-level-cache = <&L2_400>;
 135                         qcom,freq-domain = <&cpufreq_hw 1>;
 136                         power-domains = <&CPU_PD4>;
 137                         power-domain-names = "psci";
 138                         #cooling-cells = <2>;
 139                         L2_400: l2-cache {
 140                               compatible = "cache";
 141                               next-level-cache = <&L3_0>;
 142                         };
 143                 };
 144
 145                 CPU5: cpu@500 {
 146                         device_type = "cpu";
 147                         compatible = "qcom,kryo685";
 148                         reg = <0x0 0x500>;
 149                         enable-method = "psci";
 150                         next-level-cache = <&L2_500>;
 151                         qcom,freq-domain = <&cpufreq_hw 1>;
 152                         power-domains = <&CPU_PD5>;
 153                         power-domain-names = "psci";
 154                         #cooling-cells = <2>;
 155                         L2_500: l2-cache {
 156                               compatible = "cache";
 157                               next-level-cache = <&L3_0>;
 158                         };
 159
 160                 };
 161
 162                 CPU6: cpu@600 {
 163                         device_type = "cpu";
 164                         compatible = "qcom,kryo685";
 165                         reg = <0x0 0x600>;
 166                         enable-method = "psci";
 167                         next-level-cache = <&L2_600>;
 168                         qcom,freq-domain = <&cpufreq_hw 1>;
 169                         power-domains = <&CPU_PD6>;
 170                         power-domain-names = "psci";
 171                         #cooling-cells = <2>;
 172                         L2_600: l2-cache {
 173                               compatible = "cache";
 174                               next-level-cache = <&L3_0>;
 175                         };
 176                 };
 177
 178                 CPU7: cpu@700 {
 179                         device_type = "cpu";
 180                         compatible = "qcom,kryo685";
 181                         reg = <0x0 0x700>;
 182                         enable-method = "psci";
 183                         next-level-cache = <&L2_700>;
 184                         qcom,freq-domain = <&cpufreq_hw 2>;
 185                         power-domains = <&CPU_PD7>;
 186                         power-domain-names = "psci";
 187                         #cooling-cells = <2>;
 188                         L2_700: l2-cache {
 189                               compatible = "cache";
 190                               next-level-cache = <&L3_0>;
 191                         };
 192                 };
 193
 194                 cpu-map {
 195                         cluster0 {
 196                                 core0 {
 197                                         cpu = <&CPU0>;
 198                                 };
 199
 200                                 core1 {
 201                                         cpu = <&CPU1>;
 202                                 };
 203
 204                                 core2 {
 205                                         cpu = <&CPU2>;
 206                                 };
 207
 208                                 core3 {
 209                                         cpu = <&CPU3>;
 210                                 };
 211
 212                                 core4 {
 213                                         cpu = <&CPU4>;
 214                                 };
 215
 216                                 core5 {
 217                                         cpu = <&CPU5>;
 218                                 };
 219
 220                                 core6 {
 221                                         cpu = <&CPU6>;
 222                                 };
 223
 224                                 core7 {
 225                                         cpu = <&CPU7>;
 226                                 };
 227                         };
 228                 };
 229
 230                 idle-states {
 231                         entry-method = "psci";
 232
 233                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 234                                 compatible = "arm,idle-state";
 235                                 idle-state-name = "silver-rail-power-collapse";
 236                                 arm,psci-suspend-param = <0x40000004>;
 237                                 entry-latency-us = <355>;
 238                                 exit-latency-us = <909>;
 239                                 min-residency-us = <3934>;
 240                                 local-timer-stop;
 241                         };
 242
 243                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 244                                 compatible = "arm,idle-state";
 245                                 idle-state-name = "gold-rail-power-collapse";
 246                                 arm,psci-suspend-param = <0x40000004>;
 247                                 entry-latency-us = <241>;
 248                                 exit-latency-us = <1461>;
 249                                 min-residency-us = <4488>;
 250                                 local-timer-stop;
 251                         };
 252                 };
 253
 254                 domain-idle-states {
 255                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 256                                 compatible = "domain-idle-state";
 257                                 idle-state-name = "cluster-power-collapse";
 258                                 arm,psci-suspend-param = <0x4100c344>;
 259                                 entry-latency-us = <3263>;
 260                                 exit-latency-us = <6562>;
 261                                 min-residency-us = <9987>;
 262                                 local-timer-stop;
 263                         };
 264                 };
 265         };
 266
 267         firmware {
 268                 scm: scm {
 269                         compatible = "qcom,scm-sm8350", "qcom,scm";
 270                         #reset-cells = <1>;
 271                 };
 272         };
 273
 274         memory@80000000 {
 275                 device_type = "memory";
 276                 /* We expect the bootloader to fill in the size */
 277                 reg = <0x0 0x80000000 0x0 0x0>;
 278         };
 279
 280         pmu {
 281                 compatible = "arm,armv8-pmuv3";
 282                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 283         };
 284
 285         psci {
 286                 compatible = "arm,psci-1.0";
 287                 method = "smc";
 288
 289                 CPU_PD0: cpu0 {
 290                         #power-domain-cells = <0>;
 291                         power-domains = <&CLUSTER_PD>;
 292                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 293                 };
 294
 295                 CPU_PD1: cpu1 {
 296                         #power-domain-cells = <0>;
 297                         power-domains = <&CLUSTER_PD>;
 298                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 299                 };
 300
 301                 CPU_PD2: cpu2 {
 302                         #power-domain-cells = <0>;
 303                         power-domains = <&CLUSTER_PD>;
 304                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 305                 };
 306
 307                 CPU_PD3: cpu3 {
 308                         #power-domain-cells = <0>;
 309                         power-domains = <&CLUSTER_PD>;
 310                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 311                 };
 312
 313                 CPU_PD4: cpu4 {
 314                         #power-domain-cells = <0>;
 315                         power-domains = <&CLUSTER_PD>;
 316                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 317                 };
 318
 319                 CPU_PD5: cpu5 {
 320                         #power-domain-cells = <0>;
 321                         power-domains = <&CLUSTER_PD>;
 322                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 323                 };
 324
 325                 CPU_PD6: cpu6 {
 326                         #power-domain-cells = <0>;
 327                         power-domains = <&CLUSTER_PD>;
 328                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 329                 };
 330
 331                 CPU_PD7: cpu7 {
 332                         #power-domain-cells = <0>;
 333                         power-domains = <&CLUSTER_PD>;
 334                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 335                 };
 336
 337                 CLUSTER_PD: cpu-cluster0 {
 338                         #power-domain-cells = <0>;
 339                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 340                 };
 341         };
 342
 343         reserved_memory: reserved-memory {
 344                 #address-cells = <2>;
 345                 #size-cells = <2>;
 346                 ranges;
 347
 348                 hyp_mem: memory@80000000 {
 349                         reg = <0x0 0x80000000 0x0 0x600000>;
 350                         no-map;
 351                 };
 352
 353                 xbl_aop_mem: memory@80700000 {
 354                         no-map;
 355                         reg = <0x0 0x80700000 0x0 0x160000>;
 356                 };
 357
 358                 cmd_db: memory@80860000 {
 359                         compatible = "qcom,cmd-db";
 360                         reg = <0x0 0x80860000 0x0 0x20000>;
 361                         no-map;
 362                 };
 363
 364                 reserved_xbl_uefi_log: memory@80880000 {
 365                         reg = <0x0 0x80880000 0x0 0x14000>;
 366                         no-map;
 367                 };
 368
 369                 smem_mem: memory@80900000 {
 370                         reg = <0x0 0x80900000 0x0 0x200000>;
 371                         no-map;
 372                 };
 373
 374                 cpucp_fw_mem: memory@80b00000 {
 375                         reg = <0x0 0x80b00000 0x0 0x100000>;
 376                         no-map;
 377                 };
 378
 379                 cdsp_secure_heap: memory@80c00000 {
 380                         reg = <0x0 0x80c00000 0x0 0x4600000>;
 381                         no-map;
 382                 };
 383
 384                 pil_camera_mem: mmeory@85200000 {
 385                         reg = <0x0 0x85200000 0x0 0x500000>;
 386                         no-map;
 387                 };
 388
 389                 pil_video_mem: memory@85700000 {
 390                         reg = <0x0 0x85700000 0x0 0x500000>;
 391                         no-map;
 392                 };
 393
 394                 pil_cvp_mem: memory@85c00000 {
 395                         reg = <0x0 0x85c00000 0x0 0x500000>;
 396                         no-map;
 397                 };
 398
 399                 pil_adsp_mem: memory@86100000 {
 400                         reg = <0x0 0x86100000 0x0 0x2100000>;
 401                         no-map;
 402                 };
 403
 404                 pil_slpi_mem: memory@88200000 {
 405                         reg = <0x0 0x88200000 0x0 0x1500000>;
 406                         no-map;
 407                 };
 408
 409                 pil_cdsp_mem: memory@89700000 {
 410                         reg = <0x0 0x89700000 0x0 0x1e00000>;
 411                         no-map;
 412                 };
 413
 414                 pil_ipa_fw_mem: memory@8b500000 {
 415                         reg = <0x0 0x8b500000 0x0 0x10000>;
 416                         no-map;
 417                 };
 418
 419                 pil_ipa_gsi_mem: memory@8b510000 {
 420                         reg = <0x0 0x8b510000 0x0 0xa000>;
 421                         no-map;
 422                 };
 423
 424                 pil_gpu_mem: memory@8b51a000 {
 425                         reg = <0x0 0x8b51a000 0x0 0x2000>;
 426                         no-map;
 427                 };
 428
 429                 pil_spss_mem: memory@8b600000 {
 430                         reg = <0x0 0x8b600000 0x0 0x100000>;
 431                         no-map;
 432                 };
 433
 434                 pil_modem_mem: memory@8b800000 {
 435                         reg = <0x0 0x8b800000 0x0 0x10000000>;
 436                         no-map;
 437                 };
 438
 439                 rmtfs_mem: memory@9b800000 {
 440                         compatible = "qcom,rmtfs-mem";
 441                         reg = <0x0 0x9b800000 0x0 0x280000>;
 442                         no-map;
 443
 444                         qcom,client-id = <1>;
 445                         qcom,vmid = <15>;
 446                 };
 447
 448                 hyp_reserved_mem: memory@d0000000 {
 449                         reg = <0x0 0xd0000000 0x0 0x800000>;
 450                         no-map;
 451                 };
 452
 453                 pil_trustedvm_mem: memory@d0800000 {
 454                         reg = <0x0 0xd0800000 0x0 0x76f7000>;
 455                         no-map;
 456                 };
 457
 458                 qrtr_shbuf: memory@d7ef7000 {
 459                         reg = <0x0 0xd7ef7000 0x0 0x9000>;
 460                         no-map;
 461                 };
 462
 463                 chan0_shbuf: memory@d7f00000 {
 464                         reg = <0x0 0xd7f00000 0x0 0x80000>;
 465                         no-map;
 466                 };
 467
 468                 chan1_shbuf: memory@d7f80000 {
 469                         reg = <0x0 0xd7f80000 0x0 0x80000>;
 470                         no-map;
 471                 };
 472
 473                 removed_mem: memory@d8800000 {
 474                         reg = <0x0 0xd8800000 0x0 0x6800000>;
 475                         no-map;
 476                 };
 477         };
 478
 479         smem: qcom,smem {
 480                 compatible = "qcom,smem";
 481                 memory-region = <&smem_mem>;
 482                 hwlocks = <&tcsr_mutex 3>;
 483         };
 484
 485         smp2p-adsp {
 486                 compatible = "qcom,smp2p";
 487                 qcom,smem = <443>, <429>;
 488                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 489                                              IPCC_MPROC_SIGNAL_SMP2P
 490                                              IRQ_TYPE_EDGE_RISING>;
 491                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 492                                 IPCC_MPROC_SIGNAL_SMP2P>;
 493
 494                 qcom,local-pid = <0>;
 495                 qcom,remote-pid = <2>;
 496
 497                 smp2p_adsp_out: master-kernel {
 498                         qcom,entry-name = "master-kernel";
 499                         #qcom,smem-state-cells = <1>;
 500                 };
 501
 502                 smp2p_adsp_in: slave-kernel {
 503                         qcom,entry-name = "slave-kernel";
 504                         interrupt-controller;
 505                         #interrupt-cells = <2>;
 506                 };
 507         };
 508
 509         smp2p-cdsp {
 510                 compatible = "qcom,smp2p";
 511                 qcom,smem = <94>, <432>;
 512                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 513                                              IPCC_MPROC_SIGNAL_SMP2P
 514                                              IRQ_TYPE_EDGE_RISING>;
 515                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 516                                 IPCC_MPROC_SIGNAL_SMP2P>;
 517
 518                 qcom,local-pid = <0>;
 519                 qcom,remote-pid = <5>;
 520
 521                 smp2p_cdsp_out: master-kernel {
 522                         qcom,entry-name = "master-kernel";
 523                         #qcom,smem-state-cells = <1>;
 524                 };
 525
 526                 smp2p_cdsp_in: slave-kernel {
 527                         qcom,entry-name = "slave-kernel";
 528                         interrupt-controller;
 529                         #interrupt-cells = <2>;
 530                 };
 531         };
 532
 533         smp2p-modem {
 534                 compatible = "qcom,smp2p";
 535                 qcom,smem = <435>, <428>;
 536                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 537                                              IPCC_MPROC_SIGNAL_SMP2P
 538                                              IRQ_TYPE_EDGE_RISING>;
 539                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 540                                 IPCC_MPROC_SIGNAL_SMP2P>;
 541
 542                 qcom,local-pid = <0>;
 543                 qcom,remote-pid = <1>;
 544
 545                 smp2p_modem_out: master-kernel {
 546                         qcom,entry-name = "master-kernel";
 547                         #qcom,smem-state-cells = <1>;
 548                 };
 549
 550                 smp2p_modem_in: slave-kernel {
 551                         qcom,entry-name = "slave-kernel";
 552                         interrupt-controller;
 553                         #interrupt-cells = <2>;
 554                 };
 555
 556                 ipa_smp2p_out: ipa-ap-to-modem {
 557                         qcom,entry-name = "ipa";
 558                         #qcom,smem-state-cells = <1>;
 559                 };
 560
 561                 ipa_smp2p_in: ipa-modem-to-ap {
 562                         qcom,entry-name = "ipa";
 563                         interrupt-controller;
 564                         #interrupt-cells = <2>;
 565                 };
 566         };
 567
 568         smp2p-slpi {
 569                 compatible = "qcom,smp2p";
 570                 qcom,smem = <481>, <430>;
 571                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 572                                              IPCC_MPROC_SIGNAL_SMP2P
 573                                              IRQ_TYPE_EDGE_RISING>;
 574                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 575                                 IPCC_MPROC_SIGNAL_SMP2P>;
 576
 577                 qcom,local-pid = <0>;
 578                 qcom,remote-pid = <3>;
 579
 580                 smp2p_slpi_out: master-kernel {
 581                         qcom,entry-name = "master-kernel";
 582                         #qcom,smem-state-cells = <1>;
 583                 };
 584
 585                 smp2p_slpi_in: slave-kernel {
 586                         qcom,entry-name = "slave-kernel";
 587                         interrupt-controller;
 588                         #interrupt-cells = <2>;
 589                 };
 590         };
 591
 592         soc: soc@0 {
 593                 #address-cells = <2>;
 594                 #size-cells = <2>;
 595                 ranges = <0 0 0 0 0x10 0>;
 596                 dma-ranges = <0 0 0 0 0x10 0>;
 597                 compatible = "simple-bus";
 598
 599                 gcc: clock-controller@100000 {
 600                         compatible = "qcom,gcc-sm8350";
 601                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 602                         #clock-cells = <1>;
 603                         #reset-cells = <1>;
 604                         #power-domain-cells = <1>;
 605                         clock-names = "bi_tcxo",
 606                                       "sleep_clk",
 607                                       "pcie_0_pipe_clk",
 608                                       "pcie_1_pipe_clk",
 609                                       "ufs_card_rx_symbol_0_clk",
 610                                       "ufs_card_rx_symbol_1_clk",
 611                                       "ufs_card_tx_symbol_0_clk",
 612                                       "ufs_phy_rx_symbol_0_clk",
 613                                       "ufs_phy_rx_symbol_1_clk",
 614                                       "ufs_phy_tx_symbol_0_clk",
 615                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk",
 616                                       "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
 617                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 618                                  <&sleep_clk>,
 619                                  <0>,
 620                                  <0>,
 621                                  <0>,
 622                                  <0>,
 623                                  <0>,
 624                                  <&ufs_phy_rx_symbol_0_clk>,
 625                                  <&ufs_phy_rx_symbol_1_clk>,
 626                                  <&ufs_phy_tx_symbol_0_clk>,
 627                                  <0>,
 628                                  <0>;
 629                 };
 630
 631                 ipcc: mailbox@408000 {
 632                         compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
 633                         reg = <0 0x00408000 0 0x1000>;
 634                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 635                         interrupt-controller;
 636                         #interrupt-cells = <3>;
 637                         #mbox-cells = <2>;
 638                 };
 639
 640                 qup_opp_table_100mhz: qup-100mhz-opp-table {
 641                         compatible = "operating-points-v2";
 642
 643                         opp-50000000 {
 644                                 opp-hz = /bits/ 64 <50000000>;
 645                                 required-opps = <&rpmhpd_opp_min_svs>;
 646                         };
 647
 648                         opp-75000000 {
 649                                 opp-hz = /bits/ 64 <75000000>;
 650                                 required-opps = <&rpmhpd_opp_low_svs>;
 651                         };
 652
 653                         opp-100000000 {
 654                                 opp-hz = /bits/ 64 <100000000>;
 655                                 required-opps = <&rpmhpd_opp_svs>;
 656                         };
 657                 };
 658
 659                 qup_opp_table_120mhz: qup-120mhz-opp-table {
 660                         compatible = "operating-points-v2";
 661
 662                         opp-50000000 {
 663                                 opp-hz = /bits/ 64 <50000000>;
 664                                 required-opps = <&rpmhpd_opp_min_svs>;
 665                         };
 666
 667                         opp-75000000 {
 668                                 opp-hz = /bits/ 64 <75000000>;
 669                                 required-opps = <&rpmhpd_opp_low_svs>;
 670                         };
 671
 672                         opp-120000000 {
 673                                 opp-hz = /bits/ 64 <120000000>;
 674                                 required-opps = <&rpmhpd_opp_svs>;
 675                         };
 676                 };
 677
 678                 qupv3_id_2: geniqup@8c0000 {
 679                         compatible = "qcom,geni-se-qup";
 680                         reg = <0x0 0x008c0000 0x0 0x6000>;
 681                         clock-names = "m-ahb", "s-ahb";
 682                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 683                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 684                         iommus = <&apps_smmu 0x5e3 0x0>;
 685                         #address-cells = <2>;
 686                         #size-cells = <2>;
 687                         ranges;
 688                         status = "disabled";
 689
 690                         i2c14: i2c@880000 {
 691                                 compatible = "qcom,geni-i2c";
 692                                 reg = <0 0x00880000 0 0x4000>;
 693                                 clock-names = "se";
 694                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 695                                 pinctrl-names = "default";
 696                                 pinctrl-0 = <&qup_i2c14_default>;
 697                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 698                                 #address-cells = <1>;
 699                                 #size-cells = <0>;
 700                                 status = "disabled";
 701                         };
 702
 703                         spi14: spi@880000 {
 704                                 compatible = "qcom,geni-spi";
 705                                 reg = <0 0x00880000 0 0x4000>;
 706                                 clock-names = "se";
 707                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 708                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 709                                 power-domains = <&rpmhpd SM8350_CX>;
 710                                 operating-points-v2 = <&qup_opp_table_120mhz>;
 711                                 #address-cells = <1>;
 712                                 #size-cells = <0>;
 713                                 status = "disabled";
 714                         };
 715
 716                         i2c15: i2c@884000 {
 717                                 compatible = "qcom,geni-i2c";
 718                                 reg = <0 0x00884000 0 0x4000>;
 719                                 clock-names = "se";
 720                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 721                                 pinctrl-names = "default";
 722                                 pinctrl-0 = <&qup_i2c15_default>;
 723                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 724                                 #address-cells = <1>;
 725                                 #size-cells = <0>;
 726                                 status = "disabled";
 727                         };
 728
 729                         spi15: spi@884000 {
 730                                 compatible = "qcom,geni-spi";
 731                                 reg = <0 0x00884000 0 0x4000>;
 732                                 clock-names = "se";
 733                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 734                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 735                                 power-domains = <&rpmhpd SM8350_CX>;
 736                                 operating-points-v2 = <&qup_opp_table_120mhz>;
 737                                 #address-cells = <1>;
 738                                 #size-cells = <0>;
 739                                 status = "disabled";
 740                         };
 741
 742                         i2c16: i2c@888000 {
 743                                 compatible = "qcom,geni-i2c";
 744                                 reg = <0 0x00888000 0 0x4000>;
 745                                 clock-names = "se";
 746                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 747                                 pinctrl-names = "default";
 748                                 pinctrl-0 = <&qup_i2c16_default>;
 749                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 750                                 #address-cells = <1>;
 751                                 #size-cells = <0>;
 752                                 status = "disabled";
 753                         };
 754
 755                         spi16: spi@888000 {
 756                                 compatible = "qcom,geni-spi";
 757                                 reg = <0 0x00888000 0 0x4000>;
 758                                 clock-names = "se";
 759                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 760                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 761                                 power-domains = <&rpmhpd SM8350_CX>;
 762                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 763                                 #address-cells = <1>;
 764                                 #size-cells = <0>;
 765                                 status = "disabled";
 766                         };
 767
 768                         i2c17: i2c@88c000 {
 769                                 compatible = "qcom,geni-i2c";
 770                                 reg = <0 0x0088c000 0 0x4000>;
 771                                 clock-names = "se";
 772                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 773                                 pinctrl-names = "default";
 774                                 pinctrl-0 = <&qup_i2c17_default>;
 775                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 776                                 #address-cells = <1>;
 777                                 #size-cells = <0>;
 778                                 status = "disabled";
 779                         };
 780
 781                         spi17: spi@88c000 {
 782                                 compatible = "qcom,geni-spi";
 783                                 reg = <0 0x0088c000 0 0x4000>;
 784                                 clock-names = "se";
 785                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 786                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 787                                 power-domains = <&rpmhpd SM8350_CX>;
 788                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 789                                 #address-cells = <1>;
 790                                 #size-cells = <0>;
 791                                 status = "disabled";
 792                         };
 793
 794                         /* QUP no. 18 seems to be strictly SPI/UART-only */
 795
 796                         spi18: spi@890000 {
 797                                 compatible = "qcom,geni-spi";
 798                                 reg = <0 0x00890000 0 0x4000>;
 799                                 clock-names = "se";
 800                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 801                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 802                                 power-domains = <&rpmhpd SM8350_CX>;
 803                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 804                                 #address-cells = <1>;
 805                                 #size-cells = <0>;
 806                                 status = "disabled";
 807                         };
 808
 809                         uart18: serial@890000 {
 810                                 compatible = "qcom,geni-uart";
 811                                 reg = <0 0x00890000 0 0x4000>;
 812                                 clock-names = "se";
 813                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 814                                 pinctrl-names = "default";
 815                                 pinctrl-0 = <&qup_uart18_default>;
 816                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 817                                 power-domains = <&rpmhpd SM8350_CX>;
 818                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 819                                 status = "disabled";
 820                         };
 821
 822                         i2c19: i2c@894000 {
 823                                 compatible = "qcom,geni-i2c";
 824                                 reg = <0 0x00894000 0 0x4000>;
 825                                 clock-names = "se";
 826                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 827                                 pinctrl-names = "default";
 828                                 pinctrl-0 = <&qup_i2c19_default>;
 829                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 830                                 #address-cells = <1>;
 831                                 #size-cells = <0>;
 832                                 status = "disabled";
 833                         };
 834
 835                         spi19: spi@894000 {
 836                                 compatible = "qcom,geni-spi";
 837                                 reg = <0 0x00894000 0 0x4000>;
 838                                 clock-names = "se";
 839                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 840                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 841                                 power-domains = <&rpmhpd SM8350_CX>;
 842                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 843                                 #address-cells = <1>;
 844                                 #size-cells = <0>;
 845                                 status = "disabled";
 846                         };
 847                 };
 848
 849                 qupv3_id_0: geniqup@9c0000 {
 850                         compatible = "qcom,geni-se-qup";
 851                         reg = <0x0 0x009c0000 0x0 0x6000>;
 852                         clock-names = "m-ahb", "s-ahb";
 853                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 854                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 855                         iommus = <&apps_smmu 0x5a3 0>;
 856                         #address-cells = <2>;
 857                         #size-cells = <2>;
 858                         ranges;
 859                         status = "disabled";
 860
 861                         i2c0: i2c@980000 {
 862                                 compatible = "qcom,geni-i2c";
 863                                 reg = <0 0x00980000 0 0x4000>;
 864                                 clock-names = "se";
 865                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 866                                 pinctrl-names = "default";
 867                                 pinctrl-0 = <&qup_i2c0_default>;
 868                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 869                                 #address-cells = <1>;
 870                                 #size-cells = <0>;
 871                                 status = "disabled";
 872                         };
 873
 874                         spi0: spi@980000 {
 875                                 compatible = "qcom,geni-spi";
 876                                 reg = <0 0x00980000 0 0x4000>;
 877                                 clock-names = "se";
 878                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 879                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 880                                 power-domains = <&rpmhpd SM8350_CX>;
 881                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 882                                 #address-cells = <1>;
 883                                 #size-cells = <0>;
 884                                 status = "disabled";
 885                         };
 886
 887                         i2c1: i2c@984000 {
 888                                 compatible = "qcom,geni-i2c";
 889                                 reg = <0 0x00984000 0 0x4000>;
 890                                 clock-names = "se";
 891                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 892                                 pinctrl-names = "default";
 893                                 pinctrl-0 = <&qup_i2c1_default>;
 894                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 895                                 #address-cells = <1>;
 896                                 #size-cells = <0>;
 897                                 status = "disabled";
 898                         };
 899
 900                         spi1: spi@984000 {
 901                                 compatible = "qcom,geni-spi";
 902                                 reg = <0 0x00984000 0 0x4000>;
 903                                 clock-names = "se";
 904                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 905                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 906                                 power-domains = <&rpmhpd SM8350_CX>;
 907                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 908                                 #address-cells = <1>;
 909                                 #size-cells = <0>;
 910                                 status = "disabled";
 911                         };
 912
 913                         i2c2: i2c@988000 {
 914                                 compatible = "qcom,geni-i2c";
 915                                 reg = <0 0x00988000 0 0x4000>;
 916                                 clock-names = "se";
 917                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 918                                 pinctrl-names = "default";
 919                                 pinctrl-0 = <&qup_i2c2_default>;
 920                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 921                                 #address-cells = <1>;
 922                                 #size-cells = <0>;
 923                                 status = "disabled";
 924                         };
 925
 926                         spi2: spi@988000 {
 927                                 compatible = "qcom,geni-spi";
 928                                 reg = <0 0x00988000 0 0x4000>;
 929                                 clock-names = "se";
 930                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 931                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 932                                 power-domains = <&rpmhpd SM8350_CX>;
 933                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 934                                 #address-cells = <1>;
 935                                 #size-cells = <0>;
 936                                 status = "disabled";
 937                         };
 938
 939                         uart2: serial@98c000 {
 940                                 compatible = "qcom,geni-debug-uart";
 941                                 reg = <0 0x0098c000 0 0x4000>;
 942                                 clock-names = "se";
 943                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 944                                 pinctrl-names = "default";
 945                                 pinctrl-0 = <&qup_uart3_default_state>;
 946                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 947                                 power-domains = <&rpmhpd SM8350_CX>;
 948                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 949                                 #address-cells = <1>;
 950                                 #size-cells = <0>;
 951                                 status = "disabled";
 952                         };
 953
 954                         /* QUP no. 3 seems to be strictly SPI-only */
 955
 956                         spi3: spi@98c000 {
 957                                 compatible = "qcom,geni-spi";
 958                                 reg = <0 0x0098c000 0 0x4000>;
 959                                 clock-names = "se";
 960                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 961                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 962                                 power-domains = <&rpmhpd SM8350_CX>;
 963                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 964                                 #address-cells = <1>;
 965                                 #size-cells = <0>;
 966                                 status = "disabled";
 967                         };
 968
 969                         i2c4: i2c@990000 {
 970                                 compatible = "qcom,geni-i2c";
 971                                 reg = <0 0x00990000 0 0x4000>;
 972                                 clock-names = "se";
 973                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 974                                 pinctrl-names = "default";
 975                                 pinctrl-0 = <&qup_i2c4_default>;
 976                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 977                                 #address-cells = <1>;
 978                                 #size-cells = <0>;
 979                                 status = "disabled";
 980                         };
 981
 982                         spi4: spi@990000 {
 983                                 compatible = "qcom,geni-spi";
 984                                 reg = <0 0x00990000 0 0x4000>;
 985                                 clock-names = "se";
 986                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 987                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 988                                 power-domains = <&rpmhpd SM8350_CX>;
 989                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 990                                 #address-cells = <1>;
 991                                 #size-cells = <0>;
 992                                 status = "disabled";
 993                         };
 994
 995                         i2c5: i2c@994000 {
 996                                 compatible = "qcom,geni-i2c";
 997                                 reg = <0 0x00994000 0 0x4000>;
 998                                 clock-names = "se";
 999                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1000                                 pinctrl-names = "default";
1001                                 pinctrl-0 = <&qup_i2c5_default>;
1002                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1003                                 #address-cells = <1>;
1004                                 #size-cells = <0>;
1005                                 status = "disabled";
1006                         };
1007
1008                         spi5: spi@994000 {
1009                                 compatible = "qcom,geni-spi";
1010                                 reg = <0 0x00994000 0 0x4000>;
1011                                 clock-names = "se";
1012                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1013                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1014                                 power-domains = <&rpmhpd SM8350_CX>;
1015                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1016                                 #address-cells = <1>;
1017                                 #size-cells = <0>;
1018                                 status = "disabled";
1019                         };
1020
1021                         i2c6: i2c@998000 {
1022                                 compatible = "qcom,geni-i2c";
1023                                 reg = <0 0x00998000 0 0x4000>;
1024                                 clock-names = "se";
1025                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1026                                 pinctrl-names = "default";
1027                                 pinctrl-0 = <&qup_i2c6_default>;
1028                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1029                                 #address-cells = <1>;
1030                                 #size-cells = <0>;
1031                                 status = "disabled";
1032                         };
1033
1034                         spi6: spi@998000 {
1035                                 compatible = "qcom,geni-spi";
1036                                 reg = <0 0x00998000 0 0x4000>;
1037                                 clock-names = "se";
1038                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1039                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1040                                 power-domains = <&rpmhpd SM8350_CX>;
1041                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1042                                 #address-cells = <1>;
1043                                 #size-cells = <0>;
1044                                 status = "disabled";
1045                         };
1046
1047                         uart6: serial@998000 {
1048                                 compatible = "qcom,geni-uart";
1049                                 reg = <0 0x00998000 0 0x4000>;
1050                                 clock-names = "se";
1051                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1052                                 pinctrl-names = "default";
1053                                 pinctrl-0 = <&qup_uart6_default>;
1054                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1055                                 power-domains = <&rpmhpd SM8350_CX>;
1056                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1057                                 status = "disabled";
1058                         };
1059
1060                         i2c7: i2c@99c000 {
1061                                 compatible = "qcom,geni-i2c";
1062                                 reg = <0 0x0099c000 0 0x4000>;
1063                                 clock-names = "se";
1064                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1065                                 pinctrl-names = "default";
1066                                 pinctrl-0 = <&qup_i2c7_default>;
1067                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1068                                 #address-cells = <1>;
1069                                 #size-cells = <0>;
1070                                 status = "disabled";
1071                         };
1072
1073                         spi7: spi@99c000 {
1074                                 compatible = "qcom,geni-spi";
1075                                 reg = <0 0x0099c000 0 0x4000>;
1076                                 clock-names = "se";
1077                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1078                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1079                                 power-domains = <&rpmhpd SM8350_CX>;
1080                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1081                                 #address-cells = <1>;
1082                                 #size-cells = <0>;
1083                                 status = "disabled";
1084                         };
1085                 };
1086
1087                 qupv3_id_1: geniqup@ac0000 {
1088                         compatible = "qcom,geni-se-qup";
1089                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1090                         clock-names = "m-ahb", "s-ahb";
1091                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1092                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1093                         iommus = <&apps_smmu 0x43 0>;
1094                         #address-cells = <2>;
1095                         #size-cells = <2>;
1096                         ranges;
1097                         status = "disabled";
1098
1099                         i2c8: i2c@a80000 {
1100                                 compatible = "qcom,geni-i2c";
1101                                 reg = <0 0x00a80000 0 0x4000>;
1102                                 clock-names = "se";
1103                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1104                                 pinctrl-names = "default";
1105                                 pinctrl-0 = <&qup_i2c8_default>;
1106                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1107                                 #address-cells = <1>;
1108                                 #size-cells = <0>;
1109                                 status = "disabled";
1110                         };
1111
1112                         spi8: spi@a80000 {
1113                                 compatible = "qcom,geni-spi";
1114                                 reg = <0 0x00a80000 0 0x4000>;
1115                                 clock-names = "se";
1116                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1117                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1118                                 power-domains = <&rpmhpd SM8350_CX>;
1119                                 operating-points-v2 = <&qup_opp_table_120mhz>;
1120                                 #address-cells = <1>;
1121                                 #size-cells = <0>;
1122                                 status = "disabled";
1123                         };
1124
1125                         i2c9: i2c@a84000 {
1126                                 compatible = "qcom,geni-i2c";
1127                                 reg = <0 0x00a84000 0 0x4000>;
1128                                 clock-names = "se";
1129                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1130                                 pinctrl-names = "default";
1131                                 pinctrl-0 = <&qup_i2c9_default>;
1132                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1133                                 #address-cells = <1>;
1134                                 #size-cells = <0>;
1135                                 status = "disabled";
1136                         };
1137
1138                         spi9: spi@a84000 {
1139                                 compatible = "qcom,geni-spi";
1140                                 reg = <0 0x00a84000 0 0x4000>;
1141                                 clock-names = "se";
1142                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1143                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1144                                 power-domains = <&rpmhpd SM8350_CX>;
1145                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1146                                 #address-cells = <1>;
1147                                 #size-cells = <0>;
1148                                 status = "disabled";
1149                         };
1150
1151                         i2c10: i2c@a88000 {
1152                                 compatible = "qcom,geni-i2c";
1153                                 reg = <0 0x00a88000 0 0x4000>;
1154                                 clock-names = "se";
1155                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1156                                 pinctrl-names = "default";
1157                                 pinctrl-0 = <&qup_i2c10_default>;
1158                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1159                                 #address-cells = <1>;
1160                                 #size-cells = <0>;
1161                                 status = "disabled";
1162                         };
1163
1164                         spi10: spi@a88000 {
1165                                 compatible = "qcom,geni-spi";
1166                                 reg = <0 0x00a88000 0 0x4000>;
1167                                 clock-names = "se";
1168                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1169                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1170                                 power-domains = <&rpmhpd SM8350_CX>;
1171                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1172                                 #address-cells = <1>;
1173                                 #size-cells = <0>;
1174                                 status = "disabled";
1175                         };
1176
1177                         i2c11: i2c@a8c000 {
1178                                 compatible = "qcom,geni-i2c";
1179                                 reg = <0 0x00a8c000 0 0x4000>;
1180                                 clock-names = "se";
1181                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1182                                 pinctrl-names = "default";
1183                                 pinctrl-0 = <&qup_i2c11_default>;
1184                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1185                                 #address-cells = <1>;
1186                                 #size-cells = <0>;
1187                                 status = "disabled";
1188                         };
1189
1190                         spi11: spi@a8c000 {
1191                                 compatible = "qcom,geni-spi";
1192                                 reg = <0 0x00a8c000 0 0x4000>;
1193                                 clock-names = "se";
1194                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1195                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1196                                 power-domains = <&rpmhpd SM8350_CX>;
1197                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1198                                 #address-cells = <1>;
1199                                 #size-cells = <0>;
1200                                 status = "disabled";
1201                         };
1202
1203                         i2c12: i2c@a90000 {
1204                                 compatible = "qcom,geni-i2c";
1205                                 reg = <0 0x00a90000 0 0x4000>;
1206                                 clock-names = "se";
1207                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1208                                 pinctrl-names = "default";
1209                                 pinctrl-0 = <&qup_i2c12_default>;
1210                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1211                                 #address-cells = <1>;
1212                                 #size-cells = <0>;
1213                                 status = "disabled";
1214                         };
1215
1216                         spi12: spi@a90000 {
1217                                 compatible = "qcom,geni-spi";
1218                                 reg = <0 0x00a90000 0 0x4000>;
1219                                 clock-names = "se";
1220                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1221                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1222                                 power-domains = <&rpmhpd SM8350_CX>;
1223                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1224                                 #address-cells = <1>;
1225                                 #size-cells = <0>;
1226                                 status = "disabled";
1227                         };
1228
1229                         i2c13: i2c@a94000 {
1230                                 compatible = "qcom,geni-i2c";
1231                                 reg = <0 0x00a94000 0 0x4000>;
1232                                 clock-names = "se";
1233                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1234                                 pinctrl-names = "default";
1235                                 pinctrl-0 = <&qup_i2c13_default>;
1236                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1237                                 #address-cells = <1>;
1238                                 #size-cells = <0>;
1239                                 status = "disabled";
1240                         };
1241
1242                         spi13: spi@a94000 {
1243                                 compatible = "qcom,geni-spi";
1244                                 reg = <0 0x00a94000 0 0x4000>;
1245                                 clock-names = "se";
1246                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1247                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1248                                 power-domains = <&rpmhpd SM8350_CX>;
1249                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1250                                 #address-cells = <1>;
1251                                 #size-cells = <0>;
1252                                 status = "disabled";
1253                         };
1254                 };
1255
1256                 apps_smmu: iommu@15000000 {
1257                         compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
1258                         reg = <0 0x15000000 0 0x100000>;
1259                         #iommu-cells = <2>;
1260                         #global-interrupts = <2>;
1261                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1262                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1263                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1264                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1265                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1266                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1267                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1268                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1269                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1270                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1271                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1272                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1273                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1274                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1275                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1276                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1277                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1278                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1279                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1280                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1281                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1282                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1283                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1284                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1285                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1286                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1287                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1288                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1289                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1290                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1291                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1292                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1293                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1294                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1295                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1296                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1297                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1298                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1299                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1300                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1301                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1302                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1303                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1304                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1305                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1306                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1307                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1308                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1309                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1310                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1311                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1312                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1313                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1314                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1315                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1316                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1317                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1318                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1319                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1320                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1321                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1322                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1323                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1324                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1325                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1326                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1327                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1328                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1329                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1330                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1331                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1332                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1333                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1334                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1335                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1336                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1337                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1338                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1339                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1340                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1341                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1342                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1343                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1344                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1345                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1346                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1347                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1348                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1349                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1350                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
1351                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
1352                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
1353                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
1354                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
1355                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
1356                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
1357                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
1358                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
1359                 };
1360
1361                 config_noc: interconnect@1500000 {
1362                         compatible = "qcom,sm8350-config-noc";
1363                         reg = <0 0x01500000 0 0xa580>;
1364                         #interconnect-cells = <1>;
1365                         qcom,bcm-voters = <&apps_bcm_voter>;
1366                 };
1367
1368                 mc_virt: interconnect@1580000 {
1369                         compatible = "qcom,sm8350-mc-virt";
1370                         reg = <0 0x01580000 0 0x1000>;
1371                         #interconnect-cells = <1>;
1372                         qcom,bcm-voters = <&apps_bcm_voter>;
1373                 };
1374
1375                 system_noc: interconnect@1680000 {
1376                         compatible = "qcom,sm8350-system-noc";
1377                         reg = <0 0x01680000 0 0x1c200>;
1378                         #interconnect-cells = <1>;
1379                         qcom,bcm-voters = <&apps_bcm_voter>;
1380                 };
1381
1382                 aggre1_noc: interconnect@16e0000 {
1383                         compatible = "qcom,sm8350-aggre1-noc";
1384                         reg = <0 0x016e0000 0 0x1f180>;
1385                         #interconnect-cells = <1>;
1386                         qcom,bcm-voters = <&apps_bcm_voter>;
1387                 };
1388
1389                 aggre2_noc: interconnect@1700000 {
1390                         compatible = "qcom,sm8350-aggre2-noc";
1391                         reg = <0 0x01700000 0 0x33000>;
1392                         #interconnect-cells = <1>;
1393                         qcom,bcm-voters = <&apps_bcm_voter>;
1394                 };
1395
1396                 mmss_noc: interconnect@1740000 {
1397                         compatible = "qcom,sm8350-mmss-noc";
1398                         reg = <0 0x01740000 0 0x1f080>;
1399                         #interconnect-cells = <1>;
1400                         qcom,bcm-voters = <&apps_bcm_voter>;
1401                 };
1402
1403                 lpass_ag_noc: interconnect@3c40000 {
1404                         compatible = "qcom,sm8350-lpass-ag-noc";
1405                         reg = <0 0x03c40000 0 0xf080>;
1406                         #interconnect-cells = <1>;
1407                         qcom,bcm-voters = <&apps_bcm_voter>;
1408                 };
1409
1410                 compute_noc: interconnect@a0c0000{
1411                         compatible = "qcom,sm8350-compute-noc";
1412                         reg = <0 0x0a0c0000 0 0xa180>;
1413                         #interconnect-cells = <1>;
1414                         qcom,bcm-voters = <&apps_bcm_voter>;
1415                 };
1416
1417                 ipa: ipa@1e40000 {
1418                         compatible = "qcom,sm8350-ipa";
1419
1420                         iommus = <&apps_smmu 0x5c0 0x0>,
1421                                  <&apps_smmu 0x5c2 0x0>;
1422                         reg = <0 0x1e40000 0 0x8000>,
1423                               <0 0x1e50000 0 0x4b20>,
1424                               <0 0x1e04000 0 0x23000>;
1425                         reg-names = "ipa-reg",
1426                                     "ipa-shared",
1427                                     "gsi";
1428
1429                         interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1430                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1431                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1432                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1433                         interrupt-names = "ipa",
1434                                           "gsi",
1435                                           "ipa-clock-query",
1436                                           "ipa-setup-ready";
1437
1438                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1439                         clock-names = "core";
1440
1441                         interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
1442                                         <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
1443                         interconnect-names = "memory",
1444                                              "config";
1445
1446                         qcom,qmp = <&aoss_qmp>;
1447
1448                         qcom,smem-states = <&ipa_smp2p_out 0>,
1449                                            <&ipa_smp2p_out 1>;
1450                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1451                                                 "ipa-clock-enabled";
1452
1453                         status = "disabled";
1454                 };
1455
1456                 tcsr_mutex: hwlock@1f40000 {
1457                         compatible = "qcom,tcsr-mutex";
1458                         reg = <0x0 0x01f40000 0x0 0x40000>;
1459                         #hwlock-cells = <1>;
1460                 };
1461
1462                 mpss: remoteproc@4080000 {
1463                         compatible = "qcom,sm8350-mpss-pas";
1464                         reg = <0x0 0x04080000 0x0 0x4040>;
1465
1466                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1467                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1468                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1469                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1470                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1471                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1472                         interrupt-names = "wdog", "fatal", "ready", "handover",
1473                                           "stop-ack", "shutdown-ack";
1474
1475                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1476                         clock-names = "xo";
1477
1478                         power-domains = <&rpmhpd 0>,
1479                                         <&rpmhpd 12>;
1480                         power-domain-names = "cx", "mss";
1481
1482                         interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
1483
1484                         memory-region = <&pil_modem_mem>;
1485
1486                         qcom,qmp = <&aoss_qmp>;
1487
1488                         qcom,smem-states = <&smp2p_modem_out 0>;
1489                         qcom,smem-state-names = "stop";
1490
1491                         status = "disabled";
1492
1493                         glink-edge {
1494                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1495                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1496                                                              IRQ_TYPE_EDGE_RISING>;
1497                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
1498                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1499                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1500                                 label = "modem";
1501                                 qcom,remote-pid = <1>;
1502                         };
1503                 };
1504
1505                 pdc: interrupt-controller@b220000 {
1506                         compatible = "qcom,sm8350-pdc", "qcom,pdc";
1507                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1508                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,   <55 306 4>,
1509                                           <59 312 3>, <62 374 2>,  <64 434 2>,   <66 438 3>,
1510                                           <69 86 1>,  <70 520 54>, <124 609 31>, <155 63 1>,
1511                                           <156 716 12>;
1512                         #interrupt-cells = <2>;
1513                         interrupt-parent = <&intc>;
1514                         interrupt-controller;
1515                 };
1516
1517                 tsens0: thermal-sensor@c263000 {
1518                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1519                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
1520                               <0 0x0c222000 0 0x8>; /* SROT */
1521                         #qcom,sensors = <15>;
1522                         interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1523                                      <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
1524                         interrupt-names = "uplow", "critical";
1525                         #thermal-sensor-cells = <1>;
1526                 };
1527
1528                 tsens1: thermal-sensor@c265000 {
1529                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1530                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
1531                               <0 0x0c223000 0 0x8>; /* SROT */
1532                         #qcom,sensors = <14>;
1533                         interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1534                                      <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
1535                         interrupt-names = "uplow", "critical";
1536                         #thermal-sensor-cells = <1>;
1537                 };
1538
1539                 aoss_qmp: power-controller@c300000 {
1540                         compatible = "qcom,sm8350-aoss-qmp";
1541                         reg = <0 0x0c300000 0 0x400>;
1542                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1543                                                      IRQ_TYPE_EDGE_RISING>;
1544                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1545
1546                         #clock-cells = <0>;
1547                 };
1548
1549                 sram@c3f0000 {
1550                         compatible = "qcom,rpmh-stats";
1551                         reg = <0 0x0c3f0000 0 0x400>;
1552                 };
1553
1554                 spmi_bus: spmi@c440000 {
1555                         compatible = "qcom,spmi-pmic-arb";
1556                         reg = <0x0 0xc440000 0x0 0x1100>,
1557                               <0x0 0xc600000 0x0 0x2000000>,
1558                               <0x0 0xe600000 0x0 0x100000>,
1559                               <0x0 0xe700000 0x0 0xa0000>,
1560                               <0x0 0xc40a000 0x0 0x26000>;
1561                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1562                         interrupt-names = "periph_irq";
1563                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1564                         qcom,ee = <0>;
1565                         qcom,channel = <0>;
1566                         #address-cells = <2>;
1567                         #size-cells = <0>;
1568                         interrupt-controller;
1569                         #interrupt-cells = <4>;
1570                 };
1571
1572                 tlmm: pinctrl@f100000 {
1573                         compatible = "qcom,sm8350-tlmm";
1574                         reg = <0 0x0f100000 0 0x300000>;
1575                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1576                         gpio-controller;
1577                         #gpio-cells = <2>;
1578                         interrupt-controller;
1579                         #interrupt-cells = <2>;
1580                         gpio-ranges = <&tlmm 0 0 204>;
1581                         wakeup-parent = <&pdc>;
1582
1583                         qup_uart3_default_state: qup-uart3-default-state {
1584                                 rx {
1585                                         pins = "gpio18";
1586                                         function = "qup3";
1587                                 };
1588                                 tx {
1589                                         pins = "gpio19";
1590                                         function = "qup3";
1591                                 };
1592                         };
1593
1594                         qup_uart6_default: qup-uart6-default {
1595                                 pins = "gpio30", "gpio31";
1596                                 function = "qup6";
1597                                 drive-strength = <2>;
1598                                 bias-disable;
1599                         };
1600
1601                         qup_uart18_default: qup-uart18-default {
1602                                 pins = "gpio58", "gpio59";
1603                                 function = "qup18";
1604                                 drive-strength = <2>;
1605                                 bias-disable;
1606                         };
1607
1608                         qup_i2c0_default: qup-i2c0-default {
1609                                 pins = "gpio4", "gpio5";
1610                                 function = "qup0";
1611                                 drive-strength = <2>;
1612                                 bias-pull-up;
1613                         };
1614
1615                         qup_i2c1_default: qup-i2c1-default {
1616                                 pins = "gpio8", "gpio9";
1617                                 function = "qup1";
1618                                 drive-strength = <2>;
1619                                 bias-pull-up;
1620                         };
1621
1622                         qup_i2c2_default: qup-i2c2-default {
1623                                 pins = "gpio12", "gpio13";
1624                                 function = "qup2";
1625                                 drive-strength = <2>;
1626                                 bias-pull-up;
1627                         };
1628
1629                         qup_i2c4_default: qup-i2c4-default {
1630                                 pins = "gpio20", "gpio21";
1631                                 function = "qup4";
1632                                 drive-strength = <2>;
1633                                 bias-pull-up;
1634                         };
1635
1636                         qup_i2c5_default: qup-i2c5-default {
1637                                 pins = "gpio24", "gpio25";
1638                                 function = "qup5";
1639                                 drive-strength = <2>;
1640                                 bias-pull-up;
1641                         };
1642
1643                         qup_i2c6_default: qup-i2c6-default {
1644                                 pins = "gpio28", "gpio29";
1645                                 function = "qup6";
1646                                 drive-strength = <2>;
1647                                 bias-pull-up;
1648                         };
1649
1650                         qup_i2c7_default: qup-i2c7-default {
1651                                 pins = "gpio32", "gpio33";
1652                                 function = "qup7";
1653                                 drive-strength = <2>;
1654                                 bias-disable;
1655                         };
1656
1657                         qup_i2c8_default: qup-i2c8-default {
1658                                 pins = "gpio36", "gpio37";
1659                                 function = "qup8";
1660                                 drive-strength = <2>;
1661                                 bias-pull-up;
1662                         };
1663
1664                         qup_i2c9_default: qup-i2c9-default {
1665                                 pins = "gpio40", "gpio41";
1666                                 function = "qup9";
1667                                 drive-strength = <2>;
1668                                 bias-pull-up;
1669                         };
1670
1671                         qup_i2c10_default: qup-i2c10-default {
1672                                 pins = "gpio44", "gpio45";
1673                                 function = "qup10";
1674                                 drive-strength = <2>;
1675                                 bias-pull-up;
1676                         };
1677
1678                         qup_i2c11_default: qup-i2c11-default {
1679                                 pins = "gpio48", "gpio49";
1680                                 function = "qup11";
1681                                 drive-strength = <2>;
1682                                 bias-pull-up;
1683                         };
1684
1685                         qup_i2c12_default: qup-i2c12-default {
1686                                 pins = "gpio52", "gpio53";
1687                                 function = "qup12";
1688                                 drive-strength = <2>;
1689                                 bias-pull-up;
1690                         };
1691
1692                         qup_i2c13_default: qup-i2c13-default {
1693                                 pins = "gpio0", "gpio1";
1694                                 function = "qup13";
1695                                 drive-strength = <2>;
1696                                 bias-pull-up;
1697                         };
1698
1699                         qup_i2c14_default: qup-i2c14-default {
1700                                 pins = "gpio56", "gpio57";
1701                                 function = "qup14";
1702                                 drive-strength = <2>;
1703                                 bias-disable;
1704                         };
1705
1706                         qup_i2c15_default: qup-i2c15-default {
1707                                 pins = "gpio60", "gpio61";
1708                                 function = "qup15";
1709                                 drive-strength = <2>;
1710                                 bias-disable;
1711                         };
1712
1713                         qup_i2c16_default: qup-i2c16-default {
1714                                 pins = "gpio64", "gpio65";
1715                                 function = "qup16";
1716                                 drive-strength = <2>;
1717                                 bias-disable;
1718                         };
1719
1720                         qup_i2c17_default: qup-i2c17-default {
1721                                 pins = "gpio72", "gpio73";
1722                                 function = "qup17";
1723                                 drive-strength = <2>;
1724                                 bias-disable;
1725                         };
1726
1727                         qup_i2c19_default: qup-i2c19-default {
1728                                 pins = "gpio76", "gpio77";
1729                                 function = "qup19";
1730                                 drive-strength = <2>;
1731                                 bias-disable;
1732                         };
1733                 };
1734
1735                 rng: rng@10d3000 {
1736                         compatible = "qcom,prng-ee";
1737                         reg = <0 0x010d3000 0 0x1000>;
1738                         clocks = <&rpmhcc RPMH_HWKM_CLK>;
1739                         clock-names = "core";
1740                 };
1741
1742                 intc: interrupt-controller@17a00000 {
1743                         compatible = "arm,gic-v3";
1744                         #interrupt-cells = <3>;
1745                         interrupt-controller;
1746                         #redistributor-regions = <1>;
1747                         redistributor-stride = <0 0x20000>;
1748                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
1749                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
1750                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1751                 };
1752
1753                 timer@17c20000 {
1754                         compatible = "arm,armv7-timer-mem";
1755                         #address-cells = <2>;
1756                         #size-cells = <2>;
1757                         ranges;
1758                         reg = <0x0 0x17c20000 0x0 0x1000>;
1759                         clock-frequency = <19200000>;
1760
1761                         frame@17c21000 {
1762                                 frame-number = <0>;
1763                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1764                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1765                                 reg = <0x0 0x17c21000 0x0 0x1000>,
1766                                       <0x0 0x17c22000 0x0 0x1000>;
1767                         };
1768
1769                         frame@17c23000 {
1770                                 frame-number = <1>;
1771                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1772                                 reg = <0x0 0x17c23000 0x0 0x1000>;
1773                                 status = "disabled";
1774                         };
1775
1776                         frame@17c25000 {
1777                                 frame-number = <2>;
1778                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1779                                 reg = <0x0 0x17c25000 0x0 0x1000>;
1780                                 status = "disabled";
1781                         };
1782
1783                         frame@17c27000 {
1784                                 frame-number = <3>;
1785                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1786                                 reg = <0x0 0x17c27000 0x0 0x1000>;
1787                                 status = "disabled";
1788                         };
1789
1790                         frame@17c29000 {
1791                                 frame-number = <4>;
1792                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1793                                 reg = <0x0 0x17c29000 0x0 0x1000>;
1794                                 status = "disabled";
1795                         };
1796
1797                         frame@17c2b000 {
1798                                 frame-number = <5>;
1799                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1800                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
1801                                 status = "disabled";
1802                         };
1803
1804                         frame@17c2d000 {
1805                                 frame-number = <6>;
1806                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1807                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
1808                                 status = "disabled";
1809                         };
1810                 };
1811
1812                 apps_rsc: rsc@18200000 {
1813                         label = "apps_rsc";
1814                         compatible = "qcom,rpmh-rsc";
1815                         reg = <0x0 0x18200000 0x0 0x10000>,
1816                                 <0x0 0x18210000 0x0 0x10000>,
1817                                 <0x0 0x18220000 0x0 0x10000>;
1818                         reg-names = "drv-0", "drv-1", "drv-2";
1819                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1820                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1821                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1822                         qcom,tcs-offset = <0xd00>;
1823                         qcom,drv-id = <2>;
1824                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
1825                                           <WAKE_TCS    3>, <CONTROL_TCS 0>;
1826
1827                         rpmhcc: clock-controller {
1828                                 compatible = "qcom,sm8350-rpmh-clk";
1829                                 #clock-cells = <1>;
1830                                 clock-names = "xo";
1831                                 clocks = <&xo_board>;
1832                         };
1833
1834                         rpmhpd: power-controller {
1835                                 compatible = "qcom,sm8350-rpmhpd";
1836                                 #power-domain-cells = <1>;
1837                                 operating-points-v2 = <&rpmhpd_opp_table>;
1838
1839                                 rpmhpd_opp_table: opp-table {
1840                                         compatible = "operating-points-v2";
1841
1842                                         rpmhpd_opp_ret: opp1 {
1843                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1844                                         };
1845
1846                                         rpmhpd_opp_min_svs: opp2 {
1847                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1848                                         };
1849
1850                                         rpmhpd_opp_low_svs: opp3 {
1851                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1852                                         };
1853
1854                                         rpmhpd_opp_svs: opp4 {
1855                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1856                                         };
1857
1858                                         rpmhpd_opp_svs_l1: opp5 {
1859                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1860                                         };
1861
1862                                         rpmhpd_opp_nom: opp6 {
1863                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1864                                         };
1865
1866                                         rpmhpd_opp_nom_l1: opp7 {
1867                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1868                                         };
1869
1870                                         rpmhpd_opp_nom_l2: opp8 {
1871                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1872                                         };
1873
1874                                         rpmhpd_opp_turbo: opp9 {
1875                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1876                                         };
1877
1878                                         rpmhpd_opp_turbo_l1: opp10 {
1879                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1880                                         };
1881                                 };
1882                         };
1883
1884                         apps_bcm_voter: bcm_voter {
1885                                 compatible = "qcom,bcm-voter";
1886                         };
1887                 };
1888
1889                 cpufreq_hw: cpufreq@18591000 {
1890                         compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
1891                         reg = <0 0x18591000 0 0x1000>,
1892                               <0 0x18592000 0 0x1000>,
1893                               <0 0x18593000 0 0x1000>;
1894                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
1895
1896                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1897                         clock-names = "xo", "alternate";
1898
1899                         #freq-domain-cells = <1>;
1900                 };
1901
1902                 ufs_mem_hc: ufshc@1d84000 {
1903                         compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
1904                                      "jedec,ufs-2.0";
1905                         reg = <0 0x01d84000 0 0x3000>;
1906                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1907                         phys = <&ufs_mem_phy_lanes>;
1908                         phy-names = "ufsphy";
1909                         lanes-per-direction = <2>;
1910                         #reset-cells = <1>;
1911                         resets = <&gcc GCC_UFS_PHY_BCR>;
1912                         reset-names = "rst";
1913
1914                         power-domains = <&gcc UFS_PHY_GDSC>;
1915
1916                         iommus = <&apps_smmu 0xe0 0x0>;
1917
1918                         clock-names =
1919                                 "ref_clk",
1920                                 "core_clk",
1921                                 "bus_aggr_clk",
1922                                 "iface_clk",
1923                                 "core_clk_unipro",
1924                                 "ref_clk",
1925                                 "tx_lane0_sync_clk",
1926                                 "rx_lane0_sync_clk",
1927                                 "rx_lane1_sync_clk";
1928                         clocks =
1929                                 <&rpmhcc RPMH_CXO_CLK>,
1930                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1931                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1932                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1933                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1934                                 <&rpmhcc RPMH_CXO_CLK>,
1935                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1936                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1937                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1938                         freq-table-hz =
1939                                 <75000000 300000000>,
1940                                 <75000000 300000000>,
1941                                 <0 0>,
1942                                 <0 0>,
1943                                 <75000000 300000000>,
1944                                 <0 0>,
1945                                 <0 0>,
1946                                 <0 0>,
1947                                 <0 0>;
1948                         status = "disabled";
1949                 };
1950
1951                 ufs_mem_phy: phy@1d87000 {
1952                         compatible = "qcom,sm8350-qmp-ufs-phy";
1953                         reg = <0 0x01d87000 0 0xe10>;
1954                         #address-cells = <2>;
1955                         #size-cells = <2>;
1956                         ranges;
1957                         clock-names = "ref",
1958                                       "ref_aux";
1959                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1960                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1961
1962                         resets = <&ufs_mem_hc 0>;
1963                         reset-names = "ufsphy";
1964                         status = "disabled";
1965
1966                         ufs_mem_phy_lanes: phy@1d87400 {
1967                                 reg = <0 0x01d87400 0 0x108>,
1968                                       <0 0x01d87600 0 0x1e0>,
1969                                       <0 0x01d87c00 0 0x1dc>,
1970                                       <0 0x01d87800 0 0x108>,
1971                                       <0 0x01d87a00 0 0x1e0>;
1972                                 #phy-cells = <0>;
1973                                 #clock-cells = <0>;
1974                         };
1975                 };
1976
1977                 slpi: remoteproc@5c00000 {
1978                         compatible = "qcom,sm8350-slpi-pas";
1979                         reg = <0 0x05c00000 0 0x4000>;
1980
1981                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1982                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1983                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1984                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1985                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1986                         interrupt-names = "wdog", "fatal", "ready",
1987                                           "handover", "stop-ack";
1988
1989                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1990                         clock-names = "xo";
1991
1992                         power-domains = <&rpmhpd 4>,
1993                                         <&rpmhpd 5>;
1994                         power-domain-names = "lcx", "lmx";
1995
1996                         memory-region = <&pil_slpi_mem>;
1997
1998                         qcom,qmp = <&aoss_qmp>;
1999
2000                         qcom,smem-states = <&smp2p_slpi_out 0>;
2001                         qcom,smem-state-names = "stop";
2002
2003                         status = "disabled";
2004
2005                         glink-edge {
2006                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2007                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2008                                                              IRQ_TYPE_EDGE_RISING>;
2009                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2010                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2011
2012                                 label = "slpi";
2013                                 qcom,remote-pid = <3>;
2014
2015                                 fastrpc {
2016                                         compatible = "qcom,fastrpc";
2017                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2018                                         label = "sdsp";
2019                                         qcom,non-secure-domain;
2020                                         #address-cells = <1>;
2021                                         #size-cells = <0>;
2022
2023                                         compute-cb@1 {
2024                                                 compatible = "qcom,fastrpc-compute-cb";
2025                                                 reg = <1>;
2026                                                 iommus = <&apps_smmu 0x0541 0x0>;
2027                                         };
2028
2029                                         compute-cb@2 {
2030                                                 compatible = "qcom,fastrpc-compute-cb";
2031                                                 reg = <2>;
2032                                                 iommus = <&apps_smmu 0x0542 0x0>;
2033                                         };
2034
2035                                         compute-cb@3 {
2036                                                 compatible = "qcom,fastrpc-compute-cb";
2037                                                 reg = <3>;
2038                                                 iommus = <&apps_smmu 0x0543 0x0>;
2039                                                 /* note: shared-cb = <4> in downstream */
2040                                         };
2041                                 };
2042                         };
2043                 };
2044
2045                 cdsp: remoteproc@98900000 {
2046                         compatible = "qcom,sm8350-cdsp-pas";
2047                         reg = <0 0x098900000 0 0x1400000>;
2048
2049                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2050                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2051                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2052                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2053                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2054                         interrupt-names = "wdog", "fatal", "ready",
2055                                           "handover", "stop-ack";
2056
2057                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2058                         clock-names = "xo";
2059
2060                         power-domains = <&rpmhpd 0>,
2061                                         <&rpmhpd 10>;
2062                         power-domain-names = "cx", "mxc";
2063
2064                         interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
2065
2066                         memory-region = <&pil_cdsp_mem>;
2067
2068                         qcom,qmp = <&aoss_qmp>;
2069
2070                         qcom,smem-states = <&smp2p_cdsp_out 0>;
2071                         qcom,smem-state-names = "stop";
2072
2073                         status = "disabled";
2074
2075                         glink-edge {
2076                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2077                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2078                                                              IRQ_TYPE_EDGE_RISING>;
2079                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2080                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2081
2082                                 label = "cdsp";
2083                                 qcom,remote-pid = <5>;
2084
2085                                 fastrpc {
2086                                         compatible = "qcom,fastrpc";
2087                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2088                                         label = "cdsp";
2089                                         qcom,non-secure-domain;
2090                                         #address-cells = <1>;
2091                                         #size-cells = <0>;
2092
2093                                         compute-cb@1 {
2094                                                 compatible = "qcom,fastrpc-compute-cb";
2095                                                 reg = <1>;
2096                                                 iommus = <&apps_smmu 0x2161 0x0400>,
2097                                                          <&apps_smmu 0x1181 0x0420>;
2098                                         };
2099
2100                                         compute-cb@2 {
2101                                                 compatible = "qcom,fastrpc-compute-cb";
2102                                                 reg = <2>;
2103                                                 iommus = <&apps_smmu 0x2162 0x0400>,
2104                                                          <&apps_smmu 0x1182 0x0420>;
2105                                         };
2106
2107                                         compute-cb@3 {
2108                                                 compatible = "qcom,fastrpc-compute-cb";
2109                                                 reg = <3>;
2110                                                 iommus = <&apps_smmu 0x2163 0x0400>,
2111                                                          <&apps_smmu 0x1183 0x0420>;
2112                                         };
2113
2114                                         compute-cb@4 {
2115                                                 compatible = "qcom,fastrpc-compute-cb";
2116                                                 reg = <4>;
2117                                                 iommus = <&apps_smmu 0x2164 0x0400>,
2118                                                          <&apps_smmu 0x1184 0x0420>;
2119                                         };
2120
2121                                         compute-cb@5 {
2122                                                 compatible = "qcom,fastrpc-compute-cb";
2123                                                 reg = <5>;
2124                                                 iommus = <&apps_smmu 0x2165 0x0400>,
2125                                                          <&apps_smmu 0x1185 0x0420>;
2126                                         };
2127
2128                                         compute-cb@6 {
2129                                                 compatible = "qcom,fastrpc-compute-cb";
2130                                                 reg = <6>;
2131                                                 iommus = <&apps_smmu 0x2166 0x0400>,
2132                                                          <&apps_smmu 0x1186 0x0420>;
2133                                         };
2134
2135                                         compute-cb@7 {
2136                                                 compatible = "qcom,fastrpc-compute-cb";
2137                                                 reg = <7>;
2138                                                 iommus = <&apps_smmu 0x2167 0x0400>,
2139                                                          <&apps_smmu 0x1187 0x0420>;
2140                                         };
2141
2142                                         compute-cb@8 {
2143                                                 compatible = "qcom,fastrpc-compute-cb";
2144                                                 reg = <8>;
2145                                                 iommus = <&apps_smmu 0x2168 0x0400>,
2146                                                          <&apps_smmu 0x1188 0x0420>;
2147                                         };
2148
2149                                         /* note: secure cb9 in downstream */
2150                                 };
2151                         };
2152                 };
2153
2154                 usb_1_hsphy: phy@88e3000 {
2155                         compatible = "qcom,sm8350-usb-hs-phy",
2156                                      "qcom,usb-snps-hs-7nm-phy";
2157                         reg = <0 0x088e3000 0 0x400>;
2158                         status = "disabled";
2159                         #phy-cells = <0>;
2160
2161                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2162                         clock-names = "ref";
2163
2164                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2165                 };
2166
2167                 usb_2_hsphy: phy@88e4000 {
2168                         compatible = "qcom,sm8250-usb-hs-phy",
2169                                      "qcom,usb-snps-hs-7nm-phy";
2170                         reg = <0 0x088e4000 0 0x400>;
2171                         status = "disabled";
2172                         #phy-cells = <0>;
2173
2174                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2175                         clock-names = "ref";
2176
2177                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2178                 };
2179
2180                 usb_1_qmpphy: phy-wrapper@88e9000 {
2181                         compatible = "qcom,sm8350-qmp-usb3-phy";
2182                         reg = <0 0x088e9000 0 0x200>,
2183                               <0 0x088e8000 0 0x20>;
2184                         status = "disabled";
2185                         #address-cells = <2>;
2186                         #size-cells = <2>;
2187                         ranges;
2188
2189                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2190                                  <&rpmhcc RPMH_CXO_CLK>,
2191                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2192                         clock-names = "aux", "ref_clk_src", "com_aux";
2193
2194                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2195                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2196                         reset-names = "phy", "common";
2197
2198                         usb_1_ssphy: phy@88e9200 {
2199                                 reg = <0 0x088e9200 0 0x200>,
2200                                       <0 0x088e9400 0 0x200>,
2201                                       <0 0x088e9c00 0 0x400>,
2202                                       <0 0x088e9600 0 0x200>,
2203                                       <0 0x088e9800 0 0x200>,
2204                                       <0 0x088e9a00 0 0x100>;
2205                                 #phy-cells = <0>;
2206                                 #clock-cells = <1>;
2207                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2208                                 clock-names = "pipe0";
2209                                 clock-output-names = "usb3_phy_pipe_clk_src";
2210                         };
2211                 };
2212
2213                 usb_2_qmpphy: phy-wrapper@88eb000 {
2214                         compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2215                         reg = <0 0x088eb000 0 0x200>;
2216                         status = "disabled";
2217                         #address-cells = <2>;
2218                         #size-cells = <2>;
2219                         ranges;
2220
2221                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2222                                  <&rpmhcc RPMH_CXO_CLK>,
2223                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
2224                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2225                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2226
2227                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2228                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2229                         reset-names = "phy", "common";
2230
2231                         usb_2_ssphy: phy@88ebe00 {
2232                                 reg = <0 0x088ebe00 0 0x200>,
2233                                       <0 0x088ec000 0 0x200>,
2234                                       <0 0x088eb200 0 0x1100>;
2235                                 #phy-cells = <0>;
2236                                 #clock-cells = <1>;
2237                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2238                                 clock-names = "pipe0";
2239                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2240                         };
2241                 };
2242
2243                 dc_noc: interconnect@90c0000 {
2244                         compatible = "qcom,sm8350-dc-noc";
2245                         reg = <0 0x090c0000 0 0x4200>;
2246                         #interconnect-cells = <1>;
2247                         qcom,bcm-voters = <&apps_bcm_voter>;
2248                 };
2249
2250                 gem_noc: interconnect@9100000 {
2251                         compatible = "qcom,sm8350-gem-noc";
2252                         reg = <0 0x09100000 0 0xb4000>;
2253                         #interconnect-cells = <1>;
2254                         qcom,bcm-voters = <&apps_bcm_voter>;
2255                 };
2256
2257                 system-cache-controller@9200000 {
2258                         compatible = "qcom,sm8350-llcc";
2259                         reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2260                         reg-names = "llcc_base", "llcc_broadcast_base";
2261                 };
2262
2263                 usb_1: usb@a6f8800 {
2264                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2265                         reg = <0 0x0a6f8800 0 0x400>;
2266                         status = "disabled";
2267                         #address-cells = <2>;
2268                         #size-cells = <2>;
2269                         ranges;
2270
2271                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2272                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2273                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2274                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2275                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2276                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2277                                       "sleep";
2278
2279                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2280                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2281                         assigned-clock-rates = <19200000>, <200000000>;
2282
2283                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2284                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2285                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2286                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2287                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2288                                           "dm_hs_phy_irq", "ss_phy_irq";
2289
2290                         power-domains = <&gcc USB30_PRIM_GDSC>;
2291
2292                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2293
2294                         usb_1_dwc3: usb@a600000 {
2295                                 compatible = "snps,dwc3";
2296                                 reg = <0 0x0a600000 0 0xcd00>;
2297                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2298                                 iommus = <&apps_smmu 0x0 0x0>;
2299                                 snps,dis_u2_susphy_quirk;
2300                                 snps,dis_enblslpm_quirk;
2301                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2302                                 phy-names = "usb2-phy", "usb3-phy";
2303                         };
2304                 };
2305
2306                 usb_2: usb@a8f8800 {
2307                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2308                         reg = <0 0x0a8f8800 0 0x400>;
2309                         status = "disabled";
2310                         #address-cells = <2>;
2311                         #size-cells = <2>;
2312                         ranges;
2313
2314                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2315                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2316                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2317                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2318                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2319                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
2320                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2321                                       "sleep", "xo";
2322
2323                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2324                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2325                         assigned-clock-rates = <19200000>, <200000000>;
2326
2327                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2328                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2329                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2330                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2331                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2332                                           "dm_hs_phy_irq", "ss_phy_irq";
2333
2334                         power-domains = <&gcc USB30_SEC_GDSC>;
2335
2336                         resets = <&gcc GCC_USB30_SEC_BCR>;
2337
2338                         usb_2_dwc3: usb@a800000 {
2339                                 compatible = "snps,dwc3";
2340                                 reg = <0 0x0a800000 0 0xcd00>;
2341                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2342                                 iommus = <&apps_smmu 0x20 0x0>;
2343                                 snps,dis_u2_susphy_quirk;
2344                                 snps,dis_enblslpm_quirk;
2345                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2346                                 phy-names = "usb2-phy", "usb3-phy";
2347                         };
2348                 };
2349
2350                 adsp: remoteproc@17300000 {
2351                         compatible = "qcom,sm8350-adsp-pas";
2352                         reg = <0 0x17300000 0 0x100>;
2353
2354                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2355                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2356                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2357                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2358                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2359                         interrupt-names = "wdog", "fatal", "ready",
2360                                           "handover", "stop-ack";
2361
2362                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2363                         clock-names = "xo";
2364
2365                         power-domains = <&rpmhpd 4>,
2366                                         <&rpmhpd 5>;
2367                         power-domain-names = "lcx", "lmx";
2368
2369                         memory-region = <&pil_adsp_mem>;
2370
2371                         qcom,qmp = <&aoss_qmp>;
2372
2373                         qcom,smem-states = <&smp2p_adsp_out 0>;
2374                         qcom,smem-state-names = "stop";
2375
2376                         status = "disabled";
2377
2378                         glink-edge {
2379                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2380                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2381                                                              IRQ_TYPE_EDGE_RISING>;
2382                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2383                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2384
2385                                 label = "lpass";
2386                                 qcom,remote-pid = <2>;
2387
2388                                 fastrpc {
2389                                         compatible = "qcom,fastrpc";
2390                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2391                                         label = "adsp";
2392                                         qcom,non-secure-domain;
2393                                         #address-cells = <1>;
2394                                         #size-cells = <0>;
2395
2396                                         compute-cb@3 {
2397                                                 compatible = "qcom,fastrpc-compute-cb";
2398                                                 reg = <3>;
2399                                                 iommus = <&apps_smmu 0x1803 0x0>;
2400                                         };
2401
2402                                         compute-cb@4 {
2403                                                 compatible = "qcom,fastrpc-compute-cb";
2404                                                 reg = <4>;
2405                                                 iommus = <&apps_smmu 0x1804 0x0>;
2406                                         };
2407
2408                                         compute-cb@5 {
2409                                                 compatible = "qcom,fastrpc-compute-cb";
2410                                                 reg = <5>;
2411                                                 iommus = <&apps_smmu 0x1805 0x0>;
2412                                         };
2413                                 };
2414                         };
2415                 };
2416         };
2417
2418         thermal_zones: thermal-zones {
2419                 cpu0-thermal {
2420                         polling-delay-passive = <250>;
2421                         polling-delay = <1000>;
2422
2423                         thermal-sensors = <&tsens0 1>;
2424
2425                         trips {
2426                                 cpu0_alert0: trip-point0 {
2427                                         temperature = <90000>;
2428                                         hysteresis = <2000>;
2429                                         type = "passive";
2430                                 };
2431
2432                                 cpu0_alert1: trip-point1 {
2433                                         temperature = <95000>;
2434                                         hysteresis = <2000>;
2435                                         type = "passive";
2436                                 };
2437
2438                                 cpu0_crit: cpu_crit {
2439                                         temperature = <110000>;
2440                                         hysteresis = <1000>;
2441                                         type = "critical";
2442                                 };
2443                         };
2444
2445                         cooling-maps {
2446                                 map0 {
2447                                         trip = <&cpu0_alert0>;
2448                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2449                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2450                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2451                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2452                                 };
2453                                 map1 {
2454                                         trip = <&cpu0_alert1>;
2455                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2456                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2457                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2458                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2459                                 };
2460                         };
2461                 };
2462
2463                 cpu1-thermal {
2464                         polling-delay-passive = <250>;
2465                         polling-delay = <1000>;
2466
2467                         thermal-sensors = <&tsens0 2>;
2468
2469                         trips {
2470                                 cpu1_alert0: trip-point0 {
2471                                         temperature = <90000>;
2472                                         hysteresis = <2000>;
2473                                         type = "passive";
2474                                 };
2475
2476                                 cpu1_alert1: trip-point1 {
2477                                         temperature = <95000>;
2478                                         hysteresis = <2000>;
2479                                         type = "passive";
2480                                 };
2481
2482                                 cpu1_crit: cpu_crit {
2483                                         temperature = <110000>;
2484                                         hysteresis = <1000>;
2485                                         type = "critical";
2486                                 };
2487                         };
2488
2489                         cooling-maps {
2490                                 map0 {
2491                                         trip = <&cpu1_alert0>;
2492                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2493                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2494                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2495                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2496                                 };
2497                                 map1 {
2498                                         trip = <&cpu1_alert1>;
2499                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2500                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2501                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2502                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2503                                 };
2504                         };
2505                 };
2506
2507                 cpu2-thermal {
2508                         polling-delay-passive = <250>;
2509                         polling-delay = <1000>;
2510
2511                         thermal-sensors = <&tsens0 3>;
2512
2513                         trips {
2514                                 cpu2_alert0: trip-point0 {
2515                                         temperature = <90000>;
2516                                         hysteresis = <2000>;
2517                                         type = "passive";
2518                                 };
2519
2520                                 cpu2_alert1: trip-point1 {
2521                                         temperature = <95000>;
2522                                         hysteresis = <2000>;
2523                                         type = "passive";
2524                                 };
2525
2526                                 cpu2_crit: cpu_crit {
2527                                         temperature = <110000>;
2528                                         hysteresis = <1000>;
2529                                         type = "critical";
2530                                 };
2531                         };
2532
2533                         cooling-maps {
2534                                 map0 {
2535                                         trip = <&cpu2_alert0>;
2536                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2537                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2538                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2539                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2540                                 };
2541                                 map1 {
2542                                         trip = <&cpu2_alert1>;
2543                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2544                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2545                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2546                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2547                                 };
2548                         };
2549                 };
2550
2551                 cpu3-thermal {
2552                         polling-delay-passive = <250>;
2553                         polling-delay = <1000>;
2554
2555                         thermal-sensors = <&tsens0 4>;
2556
2557                         trips {
2558                                 cpu3_alert0: trip-point0 {
2559                                         temperature = <90000>;
2560                                         hysteresis = <2000>;
2561                                         type = "passive";
2562                                 };
2563
2564                                 cpu3_alert1: trip-point1 {
2565                                         temperature = <95000>;
2566                                         hysteresis = <2000>;
2567                                         type = "passive";
2568                                 };
2569
2570                                 cpu3_crit: cpu_crit {
2571                                         temperature = <110000>;
2572                                         hysteresis = <1000>;
2573                                         type = "critical";
2574                                 };
2575                         };
2576
2577                         cooling-maps {
2578                                 map0 {
2579                                         trip = <&cpu3_alert0>;
2580                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2581                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2582                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2583                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2584                                 };
2585                                 map1 {
2586                                         trip = <&cpu3_alert1>;
2587                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2588                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2589                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2590                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2591                                 };
2592                         };
2593                 };
2594
2595                 cpu4-top-thermal {
2596                         polling-delay-passive = <250>;
2597                         polling-delay = <1000>;
2598
2599                         thermal-sensors = <&tsens0 7>;
2600
2601                         trips {
2602                                 cpu4_top_alert0: trip-point0 {
2603                                         temperature = <90000>;
2604                                         hysteresis = <2000>;
2605                                         type = "passive";
2606                                 };
2607
2608                                 cpu4_top_alert1: trip-point1 {
2609                                         temperature = <95000>;
2610                                         hysteresis = <2000>;
2611                                         type = "passive";
2612                                 };
2613
2614                                 cpu4_top_crit: cpu_crit {
2615                                         temperature = <110000>;
2616                                         hysteresis = <1000>;
2617                                         type = "critical";
2618                                 };
2619                         };
2620
2621                         cooling-maps {
2622                                 map0 {
2623                                         trip = <&cpu4_top_alert0>;
2624                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2625                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2626                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2627                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2628                                 };
2629                                 map1 {
2630                                         trip = <&cpu4_top_alert1>;
2631                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2632                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2633                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2634                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2635                                 };
2636                         };
2637                 };
2638
2639                 cpu5-top-thermal {
2640                         polling-delay-passive = <250>;
2641                         polling-delay = <1000>;
2642
2643                         thermal-sensors = <&tsens0 8>;
2644
2645                         trips {
2646                                 cpu5_top_alert0: trip-point0 {
2647                                         temperature = <90000>;
2648                                         hysteresis = <2000>;
2649                                         type = "passive";
2650                                 };
2651
2652                                 cpu5_top_alert1: trip-point1 {
2653                                         temperature = <95000>;
2654                                         hysteresis = <2000>;
2655                                         type = "passive";
2656                                 };
2657
2658                                 cpu5_top_crit: cpu_crit {
2659                                         temperature = <110000>;
2660                                         hysteresis = <1000>;
2661                                         type = "critical";
2662                                 };
2663                         };
2664
2665                         cooling-maps {
2666                                 map0 {
2667                                         trip = <&cpu5_top_alert0>;
2668                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2669                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2670                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2671                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2672                                 };
2673                                 map1 {
2674                                         trip = <&cpu5_top_alert1>;
2675                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2676                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2677                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2678                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2679                                 };
2680                         };
2681                 };
2682
2683                 cpu6-top-thermal {
2684                         polling-delay-passive = <250>;
2685                         polling-delay = <1000>;
2686
2687                         thermal-sensors = <&tsens0 9>;
2688
2689                         trips {
2690                                 cpu6_top_alert0: trip-point0 {
2691                                         temperature = <90000>;
2692                                         hysteresis = <2000>;
2693                                         type = "passive";
2694                                 };
2695
2696                                 cpu6_top_alert1: trip-point1 {
2697                                         temperature = <95000>;
2698                                         hysteresis = <2000>;
2699                                         type = "passive";
2700                                 };
2701
2702                                 cpu6_top_crit: cpu_crit {
2703                                         temperature = <110000>;
2704                                         hysteresis = <1000>;
2705                                         type = "critical";
2706                                 };
2707                         };
2708
2709                         cooling-maps {
2710                                 map0 {
2711                                         trip = <&cpu6_top_alert0>;
2712                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2713                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2714                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2715                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2716                                 };
2717                                 map1 {
2718                                         trip = <&cpu6_top_alert1>;
2719                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2720                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2721                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2722                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2723                                 };
2724                         };
2725                 };
2726
2727                 cpu7-top-thermal {
2728                         polling-delay-passive = <250>;
2729                         polling-delay = <1000>;
2730
2731                         thermal-sensors = <&tsens0 10>;
2732
2733                         trips {
2734                                 cpu7_top_alert0: trip-point0 {
2735                                         temperature = <90000>;
2736                                         hysteresis = <2000>;
2737                                         type = "passive";
2738                                 };
2739
2740                                 cpu7_top_alert1: trip-point1 {
2741                                         temperature = <95000>;
2742                                         hysteresis = <2000>;
2743                                         type = "passive";
2744                                 };
2745
2746                                 cpu7_top_crit: cpu_crit {
2747                                         temperature = <110000>;
2748                                         hysteresis = <1000>;
2749                                         type = "critical";
2750                                 };
2751                         };
2752
2753                         cooling-maps {
2754                                 map0 {
2755                                         trip = <&cpu7_top_alert0>;
2756                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2757                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2758                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2759                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2760                                 };
2761                                 map1 {
2762                                         trip = <&cpu7_top_alert1>;
2763                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2764                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2765                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2766                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2767                                 };
2768                         };
2769                 };
2770
2771                 cpu4-bottom-thermal {
2772                         polling-delay-passive = <250>;
2773                         polling-delay = <1000>;
2774
2775                         thermal-sensors = <&tsens0 11>;
2776
2777                         trips {
2778                                 cpu4_bottom_alert0: trip-point0 {
2779                                         temperature = <90000>;
2780                                         hysteresis = <2000>;
2781                                         type = "passive";
2782                                 };
2783
2784                                 cpu4_bottom_alert1: trip-point1 {
2785                                         temperature = <95000>;
2786                                         hysteresis = <2000>;
2787                                         type = "passive";
2788                                 };
2789
2790                                 cpu4_bottom_crit: cpu_crit {
2791                                         temperature = <110000>;
2792                                         hysteresis = <1000>;
2793                                         type = "critical";
2794                                 };
2795                         };
2796
2797                         cooling-maps {
2798                                 map0 {
2799                                         trip = <&cpu4_bottom_alert0>;
2800                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2801                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2802                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2803                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2804                                 };
2805                                 map1 {
2806                                         trip = <&cpu4_bottom_alert1>;
2807                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2808                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2809                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2810                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2811                                 };
2812                         };
2813                 };
2814
2815                 cpu5-bottom-thermal {
2816                         polling-delay-passive = <250>;
2817                         polling-delay = <1000>;
2818
2819                         thermal-sensors = <&tsens0 12>;
2820
2821                         trips {
2822                                 cpu5_bottom_alert0: trip-point0 {
2823                                         temperature = <90000>;
2824                                         hysteresis = <2000>;
2825                                         type = "passive";
2826                                 };
2827
2828                                 cpu5_bottom_alert1: trip-point1 {
2829                                         temperature = <95000>;
2830                                         hysteresis = <2000>;
2831                                         type = "passive";
2832                                 };
2833
2834                                 cpu5_bottom_crit: cpu_crit {
2835                                         temperature = <110000>;
2836                                         hysteresis = <1000>;
2837                                         type = "critical";
2838                                 };
2839                         };
2840
2841                         cooling-maps {
2842                                 map0 {
2843                                         trip = <&cpu5_bottom_alert0>;
2844                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2845                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2846                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2847                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2848                                 };
2849                                 map1 {
2850                                         trip = <&cpu5_bottom_alert1>;
2851                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2852                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2853                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2854                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2855                                 };
2856                         };
2857                 };
2858
2859                 cpu6-bottom-thermal {
2860                         polling-delay-passive = <250>;
2861                         polling-delay = <1000>;
2862
2863                         thermal-sensors = <&tsens0 13>;
2864
2865                         trips {
2866                                 cpu6_bottom_alert0: trip-point0 {
2867                                         temperature = <90000>;
2868                                         hysteresis = <2000>;
2869                                         type = "passive";
2870                                 };
2871
2872                                 cpu6_bottom_alert1: trip-point1 {
2873                                         temperature = <95000>;
2874                                         hysteresis = <2000>;
2875                                         type = "passive";
2876                                 };
2877
2878                                 cpu6_bottom_crit: cpu_crit {
2879                                         temperature = <110000>;
2880                                         hysteresis = <1000>;
2881                                         type = "critical";
2882                                 };
2883                         };
2884
2885                         cooling-maps {
2886                                 map0 {
2887                                         trip = <&cpu6_bottom_alert0>;
2888                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2889                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2890                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2891                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2892                                 };
2893                                 map1 {
2894                                         trip = <&cpu6_bottom_alert1>;
2895                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2896                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2897                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2898                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2899                                 };
2900                         };
2901                 };
2902
2903                 cpu7-bottom-thermal {
2904                         polling-delay-passive = <250>;
2905                         polling-delay = <1000>;
2906
2907                         thermal-sensors = <&tsens0 14>;
2908
2909                         trips {
2910                                 cpu7_bottom_alert0: trip-point0 {
2911                                         temperature = <90000>;
2912                                         hysteresis = <2000>;
2913                                         type = "passive";
2914                                 };
2915
2916                                 cpu7_bottom_alert1: trip-point1 {
2917                                         temperature = <95000>;
2918                                         hysteresis = <2000>;
2919                                         type = "passive";
2920                                 };
2921
2922                                 cpu7_bottom_crit: cpu_crit {
2923                                         temperature = <110000>;
2924                                         hysteresis = <1000>;
2925                                         type = "critical";
2926                                 };
2927                         };
2928
2929                         cooling-maps {
2930                                 map0 {
2931                                         trip = <&cpu7_bottom_alert0>;
2932                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2933                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2934                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2935                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2936                                 };
2937                                 map1 {
2938                                         trip = <&cpu7_bottom_alert1>;
2939                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2940                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2941                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2942                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2943                                 };
2944                         };
2945                 };
2946
2947                 aoss0-thermal {
2948                         polling-delay-passive = <250>;
2949                         polling-delay = <1000>;
2950
2951                         thermal-sensors = <&tsens0 0>;
2952
2953                         trips {
2954                                 aoss0_alert0: trip-point0 {
2955                                         temperature = <90000>;
2956                                         hysteresis = <2000>;
2957                                         type = "hot";
2958                                 };
2959                         };
2960                 };
2961
2962                 cluster0-thermal {
2963                         polling-delay-passive = <250>;
2964                         polling-delay = <1000>;
2965
2966                         thermal-sensors = <&tsens0 5>;
2967
2968                         trips {
2969                                 cluster0_alert0: trip-point0 {
2970                                         temperature = <90000>;
2971                                         hysteresis = <2000>;
2972                                         type = "hot";
2973                                 };
2974                                 cluster0_crit: cluster0_crit {
2975                                         temperature = <110000>;
2976                                         hysteresis = <2000>;
2977                                         type = "critical";
2978                                 };
2979                         };
2980                 };
2981
2982                 cluster1-thermal {
2983                         polling-delay-passive = <250>;
2984                         polling-delay = <1000>;
2985
2986                         thermal-sensors = <&tsens0 6>;
2987
2988                         trips {
2989                                 cluster1_alert0: trip-point0 {
2990                                         temperature = <90000>;
2991                                         hysteresis = <2000>;
2992                                         type = "hot";
2993                                 };
2994                                 cluster1_crit: cluster1_crit {
2995                                         temperature = <110000>;
2996                                         hysteresis = <2000>;
2997                                         type = "critical";
2998                                 };
2999                         };
3000                 };
3001
3002                 aoss1-thermal {
3003                         polling-delay-passive = <250>;
3004                         polling-delay = <1000>;
3005
3006                         thermal-sensors = <&tsens1 0>;
3007
3008                         trips {
3009                                 aoss1_alert0: trip-point0 {
3010                                         temperature = <90000>;
3011                                         hysteresis = <2000>;
3012                                         type = "hot";
3013                                 };
3014                         };
3015                 };
3016
3017                 gpu-top-thermal {
3018                         polling-delay-passive = <250>;
3019                         polling-delay = <1000>;
3020
3021                         thermal-sensors = <&tsens1 1>;
3022
3023                         trips {
3024                                 gpu1_alert0: trip-point0 {
3025                                         temperature = <90000>;
3026                                         hysteresis = <1000>;
3027                                         type = "hot";
3028                                 };
3029                         };
3030                 };
3031
3032                 gpu-bottom-thermal {
3033                         polling-delay-passive = <250>;
3034                         polling-delay = <1000>;
3035
3036                         thermal-sensors = <&tsens1 2>;
3037
3038                         trips {
3039                                 gpu2_alert0: trip-point0 {
3040                                         temperature = <90000>;
3041                                         hysteresis = <1000>;
3042                                         type = "hot";
3043                                 };
3044                         };
3045                 };
3046
3047                 nspss1-thermal {
3048                         polling-delay-passive = <250>;
3049                         polling-delay = <1000>;
3050
3051                         thermal-sensors = <&tsens1 3>;
3052
3053                         trips {
3054                                 nspss1_alert0: trip-point0 {
3055                                         temperature = <90000>;
3056                                         hysteresis = <1000>;
3057                                         type = "hot";
3058                                 };
3059                         };
3060                 };
3061
3062                 nspss2-thermal {
3063                         polling-delay-passive = <250>;
3064                         polling-delay = <1000>;
3065
3066                         thermal-sensors = <&tsens1 4>;
3067
3068                         trips {
3069                                 nspss2_alert0: trip-point0 {
3070                                         temperature = <90000>;
3071                                         hysteresis = <1000>;
3072                                         type = "hot";
3073                                 };
3074                         };
3075                 };
3076
3077                 nspss3-thermal {
3078                         polling-delay-passive = <250>;
3079                         polling-delay = <1000>;
3080
3081                         thermal-sensors = <&tsens1 5>;
3082
3083                         trips {
3084                                 nspss3_alert0: trip-point0 {
3085                                         temperature = <90000>;
3086                                         hysteresis = <1000>;
3087                                         type = "hot";
3088                                 };
3089                         };
3090                 };
3091
3092                 video-thermal {
3093                         polling-delay-passive = <250>;
3094                         polling-delay = <1000>;
3095
3096                         thermal-sensors = <&tsens1 6>;
3097
3098                         trips {
3099                                 video_alert0: trip-point0 {
3100                                         temperature = <90000>;
3101                                         hysteresis = <2000>;
3102                                         type = "hot";
3103                                 };
3104                         };
3105                 };
3106
3107                 mem-thermal {
3108                         polling-delay-passive = <250>;
3109                         polling-delay = <1000>;
3110
3111                         thermal-sensors = <&tsens1 7>;
3112
3113                         trips {
3114                                 mem_alert0: trip-point0 {
3115                                         temperature = <90000>;
3116                                         hysteresis = <2000>;
3117                                         type = "hot";
3118                                 };
3119                         };
3120                 };
3121
3122                 modem1-top-thermal {
3123                         polling-delay-passive = <250>;
3124                         polling-delay = <1000>;
3125
3126                         thermal-sensors = <&tsens1 8>;
3127
3128                         trips {
3129                                 modem1_alert0: trip-point0 {
3130                                         temperature = <90000>;
3131                                         hysteresis = <2000>;
3132                                         type = "hot";
3133                                 };
3134                         };
3135                 };
3136
3137                 modem2-top-thermal {
3138                         polling-delay-passive = <250>;
3139                         polling-delay = <1000>;
3140
3141                         thermal-sensors = <&tsens1 9>;
3142
3143                         trips {
3144                                 modem2_alert0: trip-point0 {
3145                                         temperature = <90000>;
3146                                         hysteresis = <2000>;
3147                                         type = "hot";
3148                                 };
3149                         };
3150                 };
3151
3152                 modem3-top-thermal {
3153                         polling-delay-passive = <250>;
3154                         polling-delay = <1000>;
3155
3156                         thermal-sensors = <&tsens1 10>;
3157
3158                         trips {
3159                                 modem3_alert0: trip-point0 {
3160                                         temperature = <90000>;
3161                                         hysteresis = <2000>;
3162                                         type = "hot";
3163                                 };
3164                         };
3165                 };
3166
3167                 modem4-top-thermal {
3168                         polling-delay-passive = <250>;
3169                         polling-delay = <1000>;
3170
3171                         thermal-sensors = <&tsens1 11>;
3172
3173                         trips {
3174                                 modem4_alert0: trip-point0 {
3175                                         temperature = <90000>;
3176                                         hysteresis = <2000>;
3177                                         type = "hot";
3178                                 };
3179                         };
3180                 };
3181
3182                 camera-top-thermal {
3183                         polling-delay-passive = <250>;
3184                         polling-delay = <1000>;
3185
3186                         thermal-sensors = <&tsens1 12>;
3187
3188                         trips {
3189                                 camera1_alert0: trip-point0 {
3190                                         temperature = <90000>;
3191                                         hysteresis = <2000>;
3192                                         type = "hot";
3193                                 };
3194                         };
3195                 };
3196
3197                 cam-bottom-thermal {
3198                         polling-delay-passive = <250>;
3199                         polling-delay = <1000>;
3200
3201                         thermal-sensors = <&tsens1 13>;
3202
3203                         trips {
3204                                 camera2_alert0: trip-point0 {
3205                                         temperature = <90000>;
3206                                         hysteresis = <2000>;
3207                                         type = "hot";
3208                                 };
3209                         };
3210                 };
3211         };
3212
3213         timer {
3214                 compatible = "arm,armv8-timer";
3215                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3216                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3217                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3218                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3219         };
3220 };