arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
  12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
  13 #include <dt-bindings/dma/qcom-gpi.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  16 #include <dt-bindings/interconnect/qcom,sm8250.h>
  17 #include <dt-bindings/mailbox/qcom-ipcc.h>
  18 #include <dt-bindings/power/qcom-rpmpd.h>
  19 #include <dt-bindings/power/qcom,rpmhpd.h>
  20 #include <dt-bindings/soc/qcom,apr.h>
  21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  22 #include <dt-bindings/sound/qcom,q6afe.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
  25 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
  26
  27 / {
  28         interrupt-parent = <&intc>;
  29
  30         #address-cells = <2>;
  31         #size-cells = <2>;
  32
  33         aliases {
  34                 i2c0 = &i2c0;
  35                 i2c1 = &i2c1;
  36                 i2c2 = &i2c2;
  37                 i2c3 = &i2c3;
  38                 i2c4 = &i2c4;
  39                 i2c5 = &i2c5;
  40                 i2c6 = &i2c6;
  41                 i2c7 = &i2c7;
  42                 i2c8 = &i2c8;
  43                 i2c9 = &i2c9;
  44                 i2c10 = &i2c10;
  45                 i2c11 = &i2c11;
  46                 i2c12 = &i2c12;
  47                 i2c13 = &i2c13;
  48                 i2c14 = &i2c14;
  49                 i2c15 = &i2c15;
  50                 i2c16 = &i2c16;
  51                 i2c17 = &i2c17;
  52                 i2c18 = &i2c18;
  53                 i2c19 = &i2c19;
  54                 spi0 = &spi0;
  55                 spi1 = &spi1;
  56                 spi2 = &spi2;
  57                 spi3 = &spi3;
  58                 spi4 = &spi4;
  59                 spi5 = &spi5;
  60                 spi6 = &spi6;
  61                 spi7 = &spi7;
  62                 spi8 = &spi8;
  63                 spi9 = &spi9;
  64                 spi10 = &spi10;
  65                 spi11 = &spi11;
  66                 spi12 = &spi12;
  67                 spi13 = &spi13;
  68                 spi14 = &spi14;
  69                 spi15 = &spi15;
  70                 spi16 = &spi16;
  71                 spi17 = &spi17;
  72                 spi18 = &spi18;
  73                 spi19 = &spi19;
  74         };
  75
  76         chosen { };
  77
  78         clocks {
  79                 xo_board: xo-board {
  80                         compatible = "fixed-clock";
  81                         #clock-cells = <0>;
  82                         clock-frequency = <38400000>;
  83                         clock-output-names = "xo_board";
  84                 };
  85
  86                 sleep_clk: sleep-clk {
  87                         compatible = "fixed-clock";
  88                         clock-frequency = <32768>;
  89                         #clock-cells = <0>;
  90                 };
  91         };
  92
  93         cpus {
  94                 #address-cells = <2>;
  95                 #size-cells = <0>;
  96
  97                 CPU0: cpu@0 {
  98                         device_type = "cpu";
  99                         compatible = "qcom,kryo485";
 100                         reg = <0x0 0x0>;
 101                         clocks = <&cpufreq_hw 0>;
 102                         enable-method = "psci";
 103                         capacity-dmips-mhz = <448>;
 104                         dynamic-power-coefficient = <105>;
 105                         next-level-cache = <&L2_0>;
 106                         power-domains = <&CPU_PD0>;
 107                         power-domain-names = "psci";
 108                         qcom,freq-domain = <&cpufreq_hw 0>;
 109                         operating-points-v2 = <&cpu0_opp_table>;
 110                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 111                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 112                         #cooling-cells = <2>;
 113                         L2_0: l2-cache {
 114                                 compatible = "cache";
 115                                 cache-level = <2>;
 116                                 cache-size = <0x20000>;
 117                                 cache-unified;
 118                                 next-level-cache = <&L3_0>;
 119                                 L3_0: l3-cache {
 120                                         compatible = "cache";
 121                                         cache-level = <3>;
 122                                         cache-size = <0x400000>;
 123                                         cache-unified;
 124                                 };
 125                         };
 126                 };
 127
 128                 CPU1: cpu@100 {
 129                         device_type = "cpu";
 130                         compatible = "qcom,kryo485";
 131                         reg = <0x0 0x100>;
 132                         clocks = <&cpufreq_hw 0>;
 133                         enable-method = "psci";
 134                         capacity-dmips-mhz = <448>;
 135                         dynamic-power-coefficient = <105>;
 136                         next-level-cache = <&L2_100>;
 137                         power-domains = <&CPU_PD1>;
 138                         power-domain-names = "psci";
 139                         qcom,freq-domain = <&cpufreq_hw 0>;
 140                         operating-points-v2 = <&cpu0_opp_table>;
 141                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 142                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 143                         #cooling-cells = <2>;
 144                         L2_100: l2-cache {
 145                                 compatible = "cache";
 146                                 cache-level = <2>;
 147                                 cache-size = <0x20000>;
 148                                 cache-unified;
 149                                 next-level-cache = <&L3_0>;
 150                         };
 151                 };
 152
 153                 CPU2: cpu@200 {
 154                         device_type = "cpu";
 155                         compatible = "qcom,kryo485";
 156                         reg = <0x0 0x200>;
 157                         clocks = <&cpufreq_hw 0>;
 158                         enable-method = "psci";
 159                         capacity-dmips-mhz = <448>;
 160                         dynamic-power-coefficient = <105>;
 161                         next-level-cache = <&L2_200>;
 162                         power-domains = <&CPU_PD2>;
 163                         power-domain-names = "psci";
 164                         qcom,freq-domain = <&cpufreq_hw 0>;
 165                         operating-points-v2 = <&cpu0_opp_table>;
 166                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 167                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 168                         #cooling-cells = <2>;
 169                         L2_200: l2-cache {
 170                                 compatible = "cache";
 171                                 cache-level = <2>;
 172                                 cache-size = <0x20000>;
 173                                 cache-unified;
 174                                 next-level-cache = <&L3_0>;
 175                         };
 176                 };
 177
 178                 CPU3: cpu@300 {
 179                         device_type = "cpu";
 180                         compatible = "qcom,kryo485";
 181                         reg = <0x0 0x300>;
 182                         clocks = <&cpufreq_hw 0>;
 183                         enable-method = "psci";
 184                         capacity-dmips-mhz = <448>;
 185                         dynamic-power-coefficient = <105>;
 186                         next-level-cache = <&L2_300>;
 187                         power-domains = <&CPU_PD3>;
 188                         power-domain-names = "psci";
 189                         qcom,freq-domain = <&cpufreq_hw 0>;
 190                         operating-points-v2 = <&cpu0_opp_table>;
 191                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 192                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 193                         #cooling-cells = <2>;
 194                         L2_300: l2-cache {
 195                                 compatible = "cache";
 196                                 cache-level = <2>;
 197                                 cache-size = <0x20000>;
 198                                 cache-unified;
 199                                 next-level-cache = <&L3_0>;
 200                         };
 201                 };
 202
 203                 CPU4: cpu@400 {
 204                         device_type = "cpu";
 205                         compatible = "qcom,kryo485";
 206                         reg = <0x0 0x400>;
 207                         clocks = <&cpufreq_hw 1>;
 208                         enable-method = "psci";
 209                         capacity-dmips-mhz = <1024>;
 210                         dynamic-power-coefficient = <379>;
 211                         next-level-cache = <&L2_400>;
 212                         power-domains = <&CPU_PD4>;
 213                         power-domain-names = "psci";
 214                         qcom,freq-domain = <&cpufreq_hw 1>;
 215                         operating-points-v2 = <&cpu4_opp_table>;
 216                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 217                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 218                         #cooling-cells = <2>;
 219                         L2_400: l2-cache {
 220                                 compatible = "cache";
 221                                 cache-level = <2>;
 222                                 cache-size = <0x40000>;
 223                                 cache-unified;
 224                                 next-level-cache = <&L3_0>;
 225                         };
 226                 };
 227
 228                 CPU5: cpu@500 {
 229                         device_type = "cpu";
 230                         compatible = "qcom,kryo485";
 231                         reg = <0x0 0x500>;
 232                         clocks = <&cpufreq_hw 1>;
 233                         enable-method = "psci";
 234                         capacity-dmips-mhz = <1024>;
 235                         dynamic-power-coefficient = <379>;
 236                         next-level-cache = <&L2_500>;
 237                         power-domains = <&CPU_PD5>;
 238                         power-domain-names = "psci";
 239                         qcom,freq-domain = <&cpufreq_hw 1>;
 240                         operating-points-v2 = <&cpu4_opp_table>;
 241                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 242                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 243                         #cooling-cells = <2>;
 244                         L2_500: l2-cache {
 245                                 compatible = "cache";
 246                                 cache-level = <2>;
 247                                 cache-size = <0x40000>;
 248                                 cache-unified;
 249                                 next-level-cache = <&L3_0>;
 250                         };
 251                 };
 252
 253                 CPU6: cpu@600 {
 254                         device_type = "cpu";
 255                         compatible = "qcom,kryo485";
 256                         reg = <0x0 0x600>;
 257                         clocks = <&cpufreq_hw 1>;
 258                         enable-method = "psci";
 259                         capacity-dmips-mhz = <1024>;
 260                         dynamic-power-coefficient = <379>;
 261                         next-level-cache = <&L2_600>;
 262                         power-domains = <&CPU_PD6>;
 263                         power-domain-names = "psci";
 264                         qcom,freq-domain = <&cpufreq_hw 1>;
 265                         operating-points-v2 = <&cpu4_opp_table>;
 266                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 267                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 268                         #cooling-cells = <2>;
 269                         L2_600: l2-cache {
 270                                 compatible = "cache";
 271                                 cache-level = <2>;
 272                                 cache-size = <0x40000>;
 273                                 cache-unified;
 274                                 next-level-cache = <&L3_0>;
 275                         };
 276                 };
 277
 278                 CPU7: cpu@700 {
 279                         device_type = "cpu";
 280                         compatible = "qcom,kryo485";
 281                         reg = <0x0 0x700>;
 282                         clocks = <&cpufreq_hw 2>;
 283                         enable-method = "psci";
 284                         capacity-dmips-mhz = <1024>;
 285                         dynamic-power-coefficient = <444>;
 286                         next-level-cache = <&L2_700>;
 287                         power-domains = <&CPU_PD7>;
 288                         power-domain-names = "psci";
 289                         qcom,freq-domain = <&cpufreq_hw 2>;
 290                         operating-points-v2 = <&cpu7_opp_table>;
 291                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 292                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 293                         #cooling-cells = <2>;
 294                         L2_700: l2-cache {
 295                                 compatible = "cache";
 296                                 cache-level = <2>;
 297                                 cache-size = <0x80000>;
 298                                 cache-unified;
 299                                 next-level-cache = <&L3_0>;
 300                         };
 301                 };
 302
 303                 cpu-map {
 304                         cluster0 {
 305                                 core0 {
 306                                         cpu = <&CPU0>;
 307                                 };
 308
 309                                 core1 {
 310                                         cpu = <&CPU1>;
 311                                 };
 312
 313                                 core2 {
 314                                         cpu = <&CPU2>;
 315                                 };
 316
 317                                 core3 {
 318                                         cpu = <&CPU3>;
 319                                 };
 320
 321                                 core4 {
 322                                         cpu = <&CPU4>;
 323                                 };
 324
 325                                 core5 {
 326                                         cpu = <&CPU5>;
 327                                 };
 328
 329                                 core6 {
 330                                         cpu = <&CPU6>;
 331                                 };
 332
 333                                 core7 {
 334                                         cpu = <&CPU7>;
 335                                 };
 336                         };
 337                 };
 338
 339                 idle-states {
 340                         entry-method = "psci";
 341
 342                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 343                                 compatible = "arm,idle-state";
 344                                 idle-state-name = "silver-rail-power-collapse";
 345                                 arm,psci-suspend-param = <0x40000004>;
 346                                 entry-latency-us = <360>;
 347                                 exit-latency-us = <531>;
 348                                 min-residency-us = <3934>;
 349                                 local-timer-stop;
 350                         };
 351
 352                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 353                                 compatible = "arm,idle-state";
 354                                 idle-state-name = "gold-rail-power-collapse";
 355                                 arm,psci-suspend-param = <0x40000004>;
 356                                 entry-latency-us = <702>;
 357                                 exit-latency-us = <1061>;
 358                                 min-residency-us = <4488>;
 359                                 local-timer-stop;
 360                         };
 361                 };
 362
 363                 domain-idle-states {
 364                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 365                                 compatible = "domain-idle-state";
 366                                 arm,psci-suspend-param = <0x4100c244>;
 367                                 entry-latency-us = <3264>;
 368                                 exit-latency-us = <6562>;
 369                                 min-residency-us = <9987>;
 370                         };
 371                 };
 372         };
 373
 374         cpu0_opp_table: opp-table-cpu0 {
 375                 compatible = "operating-points-v2";
 376                 opp-shared;
 377
 378                 cpu0_opp1: opp-300000000 {
 379                         opp-hz = /bits/ 64 <300000000>;
 380                         opp-peak-kBps = <800000 9600000>;
 381                 };
 382
 383                 cpu0_opp2: opp-403200000 {
 384                         opp-hz = /bits/ 64 <403200000>;
 385                         opp-peak-kBps = <800000 9600000>;
 386                 };
 387
 388                 cpu0_opp3: opp-518400000 {
 389                         opp-hz = /bits/ 64 <518400000>;
 390                         opp-peak-kBps = <800000 16588800>;
 391                 };
 392
 393                 cpu0_opp4: opp-614400000 {
 394                         opp-hz = /bits/ 64 <614400000>;
 395                         opp-peak-kBps = <800000 16588800>;
 396                 };
 397
 398                 cpu0_opp5: opp-691200000 {
 399                         opp-hz = /bits/ 64 <691200000>;
 400                         opp-peak-kBps = <800000 19660800>;
 401                 };
 402
 403                 cpu0_opp6: opp-787200000 {
 404                         opp-hz = /bits/ 64 <787200000>;
 405                         opp-peak-kBps = <1804000 19660800>;
 406                 };
 407
 408                 cpu0_opp7: opp-883200000 {
 409                         opp-hz = /bits/ 64 <883200000>;
 410                         opp-peak-kBps = <1804000 23347200>;
 411                 };
 412
 413                 cpu0_opp8: opp-979200000 {
 414                         opp-hz = /bits/ 64 <979200000>;
 415                         opp-peak-kBps = <1804000 26419200>;
 416                 };
 417
 418                 cpu0_opp9: opp-1075200000 {
 419                         opp-hz = /bits/ 64 <1075200000>;
 420                         opp-peak-kBps = <1804000 29491200>;
 421                 };
 422
 423                 cpu0_opp10: opp-1171200000 {
 424                         opp-hz = /bits/ 64 <1171200000>;
 425                         opp-peak-kBps = <1804000 32563200>;
 426                 };
 427
 428                 cpu0_opp11: opp-1248000000 {
 429                         opp-hz = /bits/ 64 <1248000000>;
 430                         opp-peak-kBps = <1804000 36249600>;
 431                 };
 432
 433                 cpu0_opp12: opp-1344000000 {
 434                         opp-hz = /bits/ 64 <1344000000>;
 435                         opp-peak-kBps = <2188000 36249600>;
 436                 };
 437
 438                 cpu0_opp13: opp-1420800000 {
 439                         opp-hz = /bits/ 64 <1420800000>;
 440                         opp-peak-kBps = <2188000 39321600>;
 441                 };
 442
 443                 cpu0_opp14: opp-1516800000 {
 444                         opp-hz = /bits/ 64 <1516800000>;
 445                         opp-peak-kBps = <3072000 42393600>;
 446                 };
 447
 448                 cpu0_opp15: opp-1612800000 {
 449                         opp-hz = /bits/ 64 <1612800000>;
 450                         opp-peak-kBps = <3072000 42393600>;
 451                 };
 452
 453                 cpu0_opp16: opp-1708800000 {
 454                         opp-hz = /bits/ 64 <1708800000>;
 455                         opp-peak-kBps = <4068000 42393600>;
 456                 };
 457
 458                 cpu0_opp17: opp-1804800000 {
 459                         opp-hz = /bits/ 64 <1804800000>;
 460                         opp-peak-kBps = <4068000 42393600>;
 461                 };
 462         };
 463
 464         cpu4_opp_table: opp-table-cpu4 {
 465                 compatible = "operating-points-v2";
 466                 opp-shared;
 467
 468                 cpu4_opp1: opp-710400000 {
 469                         opp-hz = /bits/ 64 <710400000>;
 470                         opp-peak-kBps = <1804000 19660800>;
 471                 };
 472
 473                 cpu4_opp2: opp-825600000 {
 474                         opp-hz = /bits/ 64 <825600000>;
 475                         opp-peak-kBps = <2188000 23347200>;
 476                 };
 477
 478                 cpu4_opp3: opp-940800000 {
 479                         opp-hz = /bits/ 64 <940800000>;
 480                         opp-peak-kBps = <2188000 26419200>;
 481                 };
 482
 483                 cpu4_opp4: opp-1056000000 {
 484                         opp-hz = /bits/ 64 <1056000000>;
 485                         opp-peak-kBps = <3072000 26419200>;
 486                 };
 487
 488                 cpu4_opp5: opp-1171200000 {
 489                         opp-hz = /bits/ 64 <1171200000>;
 490                         opp-peak-kBps = <3072000 29491200>;
 491                 };
 492
 493                 cpu4_opp6: opp-1286400000 {
 494                         opp-hz = /bits/ 64 <1286400000>;
 495                         opp-peak-kBps = <4068000 29491200>;
 496                 };
 497
 498                 cpu4_opp7: opp-1382400000 {
 499                         opp-hz = /bits/ 64 <1382400000>;
 500                         opp-peak-kBps = <4068000 32563200>;
 501                 };
 502
 503                 cpu4_opp8: opp-1478400000 {
 504                         opp-hz = /bits/ 64 <1478400000>;
 505                         opp-peak-kBps = <4068000 32563200>;
 506                 };
 507
 508                 cpu4_opp9: opp-1574400000 {
 509                         opp-hz = /bits/ 64 <1574400000>;
 510                         opp-peak-kBps = <5412000 39321600>;
 511                 };
 512
 513                 cpu4_opp10: opp-1670400000 {
 514                         opp-hz = /bits/ 64 <1670400000>;
 515                         opp-peak-kBps = <5412000 42393600>;
 516                 };
 517
 518                 cpu4_opp11: opp-1766400000 {
 519                         opp-hz = /bits/ 64 <1766400000>;
 520                         opp-peak-kBps = <5412000 45465600>;
 521                 };
 522
 523                 cpu4_opp12: opp-1862400000 {
 524                         opp-hz = /bits/ 64 <1862400000>;
 525                         opp-peak-kBps = <6220000 45465600>;
 526                 };
 527
 528                 cpu4_opp13: opp-1958400000 {
 529                         opp-hz = /bits/ 64 <1958400000>;
 530                         opp-peak-kBps = <6220000 48537600>;
 531                 };
 532
 533                 cpu4_opp14: opp-2054400000 {
 534                         opp-hz = /bits/ 64 <2054400000>;
 535                         opp-peak-kBps = <7216000 48537600>;
 536                 };
 537
 538                 cpu4_opp15: opp-2150400000 {
 539                         opp-hz = /bits/ 64 <2150400000>;
 540                         opp-peak-kBps = <7216000 51609600>;
 541                 };
 542
 543                 cpu4_opp16: opp-2246400000 {
 544                         opp-hz = /bits/ 64 <2246400000>;
 545                         opp-peak-kBps = <7216000 51609600>;
 546                 };
 547
 548                 cpu4_opp17: opp-2342400000 {
 549                         opp-hz = /bits/ 64 <2342400000>;
 550                         opp-peak-kBps = <8368000 51609600>;
 551                 };
 552
 553                 cpu4_opp18: opp-2419200000 {
 554                         opp-hz = /bits/ 64 <2419200000>;
 555                         opp-peak-kBps = <8368000 51609600>;
 556                 };
 557         };
 558
 559         cpu7_opp_table: opp-table-cpu7 {
 560                 compatible = "operating-points-v2";
 561                 opp-shared;
 562
 563                 cpu7_opp1: opp-844800000 {
 564                         opp-hz = /bits/ 64 <844800000>;
 565                         opp-peak-kBps = <2188000 19660800>;
 566                 };
 567
 568                 cpu7_opp2: opp-960000000 {
 569                         opp-hz = /bits/ 64 <960000000>;
 570                         opp-peak-kBps = <2188000 26419200>;
 571                 };
 572
 573                 cpu7_opp3: opp-1075200000 {
 574                         opp-hz = /bits/ 64 <1075200000>;
 575                         opp-peak-kBps = <3072000 26419200>;
 576                 };
 577
 578                 cpu7_opp4: opp-1190400000 {
 579                         opp-hz = /bits/ 64 <1190400000>;
 580                         opp-peak-kBps = <3072000 29491200>;
 581                 };
 582
 583                 cpu7_opp5: opp-1305600000 {
 584                         opp-hz = /bits/ 64 <1305600000>;
 585                         opp-peak-kBps = <4068000 32563200>;
 586                 };
 587
 588                 cpu7_opp6: opp-1401600000 {
 589                         opp-hz = /bits/ 64 <1401600000>;
 590                         opp-peak-kBps = <4068000 32563200>;
 591                 };
 592
 593                 cpu7_opp7: opp-1516800000 {
 594                         opp-hz = /bits/ 64 <1516800000>;
 595                         opp-peak-kBps = <4068000 36249600>;
 596                 };
 597
 598                 cpu7_opp8: opp-1632000000 {
 599                         opp-hz = /bits/ 64 <1632000000>;
 600                         opp-peak-kBps = <5412000 39321600>;
 601                 };
 602
 603                 cpu7_opp9: opp-1747200000 {
 604                         opp-hz = /bits/ 64 <1708800000>;
 605                         opp-peak-kBps = <5412000 42393600>;
 606                 };
 607
 608                 cpu7_opp10: opp-1862400000 {
 609                         opp-hz = /bits/ 64 <1862400000>;
 610                         opp-peak-kBps = <6220000 45465600>;
 611                 };
 612
 613                 cpu7_opp11: opp-1977600000 {
 614                         opp-hz = /bits/ 64 <1977600000>;
 615                         opp-peak-kBps = <6220000 48537600>;
 616                 };
 617
 618                 cpu7_opp12: opp-2073600000 {
 619                         opp-hz = /bits/ 64 <2073600000>;
 620                         opp-peak-kBps = <7216000 48537600>;
 621                 };
 622
 623                 cpu7_opp13: opp-2169600000 {
 624                         opp-hz = /bits/ 64 <2169600000>;
 625                         opp-peak-kBps = <7216000 51609600>;
 626                 };
 627
 628                 cpu7_opp14: opp-2265600000 {
 629                         opp-hz = /bits/ 64 <2265600000>;
 630                         opp-peak-kBps = <7216000 51609600>;
 631                 };
 632
 633                 cpu7_opp15: opp-2361600000 {
 634                         opp-hz = /bits/ 64 <2361600000>;
 635                         opp-peak-kBps = <8368000 51609600>;
 636                 };
 637
 638                 cpu7_opp16: opp-2457600000 {
 639                         opp-hz = /bits/ 64 <2457600000>;
 640                         opp-peak-kBps = <8368000 51609600>;
 641                 };
 642
 643                 cpu7_opp17: opp-2553600000 {
 644                         opp-hz = /bits/ 64 <2553600000>;
 645                         opp-peak-kBps = <8368000 51609600>;
 646                 };
 647
 648                 cpu7_opp18: opp-2649600000 {
 649                         opp-hz = /bits/ 64 <2649600000>;
 650                         opp-peak-kBps = <8368000 51609600>;
 651                 };
 652
 653                 cpu7_opp19: opp-2745600000 {
 654                         opp-hz = /bits/ 64 <2745600000>;
 655                         opp-peak-kBps = <8368000 51609600>;
 656                 };
 657
 658                 cpu7_opp20: opp-2841600000 {
 659                         opp-hz = /bits/ 64 <2841600000>;
 660                         opp-peak-kBps = <8368000 51609600>;
 661                 };
 662         };
 663
 664         firmware {
 665                 scm: scm {
 666                         compatible = "qcom,scm-sm8250", "qcom,scm";
 667                         #reset-cells = <1>;
 668                 };
 669         };
 670
 671         memory@80000000 {
 672                 device_type = "memory";
 673                 /* We expect the bootloader to fill in the size */
 674                 reg = <0x0 0x80000000 0x0 0x0>;
 675         };
 676
 677         pmu {
 678                 compatible = "arm,armv8-pmuv3";
 679                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 680         };
 681
 682         psci {
 683                 compatible = "arm,psci-1.0";
 684                 method = "smc";
 685
 686                 CPU_PD0: power-domain-cpu0 {
 687                         #power-domain-cells = <0>;
 688                         power-domains = <&CLUSTER_PD>;
 689                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 690                 };
 691
 692                 CPU_PD1: power-domain-cpu1 {
 693                         #power-domain-cells = <0>;
 694                         power-domains = <&CLUSTER_PD>;
 695                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 696                 };
 697
 698                 CPU_PD2: power-domain-cpu2 {
 699                         #power-domain-cells = <0>;
 700                         power-domains = <&CLUSTER_PD>;
 701                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 702                 };
 703
 704                 CPU_PD3: power-domain-cpu3 {
 705                         #power-domain-cells = <0>;
 706                         power-domains = <&CLUSTER_PD>;
 707                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 708                 };
 709
 710                 CPU_PD4: power-domain-cpu4 {
 711                         #power-domain-cells = <0>;
 712                         power-domains = <&CLUSTER_PD>;
 713                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 714                 };
 715
 716                 CPU_PD5: power-domain-cpu5 {
 717                         #power-domain-cells = <0>;
 718                         power-domains = <&CLUSTER_PD>;
 719                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 720                 };
 721
 722                 CPU_PD6: power-domain-cpu6 {
 723                         #power-domain-cells = <0>;
 724                         power-domains = <&CLUSTER_PD>;
 725                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 726                 };
 727
 728                 CPU_PD7: power-domain-cpu7 {
 729                         #power-domain-cells = <0>;
 730                         power-domains = <&CLUSTER_PD>;
 731                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 732                 };
 733
 734                 CLUSTER_PD: power-domain-cpu-cluster0 {
 735                         #power-domain-cells = <0>;
 736                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 737                 };
 738         };
 739
 740         qup_opp_table: opp-table-qup {
 741                 compatible = "operating-points-v2";
 742
 743                 opp-50000000 {
 744                         opp-hz = /bits/ 64 <50000000>;
 745                         required-opps = <&rpmhpd_opp_min_svs>;
 746                 };
 747
 748                 opp-75000000 {
 749                         opp-hz = /bits/ 64 <75000000>;
 750                         required-opps = <&rpmhpd_opp_low_svs>;
 751                 };
 752
 753                 opp-120000000 {
 754                         opp-hz = /bits/ 64 <120000000>;
 755                         required-opps = <&rpmhpd_opp_svs>;
 756                 };
 757         };
 758
 759         reserved-memory {
 760                 #address-cells = <2>;
 761                 #size-cells = <2>;
 762                 ranges;
 763
 764                 hyp_mem: memory@80000000 {
 765                         reg = <0x0 0x80000000 0x0 0x600000>;
 766                         no-map;
 767                 };
 768
 769                 xbl_aop_mem: memory@80700000 {
 770                         reg = <0x0 0x80700000 0x0 0x160000>;
 771                         no-map;
 772                 };
 773
 774                 cmd_db: memory@80860000 {
 775                         compatible = "qcom,cmd-db";
 776                         reg = <0x0 0x80860000 0x0 0x20000>;
 777                         no-map;
 778                 };
 779
 780                 smem_mem: memory@80900000 {
 781                         reg = <0x0 0x80900000 0x0 0x200000>;
 782                         no-map;
 783                 };
 784
 785                 removed_mem: memory@80b00000 {
 786                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 787                         no-map;
 788                 };
 789
 790                 camera_mem: memory@86200000 {
 791                         reg = <0x0 0x86200000 0x0 0x500000>;
 792                         no-map;
 793                 };
 794
 795                 wlan_mem: memory@86700000 {
 796                         reg = <0x0 0x86700000 0x0 0x100000>;
 797                         no-map;
 798                 };
 799
 800                 ipa_fw_mem: memory@86800000 {
 801                         reg = <0x0 0x86800000 0x0 0x10000>;
 802                         no-map;
 803                 };
 804
 805                 ipa_gsi_mem: memory@86810000 {
 806                         reg = <0x0 0x86810000 0x0 0xa000>;
 807                         no-map;
 808                 };
 809
 810                 gpu_mem: memory@8681a000 {
 811                         reg = <0x0 0x8681a000 0x0 0x2000>;
 812                         no-map;
 813                 };
 814
 815                 npu_mem: memory@86900000 {
 816                         reg = <0x0 0x86900000 0x0 0x500000>;
 817                         no-map;
 818                 };
 819
 820                 video_mem: memory@86e00000 {
 821                         reg = <0x0 0x86e00000 0x0 0x500000>;
 822                         no-map;
 823                 };
 824
 825                 cvp_mem: memory@87300000 {
 826                         reg = <0x0 0x87300000 0x0 0x500000>;
 827                         no-map;
 828                 };
 829
 830                 cdsp_mem: memory@87800000 {
 831                         reg = <0x0 0x87800000 0x0 0x1400000>;
 832                         no-map;
 833                 };
 834
 835                 slpi_mem: memory@88c00000 {
 836                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 837                         no-map;
 838                 };
 839
 840                 adsp_mem: memory@8a100000 {
 841                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 842                         no-map;
 843                 };
 844
 845                 spss_mem: memory@8be00000 {
 846                         reg = <0x0 0x8be00000 0x0 0x100000>;
 847                         no-map;
 848                 };
 849
 850                 cdsp_secure_heap: memory@8bf00000 {
 851                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 852                         no-map;
 853                 };
 854         };
 855
 856         smem {
 857                 compatible = "qcom,smem";
 858                 memory-region = <&smem_mem>;
 859                 hwlocks = <&tcsr_mutex 3>;
 860         };
 861
 862         smp2p-adsp {
 863                 compatible = "qcom,smp2p";
 864                 qcom,smem = <443>, <429>;
 865                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 866                                              IPCC_MPROC_SIGNAL_SMP2P
 867                                              IRQ_TYPE_EDGE_RISING>;
 868                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 869                                 IPCC_MPROC_SIGNAL_SMP2P>;
 870
 871                 qcom,local-pid = <0>;
 872                 qcom,remote-pid = <2>;
 873
 874                 smp2p_adsp_out: master-kernel {
 875                         qcom,entry-name = "master-kernel";
 876                         #qcom,smem-state-cells = <1>;
 877                 };
 878
 879                 smp2p_adsp_in: slave-kernel {
 880                         qcom,entry-name = "slave-kernel";
 881                         interrupt-controller;
 882                         #interrupt-cells = <2>;
 883                 };
 884         };
 885
 886         smp2p-cdsp {
 887                 compatible = "qcom,smp2p";
 888                 qcom,smem = <94>, <432>;
 889                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 890                                              IPCC_MPROC_SIGNAL_SMP2P
 891                                              IRQ_TYPE_EDGE_RISING>;
 892                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 893                                 IPCC_MPROC_SIGNAL_SMP2P>;
 894
 895                 qcom,local-pid = <0>;
 896                 qcom,remote-pid = <5>;
 897
 898                 smp2p_cdsp_out: master-kernel {
 899                         qcom,entry-name = "master-kernel";
 900                         #qcom,smem-state-cells = <1>;
 901                 };
 902
 903                 smp2p_cdsp_in: slave-kernel {
 904                         qcom,entry-name = "slave-kernel";
 905                         interrupt-controller;
 906                         #interrupt-cells = <2>;
 907                 };
 908         };
 909
 910         smp2p-slpi {
 911                 compatible = "qcom,smp2p";
 912                 qcom,smem = <481>, <430>;
 913                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 914                                              IPCC_MPROC_SIGNAL_SMP2P
 915                                              IRQ_TYPE_EDGE_RISING>;
 916                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 917                                 IPCC_MPROC_SIGNAL_SMP2P>;
 918
 919                 qcom,local-pid = <0>;
 920                 qcom,remote-pid = <3>;
 921
 922                 smp2p_slpi_out: master-kernel {
 923                         qcom,entry-name = "master-kernel";
 924                         #qcom,smem-state-cells = <1>;
 925                 };
 926
 927                 smp2p_slpi_in: slave-kernel {
 928                         qcom,entry-name = "slave-kernel";
 929                         interrupt-controller;
 930                         #interrupt-cells = <2>;
 931                 };
 932         };
 933
 934         soc: soc@0 {
 935                 #address-cells = <2>;
 936                 #size-cells = <2>;
 937                 ranges = <0 0 0 0 0x10 0>;
 938                 dma-ranges = <0 0 0 0 0x10 0>;
 939                 compatible = "simple-bus";
 940
 941                 gcc: clock-controller@100000 {
 942                         compatible = "qcom,gcc-sm8250";
 943                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 944                         #clock-cells = <1>;
 945                         #reset-cells = <1>;
 946                         #power-domain-cells = <1>;
 947                         clock-names = "bi_tcxo",
 948                                       "bi_tcxo_ao",
 949                                       "sleep_clk";
 950                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 951                                  <&rpmhcc RPMH_CXO_CLK_A>,
 952                                  <&sleep_clk>;
 953                 };
 954
 955                 ipcc: mailbox@408000 {
 956                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 957                         reg = <0 0x00408000 0 0x1000>;
 958                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 959                         interrupt-controller;
 960                         #interrupt-cells = <3>;
 961                         #mbox-cells = <2>;
 962                 };
 963
 964                 qfprom: efuse@784000 {
 965                         compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
 966                         reg = <0 0x00784000 0 0x8ff>;
 967                         #address-cells = <1>;
 968                         #size-cells = <1>;
 969
 970                         gpu_speed_bin: gpu_speed_bin@19b {
 971                                 reg = <0x19b 0x1>;
 972                                 bits = <5 3>;
 973                         };
 974                 };
 975
 976                 rng: rng@793000 {
 977                         compatible = "qcom,prng-ee";
 978                         reg = <0 0x00793000 0 0x1000>;
 979                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 980                         clock-names = "core";
 981                 };
 982
 983                 gpi_dma2: dma-controller@800000 {
 984                         compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
 985                         reg = <0 0x00800000 0 0x70000>;
 986                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 987                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 988                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 989                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 990                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 991                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 992                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 993                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 994                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 995                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
 996                         dma-channels = <10>;
 997                         dma-channel-mask = <0x3f>;
 998                         iommus = <&apps_smmu 0x76 0x0>;
 999                         #dma-cells = <3>;
1000                         status = "disabled";
1001                 };
1002
1003                 qupv3_id_2: geniqup@8c0000 {
1004                         compatible = "qcom,geni-se-qup";
1005                         reg = <0x0 0x008c0000 0x0 0x6000>;
1006                         clock-names = "m-ahb", "s-ahb";
1007                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1008                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1009                         #address-cells = <2>;
1010                         #size-cells = <2>;
1011                         iommus = <&apps_smmu 0x63 0x0>;
1012                         ranges;
1013                         status = "disabled";
1014
1015                         i2c14: i2c@880000 {
1016                                 compatible = "qcom,geni-i2c";
1017                                 reg = <0 0x00880000 0 0x4000>;
1018                                 clock-names = "se";
1019                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1020                                 pinctrl-names = "default";
1021                                 pinctrl-0 = <&qup_i2c14_default>;
1022                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1023                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1024                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1025                                 dma-names = "tx", "rx";
1026                                 #address-cells = <1>;
1027                                 #size-cells = <0>;
1028                                 status = "disabled";
1029                         };
1030
1031                         spi14: spi@880000 {
1032                                 compatible = "qcom,geni-spi";
1033                                 reg = <0 0x00880000 0 0x4000>;
1034                                 clock-names = "se";
1035                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1036                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1037                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1038                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1039                                 dma-names = "tx", "rx";
1040                                 power-domains = <&rpmhpd RPMHPD_CX>;
1041                                 operating-points-v2 = <&qup_opp_table>;
1042                                 #address-cells = <1>;
1043                                 #size-cells = <0>;
1044                                 status = "disabled";
1045                         };
1046
1047                         i2c15: i2c@884000 {
1048                                 compatible = "qcom,geni-i2c";
1049                                 reg = <0 0x00884000 0 0x4000>;
1050                                 clock-names = "se";
1051                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1052                                 pinctrl-names = "default";
1053                                 pinctrl-0 = <&qup_i2c15_default>;
1054                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1055                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1056                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1057                                 dma-names = "tx", "rx";
1058                                 #address-cells = <1>;
1059                                 #size-cells = <0>;
1060                                 status = "disabled";
1061                         };
1062
1063                         spi15: spi@884000 {
1064                                 compatible = "qcom,geni-spi";
1065                                 reg = <0 0x00884000 0 0x4000>;
1066                                 clock-names = "se";
1067                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1068                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1069                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1070                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1071                                 dma-names = "tx", "rx";
1072                                 power-domains = <&rpmhpd RPMHPD_CX>;
1073                                 operating-points-v2 = <&qup_opp_table>;
1074                                 #address-cells = <1>;
1075                                 #size-cells = <0>;
1076                                 status = "disabled";
1077                         };
1078
1079                         i2c16: i2c@888000 {
1080                                 compatible = "qcom,geni-i2c";
1081                                 reg = <0 0x00888000 0 0x4000>;
1082                                 clock-names = "se";
1083                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1084                                 pinctrl-names = "default";
1085                                 pinctrl-0 = <&qup_i2c16_default>;
1086                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1087                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1088                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1089                                 dma-names = "tx", "rx";
1090                                 #address-cells = <1>;
1091                                 #size-cells = <0>;
1092                                 status = "disabled";
1093                         };
1094
1095                         spi16: spi@888000 {
1096                                 compatible = "qcom,geni-spi";
1097                                 reg = <0 0x00888000 0 0x4000>;
1098                                 clock-names = "se";
1099                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1100                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1101                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1102                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1103                                 dma-names = "tx", "rx";
1104                                 power-domains = <&rpmhpd RPMHPD_CX>;
1105                                 operating-points-v2 = <&qup_opp_table>;
1106                                 #address-cells = <1>;
1107                                 #size-cells = <0>;
1108                                 status = "disabled";
1109                         };
1110
1111                         i2c17: i2c@88c000 {
1112                                 compatible = "qcom,geni-i2c";
1113                                 reg = <0 0x0088c000 0 0x4000>;
1114                                 clock-names = "se";
1115                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1116                                 pinctrl-names = "default";
1117                                 pinctrl-0 = <&qup_i2c17_default>;
1118                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1119                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1120                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1121                                 dma-names = "tx", "rx";
1122                                 #address-cells = <1>;
1123                                 #size-cells = <0>;
1124                                 status = "disabled";
1125                         };
1126
1127                         spi17: spi@88c000 {
1128                                 compatible = "qcom,geni-spi";
1129                                 reg = <0 0x0088c000 0 0x4000>;
1130                                 clock-names = "se";
1131                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1132                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1133                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1134                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1135                                 dma-names = "tx", "rx";
1136                                 power-domains = <&rpmhpd RPMHPD_CX>;
1137                                 operating-points-v2 = <&qup_opp_table>;
1138                                 #address-cells = <1>;
1139                                 #size-cells = <0>;
1140                                 status = "disabled";
1141                         };
1142
1143                         uart17: serial@88c000 {
1144                                 compatible = "qcom,geni-uart";
1145                                 reg = <0 0x0088c000 0 0x4000>;
1146                                 clock-names = "se";
1147                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1148                                 pinctrl-names = "default";
1149                                 pinctrl-0 = <&qup_uart17_default>;
1150                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1151                                 power-domains = <&rpmhpd RPMHPD_CX>;
1152                                 operating-points-v2 = <&qup_opp_table>;
1153                                 status = "disabled";
1154                         };
1155
1156                         i2c18: i2c@890000 {
1157                                 compatible = "qcom,geni-i2c";
1158                                 reg = <0 0x00890000 0 0x4000>;
1159                                 clock-names = "se";
1160                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1161                                 pinctrl-names = "default";
1162                                 pinctrl-0 = <&qup_i2c18_default>;
1163                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1164                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1165                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1166                                 dma-names = "tx", "rx";
1167                                 #address-cells = <1>;
1168                                 #size-cells = <0>;
1169                                 status = "disabled";
1170                         };
1171
1172                         spi18: spi@890000 {
1173                                 compatible = "qcom,geni-spi";
1174                                 reg = <0 0x00890000 0 0x4000>;
1175                                 clock-names = "se";
1176                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1177                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1178                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1179                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1180                                 dma-names = "tx", "rx";
1181                                 power-domains = <&rpmhpd RPMHPD_CX>;
1182                                 operating-points-v2 = <&qup_opp_table>;
1183                                 #address-cells = <1>;
1184                                 #size-cells = <0>;
1185                                 status = "disabled";
1186                         };
1187
1188                         uart18: serial@890000 {
1189                                 compatible = "qcom,geni-uart";
1190                                 reg = <0 0x00890000 0 0x4000>;
1191                                 clock-names = "se";
1192                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1193                                 pinctrl-names = "default";
1194                                 pinctrl-0 = <&qup_uart18_default>;
1195                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1196                                 power-domains = <&rpmhpd RPMHPD_CX>;
1197                                 operating-points-v2 = <&qup_opp_table>;
1198                                 status = "disabled";
1199                         };
1200
1201                         i2c19: i2c@894000 {
1202                                 compatible = "qcom,geni-i2c";
1203                                 reg = <0 0x00894000 0 0x4000>;
1204                                 clock-names = "se";
1205                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1206                                 pinctrl-names = "default";
1207                                 pinctrl-0 = <&qup_i2c19_default>;
1208                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1209                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1210                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1211                                 dma-names = "tx", "rx";
1212                                 #address-cells = <1>;
1213                                 #size-cells = <0>;
1214                                 status = "disabled";
1215                         };
1216
1217                         spi19: spi@894000 {
1218                                 compatible = "qcom,geni-spi";
1219                                 reg = <0 0x00894000 0 0x4000>;
1220                                 clock-names = "se";
1221                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1222                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1223                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1224                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1225                                 dma-names = "tx", "rx";
1226                                 power-domains = <&rpmhpd RPMHPD_CX>;
1227                                 operating-points-v2 = <&qup_opp_table>;
1228                                 #address-cells = <1>;
1229                                 #size-cells = <0>;
1230                                 status = "disabled";
1231                         };
1232                 };
1233
1234                 gpi_dma0: dma-controller@900000 {
1235                         compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1236                         reg = <0 0x00900000 0 0x70000>;
1237                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1238                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1239                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1240                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1241                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1242                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1243                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1244                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1245                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1246                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1247                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1248                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1249                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1250                         dma-channels = <15>;
1251                         dma-channel-mask = <0x7ff>;
1252                         iommus = <&apps_smmu 0x5b6 0x0>;
1253                         #dma-cells = <3>;
1254                         status = "disabled";
1255                 };
1256
1257                 qupv3_id_0: geniqup@9c0000 {
1258                         compatible = "qcom,geni-se-qup";
1259                         reg = <0x0 0x009c0000 0x0 0x6000>;
1260                         clock-names = "m-ahb", "s-ahb";
1261                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1262                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1263                         #address-cells = <2>;
1264                         #size-cells = <2>;
1265                         iommus = <&apps_smmu 0x5a3 0x0>;
1266                         ranges;
1267                         status = "disabled";
1268
1269                         i2c0: i2c@980000 {
1270                                 compatible = "qcom,geni-i2c";
1271                                 reg = <0 0x00980000 0 0x4000>;
1272                                 clock-names = "se";
1273                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1274                                 pinctrl-names = "default";
1275                                 pinctrl-0 = <&qup_i2c0_default>;
1276                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1277                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1278                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1279                                 dma-names = "tx", "rx";
1280                                 #address-cells = <1>;
1281                                 #size-cells = <0>;
1282                                 status = "disabled";
1283                         };
1284
1285                         spi0: spi@980000 {
1286                                 compatible = "qcom,geni-spi";
1287                                 reg = <0 0x00980000 0 0x4000>;
1288                                 clock-names = "se";
1289                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1290                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1291                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1292                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1293                                 dma-names = "tx", "rx";
1294                                 power-domains = <&rpmhpd RPMHPD_CX>;
1295                                 operating-points-v2 = <&qup_opp_table>;
1296                                 #address-cells = <1>;
1297                                 #size-cells = <0>;
1298                                 status = "disabled";
1299                         };
1300
1301                         i2c1: i2c@984000 {
1302                                 compatible = "qcom,geni-i2c";
1303                                 reg = <0 0x00984000 0 0x4000>;
1304                                 clock-names = "se";
1305                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1306                                 pinctrl-names = "default";
1307                                 pinctrl-0 = <&qup_i2c1_default>;
1308                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1309                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1310                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1311                                 dma-names = "tx", "rx";
1312                                 #address-cells = <1>;
1313                                 #size-cells = <0>;
1314                                 status = "disabled";
1315                         };
1316
1317                         spi1: spi@984000 {
1318                                 compatible = "qcom,geni-spi";
1319                                 reg = <0 0x00984000 0 0x4000>;
1320                                 clock-names = "se";
1321                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1322                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1323                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1324                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1325                                 dma-names = "tx", "rx";
1326                                 power-domains = <&rpmhpd RPMHPD_CX>;
1327                                 operating-points-v2 = <&qup_opp_table>;
1328                                 #address-cells = <1>;
1329                                 #size-cells = <0>;
1330                                 status = "disabled";
1331                         };
1332
1333                         i2c2: i2c@988000 {
1334                                 compatible = "qcom,geni-i2c";
1335                                 reg = <0 0x00988000 0 0x4000>;
1336                                 clock-names = "se";
1337                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1338                                 pinctrl-names = "default";
1339                                 pinctrl-0 = <&qup_i2c2_default>;
1340                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1341                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1342                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1343                                 dma-names = "tx", "rx";
1344                                 #address-cells = <1>;
1345                                 #size-cells = <0>;
1346                                 status = "disabled";
1347                         };
1348
1349                         spi2: spi@988000 {
1350                                 compatible = "qcom,geni-spi";
1351                                 reg = <0 0x00988000 0 0x4000>;
1352                                 clock-names = "se";
1353                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1354                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1355                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1356                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1357                                 dma-names = "tx", "rx";
1358                                 power-domains = <&rpmhpd RPMHPD_CX>;
1359                                 operating-points-v2 = <&qup_opp_table>;
1360                                 #address-cells = <1>;
1361                                 #size-cells = <0>;
1362                                 status = "disabled";
1363                         };
1364
1365                         uart2: serial@988000 {
1366                                 compatible = "qcom,geni-debug-uart";
1367                                 reg = <0 0x00988000 0 0x4000>;
1368                                 clock-names = "se";
1369                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1370                                 pinctrl-names = "default";
1371                                 pinctrl-0 = <&qup_uart2_default>;
1372                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1373                                 power-domains = <&rpmhpd RPMHPD_CX>;
1374                                 operating-points-v2 = <&qup_opp_table>;
1375                                 status = "disabled";
1376                         };
1377
1378                         i2c3: i2c@98c000 {
1379                                 compatible = "qcom,geni-i2c";
1380                                 reg = <0 0x0098c000 0 0x4000>;
1381                                 clock-names = "se";
1382                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1383                                 pinctrl-names = "default";
1384                                 pinctrl-0 = <&qup_i2c3_default>;
1385                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1386                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1387                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1388                                 dma-names = "tx", "rx";
1389                                 #address-cells = <1>;
1390                                 #size-cells = <0>;
1391                                 status = "disabled";
1392                         };
1393
1394                         spi3: spi@98c000 {
1395                                 compatible = "qcom,geni-spi";
1396                                 reg = <0 0x0098c000 0 0x4000>;
1397                                 clock-names = "se";
1398                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1399                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1400                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1401                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1402                                 dma-names = "tx", "rx";
1403                                 power-domains = <&rpmhpd RPMHPD_CX>;
1404                                 operating-points-v2 = <&qup_opp_table>;
1405                                 #address-cells = <1>;
1406                                 #size-cells = <0>;
1407                                 status = "disabled";
1408                         };
1409
1410                         i2c4: i2c@990000 {
1411                                 compatible = "qcom,geni-i2c";
1412                                 reg = <0 0x00990000 0 0x4000>;
1413                                 clock-names = "se";
1414                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1415                                 pinctrl-names = "default";
1416                                 pinctrl-0 = <&qup_i2c4_default>;
1417                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1418                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1419                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1420                                 dma-names = "tx", "rx";
1421                                 #address-cells = <1>;
1422                                 #size-cells = <0>;
1423                                 status = "disabled";
1424                         };
1425
1426                         spi4: spi@990000 {
1427                                 compatible = "qcom,geni-spi";
1428                                 reg = <0 0x00990000 0 0x4000>;
1429                                 clock-names = "se";
1430                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1431                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1432                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1433                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1434                                 dma-names = "tx", "rx";
1435                                 power-domains = <&rpmhpd RPMHPD_CX>;
1436                                 operating-points-v2 = <&qup_opp_table>;
1437                                 #address-cells = <1>;
1438                                 #size-cells = <0>;
1439                                 status = "disabled";
1440                         };
1441
1442                         i2c5: i2c@994000 {
1443                                 compatible = "qcom,geni-i2c";
1444                                 reg = <0 0x00994000 0 0x4000>;
1445                                 clock-names = "se";
1446                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1447                                 pinctrl-names = "default";
1448                                 pinctrl-0 = <&qup_i2c5_default>;
1449                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1450                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1451                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1452                                 dma-names = "tx", "rx";
1453                                 #address-cells = <1>;
1454                                 #size-cells = <0>;
1455                                 status = "disabled";
1456                         };
1457
1458                         spi5: spi@994000 {
1459                                 compatible = "qcom,geni-spi";
1460                                 reg = <0 0x00994000 0 0x4000>;
1461                                 clock-names = "se";
1462                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1463                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1464                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1465                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1466                                 dma-names = "tx", "rx";
1467                                 power-domains = <&rpmhpd RPMHPD_CX>;
1468                                 operating-points-v2 = <&qup_opp_table>;
1469                                 #address-cells = <1>;
1470                                 #size-cells = <0>;
1471                                 status = "disabled";
1472                         };
1473
1474                         i2c6: i2c@998000 {
1475                                 compatible = "qcom,geni-i2c";
1476                                 reg = <0 0x00998000 0 0x4000>;
1477                                 clock-names = "se";
1478                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1479                                 pinctrl-names = "default";
1480                                 pinctrl-0 = <&qup_i2c6_default>;
1481                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1482                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1483                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1484                                 dma-names = "tx", "rx";
1485                                 #address-cells = <1>;
1486                                 #size-cells = <0>;
1487                                 status = "disabled";
1488                         };
1489
1490                         spi6: spi@998000 {
1491                                 compatible = "qcom,geni-spi";
1492                                 reg = <0 0x00998000 0 0x4000>;
1493                                 clock-names = "se";
1494                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1495                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1496                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1497                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1498                                 dma-names = "tx", "rx";
1499                                 power-domains = <&rpmhpd RPMHPD_CX>;
1500                                 operating-points-v2 = <&qup_opp_table>;
1501                                 #address-cells = <1>;
1502                                 #size-cells = <0>;
1503                                 status = "disabled";
1504                         };
1505
1506                         uart6: serial@998000 {
1507                                 compatible = "qcom,geni-uart";
1508                                 reg = <0 0x00998000 0 0x4000>;
1509                                 clock-names = "se";
1510                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1511                                 pinctrl-names = "default";
1512                                 pinctrl-0 = <&qup_uart6_default>;
1513                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1514                                 power-domains = <&rpmhpd RPMHPD_CX>;
1515                                 operating-points-v2 = <&qup_opp_table>;
1516                                 status = "disabled";
1517                         };
1518
1519                         i2c7: i2c@99c000 {
1520                                 compatible = "qcom,geni-i2c";
1521                                 reg = <0 0x0099c000 0 0x4000>;
1522                                 clock-names = "se";
1523                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1524                                 pinctrl-names = "default";
1525                                 pinctrl-0 = <&qup_i2c7_default>;
1526                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1527                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1528                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1529                                 dma-names = "tx", "rx";
1530                                 #address-cells = <1>;
1531                                 #size-cells = <0>;
1532                                 status = "disabled";
1533                         };
1534
1535                         spi7: spi@99c000 {
1536                                 compatible = "qcom,geni-spi";
1537                                 reg = <0 0x0099c000 0 0x4000>;
1538                                 clock-names = "se";
1539                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1540                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1541                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1542                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1543                                 dma-names = "tx", "rx";
1544                                 power-domains = <&rpmhpd RPMHPD_CX>;
1545                                 operating-points-v2 = <&qup_opp_table>;
1546                                 #address-cells = <1>;
1547                                 #size-cells = <0>;
1548                                 status = "disabled";
1549                         };
1550                 };
1551
1552                 gpi_dma1: dma-controller@a00000 {
1553                         compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1554                         reg = <0 0x00a00000 0 0x70000>;
1555                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1556                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1557                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1558                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1559                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1560                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1561                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1562                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1563                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1564                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1565                         dma-channels = <10>;
1566                         dma-channel-mask = <0x3f>;
1567                         iommus = <&apps_smmu 0x56 0x0>;
1568                         #dma-cells = <3>;
1569                         status = "disabled";
1570                 };
1571
1572                 qupv3_id_1: geniqup@ac0000 {
1573                         compatible = "qcom,geni-se-qup";
1574                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1575                         clock-names = "m-ahb", "s-ahb";
1576                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1577                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1578                         #address-cells = <2>;
1579                         #size-cells = <2>;
1580                         iommus = <&apps_smmu 0x43 0x0>;
1581                         ranges;
1582                         status = "disabled";
1583
1584                         i2c8: i2c@a80000 {
1585                                 compatible = "qcom,geni-i2c";
1586                                 reg = <0 0x00a80000 0 0x4000>;
1587                                 clock-names = "se";
1588                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1589                                 pinctrl-names = "default";
1590                                 pinctrl-0 = <&qup_i2c8_default>;
1591                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1592                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1593                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1594                                 dma-names = "tx", "rx";
1595                                 #address-cells = <1>;
1596                                 #size-cells = <0>;
1597                                 status = "disabled";
1598                         };
1599
1600                         spi8: spi@a80000 {
1601                                 compatible = "qcom,geni-spi";
1602                                 reg = <0 0x00a80000 0 0x4000>;
1603                                 clock-names = "se";
1604                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1605                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1606                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1607                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1608                                 dma-names = "tx", "rx";
1609                                 power-domains = <&rpmhpd RPMHPD_CX>;
1610                                 operating-points-v2 = <&qup_opp_table>;
1611                                 #address-cells = <1>;
1612                                 #size-cells = <0>;
1613                                 status = "disabled";
1614                         };
1615
1616                         i2c9: i2c@a84000 {
1617                                 compatible = "qcom,geni-i2c";
1618                                 reg = <0 0x00a84000 0 0x4000>;
1619                                 clock-names = "se";
1620                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1621                                 pinctrl-names = "default";
1622                                 pinctrl-0 = <&qup_i2c9_default>;
1623                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1624                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1625                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1626                                 dma-names = "tx", "rx";
1627                                 #address-cells = <1>;
1628                                 #size-cells = <0>;
1629                                 status = "disabled";
1630                         };
1631
1632                         spi9: spi@a84000 {
1633                                 compatible = "qcom,geni-spi";
1634                                 reg = <0 0x00a84000 0 0x4000>;
1635                                 clock-names = "se";
1636                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1637                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1638                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1639                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1640                                 dma-names = "tx", "rx";
1641                                 power-domains = <&rpmhpd RPMHPD_CX>;
1642                                 operating-points-v2 = <&qup_opp_table>;
1643                                 #address-cells = <1>;
1644                                 #size-cells = <0>;
1645                                 status = "disabled";
1646                         };
1647
1648                         i2c10: i2c@a88000 {
1649                                 compatible = "qcom,geni-i2c";
1650                                 reg = <0 0x00a88000 0 0x4000>;
1651                                 clock-names = "se";
1652                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1653                                 pinctrl-names = "default";
1654                                 pinctrl-0 = <&qup_i2c10_default>;
1655                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1656                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1657                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1658                                 dma-names = "tx", "rx";
1659                                 #address-cells = <1>;
1660                                 #size-cells = <0>;
1661                                 status = "disabled";
1662                         };
1663
1664                         spi10: spi@a88000 {
1665                                 compatible = "qcom,geni-spi";
1666                                 reg = <0 0x00a88000 0 0x4000>;
1667                                 clock-names = "se";
1668                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1669                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1670                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1671                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1672                                 dma-names = "tx", "rx";
1673                                 power-domains = <&rpmhpd RPMHPD_CX>;
1674                                 operating-points-v2 = <&qup_opp_table>;
1675                                 #address-cells = <1>;
1676                                 #size-cells = <0>;
1677                                 status = "disabled";
1678                         };
1679
1680                         i2c11: i2c@a8c000 {
1681                                 compatible = "qcom,geni-i2c";
1682                                 reg = <0 0x00a8c000 0 0x4000>;
1683                                 clock-names = "se";
1684                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1685                                 pinctrl-names = "default";
1686                                 pinctrl-0 = <&qup_i2c11_default>;
1687                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1688                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1689                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1690                                 dma-names = "tx", "rx";
1691                                 #address-cells = <1>;
1692                                 #size-cells = <0>;
1693                                 status = "disabled";
1694                         };
1695
1696                         spi11: spi@a8c000 {
1697                                 compatible = "qcom,geni-spi";
1698                                 reg = <0 0x00a8c000 0 0x4000>;
1699                                 clock-names = "se";
1700                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1701                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1702                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1703                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1704                                 dma-names = "tx", "rx";
1705                                 power-domains = <&rpmhpd RPMHPD_CX>;
1706                                 operating-points-v2 = <&qup_opp_table>;
1707                                 #address-cells = <1>;
1708                                 #size-cells = <0>;
1709                                 status = "disabled";
1710                         };
1711
1712                         i2c12: i2c@a90000 {
1713                                 compatible = "qcom,geni-i2c";
1714                                 reg = <0 0x00a90000 0 0x4000>;
1715                                 clock-names = "se";
1716                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1717                                 pinctrl-names = "default";
1718                                 pinctrl-0 = <&qup_i2c12_default>;
1719                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1720                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1721                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1722                                 dma-names = "tx", "rx";
1723                                 #address-cells = <1>;
1724                                 #size-cells = <0>;
1725                                 status = "disabled";
1726                         };
1727
1728                         spi12: spi@a90000 {
1729                                 compatible = "qcom,geni-spi";
1730                                 reg = <0 0x00a90000 0 0x4000>;
1731                                 clock-names = "se";
1732                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1733                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1734                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1735                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1736                                 dma-names = "tx", "rx";
1737                                 power-domains = <&rpmhpd RPMHPD_CX>;
1738                                 operating-points-v2 = <&qup_opp_table>;
1739                                 #address-cells = <1>;
1740                                 #size-cells = <0>;
1741                                 status = "disabled";
1742                         };
1743
1744                         uart12: serial@a90000 {
1745                                 compatible = "qcom,geni-debug-uart";
1746                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1747                                 clock-names = "se";
1748                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1749                                 pinctrl-names = "default";
1750                                 pinctrl-0 = <&qup_uart12_default>;
1751                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1752                                 power-domains = <&rpmhpd RPMHPD_CX>;
1753                                 operating-points-v2 = <&qup_opp_table>;
1754                                 status = "disabled";
1755                         };
1756
1757                         i2c13: i2c@a94000 {
1758                                 compatible = "qcom,geni-i2c";
1759                                 reg = <0 0x00a94000 0 0x4000>;
1760                                 clock-names = "se";
1761                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1762                                 pinctrl-names = "default";
1763                                 pinctrl-0 = <&qup_i2c13_default>;
1764                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1765                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1766                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1767                                 dma-names = "tx", "rx";
1768                                 #address-cells = <1>;
1769                                 #size-cells = <0>;
1770                                 status = "disabled";
1771                         };
1772
1773                         spi13: spi@a94000 {
1774                                 compatible = "qcom,geni-spi";
1775                                 reg = <0 0x00a94000 0 0x4000>;
1776                                 clock-names = "se";
1777                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1778                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1779                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1780                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1781                                 dma-names = "tx", "rx";
1782                                 power-domains = <&rpmhpd RPMHPD_CX>;
1783                                 operating-points-v2 = <&qup_opp_table>;
1784                                 #address-cells = <1>;
1785                                 #size-cells = <0>;
1786                                 status = "disabled";
1787                         };
1788                 };
1789
1790                 config_noc: interconnect@1500000 {
1791                         compatible = "qcom,sm8250-config-noc";
1792                         reg = <0 0x01500000 0 0xa580>;
1793                         #interconnect-cells = <2>;
1794                         qcom,bcm-voters = <&apps_bcm_voter>;
1795                 };
1796
1797                 system_noc: interconnect@1620000 {
1798                         compatible = "qcom,sm8250-system-noc";
1799                         reg = <0 0x01620000 0 0x1c200>;
1800                         #interconnect-cells = <2>;
1801                         qcom,bcm-voters = <&apps_bcm_voter>;
1802                 };
1803
1804                 mc_virt: interconnect@163d000 {
1805                         compatible = "qcom,sm8250-mc-virt";
1806                         reg = <0 0x0163d000 0 0x1000>;
1807                         #interconnect-cells = <2>;
1808                         qcom,bcm-voters = <&apps_bcm_voter>;
1809                 };
1810
1811                 aggre1_noc: interconnect@16e0000 {
1812                         compatible = "qcom,sm8250-aggre1-noc";
1813                         reg = <0 0x016e0000 0 0x1f180>;
1814                         #interconnect-cells = <2>;
1815                         qcom,bcm-voters = <&apps_bcm_voter>;
1816                 };
1817
1818                 aggre2_noc: interconnect@1700000 {
1819                         compatible = "qcom,sm8250-aggre2-noc";
1820                         reg = <0 0x01700000 0 0x33000>;
1821                         #interconnect-cells = <2>;
1822                         qcom,bcm-voters = <&apps_bcm_voter>;
1823                 };
1824
1825                 compute_noc: interconnect@1733000 {
1826                         compatible = "qcom,sm8250-compute-noc";
1827                         reg = <0 0x01733000 0 0xa180>;
1828                         #interconnect-cells = <2>;
1829                         qcom,bcm-voters = <&apps_bcm_voter>;
1830                 };
1831
1832                 mmss_noc: interconnect@1740000 {
1833                         compatible = "qcom,sm8250-mmss-noc";
1834                         reg = <0 0x01740000 0 0x1f080>;
1835                         #interconnect-cells = <2>;
1836                         qcom,bcm-voters = <&apps_bcm_voter>;
1837                 };
1838
1839                 pcie0: pci@1c00000 {
1840                         compatible = "qcom,pcie-sm8250";
1841                         reg = <0 0x01c00000 0 0x3000>,
1842                               <0 0x60000000 0 0xf1d>,
1843                               <0 0x60000f20 0 0xa8>,
1844                               <0 0x60001000 0 0x1000>,
1845                               <0 0x60100000 0 0x100000>,
1846                               <0 0x01c03000 0 0x1000>;
1847                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1848                         device_type = "pci";
1849                         linux,pci-domain = <0>;
1850                         bus-range = <0x00 0xff>;
1851                         num-lanes = <1>;
1852
1853                         #address-cells = <3>;
1854                         #size-cells = <2>;
1855
1856                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1857                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1858
1859                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1860                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1861                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1862                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1863                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1864                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1865                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1866                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1867                         interrupt-names = "msi0", "msi1", "msi2", "msi3",
1868                                           "msi4", "msi5", "msi6", "msi7";
1869                         #interrupt-cells = <1>;
1870                         interrupt-map-mask = <0 0 0 0x7>;
1871                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1872                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1873                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1874                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1875
1876                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1877                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1878                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1879                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1880                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1881                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1882                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1883                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1884                         clock-names = "pipe",
1885                                       "aux",
1886                                       "cfg",
1887                                       "bus_master",
1888                                       "bus_slave",
1889                                       "slave_q2a",
1890                                       "tbu",
1891                                       "ddrss_sf_tbu";
1892
1893                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1894                                     <0x100 &apps_smmu 0x1c01 0x1>;
1895
1896                         resets = <&gcc GCC_PCIE_0_BCR>;
1897                         reset-names = "pci";
1898
1899                         power-domains = <&gcc PCIE_0_GDSC>;
1900
1901                         phys = <&pcie0_lane>;
1902                         phy-names = "pciephy";
1903
1904                         perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
1905                         wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1906
1907                         pinctrl-names = "default";
1908                         pinctrl-0 = <&pcie0_default_state>;
1909                         dma-coherent;
1910
1911                         status = "disabled";
1912                 };
1913
1914                 pcie0_phy: phy@1c06000 {
1915                         compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1916                         reg = <0 0x01c06000 0 0x1c0>;
1917                         #address-cells = <2>;
1918                         #size-cells = <2>;
1919                         ranges;
1920                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1921                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1922                                  <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1923                                  <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1924                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1925
1926                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1927                         reset-names = "phy";
1928
1929                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1930                         assigned-clock-rates = <100000000>;
1931
1932                         status = "disabled";
1933
1934                         pcie0_lane: phy@1c06200 {
1935                                 reg = <0 0x01c06200 0 0x170>, /* tx */
1936                                       <0 0x01c06400 0 0x200>, /* rx */
1937                                       <0 0x01c06800 0 0x1f0>, /* pcs */
1938                                       <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1939                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1940                                 clock-names = "pipe0";
1941
1942                                 #phy-cells = <0>;
1943
1944                                 #clock-cells = <0>;
1945                                 clock-output-names = "pcie_0_pipe_clk";
1946                         };
1947                 };
1948
1949                 pcie1: pci@1c08000 {
1950                         compatible = "qcom,pcie-sm8250";
1951                         reg = <0 0x01c08000 0 0x3000>,
1952                               <0 0x40000000 0 0xf1d>,
1953                               <0 0x40000f20 0 0xa8>,
1954                               <0 0x40001000 0 0x1000>,
1955                               <0 0x40100000 0 0x100000>,
1956                               <0 0x01c0b000 0 0x1000>;
1957                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1958                         device_type = "pci";
1959                         linux,pci-domain = <1>;
1960                         bus-range = <0x00 0xff>;
1961                         num-lanes = <2>;
1962
1963                         #address-cells = <3>;
1964                         #size-cells = <2>;
1965
1966                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1967                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1968
1969                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1970                         interrupt-names = "msi";
1971                         #interrupt-cells = <1>;
1972                         interrupt-map-mask = <0 0 0 0x7>;
1973                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1974                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1975                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1976                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1977
1978                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1979                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1980                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1981                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1982                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1983                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1984                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1985                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1986                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1987                         clock-names = "pipe",
1988                                       "aux",
1989                                       "cfg",
1990                                       "bus_master",
1991                                       "bus_slave",
1992                                       "slave_q2a",
1993                                       "ref",
1994                                       "tbu",
1995                                       "ddrss_sf_tbu";
1996
1997                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1998                         assigned-clock-rates = <19200000>;
1999
2000                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
2001                                     <0x100 &apps_smmu 0x1c81 0x1>;
2002
2003                         resets = <&gcc GCC_PCIE_1_BCR>;
2004                         reset-names = "pci";
2005
2006                         power-domains = <&gcc PCIE_1_GDSC>;
2007
2008                         phys = <&pcie1_lane>;
2009                         phy-names = "pciephy";
2010
2011                         perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2012                         wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2013
2014                         pinctrl-names = "default";
2015                         pinctrl-0 = <&pcie1_default_state>;
2016                         dma-coherent;
2017
2018                         status = "disabled";
2019                 };
2020
2021                 pcie1_phy: phy@1c0e000 {
2022                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2023                         reg = <0 0x01c0e000 0 0x1c0>;
2024                         #address-cells = <2>;
2025                         #size-cells = <2>;
2026                         ranges;
2027                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2028                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2029                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2030                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2031                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2032
2033                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2034                         reset-names = "phy";
2035
2036                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2037                         assigned-clock-rates = <100000000>;
2038
2039                         status = "disabled";
2040
2041                         pcie1_lane: phy@1c0e200 {
2042                                 reg = <0 0x01c0e200 0 0x170>, /* tx0 */
2043                                       <0 0x01c0e400 0 0x200>, /* rx0 */
2044                                       <0 0x01c0ea00 0 0x1f0>, /* pcs */
2045                                       <0 0x01c0e600 0 0x170>, /* tx1 */
2046                                       <0 0x01c0e800 0 0x200>, /* rx1 */
2047                                       <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2048                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2049                                 clock-names = "pipe0";
2050
2051                                 #phy-cells = <0>;
2052
2053                                 #clock-cells = <0>;
2054                                 clock-output-names = "pcie_1_pipe_clk";
2055                         };
2056                 };
2057
2058                 pcie2: pci@1c10000 {
2059                         compatible = "qcom,pcie-sm8250";
2060                         reg = <0 0x01c10000 0 0x3000>,
2061                               <0 0x64000000 0 0xf1d>,
2062                               <0 0x64000f20 0 0xa8>,
2063                               <0 0x64001000 0 0x1000>,
2064                               <0 0x64100000 0 0x100000>,
2065                               <0 0x01c13000 0 0x1000>;
2066                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2067                         device_type = "pci";
2068                         linux,pci-domain = <2>;
2069                         bus-range = <0x00 0xff>;
2070                         num-lanes = <2>;
2071
2072                         #address-cells = <3>;
2073                         #size-cells = <2>;
2074
2075                         ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2076                                  <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2077
2078                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2079                         interrupt-names = "msi";
2080                         #interrupt-cells = <1>;
2081                         interrupt-map-mask = <0 0 0 0x7>;
2082                         interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2083                                         <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2084                                         <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2085                                         <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2086
2087                         clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2088                                  <&gcc GCC_PCIE_2_AUX_CLK>,
2089                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2090                                  <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2091                                  <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2092                                  <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2093                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2094                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2095                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2096                         clock-names = "pipe",
2097                                       "aux",
2098                                       "cfg",
2099                                       "bus_master",
2100                                       "bus_slave",
2101                                       "slave_q2a",
2102                                       "ref",
2103                                       "tbu",
2104                                       "ddrss_sf_tbu";
2105
2106                         assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2107                         assigned-clock-rates = <19200000>;
2108
2109                         iommu-map = <0x0   &apps_smmu 0x1d00 0x1>,
2110                                     <0x100 &apps_smmu 0x1d01 0x1>;
2111
2112                         resets = <&gcc GCC_PCIE_2_BCR>;
2113                         reset-names = "pci";
2114
2115                         power-domains = <&gcc PCIE_2_GDSC>;
2116
2117                         phys = <&pcie2_lane>;
2118                         phy-names = "pciephy";
2119
2120                         perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2121                         wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2122
2123                         pinctrl-names = "default";
2124                         pinctrl-0 = <&pcie2_default_state>;
2125                         dma-coherent;
2126
2127                         status = "disabled";
2128                 };
2129
2130                 pcie2_phy: phy@1c16000 {
2131                         compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2132                         reg = <0 0x01c16000 0 0x1c0>;
2133                         #address-cells = <2>;
2134                         #size-cells = <2>;
2135                         ranges;
2136                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2137                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2138                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2139                                  <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2140                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2141
2142                         resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2143                         reset-names = "phy";
2144
2145                         assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2146                         assigned-clock-rates = <100000000>;
2147
2148                         status = "disabled";
2149
2150                         pcie2_lane: phy@1c16200 {
2151                                 reg = <0 0x01c16200 0 0x170>, /* tx0 */
2152                                       <0 0x01c16400 0 0x200>, /* rx0 */
2153                                       <0 0x01c16a00 0 0x1f0>, /* pcs */
2154                                       <0 0x01c16600 0 0x170>, /* tx1 */
2155                                       <0 0x01c16800 0 0x200>, /* rx1 */
2156                                       <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2157                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
2158                                 clock-names = "pipe0";
2159
2160                                 #phy-cells = <0>;
2161
2162                                 #clock-cells = <0>;
2163                                 clock-output-names = "pcie_2_pipe_clk";
2164                         };
2165                 };
2166
2167                 ufs_mem_hc: ufshc@1d84000 {
2168                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2169                                      "jedec,ufs-2.0";
2170                         reg = <0 0x01d84000 0 0x3000>;
2171                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2172                         phys = <&ufs_mem_phy_lanes>;
2173                         phy-names = "ufsphy";
2174                         lanes-per-direction = <2>;
2175                         #reset-cells = <1>;
2176                         resets = <&gcc GCC_UFS_PHY_BCR>;
2177                         reset-names = "rst";
2178
2179                         power-domains = <&gcc UFS_PHY_GDSC>;
2180
2181                         iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2182
2183                         clock-names =
2184                                 "core_clk",
2185                                 "bus_aggr_clk",
2186                                 "iface_clk",
2187                                 "core_clk_unipro",
2188                                 "ref_clk",
2189                                 "tx_lane0_sync_clk",
2190                                 "rx_lane0_sync_clk",
2191                                 "rx_lane1_sync_clk";
2192                         clocks =
2193                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2194                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2195                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2196                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2197                                 <&rpmhcc RPMH_CXO_CLK>,
2198                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2199                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2200                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2201                         freq-table-hz =
2202                                 <37500000 300000000>,
2203                                 <0 0>,
2204                                 <0 0>,
2205                                 <37500000 300000000>,
2206                                 <0 0>,
2207                                 <0 0>,
2208                                 <0 0>,
2209                                 <0 0>;
2210
2211                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2212                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2213                         interconnect-names = "ufs-ddr", "cpu-ufs";
2214
2215                         status = "disabled";
2216                 };
2217
2218                 ufs_mem_phy: phy@1d87000 {
2219                         compatible = "qcom,sm8250-qmp-ufs-phy";
2220                         reg = <0 0x01d87000 0 0x1c0>;
2221                         #address-cells = <2>;
2222                         #size-cells = <2>;
2223                         ranges;
2224                         clock-names = "ref",
2225                                       "ref_aux";
2226                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2227                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2228
2229                         resets = <&ufs_mem_hc 0>;
2230                         reset-names = "ufsphy";
2231                         status = "disabled";
2232
2233                         ufs_mem_phy_lanes: phy@1d87400 {
2234                                 reg = <0 0x01d87400 0 0x16c>,
2235                                       <0 0x01d87600 0 0x200>,
2236                                       <0 0x01d87c00 0 0x200>,
2237                                       <0 0x01d87800 0 0x16c>,
2238                                       <0 0x01d87a00 0 0x200>;
2239                                 #phy-cells = <0>;
2240                         };
2241                 };
2242
2243                 cryptobam: dma-controller@1dc4000 {
2244                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2245                         reg = <0 0x01dc4000 0 0x24000>;
2246                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2247                         #dma-cells = <1>;
2248                         qcom,ee = <0>;
2249                         qcom,controlled-remotely;
2250                         num-channels = <8>;
2251                         qcom,num-ees = <2>;
2252                         iommus = <&apps_smmu 0x592 0x0000>,
2253                                  <&apps_smmu 0x598 0x0000>,
2254                                  <&apps_smmu 0x599 0x0000>,
2255                                  <&apps_smmu 0x59f 0x0000>,
2256                                  <&apps_smmu 0x586 0x0011>,
2257                                  <&apps_smmu 0x596 0x0011>;
2258                 };
2259
2260                 crypto: crypto@1dfa000 {
2261                         compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2262                         reg = <0 0x01dfa000 0 0x6000>;
2263                         dmas = <&cryptobam 4>, <&cryptobam 5>;
2264                         dma-names = "rx", "tx";
2265                         iommus = <&apps_smmu 0x592 0x0000>,
2266                                  <&apps_smmu 0x598 0x0000>,
2267                                  <&apps_smmu 0x599 0x0000>,
2268                                  <&apps_smmu 0x59f 0x0000>,
2269                                  <&apps_smmu 0x586 0x0011>,
2270                                  <&apps_smmu 0x596 0x0011>;
2271                         interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2272                         interconnect-names = "memory";
2273                 };
2274
2275                 tcsr_mutex: hwlock@1f40000 {
2276                         compatible = "qcom,tcsr-mutex";
2277                         reg = <0x0 0x01f40000 0x0 0x40000>;
2278                         #hwlock-cells = <1>;
2279                 };
2280
2281                 wsamacro: codec@3240000 {
2282                         compatible = "qcom,sm8250-lpass-wsa-macro";
2283                         reg = <0 0x03240000 0 0x1000>;
2284                         clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2285                                  <&audiocc LPASS_CDC_WSA_NPL>,
2286                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2287                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2288                                  <&aoncc LPASS_CDC_VA_MCLK>,
2289                                  <&vamacro>;
2290
2291                         clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2292
2293                         #clock-cells = <0>;
2294                         clock-output-names = "mclk";
2295                         #sound-dai-cells = <1>;
2296
2297                         pinctrl-names = "default";
2298                         pinctrl-0 = <&wsa_swr_active>;
2299
2300                         status = "disabled";
2301                 };
2302
2303                 swr0: soundwire-controller@3250000 {
2304                         reg = <0 0x03250000 0 0x2000>;
2305                         compatible = "qcom,soundwire-v1.5.1";
2306                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2307                         clocks = <&wsamacro>;
2308                         clock-names = "iface";
2309
2310                         qcom,din-ports = <2>;
2311                         qcom,dout-ports = <6>;
2312
2313                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2314                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2315                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2316                         qcom,ports-block-pack-mode =    /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2317
2318                         #sound-dai-cells = <1>;
2319                         #address-cells = <2>;
2320                         #size-cells = <0>;
2321
2322                         status = "disabled";
2323                 };
2324
2325                 audiocc: clock-controller@3300000 {
2326                         compatible = "qcom,sm8250-lpass-audiocc";
2327                         reg = <0 0x03300000 0 0x30000>;
2328                         #clock-cells = <1>;
2329                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2330                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2331                                 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2332                         clock-names = "core", "audio", "bus";
2333                 };
2334
2335                 vamacro: codec@3370000 {
2336                         compatible = "qcom,sm8250-lpass-va-macro";
2337                         reg = <0 0x03370000 0 0x1000>;
2338                         clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2339                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2340                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2341
2342                         clock-names = "mclk", "macro", "dcodec";
2343
2344                         #clock-cells = <0>;
2345                         clock-output-names = "fsgen";
2346                         #sound-dai-cells = <1>;
2347                 };
2348
2349                 rxmacro: rxmacro@3200000 {
2350                         pinctrl-names = "default";
2351                         pinctrl-0 = <&rx_swr_active>;
2352                         compatible = "qcom,sm8250-lpass-rx-macro";
2353                         reg = <0 0x03200000 0 0x1000>;
2354                         status = "disabled";
2355
2356                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2357                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2358                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2359                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2360                                 <&vamacro>;
2361
2362                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2363
2364                         #clock-cells = <0>;
2365                         clock-output-names = "mclk";
2366                         #sound-dai-cells = <1>;
2367                 };
2368
2369                 swr1: soundwire-controller@3210000 {
2370                         reg = <0 0x03210000 0 0x2000>;
2371                         compatible = "qcom,soundwire-v1.5.1";
2372                         status = "disabled";
2373                         interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2374                         clocks = <&rxmacro>;
2375                         clock-names = "iface";
2376                         label = "RX";
2377                         qcom,din-ports = <0>;
2378                         qcom,dout-ports = <5>;
2379
2380                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2381                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2382                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2383                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2384                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2385                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2386                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2387                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2388                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2389
2390                         #sound-dai-cells = <1>;
2391                         #address-cells = <2>;
2392                         #size-cells = <0>;
2393                 };
2394
2395                 txmacro: txmacro@3220000 {
2396                         pinctrl-names = "default";
2397                         pinctrl-0 = <&tx_swr_active>;
2398                         compatible = "qcom,sm8250-lpass-tx-macro";
2399                         reg = <0 0x03220000 0 0x1000>;
2400                         status = "disabled";
2401
2402                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2403                                  <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2404                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2405                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2406                                  <&vamacro>;
2407
2408                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2409
2410                         #clock-cells = <0>;
2411                         clock-output-names = "mclk";
2412                         #sound-dai-cells = <1>;
2413                 };
2414
2415                 /* tx macro */
2416                 swr2: soundwire-controller@3230000 {
2417                         reg = <0 0x03230000 0 0x2000>;
2418                         compatible = "qcom,soundwire-v1.5.1";
2419                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2420                         interrupt-names = "core";
2421                         status = "disabled";
2422
2423                         clocks = <&txmacro>;
2424                         clock-names = "iface";
2425                         label = "TX";
2426
2427                         qcom,din-ports = <5>;
2428                         qcom,dout-ports = <0>;
2429                         qcom,ports-sinterval-low =      /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2430                         qcom,ports-offset1 =            /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2431                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2432                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2433                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2434                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2435                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2436                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2437                         qcom,ports-lane-control =       /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2438                         #sound-dai-cells = <1>;
2439                         #address-cells = <2>;
2440                         #size-cells = <0>;
2441                 };
2442
2443                 aoncc: clock-controller@3380000 {
2444                         compatible = "qcom,sm8250-lpass-aoncc";
2445                         reg = <0 0x03380000 0 0x40000>;
2446                         #clock-cells = <1>;
2447                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2448                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2449                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2450                         clock-names = "core", "audio", "bus";
2451                 };
2452
2453                 lpass_tlmm: pinctrl@33c0000 {
2454                         compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2455                         reg = <0 0x033c0000 0x0 0x20000>,
2456                               <0 0x03550000 0x0 0x10000>;
2457                         gpio-controller;
2458                         #gpio-cells = <2>;
2459                         gpio-ranges = <&lpass_tlmm 0 0 14>;
2460
2461                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2462                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2463                         clock-names = "core", "audio";
2464
2465                         wsa_swr_active: wsa-swr-active-state {
2466                                 clk-pins {
2467                                         pins = "gpio10";
2468                                         function = "wsa_swr_clk";
2469                                         drive-strength = <2>;
2470                                         slew-rate = <1>;
2471                                         bias-disable;
2472                                 };
2473
2474                                 data-pins {
2475                                         pins = "gpio11";
2476                                         function = "wsa_swr_data";
2477                                         drive-strength = <2>;
2478                                         slew-rate = <1>;
2479                                         bias-bus-hold;
2480                                 };
2481                         };
2482
2483                         wsa_swr_sleep: wsa-swr-sleep-state {
2484                                 clk-pins {
2485                                         pins = "gpio10";
2486                                         function = "wsa_swr_clk";
2487                                         drive-strength = <2>;
2488                                         bias-pull-down;
2489                                 };
2490
2491                                 data-pins {
2492                                         pins = "gpio11";
2493                                         function = "wsa_swr_data";
2494                                         drive-strength = <2>;
2495                                         bias-pull-down;
2496                                 };
2497                         };
2498
2499                         dmic01_active: dmic01-active-state {
2500                                 clk-pins {
2501                                         pins = "gpio6";
2502                                         function = "dmic1_clk";
2503                                         drive-strength = <8>;
2504                                         output-high;
2505                                 };
2506                                 data-pins {
2507                                         pins = "gpio7";
2508                                         function = "dmic1_data";
2509                                         drive-strength = <8>;
2510                                 };
2511                         };
2512
2513                         dmic01_sleep: dmic01-sleep-state {
2514                                 clk-pins {
2515                                         pins = "gpio6";
2516                                         function = "dmic1_clk";
2517                                         drive-strength = <2>;
2518                                         bias-disable;
2519                                         output-low;
2520                                 };
2521
2522                                 data-pins {
2523                                         pins = "gpio7";
2524                                         function = "dmic1_data";
2525                                         drive-strength = <2>;
2526                                         bias-pull-down;
2527                                 };
2528                         };
2529
2530                         rx_swr_active: rx-swr-active-state {
2531                                 clk-pins {
2532                                         pins = "gpio3";
2533                                         function = "swr_rx_clk";
2534                                         drive-strength = <2>;
2535                                         slew-rate = <1>;
2536                                         bias-disable;
2537                                 };
2538
2539                                 data-pins {
2540                                         pins = "gpio4", "gpio5";
2541                                         function = "swr_rx_data";
2542                                         drive-strength = <2>;
2543                                         slew-rate = <1>;
2544                                         bias-bus-hold;
2545                                 };
2546                         };
2547
2548                         tx_swr_active: tx-swr-active-state {
2549                                 clk-pins {
2550                                         pins = "gpio0";
2551                                         function = "swr_tx_clk";
2552                                         drive-strength = <2>;
2553                                         slew-rate = <1>;
2554                                         bias-disable;
2555                                 };
2556
2557                                 data-pins {
2558                                         pins = "gpio1", "gpio2";
2559                                         function = "swr_tx_data";
2560                                         drive-strength = <2>;
2561                                         slew-rate = <1>;
2562                                         bias-bus-hold;
2563                                 };
2564                         };
2565
2566                         tx_swr_sleep: tx-swr-sleep-state {
2567                                 clk-pins {
2568                                         pins = "gpio0";
2569                                         function = "swr_tx_clk";
2570                                         drive-strength = <2>;
2571                                         bias-pull-down;
2572                                 };
2573
2574                                 data1-pins {
2575                                         pins = "gpio1";
2576                                         function = "swr_tx_data";
2577                                         drive-strength = <2>;
2578                                         bias-bus-hold;
2579                                 };
2580
2581                                 data2-pins {
2582                                         pins = "gpio2";
2583                                         function = "swr_tx_data";
2584                                         drive-strength = <2>;
2585                                         bias-pull-down;
2586                                 };
2587                         };
2588                 };
2589
2590                 gpu: gpu@3d00000 {
2591                         compatible = "qcom,adreno-650.2",
2592                                      "qcom,adreno";
2593
2594                         reg = <0 0x03d00000 0 0x40000>;
2595                         reg-names = "kgsl_3d0_reg_memory";
2596
2597                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2598
2599                         iommus = <&adreno_smmu 0 0x401>;
2600
2601                         operating-points-v2 = <&gpu_opp_table>;
2602
2603                         qcom,gmu = <&gmu>;
2604
2605                         nvmem-cells = <&gpu_speed_bin>;
2606                         nvmem-cell-names = "speed_bin";
2607
2608                         status = "disabled";
2609
2610                         zap-shader {
2611                                 memory-region = <&gpu_mem>;
2612                         };
2613
2614                         gpu_opp_table: opp-table {
2615                                 compatible = "operating-points-v2";
2616
2617                                 opp-670000000 {
2618                                         opp-hz = /bits/ 64 <670000000>;
2619                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2620                                         opp-supported-hw = <0xa>;
2621                                 };
2622
2623                                 opp-587000000 {
2624                                         opp-hz = /bits/ 64 <587000000>;
2625                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2626                                         opp-supported-hw = <0xb>;
2627                                 };
2628
2629                                 opp-525000000 {
2630                                         opp-hz = /bits/ 64 <525000000>;
2631                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2632                                         opp-supported-hw = <0xf>;
2633                                 };
2634
2635                                 opp-490000000 {
2636                                         opp-hz = /bits/ 64 <490000000>;
2637                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2638                                         opp-supported-hw = <0xf>;
2639                                 };
2640
2641                                 opp-441600000 {
2642                                         opp-hz = /bits/ 64 <441600000>;
2643                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2644                                         opp-supported-hw = <0xf>;
2645                                 };
2646
2647                                 opp-400000000 {
2648                                         opp-hz = /bits/ 64 <400000000>;
2649                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2650                                         opp-supported-hw = <0xf>;
2651                                 };
2652
2653                                 opp-305000000 {
2654                                         opp-hz = /bits/ 64 <305000000>;
2655                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2656                                         opp-supported-hw = <0xf>;
2657                                 };
2658                         };
2659                 };
2660
2661                 gmu: gmu@3d6a000 {
2662                         compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2663
2664                         reg = <0 0x03d6a000 0 0x30000>,
2665                               <0 0x3de0000 0 0x10000>,
2666                               <0 0xb290000 0 0x10000>,
2667                               <0 0xb490000 0 0x10000>;
2668                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2669
2670                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2671                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2672                         interrupt-names = "hfi", "gmu";
2673
2674                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2675                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2676                                  <&gpucc GPU_CC_CXO_CLK>,
2677                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2678                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2679                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2680
2681                         power-domains = <&gpucc GPU_CX_GDSC>,
2682                                         <&gpucc GPU_GX_GDSC>;
2683                         power-domain-names = "cx", "gx";
2684
2685                         iommus = <&adreno_smmu 5 0x400>;
2686
2687                         operating-points-v2 = <&gmu_opp_table>;
2688
2689                         status = "disabled";
2690
2691                         gmu_opp_table: opp-table {
2692                                 compatible = "operating-points-v2";
2693
2694                                 opp-200000000 {
2695                                         opp-hz = /bits/ 64 <200000000>;
2696                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2697                                 };
2698                         };
2699                 };
2700
2701                 gpucc: clock-controller@3d90000 {
2702                         compatible = "qcom,sm8250-gpucc";
2703                         reg = <0 0x03d90000 0 0x9000>;
2704                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2705                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2706                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2707                         clock-names = "bi_tcxo",
2708                                       "gcc_gpu_gpll0_clk_src",
2709                                       "gcc_gpu_gpll0_div_clk_src";
2710                         #clock-cells = <1>;
2711                         #reset-cells = <1>;
2712                         #power-domain-cells = <1>;
2713                 };
2714
2715                 adreno_smmu: iommu@3da0000 {
2716                         compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
2717                                      "qcom,smmu-500", "arm,mmu-500";
2718                         reg = <0 0x03da0000 0 0x10000>;
2719                         #iommu-cells = <2>;
2720                         #global-interrupts = <2>;
2721                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2722                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2723                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2724                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2725                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2726                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2727                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2728                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2729                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2730                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
2731                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2732                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2733                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2734                         clock-names = "ahb", "bus", "iface";
2735
2736                         power-domains = <&gpucc GPU_CX_GDSC>;
2737                         dma-coherent;
2738                 };
2739
2740                 slpi: remoteproc@5c00000 {
2741                         compatible = "qcom,sm8250-slpi-pas";
2742                         reg = <0 0x05c00000 0 0x4000>;
2743
2744                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2745                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2746                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2747                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2748                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2749                         interrupt-names = "wdog", "fatal", "ready",
2750                                           "handover", "stop-ack";
2751
2752                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2753                         clock-names = "xo";
2754
2755                         power-domains = <&rpmhpd RPMHPD_LCX>,
2756                                         <&rpmhpd RPMHPD_LMX>;
2757                         power-domain-names = "lcx", "lmx";
2758
2759                         memory-region = <&slpi_mem>;
2760
2761                         qcom,qmp = <&aoss_qmp>;
2762
2763                         qcom,smem-states = <&smp2p_slpi_out 0>;
2764                         qcom,smem-state-names = "stop";
2765
2766                         status = "disabled";
2767
2768                         glink-edge {
2769                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2770                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2771                                                              IRQ_TYPE_EDGE_RISING>;
2772                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2773                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2774
2775                                 label = "slpi";
2776                                 qcom,remote-pid = <3>;
2777
2778                                 fastrpc {
2779                                         compatible = "qcom,fastrpc";
2780                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2781                                         label = "sdsp";
2782                                         qcom,non-secure-domain;
2783                                         #address-cells = <1>;
2784                                         #size-cells = <0>;
2785
2786                                         compute-cb@1 {
2787                                                 compatible = "qcom,fastrpc-compute-cb";
2788                                                 reg = <1>;
2789                                                 iommus = <&apps_smmu 0x0541 0x0>;
2790                                         };
2791
2792                                         compute-cb@2 {
2793                                                 compatible = "qcom,fastrpc-compute-cb";
2794                                                 reg = <2>;
2795                                                 iommus = <&apps_smmu 0x0542 0x0>;
2796                                         };
2797
2798                                         compute-cb@3 {
2799                                                 compatible = "qcom,fastrpc-compute-cb";
2800                                                 reg = <3>;
2801                                                 iommus = <&apps_smmu 0x0543 0x0>;
2802                                                 /* note: shared-cb = <4> in downstream */
2803                                         };
2804                                 };
2805                         };
2806                 };
2807
2808                 stm@6002000 {
2809                         compatible = "arm,coresight-stm", "arm,primecell";
2810                         reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
2811                         reg-names = "stm-base", "stm-stimulus-base";
2812
2813                         clocks = <&aoss_qmp>;
2814                         clock-names = "apb_pclk";
2815
2816                         out-ports {
2817                                 port {
2818                                         stm_out: endpoint {
2819                                                 remote-endpoint = <&funnel0_in7>;
2820                                         };
2821                                 };
2822                         };
2823                 };
2824
2825                 tpda@6004000 {
2826                         compatible = "qcom,coresight-tpda", "arm,primecell";
2827                         reg = <0 0x06004000 0 0x1000>;
2828
2829                         clocks = <&aoss_qmp>;
2830                         clock-names = "apb_pclk";
2831
2832                         out-ports {
2833                                 #address-cells = <1>;
2834                                 #size-cells = <0>;
2835
2836                                 port@0 {
2837                                         reg = <0>;
2838                                         tpda_out_funnel_qatb: endpoint {
2839                                                 remote-endpoint = <&funnel_qatb_in_tpda>;
2840                                         };
2841                                 };
2842                         };
2843
2844                         in-ports {
2845                                 #address-cells = <1>;
2846                                 #size-cells = <0>;
2847
2848                                 port@9 {
2849                                         reg = <9>;
2850                                         tpda_9_in_tpdm_mm: endpoint {
2851                                                 remote-endpoint = <&tpdm_mm_out_tpda9>;
2852                                         };
2853                                 };
2854
2855                                 port@17 {
2856                                         reg = <23>;
2857                                         tpda_23_in_tpdm_prng: endpoint {
2858                                                 remote-endpoint = <&tpdm_prng_out_tpda_23>;
2859                                         };
2860                                 };
2861                         };
2862                 };
2863
2864                 funnel@6005000 {
2865                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2866                         reg = <0 0x06005000 0 0x1000>;
2867
2868                         clocks = <&aoss_qmp>;
2869                         clock-names = "apb_pclk";
2870
2871                         out-ports {
2872                                 port {
2873                                         funnel_qatb_out_funnel_in0: endpoint {
2874                                                 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
2875                                         };
2876                                 };
2877                         };
2878
2879                         in-ports {
2880                                 #address-cells = <1>;
2881                                 #size-cells = <0>;
2882
2883                                 port@0 {
2884                                         reg = <0>;
2885                                         funnel_qatb_in_tpda: endpoint {
2886                                                 remote-endpoint = <&tpda_out_funnel_qatb>;
2887                                         };
2888                                 };
2889                         };
2890                 };
2891
2892                 funnel@6041000 {
2893                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2894                         reg = <0 0x06041000 0 0x1000>;
2895
2896                         clocks = <&aoss_qmp>;
2897                         clock-names = "apb_pclk";
2898
2899                         out-ports {
2900                                 port {
2901                                         funnel_in0_out_funnel_merg: endpoint {
2902                                                 remote-endpoint = <&funnel_merg_in_funnel_in0>;
2903                                         };
2904                                 };
2905                         };
2906
2907                         in-ports {
2908                                 #address-cells = <1>;
2909                                 #size-cells = <0>;
2910
2911                                 port@6 {
2912                                         reg = <6>;
2913                                         funnel_in0_in_funnel_qatb: endpoint {
2914                                                 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
2915                                         };
2916                                 };
2917
2918                                 port@7 {
2919                                         reg = <7>;
2920                                         funnel0_in7: endpoint {
2921                                                 remote-endpoint = <&stm_out>;
2922                                         };
2923                                 };
2924                         };
2925                 };
2926
2927                 funnel@6042000 {
2928                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2929                         reg = <0 0x06042000 0 0x1000>;
2930
2931                         clocks = <&aoss_qmp>;
2932                         clock-names = "apb_pclk";
2933
2934                         out-ports {
2935                                 port {
2936                                         funnel_in1_out_funnel_merg: endpoint {
2937                                                 remote-endpoint = <&funnel_merg_in_funnel_in1>;
2938                                         };
2939                                 };
2940                         };
2941
2942                         in-ports {
2943                                 #address-cells = <1>;
2944                                 #size-cells = <0>;
2945
2946                                 port@4 {
2947                                         reg = <4>;
2948                                         funnel_in1_in_funnel_apss_merg: endpoint {
2949                                         remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
2950                                         };
2951                                 };
2952                         };
2953                 };
2954
2955                 funnel@6045000 {
2956                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2957                         reg = <0 0x06045000 0 0x1000>;
2958
2959                         clocks = <&aoss_qmp>;
2960                         clock-names = "apb_pclk";
2961
2962                         out-ports {
2963                                 port {
2964                                         funnel_merg_out_funnel_swao: endpoint {
2965                                         remote-endpoint = <&funnel_swao_in_funnel_merg>;
2966                                         };
2967                                 };
2968                         };
2969
2970                         in-ports {
2971                                 #address-cells = <1>;
2972                                 #size-cells = <0>;
2973
2974                                 port@0 {
2975                                         reg = <0>;
2976                                         funnel_merg_in_funnel_in0: endpoint {
2977                                         remote-endpoint = <&funnel_in0_out_funnel_merg>;
2978                                         };
2979                                 };
2980
2981                                 port@1 {
2982                                         reg = <1>;
2983                                         funnel_merg_in_funnel_in1: endpoint {
2984                                         remote-endpoint = <&funnel_in1_out_funnel_merg>;
2985                                         };
2986                                 };
2987                         };
2988                 };
2989
2990                 replicator@6046000 {
2991                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2992                         reg = <0 0x06046000 0 0x1000>;
2993
2994                         clocks = <&aoss_qmp>;
2995                         clock-names = "apb_pclk";
2996
2997                         out-ports {
2998                                 port {
2999                                         replicator_out: endpoint {
3000                                                 remote-endpoint = <&etr_in>;
3001                                         };
3002                                 };
3003                         };
3004
3005                         in-ports {
3006                                 port {
3007                                         replicator_cx_in_swao_out: endpoint {
3008                                                 remote-endpoint = <&replicator_swao_out_cx_in>;
3009                                         };
3010                                 };
3011                         };
3012                 };
3013
3014                 etr@6048000 {
3015                         compatible = "arm,coresight-tmc", "arm,primecell";
3016                         reg = <0 0x06048000 0 0x1000>;
3017
3018                         clocks = <&aoss_qmp>;
3019                         clock-names = "apb_pclk";
3020                         arm,scatter-gather;
3021
3022                         in-ports {
3023                                 port {
3024                                         etr_in: endpoint {
3025                                                 remote-endpoint = <&replicator_out>;
3026                                         };
3027                                 };
3028                         };
3029                 };
3030
3031                 tpdm@684c000 {
3032                         compatible = "qcom,coresight-tpdm", "arm,primecell";
3033                         reg = <0 0x0684c000 0 0x1000>;
3034
3035                         clocks = <&aoss_qmp>;
3036                         clock-names = "apb_pclk";
3037
3038                         out-ports {
3039                                 port {
3040                                         tpdm_prng_out_tpda_23: endpoint {
3041                                                 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3042                                         };
3043                                 };
3044                         };
3045                 };
3046
3047                 funnel@6b04000 {
3048                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3049                         arm,primecell-periphid = <0x000bb908>;
3050
3051                         reg = <0 0x06b04000 0 0x1000>;
3052
3053                         clocks = <&aoss_qmp>;
3054                         clock-names = "apb_pclk";
3055
3056                         out-ports {
3057                                 port {
3058                                         funnel_swao_out_etf: endpoint {
3059                                                 remote-endpoint = <&etf_in_funnel_swao_out>;
3060                                         };
3061                                 };
3062                         };
3063
3064                         in-ports {
3065                                 #address-cells = <1>;
3066                                 #size-cells = <0>;
3067
3068                                 port@7 {
3069                                         reg = <7>;
3070                                         funnel_swao_in_funnel_merg: endpoint {
3071                                                 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3072                                         };
3073                                 };
3074                         };
3075                 };
3076
3077                 etf@6b05000 {
3078                         compatible = "arm,coresight-tmc", "arm,primecell";
3079                         reg = <0 0x06b05000 0 0x1000>;
3080
3081                         clocks = <&aoss_qmp>;
3082                         clock-names = "apb_pclk";
3083
3084                         out-ports {
3085                                 port {
3086                                         etf_out: endpoint {
3087                                                 remote-endpoint = <&replicator_in>;
3088                                         };
3089                                 };
3090                         };
3091
3092                         in-ports {
3093                                 #address-cells = <1>;
3094                                 #size-cells = <0>;
3095
3096                                 port@0 {
3097                                         reg = <0>;
3098                                         etf_in_funnel_swao_out: endpoint {
3099                                                 remote-endpoint = <&funnel_swao_out_etf>;
3100                                         };
3101                                 };
3102                         };
3103                 };
3104
3105                 replicator@6b06000 {
3106                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3107                         reg = <0 0x06b06000 0 0x1000>;
3108
3109                         clocks = <&aoss_qmp>;
3110                         clock-names = "apb_pclk";
3111
3112                         out-ports {
3113                                 port {
3114                                         replicator_swao_out_cx_in: endpoint {
3115                                                 remote-endpoint = <&replicator_cx_in_swao_out>;
3116                                         };
3117                                 };
3118                         };
3119
3120                         in-ports {
3121                                 port {
3122                                         replicator_in: endpoint {
3123                                                 remote-endpoint = <&etf_out>;
3124                                         };
3125                                 };
3126                         };
3127                 };
3128
3129                 tpdm@6c08000 {
3130                         compatible = "qcom,coresight-tpdm", "arm,primecell";
3131                         reg = <0 0x06c08000 0 0x1000>;
3132
3133                         clocks = <&aoss_qmp>;
3134                         clock-names = "apb_pclk";
3135
3136                         out-ports {
3137                                 port {
3138                                         tpdm_mm_out_funnel_dl_mm: endpoint {
3139                                                 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3140                                         };
3141                                 };
3142                         };
3143                 };
3144
3145                 funnel@6c0b000 {
3146                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3147                         reg = <0 0x06c0b000 0 0x1000>;
3148
3149                         clocks = <&aoss_qmp>;
3150                         clock-names = "apb_pclk";
3151
3152                         out-ports {
3153                                 port {
3154                                         funnel_dl_mm_out_funnel_dl_center: endpoint {
3155                                         remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3156                                         };
3157                                 };
3158                         };
3159
3160                         in-ports {
3161                                 #address-cells = <1>;
3162                                 #size-cells = <0>;
3163
3164                                 port@3 {
3165                                         reg = <3>;
3166                                         funnel_dl_mm_in_tpdm_mm: endpoint {
3167                                                 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3168                                         };
3169                                 };
3170                         };
3171                 };
3172
3173                 funnel@6c2d000 {
3174                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3175                         reg = <0 0x06c2d000 0 0x1000>;
3176
3177                         clocks = <&aoss_qmp>;
3178                         clock-names = "apb_pclk";
3179
3180                         out-ports {
3181                                 #address-cells = <1>;
3182                                 #size-cells = <0>;
3183                                 port {
3184                                         tpdm_mm_out_tpda9: endpoint {
3185                                                 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3186                                         };
3187                                 };
3188                         };
3189
3190                         in-ports {
3191                                 #address-cells = <1>;
3192                                 #size-cells = <0>;
3193
3194                                 port@2 {
3195                                         reg = <2>;
3196                                         funnel_dl_center_in_funnel_dl_mm: endpoint {
3197                                         remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3198                                         };
3199                                 };
3200                         };
3201                 };
3202
3203                 etm@7040000 {
3204                         compatible = "arm,coresight-etm4x", "arm,primecell";
3205                         reg = <0 0x07040000 0 0x1000>;
3206
3207                         cpu = <&CPU0>;
3208
3209                         clocks = <&aoss_qmp>;
3210                         clock-names = "apb_pclk";
3211                         arm,coresight-loses-context-with-cpu;
3212
3213                         out-ports {
3214                                 port {
3215                                         etm0_out: endpoint {
3216                                                 remote-endpoint = <&apss_funnel_in0>;
3217                                         };
3218                                 };
3219                         };
3220                 };
3221
3222                 etm@7140000 {
3223                         compatible = "arm,coresight-etm4x", "arm,primecell";
3224                         reg = <0 0x07140000 0 0x1000>;
3225
3226                         cpu = <&CPU1>;
3227
3228                         clocks = <&aoss_qmp>;
3229                         clock-names = "apb_pclk";
3230                         arm,coresight-loses-context-with-cpu;
3231
3232                         out-ports {
3233                                 port {
3234                                         etm1_out: endpoint {
3235                                                 remote-endpoint = <&apss_funnel_in1>;
3236                                         };
3237                                 };
3238                         };
3239                 };
3240
3241                 etm@7240000 {
3242                         compatible = "arm,coresight-etm4x", "arm,primecell";
3243                         reg = <0 0x07240000 0 0x1000>;
3244
3245                         cpu = <&CPU2>;
3246
3247                         clocks = <&aoss_qmp>;
3248                         clock-names = "apb_pclk";
3249                         arm,coresight-loses-context-with-cpu;
3250
3251                         out-ports {
3252                                 port {
3253                                         etm2_out: endpoint {
3254                                                 remote-endpoint = <&apss_funnel_in2>;
3255                                         };
3256                                 };
3257                         };
3258                 };
3259
3260                 etm@7340000 {
3261                         compatible = "arm,coresight-etm4x", "arm,primecell";
3262                         reg = <0 0x07340000 0 0x1000>;
3263
3264                         cpu = <&CPU3>;
3265
3266                         clocks = <&aoss_qmp>;
3267                         clock-names = "apb_pclk";
3268                         arm,coresight-loses-context-with-cpu;
3269
3270                         out-ports {
3271                                 port {
3272                                         etm3_out: endpoint {
3273                                                 remote-endpoint = <&apss_funnel_in3>;
3274                                         };
3275                                 };
3276                         };
3277                 };
3278
3279                 etm@7440000 {
3280                         compatible = "arm,coresight-etm4x", "arm,primecell";
3281                         reg = <0 0x07440000 0 0x1000>;
3282
3283                         cpu = <&CPU4>;
3284
3285                         clocks = <&aoss_qmp>;
3286                         clock-names = "apb_pclk";
3287                         arm,coresight-loses-context-with-cpu;
3288
3289                         out-ports {
3290                                 port {
3291                                         etm4_out: endpoint {
3292                                                 remote-endpoint = <&apss_funnel_in4>;
3293                                         };
3294                                 };
3295                         };
3296                 };
3297
3298                 etm@7540000 {
3299                         compatible = "arm,coresight-etm4x", "arm,primecell";
3300                         reg = <0 0x07540000 0 0x1000>;
3301
3302                         cpu = <&CPU5>;
3303
3304                         clocks = <&aoss_qmp>;
3305                         clock-names = "apb_pclk";
3306                         arm,coresight-loses-context-with-cpu;
3307
3308                         out-ports {
3309                                 port {
3310                                         etm5_out: endpoint {
3311                                                 remote-endpoint = <&apss_funnel_in5>;
3312                                         };
3313                                 };
3314                         };
3315                 };
3316
3317                 etm@7640000 {
3318                         compatible = "arm,coresight-etm4x", "arm,primecell";
3319                         reg = <0 0x07640000 0 0x1000>;
3320
3321                         cpu = <&CPU6>;
3322
3323                         clocks = <&aoss_qmp>;
3324                         clock-names = "apb_pclk";
3325                         arm,coresight-loses-context-with-cpu;
3326
3327                         out-ports {
3328                                 port {
3329                                         etm6_out: endpoint {
3330                                                 remote-endpoint = <&apss_funnel_in6>;
3331                                         };
3332                                 };
3333                         };
3334                 };
3335
3336                 etm@7740000 {
3337                         compatible = "arm,coresight-etm4x", "arm,primecell";
3338                         reg = <0 0x07740000 0 0x1000>;
3339
3340                         cpu = <&CPU7>;
3341
3342                         clocks = <&aoss_qmp>;
3343                         clock-names = "apb_pclk";
3344                         arm,coresight-loses-context-with-cpu;
3345
3346                         out-ports {
3347                                 port {
3348                                         etm7_out: endpoint {
3349                                                 remote-endpoint = <&apss_funnel_in7>;
3350                                         };
3351                                 };
3352                         };
3353                 };
3354
3355                 funnel@7800000 {
3356                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3357                         reg = <0 0x07800000 0 0x1000>;
3358
3359                         clocks = <&aoss_qmp>;
3360                         clock-names = "apb_pclk";
3361
3362                         out-ports {
3363                                 port {
3364                                         funnel_apss_out_funnel_apss_merg: endpoint {
3365                                         remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3366                                         };
3367                                 };
3368                         };
3369
3370                         in-ports {
3371                                 #address-cells = <1>;
3372                                 #size-cells = <0>;
3373
3374                                 port@0 {
3375                                         reg = <0>;
3376                                         apss_funnel_in0: endpoint {
3377                                                 remote-endpoint = <&etm0_out>;
3378                                         };
3379                                 };
3380
3381                                 port@1 {
3382                                         reg = <1>;
3383                                         apss_funnel_in1: endpoint {
3384                                                 remote-endpoint = <&etm1_out>;
3385                                         };
3386                                 };
3387
3388                                 port@2 {
3389                                         reg = <2>;
3390                                         apss_funnel_in2: endpoint {
3391                                                 remote-endpoint = <&etm2_out>;
3392                                         };
3393                                 };
3394
3395                                 port@3 {
3396                                         reg = <3>;
3397                                         apss_funnel_in3: endpoint {
3398                                                 remote-endpoint = <&etm3_out>;
3399                                         };
3400                                 };
3401
3402                                 port@4 {
3403                                         reg = <4>;
3404                                         apss_funnel_in4: endpoint {
3405                                                 remote-endpoint = <&etm4_out>;
3406                                         };
3407                                 };
3408
3409                                 port@5 {
3410                                         reg = <5>;
3411                                         apss_funnel_in5: endpoint {
3412                                                 remote-endpoint = <&etm5_out>;
3413                                         };
3414                                 };
3415
3416                                 port@6 {
3417                                         reg = <6>;
3418                                         apss_funnel_in6: endpoint {
3419                                                 remote-endpoint = <&etm6_out>;
3420                                         };
3421                                 };
3422
3423                                 port@7 {
3424                                         reg = <7>;
3425                                         apss_funnel_in7: endpoint {
3426                                                 remote-endpoint = <&etm7_out>;
3427                                         };
3428                                 };
3429                         };
3430                 };
3431
3432                 funnel@7810000 {
3433                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3434                         reg = <0 0x07810000 0 0x1000>;
3435
3436                         clocks = <&aoss_qmp>;
3437                         clock-names = "apb_pclk";
3438
3439                         out-ports {
3440                                 port {
3441                                         funnel_apss_merg_out_funnel_in1: endpoint {
3442                                         remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3443                                         };
3444                                 };
3445                         };
3446
3447                         in-ports {
3448                                 #address-cells = <1>;
3449                                 #size-cells = <0>;
3450
3451                                 port@0 {
3452                                         reg = <0>;
3453                                         funnel_apss_merg_in_funnel_apss: endpoint {
3454                                         remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3455                                         };
3456                                 };
3457                         };
3458                 };
3459
3460                 cdsp: remoteproc@8300000 {
3461                         compatible = "qcom,sm8250-cdsp-pas";
3462                         reg = <0 0x08300000 0 0x10000>;
3463
3464                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3465                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3466                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3467                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3468                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3469                         interrupt-names = "wdog", "fatal", "ready",
3470                                           "handover", "stop-ack";
3471
3472                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3473                         clock-names = "xo";
3474
3475                         power-domains = <&rpmhpd RPMHPD_CX>;
3476
3477                         memory-region = <&cdsp_mem>;
3478
3479                         qcom,qmp = <&aoss_qmp>;
3480
3481                         qcom,smem-states = <&smp2p_cdsp_out 0>;
3482                         qcom,smem-state-names = "stop";
3483
3484                         status = "disabled";
3485
3486                         glink-edge {
3487                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3488                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3489                                                              IRQ_TYPE_EDGE_RISING>;
3490                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
3491                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3492
3493                                 label = "cdsp";
3494                                 qcom,remote-pid = <5>;
3495
3496                                 fastrpc {
3497                                         compatible = "qcom,fastrpc";
3498                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3499                                         label = "cdsp";
3500                                         qcom,non-secure-domain;
3501                                         #address-cells = <1>;
3502                                         #size-cells = <0>;
3503
3504                                         compute-cb@1 {
3505                                                 compatible = "qcom,fastrpc-compute-cb";
3506                                                 reg = <1>;
3507                                                 iommus = <&apps_smmu 0x1001 0x0460>;
3508                                         };
3509
3510                                         compute-cb@2 {
3511                                                 compatible = "qcom,fastrpc-compute-cb";
3512                                                 reg = <2>;
3513                                                 iommus = <&apps_smmu 0x1002 0x0460>;
3514                                         };
3515
3516                                         compute-cb@3 {
3517                                                 compatible = "qcom,fastrpc-compute-cb";
3518                                                 reg = <3>;
3519                                                 iommus = <&apps_smmu 0x1003 0x0460>;
3520                                         };
3521
3522                                         compute-cb@4 {
3523                                                 compatible = "qcom,fastrpc-compute-cb";
3524                                                 reg = <4>;
3525                                                 iommus = <&apps_smmu 0x1004 0x0460>;
3526                                         };
3527
3528                                         compute-cb@5 {
3529                                                 compatible = "qcom,fastrpc-compute-cb";
3530                                                 reg = <5>;
3531                                                 iommus = <&apps_smmu 0x1005 0x0460>;
3532                                         };
3533
3534                                         compute-cb@6 {
3535                                                 compatible = "qcom,fastrpc-compute-cb";
3536                                                 reg = <6>;
3537                                                 iommus = <&apps_smmu 0x1006 0x0460>;
3538                                         };
3539
3540                                         compute-cb@7 {
3541                                                 compatible = "qcom,fastrpc-compute-cb";
3542                                                 reg = <7>;
3543                                                 iommus = <&apps_smmu 0x1007 0x0460>;
3544                                         };
3545
3546                                         compute-cb@8 {
3547                                                 compatible = "qcom,fastrpc-compute-cb";
3548                                                 reg = <8>;
3549                                                 iommus = <&apps_smmu 0x1008 0x0460>;
3550                                         };
3551
3552                                         /* note: secure cb9 in downstream */
3553                                 };
3554                         };
3555                 };
3556
3557                 usb_1_hsphy: phy@88e3000 {
3558                         compatible = "qcom,sm8250-usb-hs-phy",
3559                                      "qcom,usb-snps-hs-7nm-phy";
3560                         reg = <0 0x088e3000 0 0x400>;
3561                         status = "disabled";
3562                         #phy-cells = <0>;
3563
3564                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3565                         clock-names = "ref";
3566
3567                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3568                 };
3569
3570                 usb_2_hsphy: phy@88e4000 {
3571                         compatible = "qcom,sm8250-usb-hs-phy",
3572                                      "qcom,usb-snps-hs-7nm-phy";
3573                         reg = <0 0x088e4000 0 0x400>;
3574                         status = "disabled";
3575                         #phy-cells = <0>;
3576
3577                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3578                         clock-names = "ref";
3579
3580                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3581                 };
3582
3583                 usb_1_qmpphy: phy@88e9000 {
3584                         compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3585                         reg = <0 0x088e9000 0 0x200>,
3586                               <0 0x088e8000 0 0x40>,
3587                               <0 0x088ea000 0 0x200>;
3588                         status = "disabled";
3589                         #address-cells = <2>;
3590                         #size-cells = <2>;
3591                         ranges;
3592
3593                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3594                                  <&rpmhcc RPMH_CXO_CLK>,
3595                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3596                         clock-names = "aux", "ref_clk_src", "com_aux";
3597
3598                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3599                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3600                         reset-names = "phy", "common";
3601
3602                         usb_1_ssphy: usb3-phy@88e9200 {
3603                                 reg = <0 0x088e9200 0 0x200>,
3604                                       <0 0x088e9400 0 0x200>,
3605                                       <0 0x088e9c00 0 0x400>,
3606                                       <0 0x088e9600 0 0x200>,
3607                                       <0 0x088e9800 0 0x200>,
3608                                       <0 0x088e9a00 0 0x100>;
3609                                 #clock-cells = <0>;
3610                                 #phy-cells = <0>;
3611                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3612                                 clock-names = "pipe0";
3613                                 clock-output-names = "usb3_phy_pipe_clk_src";
3614                         };
3615
3616                         dp_phy: dp-phy@88ea200 {
3617                                 reg = <0 0x088ea200 0 0x200>,
3618                                       <0 0x088ea400 0 0x200>,
3619                                       <0 0x088eaa00 0 0x200>,
3620                                       <0 0x088ea600 0 0x200>,
3621                                       <0 0x088ea800 0 0x200>;
3622                                 #phy-cells = <0>;
3623                                 #clock-cells = <1>;
3624                         };
3625                 };
3626
3627                 usb_2_qmpphy: phy@88eb000 {
3628                         compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3629                         reg = <0 0x088eb000 0 0x200>;
3630                         status = "disabled";
3631                         #address-cells = <2>;
3632                         #size-cells = <2>;
3633                         ranges;
3634
3635                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3636                                  <&rpmhcc RPMH_CXO_CLK>,
3637                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
3638                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3639                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3640
3641                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3642                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3643                         reset-names = "phy", "common";
3644
3645                         usb_2_ssphy: phy@88eb200 {
3646                                 reg = <0 0x088eb200 0 0x200>,
3647                                       <0 0x088eb400 0 0x200>,
3648                                       <0 0x088eb800 0 0x800>;
3649                                 #clock-cells = <0>;
3650                                 #phy-cells = <0>;
3651                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3652                                 clock-names = "pipe0";
3653                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3654                         };
3655                 };
3656
3657                 sdhc_2: mmc@8804000 {
3658                         compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3659                         reg = <0 0x08804000 0 0x1000>;
3660
3661                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3662                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3663                         interrupt-names = "hc_irq", "pwr_irq";
3664
3665                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3666                                  <&gcc GCC_SDCC2_APPS_CLK>,
3667                                  <&rpmhcc RPMH_CXO_CLK>;
3668                         clock-names = "iface", "core", "xo";
3669                         iommus = <&apps_smmu 0x4a0 0x0>;
3670                         qcom,dll-config = <0x0007642c>;
3671                         qcom,ddr-config = <0x80040868>;
3672                         power-domains = <&rpmhpd RPMHPD_CX>;
3673                         operating-points-v2 = <&sdhc2_opp_table>;
3674
3675                         status = "disabled";
3676
3677                         sdhc2_opp_table: opp-table {
3678                                 compatible = "operating-points-v2";
3679
3680                                 opp-19200000 {
3681                                         opp-hz = /bits/ 64 <19200000>;
3682                                         required-opps = <&rpmhpd_opp_min_svs>;
3683                                 };
3684
3685                                 opp-50000000 {
3686                                         opp-hz = /bits/ 64 <50000000>;
3687                                         required-opps = <&rpmhpd_opp_low_svs>;
3688                                 };
3689
3690                                 opp-100000000 {
3691                                         opp-hz = /bits/ 64 <100000000>;
3692                                         required-opps = <&rpmhpd_opp_svs>;
3693                                 };
3694
3695                                 opp-202000000 {
3696                                         opp-hz = /bits/ 64 <202000000>;
3697                                         required-opps = <&rpmhpd_opp_svs_l1>;
3698                                 };
3699                         };
3700                 };
3701
3702                 pmu@9091000 {
3703                         compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3704                         reg = <0 0x09091000 0 0x1000>;
3705
3706                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3707
3708                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>;
3709
3710                         operating-points-v2 = <&llcc_bwmon_opp_table>;
3711
3712                         llcc_bwmon_opp_table: opp-table {
3713                                 compatible = "operating-points-v2";
3714
3715                                 opp-800000 {
3716                                         opp-peak-kBps = <(200 * 4 * 1000)>;
3717                                 };
3718
3719                                 opp-1200000 {
3720                                         opp-peak-kBps = <(300 * 4 * 1000)>;
3721                                 };
3722
3723                                 opp-1804000 {
3724                                         opp-peak-kBps = <(451 * 4 * 1000)>;
3725                                 };
3726
3727                                 opp-2188000 {
3728                                         opp-peak-kBps = <(547 * 4 * 1000)>;
3729                                 };
3730
3731                                 opp-2724000 {
3732                                         opp-peak-kBps = <(681 * 4 * 1000)>;
3733                                 };
3734
3735                                 opp-3072000 {
3736                                         opp-peak-kBps = <(768 * 4 * 1000)>;
3737                                 };
3738
3739                                 opp-4068000 {
3740                                         opp-peak-kBps = <(1017 * 4 * 1000)>;
3741                                 };
3742
3743                                 /* 1353 MHz, LPDDR4X */
3744
3745                                 opp-6220000 {
3746                                         opp-peak-kBps = <(1555 * 4 * 1000)>;
3747                                 };
3748
3749                                 opp-7216000 {
3750                                         opp-peak-kBps = <(1804 * 4 * 1000)>;
3751                                 };
3752
3753                                 opp-8368000 {
3754                                         opp-peak-kBps = <(2092 * 4 * 1000)>;
3755                                 };
3756
3757                                 /* LPDDR5 */
3758                                 opp-10944000 {
3759                                         opp-peak-kBps = <(2736 * 4 * 1000)>;
3760                                 };
3761                         };
3762                 };
3763
3764                 pmu@90b6400 {
3765                         compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
3766                         reg = <0 0x090b6400 0 0x600>;
3767
3768                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3769
3770                         interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>;
3771                         operating-points-v2 = <&cpu_bwmon_opp_table>;
3772
3773                         cpu_bwmon_opp_table: opp-table {
3774                                 compatible = "operating-points-v2";
3775
3776                                 opp-800000 {
3777                                         opp-peak-kBps = <(200 * 4 * 1000)>;
3778                                 };
3779
3780                                 opp-1804000 {
3781                                         opp-peak-kBps = <(451 * 4 * 1000)>;
3782                                 };
3783
3784                                 opp-2188000 {
3785                                         opp-peak-kBps = <(547 * 4 * 1000)>;
3786                                 };
3787
3788                                 opp-2724000 {
3789                                         opp-peak-kBps = <(681 * 4 * 1000)>;
3790                                 };
3791
3792                                 opp-3072000 {
3793                                         opp-peak-kBps = <(768 * 4 * 1000)>;
3794                                 };
3795
3796                                 /* 1017MHz, 1353 MHz, LPDDR4X */
3797
3798                                 opp-6220000 {
3799                                         opp-peak-kBps = <(1555 * 4 * 1000)>;
3800                                 };
3801
3802                                 opp-6832000 {
3803                                         opp-peak-kBps = <(1708 * 4 * 1000)>;
3804                                 };
3805
3806                                 opp-8368000 {
3807                                         opp-peak-kBps = <(2092 * 4 * 1000)>;
3808                                 };
3809
3810                                 /* 2133MHz, LPDDR4X */
3811
3812                                 /* LPDDR5 */
3813                                 opp-10944000 {
3814                                         opp-peak-kBps = <(2736 * 4 * 1000)>;
3815                                 };
3816
3817                                 /* LPDDR5 */
3818                                 opp-12784000 {
3819                                         opp-peak-kBps = <(3196 * 4 * 1000)>;
3820                                 };
3821                         };
3822                 };
3823
3824                 dc_noc: interconnect@90c0000 {
3825                         compatible = "qcom,sm8250-dc-noc";
3826                         reg = <0 0x090c0000 0 0x4200>;
3827                         #interconnect-cells = <2>;
3828                         qcom,bcm-voters = <&apps_bcm_voter>;
3829                 };
3830
3831                 gem_noc: interconnect@9100000 {
3832                         compatible = "qcom,sm8250-gem-noc";
3833                         reg = <0 0x09100000 0 0xb4000>;
3834                         #interconnect-cells = <2>;
3835                         qcom,bcm-voters = <&apps_bcm_voter>;
3836                 };
3837
3838                 npu_noc: interconnect@9990000 {
3839                         compatible = "qcom,sm8250-npu-noc";
3840                         reg = <0 0x09990000 0 0x1600>;
3841                         #interconnect-cells = <2>;
3842                         qcom,bcm-voters = <&apps_bcm_voter>;
3843                 };
3844
3845                 usb_1: usb@a6f8800 {
3846                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3847                         reg = <0 0x0a6f8800 0 0x400>;
3848                         status = "disabled";
3849                         #address-cells = <2>;
3850                         #size-cells = <2>;
3851                         ranges;
3852                         dma-ranges;
3853
3854                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3855                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3856                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3857                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3858                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3859                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
3860                         clock-names = "cfg_noc",
3861                                       "core",
3862                                       "iface",
3863                                       "sleep",
3864                                       "mock_utmi",
3865                                       "xo";
3866
3867                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3868                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3869                         assigned-clock-rates = <19200000>, <200000000>;
3870
3871                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3872                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
3873                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3874                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
3875                         interrupt-names = "hs_phy_irq",
3876                                           "ss_phy_irq",
3877                                           "dm_hs_phy_irq",
3878                                           "dp_hs_phy_irq";
3879
3880                         power-domains = <&gcc USB30_PRIM_GDSC>;
3881
3882                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3883
3884                         interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3885                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3886                         interconnect-names = "usb-ddr", "apps-usb";
3887
3888                         usb_1_dwc3: usb@a600000 {
3889                                 compatible = "snps,dwc3";
3890                                 reg = <0 0x0a600000 0 0xcd00>;
3891                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3892                                 iommus = <&apps_smmu 0x0 0x0>;
3893                                 snps,dis_u2_susphy_quirk;
3894                                 snps,dis_enblslpm_quirk;
3895                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3896                                 phy-names = "usb2-phy", "usb3-phy";
3897                         };
3898                 };
3899
3900                 system-cache-controller@9200000 {
3901                         compatible = "qcom,sm8250-llcc";
3902                         reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
3903                               <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
3904                               <0 0x09600000 0 0x50000>;
3905                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3906                                     "llcc3_base", "llcc_broadcast_base";
3907                 };
3908
3909                 usb_2: usb@a8f8800 {
3910                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3911                         reg = <0 0x0a8f8800 0 0x400>;
3912                         status = "disabled";
3913                         #address-cells = <2>;
3914                         #size-cells = <2>;
3915                         ranges;
3916                         dma-ranges;
3917
3918                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3919                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3920                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3921                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3922                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3923                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
3924                         clock-names = "cfg_noc",
3925                                       "core",
3926                                       "iface",
3927                                       "sleep",
3928                                       "mock_utmi",
3929                                       "xo";
3930
3931                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3932                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3933                         assigned-clock-rates = <19200000>, <200000000>;
3934
3935                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3936                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
3937                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3938                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
3939                         interrupt-names = "hs_phy_irq",
3940                                           "ss_phy_irq",
3941                                           "dm_hs_phy_irq",
3942                                           "dp_hs_phy_irq";
3943
3944                         power-domains = <&gcc USB30_SEC_GDSC>;
3945
3946                         resets = <&gcc GCC_USB30_SEC_BCR>;
3947
3948                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3949                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3950                         interconnect-names = "usb-ddr", "apps-usb";
3951
3952                         usb_2_dwc3: usb@a800000 {
3953                                 compatible = "snps,dwc3";
3954                                 reg = <0 0x0a800000 0 0xcd00>;
3955                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3956                                 iommus = <&apps_smmu 0x20 0>;
3957                                 snps,dis_u2_susphy_quirk;
3958                                 snps,dis_enblslpm_quirk;
3959                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3960                                 phy-names = "usb2-phy", "usb3-phy";
3961                         };
3962                 };
3963
3964                 venus: video-codec@aa00000 {
3965                         compatible = "qcom,sm8250-venus";
3966                         reg = <0 0x0aa00000 0 0x100000>;
3967                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3968                         power-domains = <&videocc MVS0C_GDSC>,
3969                                         <&videocc MVS0_GDSC>,
3970                                         <&rpmhpd RPMHPD_MX>;
3971                         power-domain-names = "venus", "vcodec0", "mx";
3972                         operating-points-v2 = <&venus_opp_table>;
3973
3974                         clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
3975                                  <&videocc VIDEO_CC_MVS0C_CLK>,
3976                                  <&videocc VIDEO_CC_MVS0_CLK>;
3977                         clock-names = "iface", "core", "vcodec0_core";
3978
3979                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
3980                                         <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
3981                         interconnect-names = "cpu-cfg", "video-mem";
3982
3983                         iommus = <&apps_smmu 0x2100 0x0400>;
3984                         memory-region = <&video_mem>;
3985
3986                         resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
3987                                  <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
3988                         reset-names = "bus", "core";
3989
3990                         status = "disabled";
3991
3992                         video-decoder {
3993                                 compatible = "venus-decoder";
3994                         };
3995
3996                         video-encoder {
3997                                 compatible = "venus-encoder";
3998                         };
3999
4000                         venus_opp_table: opp-table {
4001                                 compatible = "operating-points-v2";
4002
4003                                 opp-720000000 {
4004                                         opp-hz = /bits/ 64 <720000000>;
4005                                         required-opps = <&rpmhpd_opp_low_svs>;
4006                                 };
4007
4008                                 opp-1014000000 {
4009                                         opp-hz = /bits/ 64 <1014000000>;
4010                                         required-opps = <&rpmhpd_opp_svs>;
4011                                 };
4012
4013                                 opp-1098000000 {
4014                                         opp-hz = /bits/ 64 <1098000000>;
4015                                         required-opps = <&rpmhpd_opp_svs_l1>;
4016                                 };
4017
4018                                 opp-1332000000 {
4019                                         opp-hz = /bits/ 64 <1332000000>;
4020                                         required-opps = <&rpmhpd_opp_nom>;
4021                                 };
4022                         };
4023                 };
4024
4025                 videocc: clock-controller@abf0000 {
4026                         compatible = "qcom,sm8250-videocc";
4027                         reg = <0 0x0abf0000 0 0x10000>;
4028                         clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4029                                  <&rpmhcc RPMH_CXO_CLK>,
4030                                  <&rpmhcc RPMH_CXO_CLK_A>;
4031                         power-domains = <&rpmhpd RPMHPD_MMCX>;
4032                         required-opps = <&rpmhpd_opp_low_svs>;
4033                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4034                         #clock-cells = <1>;
4035                         #reset-cells = <1>;
4036                         #power-domain-cells = <1>;
4037                 };
4038
4039                 cci0: cci@ac4f000 {
4040                         compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4041                         #address-cells = <1>;
4042                         #size-cells = <0>;
4043
4044                         reg = <0 0x0ac4f000 0 0x1000>;
4045                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4046                         power-domains = <&camcc TITAN_TOP_GDSC>;
4047
4048                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4049                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4050                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
4051                                  <&camcc CAM_CC_CCI_0_CLK>,
4052                                  <&camcc CAM_CC_CCI_0_CLK_SRC>;
4053                         clock-names = "camnoc_axi",
4054                                       "slow_ahb_src",
4055                                       "cpas_ahb",
4056                                       "cci",
4057                                       "cci_src";
4058
4059                         pinctrl-0 = <&cci0_default>;
4060                         pinctrl-1 = <&cci0_sleep>;
4061                         pinctrl-names = "default", "sleep";
4062
4063                         status = "disabled";
4064
4065                         cci0_i2c0: i2c-bus@0 {
4066                                 reg = <0>;
4067                                 clock-frequency = <1000000>;
4068                                 #address-cells = <1>;
4069                                 #size-cells = <0>;
4070                         };
4071
4072                         cci0_i2c1: i2c-bus@1 {
4073                                 reg = <1>;
4074                                 clock-frequency = <1000000>;
4075                                 #address-cells = <1>;
4076                                 #size-cells = <0>;
4077                         };
4078                 };
4079
4080                 cci1: cci@ac50000 {
4081                         compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4082                         #address-cells = <1>;
4083                         #size-cells = <0>;
4084
4085                         reg = <0 0x0ac50000 0 0x1000>;
4086                         interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4087                         power-domains = <&camcc TITAN_TOP_GDSC>;
4088
4089                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4090                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4091                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
4092                                  <&camcc CAM_CC_CCI_1_CLK>,
4093                                  <&camcc CAM_CC_CCI_1_CLK_SRC>;
4094                         clock-names = "camnoc_axi",
4095                                       "slow_ahb_src",
4096                                       "cpas_ahb",
4097                                       "cci",
4098                                       "cci_src";
4099
4100                         pinctrl-0 = <&cci1_default>;
4101                         pinctrl-1 = <&cci1_sleep>;
4102                         pinctrl-names = "default", "sleep";
4103
4104                         status = "disabled";
4105
4106                         cci1_i2c0: i2c-bus@0 {
4107                                 reg = <0>;
4108                                 clock-frequency = <1000000>;
4109                                 #address-cells = <1>;
4110                                 #size-cells = <0>;
4111                         };
4112
4113                         cci1_i2c1: i2c-bus@1 {
4114                                 reg = <1>;
4115                                 clock-frequency = <1000000>;
4116                                 #address-cells = <1>;
4117                                 #size-cells = <0>;
4118                         };
4119                 };
4120
4121                 camss: camss@ac6a000 {
4122                         compatible = "qcom,sm8250-camss";
4123                         status = "disabled";
4124
4125                         reg = <0 0x0ac6a000 0 0x2000>,
4126                               <0 0x0ac6c000 0 0x2000>,
4127                               <0 0x0ac6e000 0 0x1000>,
4128                               <0 0x0ac70000 0 0x1000>,
4129                               <0 0x0ac72000 0 0x1000>,
4130                               <0 0x0ac74000 0 0x1000>,
4131                               <0 0x0acb4000 0 0xd000>,
4132                               <0 0x0acc3000 0 0xd000>,
4133                               <0 0x0acd9000 0 0x2200>,
4134                               <0 0x0acdb200 0 0x2200>;
4135                         reg-names = "csiphy0",
4136                                     "csiphy1",
4137                                     "csiphy2",
4138                                     "csiphy3",
4139                                     "csiphy4",
4140                                     "csiphy5",
4141                                     "vfe0",
4142                                     "vfe1",
4143                                     "vfe_lite0",
4144                                     "vfe_lite1";
4145
4146                         interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4147                                      <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4148                                      <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4149                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4150                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4151                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4152                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4153                                      <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4154                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4155                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4156                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4157                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4158                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4159                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4160                         interrupt-names = "csiphy0",
4161                                           "csiphy1",
4162                                           "csiphy2",
4163                                           "csiphy3",
4164                                           "csiphy4",
4165                                           "csiphy5",
4166                                           "csid0",
4167                                           "csid1",
4168                                           "csid2",
4169                                           "csid3",
4170                                           "vfe0",
4171                                           "vfe1",
4172                                           "vfe_lite0",
4173                                           "vfe_lite1";
4174
4175                         power-domains = <&camcc IFE_0_GDSC>,
4176                                         <&camcc IFE_1_GDSC>,
4177                                         <&camcc TITAN_TOP_GDSC>;
4178
4179                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4180                                  <&gcc GCC_CAMERA_HF_AXI_CLK>,
4181                                  <&gcc GCC_CAMERA_SF_AXI_CLK>,
4182                                  <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4183                                  <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4184                                  <&camcc CAM_CC_CORE_AHB_CLK>,
4185                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
4186                                  <&camcc CAM_CC_CSIPHY0_CLK>,
4187                                  <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4188                                  <&camcc CAM_CC_CSIPHY1_CLK>,
4189                                  <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4190                                  <&camcc CAM_CC_CSIPHY2_CLK>,
4191                                  <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4192                                  <&camcc CAM_CC_CSIPHY3_CLK>,
4193                                  <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4194                                  <&camcc CAM_CC_CSIPHY4_CLK>,
4195                                  <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4196                                  <&camcc CAM_CC_CSIPHY5_CLK>,
4197                                  <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4198                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4199                                  <&camcc CAM_CC_IFE_0_AHB_CLK>,
4200                                  <&camcc CAM_CC_IFE_0_AXI_CLK>,
4201                                  <&camcc CAM_CC_IFE_0_CLK>,
4202                                  <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4203                                  <&camcc CAM_CC_IFE_0_CSID_CLK>,
4204                                  <&camcc CAM_CC_IFE_0_AREG_CLK>,
4205                                  <&camcc CAM_CC_IFE_1_AHB_CLK>,
4206                                  <&camcc CAM_CC_IFE_1_AXI_CLK>,
4207                                  <&camcc CAM_CC_IFE_1_CLK>,
4208                                  <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4209                                  <&camcc CAM_CC_IFE_1_CSID_CLK>,
4210                                  <&camcc CAM_CC_IFE_1_AREG_CLK>,
4211                                  <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4212                                  <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4213                                  <&camcc CAM_CC_IFE_LITE_CLK>,
4214                                  <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4215                                  <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4216
4217                         clock-names = "cam_ahb_clk",
4218                                       "cam_hf_axi",
4219                                       "cam_sf_axi",
4220                                       "camnoc_axi",
4221                                       "camnoc_axi_src",
4222                                       "core_ahb",
4223                                       "cpas_ahb",
4224                                       "csiphy0",
4225                                       "csiphy0_timer",
4226                                       "csiphy1",
4227                                       "csiphy1_timer",
4228                                       "csiphy2",
4229                                       "csiphy2_timer",
4230                                       "csiphy3",
4231                                       "csiphy3_timer",
4232                                       "csiphy4",
4233                                       "csiphy4_timer",
4234                                       "csiphy5",
4235                                       "csiphy5_timer",
4236                                       "slow_ahb_src",
4237                                       "vfe0_ahb",
4238                                       "vfe0_axi",
4239                                       "vfe0",
4240                                       "vfe0_cphy_rx",
4241                                       "vfe0_csid",
4242                                       "vfe0_areg",
4243                                       "vfe1_ahb",
4244                                       "vfe1_axi",
4245                                       "vfe1",
4246                                       "vfe1_cphy_rx",
4247                                       "vfe1_csid",
4248                                       "vfe1_areg",
4249                                       "vfe_lite_ahb",
4250                                       "vfe_lite_axi",
4251                                       "vfe_lite",
4252                                       "vfe_lite_cphy_rx",
4253                                       "vfe_lite_csid";
4254
4255                         iommus = <&apps_smmu 0x800 0x400>,
4256                                  <&apps_smmu 0x801 0x400>,
4257                                  <&apps_smmu 0x840 0x400>,
4258                                  <&apps_smmu 0x841 0x400>,
4259                                  <&apps_smmu 0xc00 0x400>,
4260                                  <&apps_smmu 0xc01 0x400>,
4261                                  <&apps_smmu 0xc40 0x400>,
4262                                  <&apps_smmu 0xc41 0x400>;
4263
4264                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4265                                         <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4266                                         <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4267                                         <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4268                         interconnect-names = "cam_ahb",
4269                                              "cam_hf_0_mnoc",
4270                                              "cam_sf_0_mnoc",
4271                                              "cam_sf_icp_mnoc";
4272
4273                         ports {
4274                                 #address-cells = <1>;
4275                                 #size-cells = <0>;
4276
4277                                 port@0 {
4278                                         reg = <0>;
4279                                 };
4280
4281                                 port@1 {
4282                                         reg = <1>;
4283                                 };
4284
4285                                 port@2 {
4286                                         reg = <2>;
4287                                 };
4288
4289                                 port@3 {
4290                                         reg = <3>;
4291                                 };
4292
4293                                 port@4 {
4294                                         reg = <4>;
4295                                 };
4296
4297                                 port@5 {
4298                                         reg = <5>;
4299                                 };
4300                         };
4301                 };
4302
4303                 camcc: clock-controller@ad00000 {
4304                         compatible = "qcom,sm8250-camcc";
4305                         reg = <0 0x0ad00000 0 0x10000>;
4306                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4307                                  <&rpmhcc RPMH_CXO_CLK>,
4308                                  <&rpmhcc RPMH_CXO_CLK_A>,
4309                                  <&sleep_clk>;
4310                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4311                         power-domains = <&rpmhpd RPMHPD_MMCX>;
4312                         required-opps = <&rpmhpd_opp_low_svs>;
4313                         status = "disabled";
4314                         #clock-cells = <1>;
4315                         #reset-cells = <1>;
4316                         #power-domain-cells = <1>;
4317                 };
4318
4319                 mdss: display-subsystem@ae00000 {
4320                         compatible = "qcom,sm8250-mdss";
4321                         reg = <0 0x0ae00000 0 0x1000>;
4322                         reg-names = "mdss";
4323
4324                         interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4325                                         <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4326                         interconnect-names = "mdp0-mem", "mdp1-mem";
4327
4328                         power-domains = <&dispcc MDSS_GDSC>;
4329
4330                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4331                                  <&gcc GCC_DISP_HF_AXI_CLK>,
4332                                  <&gcc GCC_DISP_SF_AXI_CLK>,
4333                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
4334                         clock-names = "iface", "bus", "nrt_bus", "core";
4335
4336                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4337                         interrupt-controller;
4338                         #interrupt-cells = <1>;
4339
4340                         iommus = <&apps_smmu 0x820 0x402>;
4341
4342                         status = "disabled";
4343
4344                         #address-cells = <2>;
4345                         #size-cells = <2>;
4346                         ranges;
4347
4348                         mdss_mdp: display-controller@ae01000 {
4349                                 compatible = "qcom,sm8250-dpu";
4350                                 reg = <0 0x0ae01000 0 0x8f000>,
4351                                       <0 0x0aeb0000 0 0x2008>;
4352                                 reg-names = "mdp", "vbif";
4353
4354                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4355                                          <&gcc GCC_DISP_HF_AXI_CLK>,
4356                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
4357                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4358                                 clock-names = "iface", "bus", "core", "vsync";
4359
4360                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4361                                 assigned-clock-rates = <19200000>;
4362
4363                                 operating-points-v2 = <&mdp_opp_table>;
4364                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
4365
4366                                 interrupt-parent = <&mdss>;
4367                                 interrupts = <0>;
4368
4369                                 ports {
4370                                         #address-cells = <1>;
4371                                         #size-cells = <0>;
4372
4373                                         port@0 {
4374                                                 reg = <0>;
4375                                                 dpu_intf1_out: endpoint {
4376                                                         remote-endpoint = <&mdss_dsi0_in>;
4377                                                 };
4378                                         };
4379
4380                                         port@1 {
4381                                                 reg = <1>;
4382                                                 dpu_intf2_out: endpoint {
4383                                                         remote-endpoint = <&mdss_dsi1_in>;
4384                                                 };
4385                                         };
4386                                 };
4387
4388                                 mdp_opp_table: opp-table {
4389                                         compatible = "operating-points-v2";
4390
4391                                         opp-200000000 {
4392                                                 opp-hz = /bits/ 64 <200000000>;
4393                                                 required-opps = <&rpmhpd_opp_low_svs>;
4394                                         };
4395
4396                                         opp-300000000 {
4397                                                 opp-hz = /bits/ 64 <300000000>;
4398                                                 required-opps = <&rpmhpd_opp_svs>;
4399                                         };
4400
4401                                         opp-345000000 {
4402                                                 opp-hz = /bits/ 64 <345000000>;
4403                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4404                                         };
4405
4406                                         opp-460000000 {
4407                                                 opp-hz = /bits/ 64 <460000000>;
4408                                                 required-opps = <&rpmhpd_opp_nom>;
4409                                         };
4410                                 };
4411                         };
4412
4413                         mdss_dsi0: dsi@ae94000 {
4414                                 compatible = "qcom,sm8250-dsi-ctrl",
4415                                              "qcom,mdss-dsi-ctrl";
4416                                 reg = <0 0x0ae94000 0 0x400>;
4417                                 reg-names = "dsi_ctrl";
4418
4419                                 interrupt-parent = <&mdss>;
4420                                 interrupts = <4>;
4421
4422                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4423                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4424                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4425                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4426                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4427                                         <&gcc GCC_DISP_HF_AXI_CLK>;
4428                                 clock-names = "byte",
4429                                               "byte_intf",
4430                                               "pixel",
4431                                               "core",
4432                                               "iface",
4433                                               "bus";
4434
4435                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4436                                 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4437
4438                                 operating-points-v2 = <&dsi_opp_table>;
4439                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
4440
4441                                 phys = <&mdss_dsi0_phy>;
4442
4443                                 status = "disabled";
4444
4445                                 #address-cells = <1>;
4446                                 #size-cells = <0>;
4447
4448                                 ports {
4449                                         #address-cells = <1>;
4450                                         #size-cells = <0>;
4451
4452                                         port@0 {
4453                                                 reg = <0>;
4454                                                 mdss_dsi0_in: endpoint {
4455                                                         remote-endpoint = <&dpu_intf1_out>;
4456                                                 };
4457                                         };
4458
4459                                         port@1 {
4460                                                 reg = <1>;
4461                                                 mdss_dsi0_out: endpoint {
4462                                                 };
4463                                         };
4464                                 };
4465
4466                                 dsi_opp_table: opp-table {
4467                                         compatible = "operating-points-v2";
4468
4469                                         opp-187500000 {
4470                                                 opp-hz = /bits/ 64 <187500000>;
4471                                                 required-opps = <&rpmhpd_opp_low_svs>;
4472                                         };
4473
4474                                         opp-300000000 {
4475                                                 opp-hz = /bits/ 64 <300000000>;
4476                                                 required-opps = <&rpmhpd_opp_svs>;
4477                                         };
4478
4479                                         opp-358000000 {
4480                                                 opp-hz = /bits/ 64 <358000000>;
4481                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4482                                         };
4483                                 };
4484                         };
4485
4486                         mdss_dsi0_phy: phy@ae94400 {
4487                                 compatible = "qcom,dsi-phy-7nm";
4488                                 reg = <0 0x0ae94400 0 0x200>,
4489                                       <0 0x0ae94600 0 0x280>,
4490                                       <0 0x0ae94900 0 0x260>;
4491                                 reg-names = "dsi_phy",
4492                                             "dsi_phy_lane",
4493                                             "dsi_pll";
4494
4495                                 #clock-cells = <1>;
4496                                 #phy-cells = <0>;
4497
4498                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4499                                          <&rpmhcc RPMH_CXO_CLK>;
4500                                 clock-names = "iface", "ref";
4501
4502                                 status = "disabled";
4503                         };
4504
4505                         mdss_dsi1: dsi@ae96000 {
4506                                 compatible = "qcom,sm8250-dsi-ctrl",
4507                                              "qcom,mdss-dsi-ctrl";
4508                                 reg = <0 0x0ae96000 0 0x400>;
4509                                 reg-names = "dsi_ctrl";
4510
4511                                 interrupt-parent = <&mdss>;
4512                                 interrupts = <5>;
4513
4514                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4515                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4516                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4517                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4518                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4519                                          <&gcc GCC_DISP_HF_AXI_CLK>;
4520                                 clock-names = "byte",
4521                                               "byte_intf",
4522                                               "pixel",
4523                                               "core",
4524                                               "iface",
4525                                               "bus";
4526
4527                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4528                                 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4529
4530                                 operating-points-v2 = <&dsi_opp_table>;
4531                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
4532
4533                                 phys = <&mdss_dsi1_phy>;
4534
4535                                 status = "disabled";
4536
4537                                 #address-cells = <1>;
4538                                 #size-cells = <0>;
4539
4540                                 ports {
4541                                         #address-cells = <1>;
4542                                         #size-cells = <0>;
4543
4544                                         port@0 {
4545                                                 reg = <0>;
4546                                                 mdss_dsi1_in: endpoint {
4547                                                         remote-endpoint = <&dpu_intf2_out>;
4548                                                 };
4549                                         };
4550
4551                                         port@1 {
4552                                                 reg = <1>;
4553                                                 mdss_dsi1_out: endpoint {
4554                                                 };
4555                                         };
4556                                 };
4557                         };
4558
4559                         mdss_dsi1_phy: phy@ae96400 {
4560                                 compatible = "qcom,dsi-phy-7nm";
4561                                 reg = <0 0x0ae96400 0 0x200>,
4562                                       <0 0x0ae96600 0 0x280>,
4563                                       <0 0x0ae96900 0 0x260>;
4564                                 reg-names = "dsi_phy",
4565                                             "dsi_phy_lane",
4566                                             "dsi_pll";
4567
4568                                 #clock-cells = <1>;
4569                                 #phy-cells = <0>;
4570
4571                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4572                                          <&rpmhcc RPMH_CXO_CLK>;
4573                                 clock-names = "iface", "ref";
4574
4575                                 status = "disabled";
4576                         };
4577                 };
4578
4579                 dispcc: clock-controller@af00000 {
4580                         compatible = "qcom,sm8250-dispcc";
4581                         reg = <0 0x0af00000 0 0x10000>;
4582                         power-domains = <&rpmhpd RPMHPD_MMCX>;
4583                         required-opps = <&rpmhpd_opp_low_svs>;
4584                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4585                                  <&mdss_dsi0_phy 0>,
4586                                  <&mdss_dsi0_phy 1>,
4587                                  <&mdss_dsi1_phy 0>,
4588                                  <&mdss_dsi1_phy 1>,
4589                                  <&dp_phy 0>,
4590                                  <&dp_phy 1>;
4591                         clock-names = "bi_tcxo",
4592                                       "dsi0_phy_pll_out_byteclk",
4593                                       "dsi0_phy_pll_out_dsiclk",
4594                                       "dsi1_phy_pll_out_byteclk",
4595                                       "dsi1_phy_pll_out_dsiclk",
4596                                       "dp_phy_pll_link_clk",
4597                                       "dp_phy_pll_vco_div_clk";
4598                         #clock-cells = <1>;
4599                         #reset-cells = <1>;
4600                         #power-domain-cells = <1>;
4601                 };
4602
4603                 pdc: interrupt-controller@b220000 {
4604                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
4605                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4606                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4607                                           <125 63 1>, <126 716 12>;
4608                         #interrupt-cells = <2>;
4609                         interrupt-parent = <&intc>;
4610                         interrupt-controller;
4611                 };
4612
4613                 tsens0: thermal-sensor@c263000 {
4614                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4615                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4616                               <0 0x0c222000 0 0x1ff>; /* SROT */
4617                         #qcom,sensors = <16>;
4618                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4619                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4620                         interrupt-names = "uplow", "critical";
4621                         #thermal-sensor-cells = <1>;
4622                 };
4623
4624                 tsens1: thermal-sensor@c265000 {
4625                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4626                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4627                               <0 0x0c223000 0 0x1ff>; /* SROT */
4628                         #qcom,sensors = <9>;
4629                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4630                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4631                         interrupt-names = "uplow", "critical";
4632                         #thermal-sensor-cells = <1>;
4633                 };
4634
4635                 aoss_qmp: power-management@c300000 {
4636                         compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
4637                         reg = <0 0x0c300000 0 0x400>;
4638                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4639                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
4640                                                      IRQ_TYPE_EDGE_RISING>;
4641                         mboxes = <&ipcc IPCC_CLIENT_AOP
4642                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
4643
4644                         #clock-cells = <0>;
4645                 };
4646
4647                 sram@c3f0000 {
4648                         compatible = "qcom,rpmh-stats";
4649                         reg = <0 0x0c3f0000 0 0x400>;
4650                 };
4651
4652                 spmi_bus: spmi@c440000 {
4653                         compatible = "qcom,spmi-pmic-arb";
4654                         reg = <0x0 0x0c440000 0x0 0x0001100>,
4655                               <0x0 0x0c600000 0x0 0x2000000>,
4656                               <0x0 0x0e600000 0x0 0x0100000>,
4657                               <0x0 0x0e700000 0x0 0x00a0000>,
4658                               <0x0 0x0c40a000 0x0 0x0026000>;
4659                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4660                         interrupt-names = "periph_irq";
4661                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4662                         qcom,ee = <0>;
4663                         qcom,channel = <0>;
4664                         #address-cells = <2>;
4665                         #size-cells = <0>;
4666                         interrupt-controller;
4667                         #interrupt-cells = <4>;
4668                 };
4669
4670                 tlmm: pinctrl@f100000 {
4671                         compatible = "qcom,sm8250-pinctrl";
4672                         reg = <0 0x0f100000 0 0x300000>,
4673                               <0 0x0f500000 0 0x300000>,
4674                               <0 0x0f900000 0 0x300000>;
4675                         reg-names = "west", "south", "north";
4676                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4677                         gpio-controller;
4678                         #gpio-cells = <2>;
4679                         interrupt-controller;
4680                         #interrupt-cells = <2>;
4681                         gpio-ranges = <&tlmm 0 0 181>;
4682                         wakeup-parent = <&pdc>;
4683
4684                         cam2_default: cam2-default-state {
4685                                 rst-pins {
4686                                         pins = "gpio78";
4687                                         function = "gpio";
4688                                         drive-strength = <2>;
4689                                         bias-disable;
4690                                 };
4691
4692                                 mclk-pins {
4693                                         pins = "gpio96";
4694                                         function = "cam_mclk";
4695                                         drive-strength = <16>;
4696                                         bias-disable;
4697                                 };
4698                         };
4699
4700                         cam2_suspend: cam2-suspend-state {
4701                                 rst-pins {
4702                                         pins = "gpio78";
4703                                         function = "gpio";
4704                                         drive-strength = <2>;
4705                                         bias-pull-down;
4706                                         output-low;
4707                                 };
4708
4709                                 mclk-pins {
4710                                         pins = "gpio96";
4711                                         function = "cam_mclk";
4712                                         drive-strength = <2>;
4713                                         bias-disable;
4714                                 };
4715                         };
4716
4717                         cci0_default: cci0-default-state {
4718                                 cci0_i2c0_default: cci0-i2c0-default-pins {
4719                                         /* SDA, SCL */
4720                                         pins = "gpio101", "gpio102";
4721                                         function = "cci_i2c";
4722
4723                                         bias-pull-up;
4724                                         drive-strength = <2>; /* 2 mA */
4725                                 };
4726
4727                                 cci0_i2c1_default: cci0-i2c1-default-pins {
4728                                         /* SDA, SCL */
4729                                         pins = "gpio103", "gpio104";
4730                                         function = "cci_i2c";
4731
4732                                         bias-pull-up;
4733                                         drive-strength = <2>; /* 2 mA */
4734                                 };
4735                         };
4736
4737                         cci0_sleep: cci0-sleep-state {
4738                                 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
4739                                         /* SDA, SCL */
4740                                         pins = "gpio101", "gpio102";
4741                                         function = "cci_i2c";
4742
4743                                         drive-strength = <2>; /* 2 mA */
4744                                         bias-pull-down;
4745                                 };
4746
4747                                 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
4748                                         /* SDA, SCL */
4749                                         pins = "gpio103", "gpio104";
4750                                         function = "cci_i2c";
4751
4752                                         drive-strength = <2>; /* 2 mA */
4753                                         bias-pull-down;
4754                                 };
4755                         };
4756
4757                         cci1_default: cci1-default-state {
4758                                 cci1_i2c0_default: cci1-i2c0-default-pins {
4759                                         /* SDA, SCL */
4760                                         pins = "gpio105","gpio106";
4761                                         function = "cci_i2c";
4762
4763                                         bias-pull-up;
4764                                         drive-strength = <2>; /* 2 mA */
4765                                 };
4766
4767                                 cci1_i2c1_default: cci1-i2c1-default-pins {
4768                                         /* SDA, SCL */
4769                                         pins = "gpio107","gpio108";
4770                                         function = "cci_i2c";
4771
4772                                         bias-pull-up;
4773                                         drive-strength = <2>; /* 2 mA */
4774                                 };
4775                         };
4776
4777                         cci1_sleep: cci1-sleep-state {
4778                                 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
4779                                         /* SDA, SCL */
4780                                         pins = "gpio105","gpio106";
4781                                         function = "cci_i2c";
4782
4783                                         bias-pull-down;
4784                                         drive-strength = <2>; /* 2 mA */
4785                                 };
4786
4787                                 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
4788                                         /* SDA, SCL */
4789                                         pins = "gpio107","gpio108";
4790                                         function = "cci_i2c";
4791
4792                                         bias-pull-down;
4793                                         drive-strength = <2>; /* 2 mA */
4794                                 };
4795                         };
4796
4797                         pri_mi2s_active: pri-mi2s-active-state {
4798                                 sclk-pins {
4799                                         pins = "gpio138";
4800                                         function = "mi2s0_sck";
4801                                         drive-strength = <8>;
4802                                         bias-disable;
4803                                 };
4804
4805                                 ws-pins {
4806                                         pins = "gpio141";
4807                                         function = "mi2s0_ws";
4808                                         drive-strength = <8>;
4809                                         output-high;
4810                                 };
4811
4812                                 data0-pins {
4813                                         pins = "gpio139";
4814                                         function = "mi2s0_data0";
4815                                         drive-strength = <8>;
4816                                         bias-disable;
4817                                         output-high;
4818                                 };
4819
4820                                 data1-pins {
4821                                         pins = "gpio140";
4822                                         function = "mi2s0_data1";
4823                                         drive-strength = <8>;
4824                                         output-high;
4825                                 };
4826                         };
4827
4828                         qup_i2c0_default: qup-i2c0-default-state {
4829                                 pins = "gpio28", "gpio29";
4830                                 function = "qup0";
4831                                 drive-strength = <2>;
4832                                 bias-disable;
4833                         };
4834
4835                         qup_i2c1_default: qup-i2c1-default-state {
4836                                 pins = "gpio4", "gpio5";
4837                                 function = "qup1";
4838                                 drive-strength = <2>;
4839                                 bias-disable;
4840                         };
4841
4842                         qup_i2c2_default: qup-i2c2-default-state {
4843                                 pins = "gpio115", "gpio116";
4844                                 function = "qup2";
4845                                 drive-strength = <2>;
4846                                 bias-disable;
4847                         };
4848
4849                         qup_i2c3_default: qup-i2c3-default-state {
4850                                 pins = "gpio119", "gpio120";
4851                                 function = "qup3";
4852                                 drive-strength = <2>;
4853                                 bias-disable;
4854                         };
4855
4856                         qup_i2c4_default: qup-i2c4-default-state {
4857                                 pins = "gpio8", "gpio9";
4858                                 function = "qup4";
4859                                 drive-strength = <2>;
4860                                 bias-disable;
4861                         };
4862
4863                         qup_i2c5_default: qup-i2c5-default-state {
4864                                 pins = "gpio12", "gpio13";
4865                                 function = "qup5";
4866                                 drive-strength = <2>;
4867                                 bias-disable;
4868                         };
4869
4870                         qup_i2c6_default: qup-i2c6-default-state {
4871                                 pins = "gpio16", "gpio17";
4872                                 function = "qup6";
4873                                 drive-strength = <2>;
4874                                 bias-disable;
4875                         };
4876
4877                         qup_i2c7_default: qup-i2c7-default-state {
4878                                 pins = "gpio20", "gpio21";
4879                                 function = "qup7";
4880                                 drive-strength = <2>;
4881                                 bias-disable;
4882                         };
4883
4884                         qup_i2c8_default: qup-i2c8-default-state {
4885                                 pins = "gpio24", "gpio25";
4886                                 function = "qup8";
4887                                 drive-strength = <2>;
4888                                 bias-disable;
4889                         };
4890
4891                         qup_i2c9_default: qup-i2c9-default-state {
4892                                 pins = "gpio125", "gpio126";
4893                                 function = "qup9";
4894                                 drive-strength = <2>;
4895                                 bias-disable;
4896                         };
4897
4898                         qup_i2c10_default: qup-i2c10-default-state {
4899                                 pins = "gpio129", "gpio130";
4900                                 function = "qup10";
4901                                 drive-strength = <2>;
4902                                 bias-disable;
4903                         };
4904
4905                         qup_i2c11_default: qup-i2c11-default-state {
4906                                 pins = "gpio60", "gpio61";
4907                                 function = "qup11";
4908                                 drive-strength = <2>;
4909                                 bias-disable;
4910                         };
4911
4912                         qup_i2c12_default: qup-i2c12-default-state {
4913                                 pins = "gpio32", "gpio33";
4914                                 function = "qup12";
4915                                 drive-strength = <2>;
4916                                 bias-disable;
4917                         };
4918
4919                         qup_i2c13_default: qup-i2c13-default-state {
4920                                 pins = "gpio36", "gpio37";
4921                                 function = "qup13";
4922                                 drive-strength = <2>;
4923                                 bias-disable;
4924                         };
4925
4926                         qup_i2c14_default: qup-i2c14-default-state {
4927                                 pins = "gpio40", "gpio41";
4928                                 function = "qup14";
4929                                 drive-strength = <2>;
4930                                 bias-disable;
4931                         };
4932
4933                         qup_i2c15_default: qup-i2c15-default-state {
4934                                 pins = "gpio44", "gpio45";
4935                                 function = "qup15";
4936                                 drive-strength = <2>;
4937                                 bias-disable;
4938                         };
4939
4940                         qup_i2c16_default: qup-i2c16-default-state {
4941                                 pins = "gpio48", "gpio49";
4942                                 function = "qup16";
4943                                 drive-strength = <2>;
4944                                 bias-disable;
4945                         };
4946
4947                         qup_i2c17_default: qup-i2c17-default-state {
4948                                 pins = "gpio52", "gpio53";
4949                                 function = "qup17";
4950                                 drive-strength = <2>;
4951                                 bias-disable;
4952                         };
4953
4954                         qup_i2c18_default: qup-i2c18-default-state {
4955                                 pins = "gpio56", "gpio57";
4956                                 function = "qup18";
4957                                 drive-strength = <2>;
4958                                 bias-disable;
4959                         };
4960
4961                         qup_i2c19_default: qup-i2c19-default-state {
4962                                 pins = "gpio0", "gpio1";
4963                                 function = "qup19";
4964                                 drive-strength = <2>;
4965                                 bias-disable;
4966                         };
4967
4968                         qup_spi0_cs: qup-spi0-cs-state {
4969                                 pins = "gpio31";
4970                                 function = "qup0";
4971                         };
4972
4973                         qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
4974                                 pins = "gpio31";
4975                                 function = "gpio";
4976                         };
4977
4978                         qup_spi0_data_clk: qup-spi0-data-clk-state {
4979                                 pins = "gpio28", "gpio29",
4980                                        "gpio30";
4981                                 function = "qup0";
4982                         };
4983
4984                         qup_spi1_cs: qup-spi1-cs-state {
4985                                 pins = "gpio7";
4986                                 function = "qup1";
4987                         };
4988
4989                         qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
4990                                 pins = "gpio7";
4991                                 function = "gpio";
4992                         };
4993
4994                         qup_spi1_data_clk: qup-spi1-data-clk-state {
4995                                 pins = "gpio4", "gpio5",
4996                                        "gpio6";
4997                                 function = "qup1";
4998                         };
4999
5000                         qup_spi2_cs: qup-spi2-cs-state {
5001                                 pins = "gpio118";
5002                                 function = "qup2";
5003                         };
5004
5005                         qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5006                                 pins = "gpio118";
5007                                 function = "gpio";
5008                         };
5009
5010                         qup_spi2_data_clk: qup-spi2-data-clk-state {
5011                                 pins = "gpio115", "gpio116",
5012                                        "gpio117";
5013                                 function = "qup2";
5014                         };
5015
5016                         qup_spi3_cs: qup-spi3-cs-state {
5017                                 pins = "gpio122";
5018                                 function = "qup3";
5019                         };
5020
5021                         qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5022                                 pins = "gpio122";
5023                                 function = "gpio";
5024                         };
5025
5026                         qup_spi3_data_clk: qup-spi3-data-clk-state {
5027                                 pins = "gpio119", "gpio120",
5028                                        "gpio121";
5029                                 function = "qup3";
5030                         };
5031
5032                         qup_spi4_cs: qup-spi4-cs-state {
5033                                 pins = "gpio11";
5034                                 function = "qup4";
5035                         };
5036
5037                         qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5038                                 pins = "gpio11";
5039                                 function = "gpio";
5040                         };
5041
5042                         qup_spi4_data_clk: qup-spi4-data-clk-state {
5043                                 pins = "gpio8", "gpio9",
5044                                        "gpio10";
5045                                 function = "qup4";
5046                         };
5047
5048                         qup_spi5_cs: qup-spi5-cs-state {
5049                                 pins = "gpio15";
5050                                 function = "qup5";
5051                         };
5052
5053                         qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5054                                 pins = "gpio15";
5055                                 function = "gpio";
5056                         };
5057
5058                         qup_spi5_data_clk: qup-spi5-data-clk-state {
5059                                 pins = "gpio12", "gpio13",
5060                                        "gpio14";
5061                                 function = "qup5";
5062                         };
5063
5064                         qup_spi6_cs: qup-spi6-cs-state {
5065                                 pins = "gpio19";
5066                                 function = "qup6";
5067                         };
5068
5069                         qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5070                                 pins = "gpio19";
5071                                 function = "gpio";
5072                         };
5073
5074                         qup_spi6_data_clk: qup-spi6-data-clk-state {
5075                                 pins = "gpio16", "gpio17",
5076                                        "gpio18";
5077                                 function = "qup6";
5078                         };
5079
5080                         qup_spi7_cs: qup-spi7-cs-state {
5081                                 pins = "gpio23";
5082                                 function = "qup7";
5083                         };
5084
5085                         qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5086                                 pins = "gpio23";
5087                                 function = "gpio";
5088                         };
5089
5090                         qup_spi7_data_clk: qup-spi7-data-clk-state {
5091                                 pins = "gpio20", "gpio21",
5092                                        "gpio22";
5093                                 function = "qup7";
5094                         };
5095
5096                         qup_spi8_cs: qup-spi8-cs-state {
5097                                 pins = "gpio27";
5098                                 function = "qup8";
5099                         };
5100
5101                         qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5102                                 pins = "gpio27";
5103                                 function = "gpio";
5104                         };
5105
5106                         qup_spi8_data_clk: qup-spi8-data-clk-state {
5107                                 pins = "gpio24", "gpio25",
5108                                        "gpio26";
5109                                 function = "qup8";
5110                         };
5111
5112                         qup_spi9_cs: qup-spi9-cs-state {
5113                                 pins = "gpio128";
5114                                 function = "qup9";
5115                         };
5116
5117                         qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5118                                 pins = "gpio128";
5119                                 function = "gpio";
5120                         };
5121
5122                         qup_spi9_data_clk: qup-spi9-data-clk-state {
5123                                 pins = "gpio125", "gpio126",
5124                                        "gpio127";
5125                                 function = "qup9";
5126                         };
5127
5128                         qup_spi10_cs: qup-spi10-cs-state {
5129                                 pins = "gpio132";
5130                                 function = "qup10";
5131                         };
5132
5133                         qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5134                                 pins = "gpio132";
5135                                 function = "gpio";
5136                         };
5137
5138                         qup_spi10_data_clk: qup-spi10-data-clk-state {
5139                                 pins = "gpio129", "gpio130",
5140                                        "gpio131";
5141                                 function = "qup10";
5142                         };
5143
5144                         qup_spi11_cs: qup-spi11-cs-state {
5145                                 pins = "gpio63";
5146                                 function = "qup11";
5147                         };
5148
5149                         qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5150                                 pins = "gpio63";
5151                                 function = "gpio";
5152                         };
5153
5154                         qup_spi11_data_clk: qup-spi11-data-clk-state {
5155                                 pins = "gpio60", "gpio61",
5156                                        "gpio62";
5157                                 function = "qup11";
5158                         };
5159
5160                         qup_spi12_cs: qup-spi12-cs-state {
5161                                 pins = "gpio35";
5162                                 function = "qup12";
5163                         };
5164
5165                         qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5166                                 pins = "gpio35";
5167                                 function = "gpio";
5168                         };
5169
5170                         qup_spi12_data_clk: qup-spi12-data-clk-state {
5171                                 pins = "gpio32", "gpio33",
5172                                        "gpio34";
5173                                 function = "qup12";
5174                         };
5175
5176                         qup_spi13_cs: qup-spi13-cs-state {
5177                                 pins = "gpio39";
5178                                 function = "qup13";
5179                         };
5180
5181                         qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5182                                 pins = "gpio39";
5183                                 function = "gpio";
5184                         };
5185
5186                         qup_spi13_data_clk: qup-spi13-data-clk-state {
5187                                 pins = "gpio36", "gpio37",
5188                                        "gpio38";
5189                                 function = "qup13";
5190                         };
5191
5192                         qup_spi14_cs: qup-spi14-cs-state {
5193                                 pins = "gpio43";
5194                                 function = "qup14";
5195                         };
5196
5197                         qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5198                                 pins = "gpio43";
5199                                 function = "gpio";
5200                         };
5201
5202                         qup_spi14_data_clk: qup-spi14-data-clk-state {
5203                                 pins = "gpio40", "gpio41",
5204                                        "gpio42";
5205                                 function = "qup14";
5206                         };
5207
5208                         qup_spi15_cs: qup-spi15-cs-state {
5209                                 pins = "gpio47";
5210                                 function = "qup15";
5211                         };
5212
5213                         qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5214                                 pins = "gpio47";
5215                                 function = "gpio";
5216                         };
5217
5218                         qup_spi15_data_clk: qup-spi15-data-clk-state {
5219                                 pins = "gpio44", "gpio45",
5220                                        "gpio46";
5221                                 function = "qup15";
5222                         };
5223
5224                         qup_spi16_cs: qup-spi16-cs-state {
5225                                 pins = "gpio51";
5226                                 function = "qup16";
5227                         };
5228
5229                         qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5230                                 pins = "gpio51";
5231                                 function = "gpio";
5232                         };
5233
5234                         qup_spi16_data_clk: qup-spi16-data-clk-state {
5235                                 pins = "gpio48", "gpio49",
5236                                        "gpio50";
5237                                 function = "qup16";
5238                         };
5239
5240                         qup_spi17_cs: qup-spi17-cs-state {
5241                                 pins = "gpio55";
5242                                 function = "qup17";
5243                         };
5244
5245                         qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5246                                 pins = "gpio55";
5247                                 function = "gpio";
5248                         };
5249
5250                         qup_spi17_data_clk: qup-spi17-data-clk-state {
5251                                 pins = "gpio52", "gpio53",
5252                                        "gpio54";
5253                                 function = "qup17";
5254                         };
5255
5256                         qup_spi18_cs: qup-spi18-cs-state {
5257                                 pins = "gpio59";
5258                                 function = "qup18";
5259                         };
5260
5261                         qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5262                                 pins = "gpio59";
5263                                 function = "gpio";
5264                         };
5265
5266                         qup_spi18_data_clk: qup-spi18-data-clk-state {
5267                                 pins = "gpio56", "gpio57",
5268                                        "gpio58";
5269                                 function = "qup18";
5270                         };
5271
5272                         qup_spi19_cs: qup-spi19-cs-state {
5273                                 pins = "gpio3";
5274                                 function = "qup19";
5275                         };
5276
5277                         qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5278                                 pins = "gpio3";
5279                                 function = "gpio";
5280                         };
5281
5282                         qup_spi19_data_clk: qup-spi19-data-clk-state {
5283                                 pins = "gpio0", "gpio1",
5284                                        "gpio2";
5285                                 function = "qup19";
5286                         };
5287
5288                         qup_uart2_default: qup-uart2-default-state {
5289                                 pins = "gpio117", "gpio118";
5290                                 function = "qup2";
5291                         };
5292
5293                         qup_uart6_default: qup-uart6-default-state {
5294                                 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5295                                 function = "qup6";
5296                         };
5297
5298                         qup_uart12_default: qup-uart12-default-state {
5299                                 pins = "gpio34", "gpio35";
5300                                 function = "qup12";
5301                         };
5302
5303                         qup_uart17_default: qup-uart17-default-state {
5304                                 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5305                                 function = "qup17";
5306                         };
5307
5308                         qup_uart18_default: qup-uart18-default-state {
5309                                 pins = "gpio58", "gpio59";
5310                                 function = "qup18";
5311                         };
5312
5313                         tert_mi2s_active: tert-mi2s-active-state {
5314                                 sck-pins {
5315                                         pins = "gpio133";
5316                                         function = "mi2s2_sck";
5317                                         drive-strength = <8>;
5318                                         bias-disable;
5319                                 };
5320
5321                                 data0-pins {
5322                                         pins = "gpio134";
5323                                         function = "mi2s2_data0";
5324                                         drive-strength = <8>;
5325                                         bias-disable;
5326                                         output-high;
5327                                 };
5328
5329                                 ws-pins {
5330                                         pins = "gpio135";
5331                                         function = "mi2s2_ws";
5332                                         drive-strength = <8>;
5333                                         output-high;
5334                                 };
5335                         };
5336
5337                         sdc2_sleep_state: sdc2-sleep-state {
5338                                 clk-pins {
5339                                         pins = "sdc2_clk";
5340                                         drive-strength = <2>;
5341                                         bias-disable;
5342                                 };
5343
5344                                 cmd-pins {
5345                                         pins = "sdc2_cmd";
5346                                         drive-strength = <2>;
5347                                         bias-pull-up;
5348                                 };
5349
5350                                 data-pins {
5351                                         pins = "sdc2_data";
5352                                         drive-strength = <2>;
5353                                         bias-pull-up;
5354                                 };
5355                         };
5356
5357                         pcie0_default_state: pcie0-default-state {
5358                                 perst-pins {
5359                                         pins = "gpio79";
5360                                         function = "gpio";
5361                                         drive-strength = <2>;
5362                                         bias-pull-down;
5363                                 };
5364
5365                                 clkreq-pins {
5366                                         pins = "gpio80";
5367                                         function = "pci_e0";
5368                                         drive-strength = <2>;
5369                                         bias-pull-up;
5370                                 };
5371
5372                                 wake-pins {
5373                                         pins = "gpio81";
5374                                         function = "gpio";
5375                                         drive-strength = <2>;
5376                                         bias-pull-up;
5377                                 };
5378                         };
5379
5380                         pcie1_default_state: pcie1-default-state {
5381                                 perst-pins {
5382                                         pins = "gpio82";
5383                                         function = "gpio";
5384                                         drive-strength = <2>;
5385                                         bias-pull-down;
5386                                 };
5387
5388                                 clkreq-pins {
5389                                         pins = "gpio83";
5390                                         function = "pci_e1";
5391                                         drive-strength = <2>;
5392                                         bias-pull-up;
5393                                 };
5394
5395                                 wake-pins {
5396                                         pins = "gpio84";
5397                                         function = "gpio";
5398                                         drive-strength = <2>;
5399                                         bias-pull-up;
5400                                 };
5401                         };
5402
5403                         pcie2_default_state: pcie2-default-state {
5404                                 perst-pins {
5405                                         pins = "gpio85";
5406                                         function = "gpio";
5407                                         drive-strength = <2>;
5408                                         bias-pull-down;
5409                                 };
5410
5411                                 clkreq-pins {
5412                                         pins = "gpio86";
5413                                         function = "pci_e2";
5414                                         drive-strength = <2>;
5415                                         bias-pull-up;
5416                                 };
5417
5418                                 wake-pins {
5419                                         pins = "gpio87";
5420                                         function = "gpio";
5421                                         drive-strength = <2>;
5422                                         bias-pull-up;
5423                                 };
5424                         };
5425                 };
5426
5427                 apps_smmu: iommu@15000000 {
5428                         compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5429                         reg = <0 0x15000000 0 0x100000>;
5430                         #iommu-cells = <2>;
5431                         #global-interrupts = <2>;
5432                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5433                                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5434                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5435                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5436                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5437                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5438                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5439                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5440                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5441                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5442                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5443                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5444                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5445                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5446                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5447                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5448                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5449                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5450                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5451                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5452                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5453                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5454                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5455                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5456                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5457                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5458                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5459                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5460                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5461                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5462                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5463                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5464                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5465                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5466                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5467                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5468                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5469                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5470                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5471                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5472                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5473                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5474                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5475                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5476                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5477                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5478                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5479                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5480                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5481                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5482                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5483                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5484                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5485                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5486                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5487                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5488                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5489                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5490                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5491                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5492                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5493                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5494                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5495                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5496                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5497                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5498                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5499                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5500                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5501                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5502                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5503                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5504                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5505                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5506                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5507                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5508                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5509                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5510                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5511                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5512                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5513                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5514                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5515                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5516                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5517                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5518                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5519                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5520                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5521                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5522                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5523                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5524                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5525                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5526                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5527                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5528                                      <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5529                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5530                         dma-coherent;
5531                 };
5532
5533                 adsp: remoteproc@17300000 {
5534                         compatible = "qcom,sm8250-adsp-pas";
5535                         reg = <0 0x17300000 0 0x100>;
5536
5537                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5538                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5539                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5540                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5541                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5542                         interrupt-names = "wdog", "fatal", "ready",
5543                                           "handover", "stop-ack";
5544
5545                         clocks = <&rpmhcc RPMH_CXO_CLK>;
5546                         clock-names = "xo";
5547
5548                         power-domains = <&rpmhpd RPMHPD_LCX>,
5549                                         <&rpmhpd RPMHPD_LMX>;
5550                         power-domain-names = "lcx", "lmx";
5551
5552                         memory-region = <&adsp_mem>;
5553
5554                         qcom,qmp = <&aoss_qmp>;
5555
5556                         qcom,smem-states = <&smp2p_adsp_out 0>;
5557                         qcom,smem-state-names = "stop";
5558
5559                         status = "disabled";
5560
5561                         glink-edge {
5562                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5563                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
5564                                                              IRQ_TYPE_EDGE_RISING>;
5565                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
5566                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5567
5568                                 label = "lpass";
5569                                 qcom,remote-pid = <2>;
5570
5571                                 apr {
5572                                         compatible = "qcom,apr-v2";
5573                                         qcom,glink-channels = "apr_audio_svc";
5574                                         qcom,domain = <APR_DOMAIN_ADSP>;
5575                                         #address-cells = <1>;
5576                                         #size-cells = <0>;
5577
5578                                         service@3 {
5579                                                 reg = <APR_SVC_ADSP_CORE>;
5580                                                 compatible = "qcom,q6core";
5581                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5582                                         };
5583
5584                                         q6afe: service@4 {
5585                                                 compatible = "qcom,q6afe";
5586                                                 reg = <APR_SVC_AFE>;
5587                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5588                                                 q6afedai: dais {
5589                                                         compatible = "qcom,q6afe-dais";
5590                                                         #address-cells = <1>;
5591                                                         #size-cells = <0>;
5592                                                         #sound-dai-cells = <1>;
5593                                                 };
5594
5595                                                 q6afecc: clock-controller {
5596                                                         compatible = "qcom,q6afe-clocks";
5597                                                         #clock-cells = <2>;
5598                                                 };
5599                                         };
5600
5601                                         q6asm: service@7 {
5602                                                 compatible = "qcom,q6asm";
5603                                                 reg = <APR_SVC_ASM>;
5604                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5605                                                 q6asmdai: dais {
5606                                                         compatible = "qcom,q6asm-dais";
5607                                                         #address-cells = <1>;
5608                                                         #size-cells = <0>;
5609                                                         #sound-dai-cells = <1>;
5610                                                         iommus = <&apps_smmu 0x1801 0x0>;
5611                                                 };
5612                                         };
5613
5614                                         q6adm: service@8 {
5615                                                 compatible = "qcom,q6adm";
5616                                                 reg = <APR_SVC_ADM>;
5617                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5618                                                 q6routing: routing {
5619                                                         compatible = "qcom,q6adm-routing";
5620                                                         #sound-dai-cells = <0>;
5621                                                 };
5622                                         };
5623                                 };
5624
5625                                 fastrpc {
5626                                         compatible = "qcom,fastrpc";
5627                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
5628                                         label = "adsp";
5629                                         qcom,non-secure-domain;
5630                                         #address-cells = <1>;
5631                                         #size-cells = <0>;
5632
5633                                         compute-cb@3 {
5634                                                 compatible = "qcom,fastrpc-compute-cb";
5635                                                 reg = <3>;
5636                                                 iommus = <&apps_smmu 0x1803 0x0>;
5637                                         };
5638
5639                                         compute-cb@4 {
5640                                                 compatible = "qcom,fastrpc-compute-cb";
5641                                                 reg = <4>;
5642                                                 iommus = <&apps_smmu 0x1804 0x0>;
5643                                         };
5644
5645                                         compute-cb@5 {
5646                                                 compatible = "qcom,fastrpc-compute-cb";
5647                                                 reg = <5>;
5648                                                 iommus = <&apps_smmu 0x1805 0x0>;
5649                                         };
5650                                 };
5651                         };
5652                 };
5653
5654                 intc: interrupt-controller@17a00000 {
5655                         compatible = "arm,gic-v3";
5656                         #interrupt-cells = <3>;
5657                         interrupt-controller;
5658                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
5659                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
5660                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5661                 };
5662
5663                 watchdog@17c10000 {
5664                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
5665                         reg = <0 0x17c10000 0 0x1000>;
5666                         clocks = <&sleep_clk>;
5667                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5668                 };
5669
5670                 timer@17c20000 {
5671                         #address-cells = <1>;
5672                         #size-cells = <1>;
5673                         ranges = <0 0 0 0x20000000>;
5674                         compatible = "arm,armv7-timer-mem";
5675                         reg = <0x0 0x17c20000 0x0 0x1000>;
5676                         clock-frequency = <19200000>;
5677
5678                         frame@17c21000 {
5679                                 frame-number = <0>;
5680                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5681                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5682                                 reg = <0x17c21000 0x1000>,
5683                                       <0x17c22000 0x1000>;
5684                         };
5685
5686                         frame@17c23000 {
5687                                 frame-number = <1>;
5688                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5689                                 reg = <0x17c23000 0x1000>;
5690                                 status = "disabled";
5691                         };
5692
5693                         frame@17c25000 {
5694                                 frame-number = <2>;
5695                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5696                                 reg = <0x17c25000 0x1000>;
5697                                 status = "disabled";
5698                         };
5699
5700                         frame@17c27000 {
5701                                 frame-number = <3>;
5702                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5703                                 reg = <0x17c27000 0x1000>;
5704                                 status = "disabled";
5705                         };
5706
5707                         frame@17c29000 {
5708                                 frame-number = <4>;
5709                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5710                                 reg = <0x17c29000 0x1000>;
5711                                 status = "disabled";
5712                         };
5713
5714                         frame@17c2b000 {
5715                                 frame-number = <5>;
5716                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5717                                 reg = <0x17c2b000 0x1000>;
5718                                 status = "disabled";
5719                         };
5720
5721                         frame@17c2d000 {
5722                                 frame-number = <6>;
5723                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5724                                 reg = <0x17c2d000 0x1000>;
5725                                 status = "disabled";
5726                         };
5727                 };
5728
5729                 apps_rsc: rsc@18200000 {
5730                         label = "apps_rsc";
5731                         compatible = "qcom,rpmh-rsc";
5732                         reg = <0x0 0x18200000 0x0 0x10000>,
5733                                 <0x0 0x18210000 0x0 0x10000>,
5734                                 <0x0 0x18220000 0x0 0x10000>;
5735                         reg-names = "drv-0", "drv-1", "drv-2";
5736                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5737                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5738                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5739                         qcom,tcs-offset = <0xd00>;
5740                         qcom,drv-id = <2>;
5741                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
5742                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
5743                         power-domains = <&CLUSTER_PD>;
5744
5745                         rpmhcc: clock-controller {
5746                                 compatible = "qcom,sm8250-rpmh-clk";
5747                                 #clock-cells = <1>;
5748                                 clock-names = "xo";
5749                                 clocks = <&xo_board>;
5750                         };
5751
5752                         rpmhpd: power-controller {
5753                                 compatible = "qcom,sm8250-rpmhpd";
5754                                 #power-domain-cells = <1>;
5755                                 operating-points-v2 = <&rpmhpd_opp_table>;
5756
5757                                 rpmhpd_opp_table: opp-table {
5758                                         compatible = "operating-points-v2";
5759
5760                                         rpmhpd_opp_ret: opp1 {
5761                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5762                                         };
5763
5764                                         rpmhpd_opp_min_svs: opp2 {
5765                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5766                                         };
5767
5768                                         rpmhpd_opp_low_svs: opp3 {
5769                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5770                                         };
5771
5772                                         rpmhpd_opp_svs: opp4 {
5773                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5774                                         };
5775
5776                                         rpmhpd_opp_svs_l1: opp5 {
5777                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5778                                         };
5779
5780                                         rpmhpd_opp_nom: opp6 {
5781                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5782                                         };
5783
5784                                         rpmhpd_opp_nom_l1: opp7 {
5785                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5786                                         };
5787
5788                                         rpmhpd_opp_nom_l2: opp8 {
5789                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5790                                         };
5791
5792                                         rpmhpd_opp_turbo: opp9 {
5793                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5794                                         };
5795
5796                                         rpmhpd_opp_turbo_l1: opp10 {
5797                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5798                                         };
5799                                 };
5800                         };
5801
5802                         apps_bcm_voter: bcm-voter {
5803                                 compatible = "qcom,bcm-voter";
5804                         };
5805                 };
5806
5807                 epss_l3: interconnect@18590000 {
5808                         compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
5809                         reg = <0 0x18590000 0 0x1000>;
5810
5811                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5812                         clock-names = "xo", "alternate";
5813
5814                         #interconnect-cells = <1>;
5815                 };
5816
5817                 cpufreq_hw: cpufreq@18591000 {
5818                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
5819                         reg = <0 0x18591000 0 0x1000>,
5820                               <0 0x18592000 0 0x1000>,
5821                               <0 0x18593000 0 0x1000>;
5822                         reg-names = "freq-domain0", "freq-domain1",
5823                                     "freq-domain2";
5824
5825                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5826                         clock-names = "xo", "alternate";
5827                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
5828                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5829                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5830                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5831                         #freq-domain-cells = <1>;
5832                         #clock-cells = <1>;
5833                 };
5834         };
5835
5836         sound: sound {
5837         };
5838
5839         timer {
5840                 compatible = "arm,armv8-timer";
5841                 interrupts = <GIC_PPI 13
5842                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5843                              <GIC_PPI 14
5844                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5845                              <GIC_PPI 11
5846                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5847                              <GIC_PPI 10
5848                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5849         };
5850
5851         thermal-zones {
5852                 cpu0-thermal {
5853                         polling-delay-passive = <250>;
5854                         polling-delay = <1000>;
5855
5856                         thermal-sensors = <&tsens0 1>;
5857
5858                         trips {
5859                                 cpu0_alert0: trip-point0 {
5860                                         temperature = <90000>;
5861                                         hysteresis = <2000>;
5862                                         type = "passive";
5863                                 };
5864
5865                                 cpu0_alert1: trip-point1 {
5866                                         temperature = <95000>;
5867                                         hysteresis = <2000>;
5868                                         type = "passive";
5869                                 };
5870
5871                                 cpu0_crit: cpu-crit {
5872                                         temperature = <110000>;
5873                                         hysteresis = <1000>;
5874                                         type = "critical";
5875                                 };
5876                         };
5877
5878                         cooling-maps {
5879                                 map0 {
5880                                         trip = <&cpu0_alert0>;
5881                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5882                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5883                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5884                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5885                                 };
5886                                 map1 {
5887                                         trip = <&cpu0_alert1>;
5888                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5889                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5890                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5891                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5892                                 };
5893                         };
5894                 };
5895
5896                 cpu1-thermal {
5897                         polling-delay-passive = <250>;
5898                         polling-delay = <1000>;
5899
5900                         thermal-sensors = <&tsens0 2>;
5901
5902                         trips {
5903                                 cpu1_alert0: trip-point0 {
5904                                         temperature = <90000>;
5905                                         hysteresis = <2000>;
5906                                         type = "passive";
5907                                 };
5908
5909                                 cpu1_alert1: trip-point1 {
5910                                         temperature = <95000>;
5911                                         hysteresis = <2000>;
5912                                         type = "passive";
5913                                 };
5914
5915                                 cpu1_crit: cpu-crit {
5916                                         temperature = <110000>;
5917                                         hysteresis = <1000>;
5918                                         type = "critical";
5919                                 };
5920                         };
5921
5922                         cooling-maps {
5923                                 map0 {
5924                                         trip = <&cpu1_alert0>;
5925                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5926                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5927                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5928                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5929                                 };
5930                                 map1 {
5931                                         trip = <&cpu1_alert1>;
5932                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5933                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5934                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5935                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5936                                 };
5937                         };
5938                 };
5939
5940                 cpu2-thermal {
5941                         polling-delay-passive = <250>;
5942                         polling-delay = <1000>;
5943
5944                         thermal-sensors = <&tsens0 3>;
5945
5946                         trips {
5947                                 cpu2_alert0: trip-point0 {
5948                                         temperature = <90000>;
5949                                         hysteresis = <2000>;
5950                                         type = "passive";
5951                                 };
5952
5953                                 cpu2_alert1: trip-point1 {
5954                                         temperature = <95000>;
5955                                         hysteresis = <2000>;
5956                                         type = "passive";
5957                                 };
5958
5959                                 cpu2_crit: cpu-crit {
5960                                         temperature = <110000>;
5961                                         hysteresis = <1000>;
5962                                         type = "critical";
5963                                 };
5964                         };
5965
5966                         cooling-maps {
5967                                 map0 {
5968                                         trip = <&cpu2_alert0>;
5969                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5970                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5971                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5972                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5973                                 };
5974                                 map1 {
5975                                         trip = <&cpu2_alert1>;
5976                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5977                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5978                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5979                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5980                                 };
5981                         };
5982                 };
5983
5984                 cpu3-thermal {
5985                         polling-delay-passive = <250>;
5986                         polling-delay = <1000>;
5987
5988                         thermal-sensors = <&tsens0 4>;
5989
5990                         trips {
5991                                 cpu3_alert0: trip-point0 {
5992                                         temperature = <90000>;
5993                                         hysteresis = <2000>;
5994                                         type = "passive";
5995                                 };
5996
5997                                 cpu3_alert1: trip-point1 {
5998                                         temperature = <95000>;
5999                                         hysteresis = <2000>;
6000                                         type = "passive";
6001                                 };
6002
6003                                 cpu3_crit: cpu-crit {
6004                                         temperature = <110000>;
6005                                         hysteresis = <1000>;
6006                                         type = "critical";
6007                                 };
6008                         };
6009
6010                         cooling-maps {
6011                                 map0 {
6012                                         trip = <&cpu3_alert0>;
6013                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6014                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6015                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6016                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6017                                 };
6018                                 map1 {
6019                                         trip = <&cpu3_alert1>;
6020                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6021                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6022                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6023                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6024                                 };
6025                         };
6026                 };
6027
6028                 cpu4-top-thermal {
6029                         polling-delay-passive = <250>;
6030                         polling-delay = <1000>;
6031
6032                         thermal-sensors = <&tsens0 7>;
6033
6034                         trips {
6035                                 cpu4_top_alert0: trip-point0 {
6036                                         temperature = <90000>;
6037                                         hysteresis = <2000>;
6038                                         type = "passive";
6039                                 };
6040
6041                                 cpu4_top_alert1: trip-point1 {
6042                                         temperature = <95000>;
6043                                         hysteresis = <2000>;
6044                                         type = "passive";
6045                                 };
6046
6047                                 cpu4_top_crit: cpu-crit {
6048                                         temperature = <110000>;
6049                                         hysteresis = <1000>;
6050                                         type = "critical";
6051                                 };
6052                         };
6053
6054                         cooling-maps {
6055                                 map0 {
6056                                         trip = <&cpu4_top_alert0>;
6057                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6058                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6059                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6060                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6061                                 };
6062                                 map1 {
6063                                         trip = <&cpu4_top_alert1>;
6064                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6065                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6066                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6067                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6068                                 };
6069                         };
6070                 };
6071
6072                 cpu5-top-thermal {
6073                         polling-delay-passive = <250>;
6074                         polling-delay = <1000>;
6075
6076                         thermal-sensors = <&tsens0 8>;
6077
6078                         trips {
6079                                 cpu5_top_alert0: trip-point0 {
6080                                         temperature = <90000>;
6081                                         hysteresis = <2000>;
6082                                         type = "passive";
6083                                 };
6084
6085                                 cpu5_top_alert1: trip-point1 {
6086                                         temperature = <95000>;
6087                                         hysteresis = <2000>;
6088                                         type = "passive";
6089                                 };
6090
6091                                 cpu5_top_crit: cpu-crit {
6092                                         temperature = <110000>;
6093                                         hysteresis = <1000>;
6094                                         type = "critical";
6095                                 };
6096                         };
6097
6098                         cooling-maps {
6099                                 map0 {
6100                                         trip = <&cpu5_top_alert0>;
6101                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6102                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6103                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6104                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6105                                 };
6106                                 map1 {
6107                                         trip = <&cpu5_top_alert1>;
6108                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6109                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6110                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6111                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6112                                 };
6113                         };
6114                 };
6115
6116                 cpu6-top-thermal {
6117                         polling-delay-passive = <250>;
6118                         polling-delay = <1000>;
6119
6120                         thermal-sensors = <&tsens0 9>;
6121
6122                         trips {
6123                                 cpu6_top_alert0: trip-point0 {
6124                                         temperature = <90000>;
6125                                         hysteresis = <2000>;
6126                                         type = "passive";
6127                                 };
6128
6129                                 cpu6_top_alert1: trip-point1 {
6130                                         temperature = <95000>;
6131                                         hysteresis = <2000>;
6132                                         type = "passive";
6133                                 };
6134
6135                                 cpu6_top_crit: cpu-crit {
6136                                         temperature = <110000>;
6137                                         hysteresis = <1000>;
6138                                         type = "critical";
6139                                 };
6140                         };
6141
6142                         cooling-maps {
6143                                 map0 {
6144                                         trip = <&cpu6_top_alert0>;
6145                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6146                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6147                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6148                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6149                                 };
6150                                 map1 {
6151                                         trip = <&cpu6_top_alert1>;
6152                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6153                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6154                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6155                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6156                                 };
6157                         };
6158                 };
6159
6160                 cpu7-top-thermal {
6161                         polling-delay-passive = <250>;
6162                         polling-delay = <1000>;
6163
6164                         thermal-sensors = <&tsens0 10>;
6165
6166                         trips {
6167                                 cpu7_top_alert0: trip-point0 {
6168                                         temperature = <90000>;
6169                                         hysteresis = <2000>;
6170                                         type = "passive";
6171                                 };
6172
6173                                 cpu7_top_alert1: trip-point1 {
6174                                         temperature = <95000>;
6175                                         hysteresis = <2000>;
6176                                         type = "passive";
6177                                 };
6178
6179                                 cpu7_top_crit: cpu-crit {
6180                                         temperature = <110000>;
6181                                         hysteresis = <1000>;
6182                                         type = "critical";
6183                                 };
6184                         };
6185
6186                         cooling-maps {
6187                                 map0 {
6188                                         trip = <&cpu7_top_alert0>;
6189                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6190                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6191                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6192                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6193                                 };
6194                                 map1 {
6195                                         trip = <&cpu7_top_alert1>;
6196                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6197                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6198                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6199                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6200                                 };
6201                         };
6202                 };
6203
6204                 cpu4-bottom-thermal {
6205                         polling-delay-passive = <250>;
6206                         polling-delay = <1000>;
6207
6208                         thermal-sensors = <&tsens0 11>;
6209
6210                         trips {
6211                                 cpu4_bottom_alert0: trip-point0 {
6212                                         temperature = <90000>;
6213                                         hysteresis = <2000>;
6214                                         type = "passive";
6215                                 };
6216
6217                                 cpu4_bottom_alert1: trip-point1 {
6218                                         temperature = <95000>;
6219                                         hysteresis = <2000>;
6220                                         type = "passive";
6221                                 };
6222
6223                                 cpu4_bottom_crit: cpu-crit {
6224                                         temperature = <110000>;
6225                                         hysteresis = <1000>;
6226                                         type = "critical";
6227                                 };
6228                         };
6229
6230                         cooling-maps {
6231                                 map0 {
6232                                         trip = <&cpu4_bottom_alert0>;
6233                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6234                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6235                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6236                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6237                                 };
6238                                 map1 {
6239                                         trip = <&cpu4_bottom_alert1>;
6240                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6241                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6242                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6243                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6244                                 };
6245                         };
6246                 };
6247
6248                 cpu5-bottom-thermal {
6249                         polling-delay-passive = <250>;
6250                         polling-delay = <1000>;
6251
6252                         thermal-sensors = <&tsens0 12>;
6253
6254                         trips {
6255                                 cpu5_bottom_alert0: trip-point0 {
6256                                         temperature = <90000>;
6257                                         hysteresis = <2000>;
6258                                         type = "passive";
6259                                 };
6260
6261                                 cpu5_bottom_alert1: trip-point1 {
6262                                         temperature = <95000>;
6263                                         hysteresis = <2000>;
6264                                         type = "passive";
6265                                 };
6266
6267                                 cpu5_bottom_crit: cpu-crit {
6268                                         temperature = <110000>;
6269                                         hysteresis = <1000>;
6270                                         type = "critical";
6271                                 };
6272                         };
6273
6274                         cooling-maps {
6275                                 map0 {
6276                                         trip = <&cpu5_bottom_alert0>;
6277                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6278                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6279                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6280                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6281                                 };
6282                                 map1 {
6283                                         trip = <&cpu5_bottom_alert1>;
6284                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6285                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6286                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6287                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6288                                 };
6289                         };
6290                 };
6291
6292                 cpu6-bottom-thermal {
6293                         polling-delay-passive = <250>;
6294                         polling-delay = <1000>;
6295
6296                         thermal-sensors = <&tsens0 13>;
6297
6298                         trips {
6299                                 cpu6_bottom_alert0: trip-point0 {
6300                                         temperature = <90000>;
6301                                         hysteresis = <2000>;
6302                                         type = "passive";
6303                                 };
6304
6305                                 cpu6_bottom_alert1: trip-point1 {
6306                                         temperature = <95000>;
6307                                         hysteresis = <2000>;
6308                                         type = "passive";
6309                                 };
6310
6311                                 cpu6_bottom_crit: cpu-crit {
6312                                         temperature = <110000>;
6313                                         hysteresis = <1000>;
6314                                         type = "critical";
6315                                 };
6316                         };
6317
6318                         cooling-maps {
6319                                 map0 {
6320                                         trip = <&cpu6_bottom_alert0>;
6321                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6322                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6323                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6324                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6325                                 };
6326                                 map1 {
6327                                         trip = <&cpu6_bottom_alert1>;
6328                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6329                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6330                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6331                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6332                                 };
6333                         };
6334                 };
6335
6336                 cpu7-bottom-thermal {
6337                         polling-delay-passive = <250>;
6338                         polling-delay = <1000>;
6339
6340                         thermal-sensors = <&tsens0 14>;
6341
6342                         trips {
6343                                 cpu7_bottom_alert0: trip-point0 {
6344                                         temperature = <90000>;
6345                                         hysteresis = <2000>;
6346                                         type = "passive";
6347                                 };
6348
6349                                 cpu7_bottom_alert1: trip-point1 {
6350                                         temperature = <95000>;
6351                                         hysteresis = <2000>;
6352                                         type = "passive";
6353                                 };
6354
6355                                 cpu7_bottom_crit: cpu-crit {
6356                                         temperature = <110000>;
6357                                         hysteresis = <1000>;
6358                                         type = "critical";
6359                                 };
6360                         };
6361
6362                         cooling-maps {
6363                                 map0 {
6364                                         trip = <&cpu7_bottom_alert0>;
6365                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6366                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6367                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6368                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6369                                 };
6370                                 map1 {
6371                                         trip = <&cpu7_bottom_alert1>;
6372                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6373                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6374                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6375                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6376                                 };
6377                         };
6378                 };
6379
6380                 aoss0-thermal {
6381                         polling-delay-passive = <250>;
6382                         polling-delay = <1000>;
6383
6384                         thermal-sensors = <&tsens0 0>;
6385
6386                         trips {
6387                                 aoss0_alert0: trip-point0 {
6388                                         temperature = <90000>;
6389                                         hysteresis = <2000>;
6390                                         type = "hot";
6391                                 };
6392                         };
6393                 };
6394
6395                 cluster0-thermal {
6396                         polling-delay-passive = <250>;
6397                         polling-delay = <1000>;
6398
6399                         thermal-sensors = <&tsens0 5>;
6400
6401                         trips {
6402                                 cluster0_alert0: trip-point0 {
6403                                         temperature = <90000>;
6404                                         hysteresis = <2000>;
6405                                         type = "hot";
6406                                 };
6407                                 cluster0_crit: cluster0_crit {
6408                                         temperature = <110000>;
6409                                         hysteresis = <2000>;
6410                                         type = "critical";
6411                                 };
6412                         };
6413                 };
6414
6415                 cluster1-thermal {
6416                         polling-delay-passive = <250>;
6417                         polling-delay = <1000>;
6418
6419                         thermal-sensors = <&tsens0 6>;
6420
6421                         trips {
6422                                 cluster1_alert0: trip-point0 {
6423                                         temperature = <90000>;
6424                                         hysteresis = <2000>;
6425                                         type = "hot";
6426                                 };
6427                                 cluster1_crit: cluster1_crit {
6428                                         temperature = <110000>;
6429                                         hysteresis = <2000>;
6430                                         type = "critical";
6431                                 };
6432                         };
6433                 };
6434
6435                 gpu-top-thermal {
6436                         polling-delay-passive = <250>;
6437                         polling-delay = <1000>;
6438
6439                         thermal-sensors = <&tsens0 15>;
6440
6441                         trips {
6442                                 gpu1_alert0: trip-point0 {
6443                                         temperature = <90000>;
6444                                         hysteresis = <2000>;
6445                                         type = "hot";
6446                                 };
6447                         };
6448                 };
6449
6450                 aoss1-thermal {
6451                         polling-delay-passive = <250>;
6452                         polling-delay = <1000>;
6453
6454                         thermal-sensors = <&tsens1 0>;
6455
6456                         trips {
6457                                 aoss1_alert0: trip-point0 {
6458                                         temperature = <90000>;
6459                                         hysteresis = <2000>;
6460                                         type = "hot";
6461                                 };
6462                         };
6463                 };
6464
6465                 wlan-thermal {
6466                         polling-delay-passive = <250>;
6467                         polling-delay = <1000>;
6468
6469                         thermal-sensors = <&tsens1 1>;
6470
6471                         trips {
6472                                 wlan_alert0: trip-point0 {
6473                                         temperature = <90000>;
6474                                         hysteresis = <2000>;
6475                                         type = "hot";
6476                                 };
6477                         };
6478                 };
6479
6480                 video-thermal {
6481                         polling-delay-passive = <250>;
6482                         polling-delay = <1000>;
6483
6484                         thermal-sensors = <&tsens1 2>;
6485
6486                         trips {
6487                                 video_alert0: trip-point0 {
6488                                         temperature = <90000>;
6489                                         hysteresis = <2000>;
6490                                         type = "hot";
6491                                 };
6492                         };
6493                 };
6494
6495                 mem-thermal {
6496                         polling-delay-passive = <250>;
6497                         polling-delay = <1000>;
6498
6499                         thermal-sensors = <&tsens1 3>;
6500
6501                         trips {
6502                                 mem_alert0: trip-point0 {
6503                                         temperature = <90000>;
6504                                         hysteresis = <2000>;
6505                                         type = "hot";
6506                                 };
6507                         };
6508                 };
6509
6510                 q6-hvx-thermal {
6511                         polling-delay-passive = <250>;
6512                         polling-delay = <1000>;
6513
6514                         thermal-sensors = <&tsens1 4>;
6515
6516                         trips {
6517                                 q6_hvx_alert0: trip-point0 {
6518                                         temperature = <90000>;
6519                                         hysteresis = <2000>;
6520                                         type = "hot";
6521                                 };
6522                         };
6523                 };
6524
6525                 camera-thermal {
6526                         polling-delay-passive = <250>;
6527                         polling-delay = <1000>;
6528
6529                         thermal-sensors = <&tsens1 5>;
6530
6531                         trips {
6532                                 camera_alert0: trip-point0 {
6533                                         temperature = <90000>;
6534                                         hysteresis = <2000>;
6535                                         type = "hot";
6536                                 };
6537                         };
6538                 };
6539
6540                 compute-thermal {
6541                         polling-delay-passive = <250>;
6542                         polling-delay = <1000>;
6543
6544                         thermal-sensors = <&tsens1 6>;
6545
6546                         trips {
6547                                 compute_alert0: trip-point0 {
6548                                         temperature = <90000>;
6549                                         hysteresis = <2000>;
6550                                         type = "hot";
6551                                 };
6552                         };
6553                 };
6554
6555                 npu-thermal {
6556                         polling-delay-passive = <250>;
6557                         polling-delay = <1000>;
6558
6559                         thermal-sensors = <&tsens1 7>;
6560
6561                         trips {
6562                                 npu_alert0: trip-point0 {
6563                                         temperature = <90000>;
6564                                         hysteresis = <2000>;
6565                                         type = "hot";
6566                                 };
6567                         };
6568                 };
6569
6570                 gpu-bottom-thermal {
6571                         polling-delay-passive = <250>;
6572                         polling-delay = <1000>;
6573
6574                         thermal-sensors = <&tsens1 8>;
6575
6576                         trips {
6577                                 gpu2_alert0: trip-point0 {
6578                                         temperature = <90000>;
6579                                         hysteresis = <2000>;
6580                                         type = "hot";
6581                                 };
6582                         };
6583                 };
6584         };
6585 };