1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
13 #include <dt-bindings/interconnect/qcom,sm8250.h>
14 #include <dt-bindings/mailbox/qcom-ipcc.h>
15 #include <dt-bindings/power/qcom-aoss-qmp.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/soc/qcom,apr.h>
18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
19 #include <dt-bindings/sound/qcom,q6afe.h>
20 #include <dt-bindings/thermal/thermal.h>
21 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
24 interrupt-parent = <&intc>;
76 compatible = "fixed-clock";
78 clock-frequency = <38400000>;
79 clock-output-names = "xo_board";
82 sleep_clk: sleep-clk {
83 compatible = "fixed-clock";
84 clock-frequency = <32768>;
95 compatible = "qcom,kryo485";
97 enable-method = "psci";
98 capacity-dmips-mhz = <448>;
99 dynamic-power-coefficient = <205>;
100 next-level-cache = <&L2_0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 #cooling-cells = <2>;
104 compatible = "cache";
105 next-level-cache = <&L3_0>;
107 compatible = "cache";
114 compatible = "qcom,kryo485";
116 enable-method = "psci";
117 capacity-dmips-mhz = <448>;
118 dynamic-power-coefficient = <205>;
119 next-level-cache = <&L2_100>;
120 qcom,freq-domain = <&cpufreq_hw 0>;
121 #cooling-cells = <2>;
123 compatible = "cache";
124 next-level-cache = <&L3_0>;
130 compatible = "qcom,kryo485";
132 enable-method = "psci";
133 capacity-dmips-mhz = <448>;
134 dynamic-power-coefficient = <205>;
135 next-level-cache = <&L2_200>;
136 qcom,freq-domain = <&cpufreq_hw 0>;
137 #cooling-cells = <2>;
139 compatible = "cache";
140 next-level-cache = <&L3_0>;
146 compatible = "qcom,kryo485";
148 enable-method = "psci";
149 capacity-dmips-mhz = <448>;
150 dynamic-power-coefficient = <205>;
151 next-level-cache = <&L2_300>;
152 qcom,freq-domain = <&cpufreq_hw 0>;
153 #cooling-cells = <2>;
155 compatible = "cache";
156 next-level-cache = <&L3_0>;
162 compatible = "qcom,kryo485";
164 enable-method = "psci";
165 capacity-dmips-mhz = <1024>;
166 dynamic-power-coefficient = <379>;
167 next-level-cache = <&L2_400>;
168 qcom,freq-domain = <&cpufreq_hw 1>;
169 #cooling-cells = <2>;
171 compatible = "cache";
172 next-level-cache = <&L3_0>;
178 compatible = "qcom,kryo485";
180 enable-method = "psci";
181 capacity-dmips-mhz = <1024>;
182 dynamic-power-coefficient = <379>;
183 next-level-cache = <&L2_500>;
184 qcom,freq-domain = <&cpufreq_hw 1>;
185 #cooling-cells = <2>;
187 compatible = "cache";
188 next-level-cache = <&L3_0>;
195 compatible = "qcom,kryo485";
197 enable-method = "psci";
198 capacity-dmips-mhz = <1024>;
199 dynamic-power-coefficient = <379>;
200 next-level-cache = <&L2_600>;
201 qcom,freq-domain = <&cpufreq_hw 1>;
202 #cooling-cells = <2>;
204 compatible = "cache";
205 next-level-cache = <&L3_0>;
211 compatible = "qcom,kryo485";
213 enable-method = "psci";
214 capacity-dmips-mhz = <1024>;
215 dynamic-power-coefficient = <444>;
216 next-level-cache = <&L2_700>;
217 qcom,freq-domain = <&cpufreq_hw 2>;
218 #cooling-cells = <2>;
220 compatible = "cache";
221 next-level-cache = <&L3_0>;
264 compatible = "qcom,scm";
270 device_type = "memory";
271 /* We expect the bootloader to fill in the size */
272 reg = <0x0 0x80000000 0x0 0x0>;
276 compatible = "regulator-fixed-domain";
277 power-domains = <&rpmhpd SM8250_MMCX>;
278 required-opps = <&rpmhpd_opp_low_svs>;
279 regulator-name = "MMCX";
283 compatible = "arm,armv8-pmuv3";
284 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
288 compatible = "arm,psci-1.0";
293 #address-cells = <2>;
297 hyp_mem: memory@80000000 {
298 reg = <0x0 0x80000000 0x0 0x600000>;
302 xbl_aop_mem: memory@80700000 {
303 reg = <0x0 0x80700000 0x0 0x160000>;
307 cmd_db: memory@80860000 {
308 compatible = "qcom,cmd-db";
309 reg = <0x0 0x80860000 0x0 0x20000>;
313 smem_mem: memory@80900000 {
314 reg = <0x0 0x80900000 0x0 0x200000>;
318 removed_mem: memory@80b00000 {
319 reg = <0x0 0x80b00000 0x0 0x5300000>;
323 camera_mem: memory@86200000 {
324 reg = <0x0 0x86200000 0x0 0x500000>;
328 wlan_mem: memory@86700000 {
329 reg = <0x0 0x86700000 0x0 0x100000>;
333 ipa_fw_mem: memory@86800000 {
334 reg = <0x0 0x86800000 0x0 0x10000>;
338 ipa_gsi_mem: memory@86810000 {
339 reg = <0x0 0x86810000 0x0 0xa000>;
343 gpu_mem: memory@8681a000 {
344 reg = <0x0 0x8681a000 0x0 0x2000>;
348 npu_mem: memory@86900000 {
349 reg = <0x0 0x86900000 0x0 0x500000>;
353 video_mem: memory@86e00000 {
354 reg = <0x0 0x86e00000 0x0 0x500000>;
358 cvp_mem: memory@87300000 {
359 reg = <0x0 0x87300000 0x0 0x500000>;
363 cdsp_mem: memory@87800000 {
364 reg = <0x0 0x87800000 0x0 0x1400000>;
368 slpi_mem: memory@88c00000 {
369 reg = <0x0 0x88c00000 0x0 0x1500000>;
373 adsp_mem: memory@8a100000 {
374 reg = <0x0 0x8a100000 0x0 0x1d00000>;
378 spss_mem: memory@8be00000 {
379 reg = <0x0 0x8be00000 0x0 0x100000>;
383 cdsp_secure_heap: memory@8bf00000 {
384 reg = <0x0 0x8bf00000 0x0 0x4600000>;
390 compatible = "qcom,smem";
391 memory-region = <&smem_mem>;
392 hwlocks = <&tcsr_mutex 3>;
396 compatible = "qcom,smp2p";
397 qcom,smem = <443>, <429>;
398 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
399 IPCC_MPROC_SIGNAL_SMP2P
400 IRQ_TYPE_EDGE_RISING>;
401 mboxes = <&ipcc IPCC_CLIENT_LPASS
402 IPCC_MPROC_SIGNAL_SMP2P>;
404 qcom,local-pid = <0>;
405 qcom,remote-pid = <2>;
407 smp2p_adsp_out: master-kernel {
408 qcom,entry-name = "master-kernel";
409 #qcom,smem-state-cells = <1>;
412 smp2p_adsp_in: slave-kernel {
413 qcom,entry-name = "slave-kernel";
414 interrupt-controller;
415 #interrupt-cells = <2>;
420 compatible = "qcom,smp2p";
421 qcom,smem = <94>, <432>;
422 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
423 IPCC_MPROC_SIGNAL_SMP2P
424 IRQ_TYPE_EDGE_RISING>;
425 mboxes = <&ipcc IPCC_CLIENT_CDSP
426 IPCC_MPROC_SIGNAL_SMP2P>;
428 qcom,local-pid = <0>;
429 qcom,remote-pid = <5>;
431 smp2p_cdsp_out: master-kernel {
432 qcom,entry-name = "master-kernel";
433 #qcom,smem-state-cells = <1>;
436 smp2p_cdsp_in: slave-kernel {
437 qcom,entry-name = "slave-kernel";
438 interrupt-controller;
439 #interrupt-cells = <2>;
444 compatible = "qcom,smp2p";
445 qcom,smem = <481>, <430>;
446 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
447 IPCC_MPROC_SIGNAL_SMP2P
448 IRQ_TYPE_EDGE_RISING>;
449 mboxes = <&ipcc IPCC_CLIENT_SLPI
450 IPCC_MPROC_SIGNAL_SMP2P>;
452 qcom,local-pid = <0>;
453 qcom,remote-pid = <3>;
455 smp2p_slpi_out: master-kernel {
456 qcom,entry-name = "master-kernel";
457 #qcom,smem-state-cells = <1>;
460 smp2p_slpi_in: slave-kernel {
461 qcom,entry-name = "slave-kernel";
462 interrupt-controller;
463 #interrupt-cells = <2>;
468 #address-cells = <2>;
470 ranges = <0 0 0 0 0x10 0>;
471 dma-ranges = <0 0 0 0 0x10 0>;
472 compatible = "simple-bus";
474 gcc: clock-controller@100000 {
475 compatible = "qcom,gcc-sm8250";
476 reg = <0x0 0x00100000 0x0 0x1f0000>;
479 #power-domain-cells = <1>;
480 clock-names = "bi_tcxo",
483 clocks = <&rpmhcc RPMH_CXO_CLK>,
484 <&rpmhcc RPMH_CXO_CLK_A>,
488 ipcc: mailbox@408000 {
489 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
490 reg = <0 0x00408000 0 0x1000>;
491 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
492 interrupt-controller;
493 #interrupt-cells = <3>;
498 compatible = "qcom,prng-ee";
499 reg = <0 0x00793000 0 0x1000>;
500 clocks = <&gcc GCC_PRNG_AHB_CLK>;
501 clock-names = "core";
504 qup_opp_table: qup-opp-table {
505 compatible = "operating-points-v2";
508 opp-hz = /bits/ 64 <50000000>;
509 required-opps = <&rpmhpd_opp_min_svs>;
513 opp-hz = /bits/ 64 <75000000>;
514 required-opps = <&rpmhpd_opp_low_svs>;
518 opp-hz = /bits/ 64 <120000000>;
519 required-opps = <&rpmhpd_opp_svs>;
523 gpi_dma2: dma-controller@800000 {
524 compatible = "qcom,sm8250-gpi-dma";
525 reg = <0 0x00800000 0 0x70000>;
526 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
537 dma-channel-mask = <0x3f>;
538 iommus = <&apps_smmu 0x76 0x0>;
543 qupv3_id_2: geniqup@8c0000 {
544 compatible = "qcom,geni-se-qup";
545 reg = <0x0 0x008c0000 0x0 0x6000>;
546 clock-names = "m-ahb", "s-ahb";
547 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
548 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
549 #address-cells = <2>;
551 iommus = <&apps_smmu 0x63 0x0>;
556 compatible = "qcom,geni-i2c";
557 reg = <0 0x00880000 0 0x4000>;
559 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&qup_i2c14_default>;
562 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
563 #address-cells = <1>;
569 compatible = "qcom,geni-spi";
570 reg = <0 0x00880000 0 0x4000>;
572 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
573 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
574 #address-cells = <1>;
576 power-domains = <&rpmhpd SM8250_CX>;
577 operating-points-v2 = <&qup_opp_table>;
582 compatible = "qcom,geni-i2c";
583 reg = <0 0x00884000 0 0x4000>;
585 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&qup_i2c15_default>;
588 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
589 #address-cells = <1>;
595 compatible = "qcom,geni-spi";
596 reg = <0 0x00884000 0 0x4000>;
598 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
599 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
600 #address-cells = <1>;
602 power-domains = <&rpmhpd SM8250_CX>;
603 operating-points-v2 = <&qup_opp_table>;
608 compatible = "qcom,geni-i2c";
609 reg = <0 0x00888000 0 0x4000>;
611 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&qup_i2c16_default>;
614 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
615 #address-cells = <1>;
621 compatible = "qcom,geni-spi";
622 reg = <0 0x00888000 0 0x4000>;
624 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
625 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
626 #address-cells = <1>;
628 power-domains = <&rpmhpd SM8250_CX>;
629 operating-points-v2 = <&qup_opp_table>;
634 compatible = "qcom,geni-i2c";
635 reg = <0 0x0088c000 0 0x4000>;
637 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&qup_i2c17_default>;
640 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
641 #address-cells = <1>;
647 compatible = "qcom,geni-spi";
648 reg = <0 0x0088c000 0 0x4000>;
650 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
651 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
652 #address-cells = <1>;
654 power-domains = <&rpmhpd SM8250_CX>;
655 operating-points-v2 = <&qup_opp_table>;
659 uart17: serial@88c000 {
660 compatible = "qcom,geni-uart";
661 reg = <0 0x0088c000 0 0x4000>;
663 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
664 pinctrl-names = "default";
665 pinctrl-0 = <&qup_uart17_default>;
666 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
667 power-domains = <&rpmhpd SM8250_CX>;
668 operating-points-v2 = <&qup_opp_table>;
673 compatible = "qcom,geni-i2c";
674 reg = <0 0x00890000 0 0x4000>;
676 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
677 pinctrl-names = "default";
678 pinctrl-0 = <&qup_i2c18_default>;
679 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
680 #address-cells = <1>;
686 compatible = "qcom,geni-spi";
687 reg = <0 0x00890000 0 0x4000>;
689 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
690 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
691 #address-cells = <1>;
693 power-domains = <&rpmhpd SM8250_CX>;
694 operating-points-v2 = <&qup_opp_table>;
698 uart18: serial@890000 {
699 compatible = "qcom,geni-uart";
700 reg = <0 0x00890000 0 0x4000>;
702 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
703 pinctrl-names = "default";
704 pinctrl-0 = <&qup_uart18_default>;
705 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
706 power-domains = <&rpmhpd SM8250_CX>;
707 operating-points-v2 = <&qup_opp_table>;
712 compatible = "qcom,geni-i2c";
713 reg = <0 0x00894000 0 0x4000>;
715 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
716 pinctrl-names = "default";
717 pinctrl-0 = <&qup_i2c19_default>;
718 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
719 #address-cells = <1>;
725 compatible = "qcom,geni-spi";
726 reg = <0 0x00894000 0 0x4000>;
728 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
729 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
730 #address-cells = <1>;
732 power-domains = <&rpmhpd SM8250_CX>;
733 operating-points-v2 = <&qup_opp_table>;
738 gpi_dma0: dma-controller@900000 {
739 compatible = "qcom,sm8250-gpi-dma";
740 reg = <0 0x00900000 0 0x70000>;
741 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
755 dma-channel-mask = <0x7ff>;
756 iommus = <&apps_smmu 0x5b6 0x0>;
761 qupv3_id_0: geniqup@9c0000 {
762 compatible = "qcom,geni-se-qup";
763 reg = <0x0 0x009c0000 0x0 0x6000>;
764 clock-names = "m-ahb", "s-ahb";
765 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
766 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
767 #address-cells = <2>;
769 iommus = <&apps_smmu 0x5a3 0x0>;
774 compatible = "qcom,geni-i2c";
775 reg = <0 0x00980000 0 0x4000>;
777 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
778 pinctrl-names = "default";
779 pinctrl-0 = <&qup_i2c0_default>;
780 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
781 #address-cells = <1>;
787 compatible = "qcom,geni-spi";
788 reg = <0 0x00980000 0 0x4000>;
790 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
791 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
792 #address-cells = <1>;
794 power-domains = <&rpmhpd SM8250_CX>;
795 operating-points-v2 = <&qup_opp_table>;
800 compatible = "qcom,geni-i2c";
801 reg = <0 0x00984000 0 0x4000>;
803 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
804 pinctrl-names = "default";
805 pinctrl-0 = <&qup_i2c1_default>;
806 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
807 #address-cells = <1>;
813 compatible = "qcom,geni-spi";
814 reg = <0 0x00984000 0 0x4000>;
816 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
817 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>;
820 power-domains = <&rpmhpd SM8250_CX>;
821 operating-points-v2 = <&qup_opp_table>;
826 compatible = "qcom,geni-i2c";
827 reg = <0 0x00988000 0 0x4000>;
829 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
830 pinctrl-names = "default";
831 pinctrl-0 = <&qup_i2c2_default>;
832 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
833 #address-cells = <1>;
839 compatible = "qcom,geni-spi";
840 reg = <0 0x00988000 0 0x4000>;
842 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
843 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
844 #address-cells = <1>;
846 power-domains = <&rpmhpd SM8250_CX>;
847 operating-points-v2 = <&qup_opp_table>;
851 uart2: serial@988000 {
852 compatible = "qcom,geni-debug-uart";
853 reg = <0 0x00988000 0 0x4000>;
855 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
856 pinctrl-names = "default";
857 pinctrl-0 = <&qup_uart2_default>;
858 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
859 power-domains = <&rpmhpd SM8250_CX>;
860 operating-points-v2 = <&qup_opp_table>;
865 compatible = "qcom,geni-i2c";
866 reg = <0 0x0098c000 0 0x4000>;
868 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
869 pinctrl-names = "default";
870 pinctrl-0 = <&qup_i2c3_default>;
871 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
872 #address-cells = <1>;
878 compatible = "qcom,geni-spi";
879 reg = <0 0x0098c000 0 0x4000>;
881 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
882 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
883 #address-cells = <1>;
885 power-domains = <&rpmhpd SM8250_CX>;
886 operating-points-v2 = <&qup_opp_table>;
891 compatible = "qcom,geni-i2c";
892 reg = <0 0x00990000 0 0x4000>;
894 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
895 pinctrl-names = "default";
896 pinctrl-0 = <&qup_i2c4_default>;
897 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
898 #address-cells = <1>;
904 compatible = "qcom,geni-spi";
905 reg = <0 0x00990000 0 0x4000>;
907 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
908 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
909 #address-cells = <1>;
911 power-domains = <&rpmhpd SM8250_CX>;
912 operating-points-v2 = <&qup_opp_table>;
917 compatible = "qcom,geni-i2c";
918 reg = <0 0x00994000 0 0x4000>;
920 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&qup_i2c5_default>;
923 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
924 #address-cells = <1>;
930 compatible = "qcom,geni-spi";
931 reg = <0 0x00994000 0 0x4000>;
933 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
934 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
935 #address-cells = <1>;
937 power-domains = <&rpmhpd SM8250_CX>;
938 operating-points-v2 = <&qup_opp_table>;
943 compatible = "qcom,geni-i2c";
944 reg = <0 0x00998000 0 0x4000>;
946 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
947 pinctrl-names = "default";
948 pinctrl-0 = <&qup_i2c6_default>;
949 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
950 #address-cells = <1>;
956 compatible = "qcom,geni-spi";
957 reg = <0 0x00998000 0 0x4000>;
959 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
960 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
961 #address-cells = <1>;
963 power-domains = <&rpmhpd SM8250_CX>;
964 operating-points-v2 = <&qup_opp_table>;
968 uart6: serial@998000 {
969 compatible = "qcom,geni-uart";
970 reg = <0 0x00998000 0 0x4000>;
972 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
973 pinctrl-names = "default";
974 pinctrl-0 = <&qup_uart6_default>;
975 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
976 power-domains = <&rpmhpd SM8250_CX>;
977 operating-points-v2 = <&qup_opp_table>;
982 compatible = "qcom,geni-i2c";
983 reg = <0 0x0099c000 0 0x4000>;
985 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
986 pinctrl-names = "default";
987 pinctrl-0 = <&qup_i2c7_default>;
988 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
989 #address-cells = <1>;
995 compatible = "qcom,geni-spi";
996 reg = <0 0x0099c000 0 0x4000>;
998 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
999 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1000 #address-cells = <1>;
1002 power-domains = <&rpmhpd SM8250_CX>;
1003 operating-points-v2 = <&qup_opp_table>;
1004 status = "disabled";
1008 gpi_dma1: dma-controller@a00000 {
1009 compatible = "qcom,sm8250-gpi-dma";
1010 reg = <0 0x00a00000 0 0x70000>;
1011 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1012 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1013 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1014 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1018 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1019 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1020 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1021 dma-channels = <10>;
1022 dma-channel-mask = <0x3f>;
1023 iommus = <&apps_smmu 0x56 0x0>;
1025 status = "disabled";
1028 qupv3_id_1: geniqup@ac0000 {
1029 compatible = "qcom,geni-se-qup";
1030 reg = <0x0 0x00ac0000 0x0 0x6000>;
1031 clock-names = "m-ahb", "s-ahb";
1032 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1033 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1034 #address-cells = <2>;
1036 iommus = <&apps_smmu 0x43 0x0>;
1038 status = "disabled";
1041 compatible = "qcom,geni-i2c";
1042 reg = <0 0x00a80000 0 0x4000>;
1044 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&qup_i2c8_default>;
1047 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1048 #address-cells = <1>;
1050 status = "disabled";
1054 compatible = "qcom,geni-spi";
1055 reg = <0 0x00a80000 0 0x4000>;
1057 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1058 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1059 #address-cells = <1>;
1061 power-domains = <&rpmhpd SM8250_CX>;
1062 operating-points-v2 = <&qup_opp_table>;
1063 status = "disabled";
1067 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00a84000 0 0x4000>;
1070 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1071 pinctrl-names = "default";
1072 pinctrl-0 = <&qup_i2c9_default>;
1073 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1074 #address-cells = <1>;
1076 status = "disabled";
1080 compatible = "qcom,geni-spi";
1081 reg = <0 0x00a84000 0 0x4000>;
1083 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1084 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1085 #address-cells = <1>;
1087 power-domains = <&rpmhpd SM8250_CX>;
1088 operating-points-v2 = <&qup_opp_table>;
1089 status = "disabled";
1093 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00a88000 0 0x4000>;
1096 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1097 pinctrl-names = "default";
1098 pinctrl-0 = <&qup_i2c10_default>;
1099 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1100 #address-cells = <1>;
1102 status = "disabled";
1106 compatible = "qcom,geni-spi";
1107 reg = <0 0x00a88000 0 0x4000>;
1109 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1110 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1111 #address-cells = <1>;
1113 power-domains = <&rpmhpd SM8250_CX>;
1114 operating-points-v2 = <&qup_opp_table>;
1115 status = "disabled";
1119 compatible = "qcom,geni-i2c";
1120 reg = <0 0x00a8c000 0 0x4000>;
1122 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1123 pinctrl-names = "default";
1124 pinctrl-0 = <&qup_i2c11_default>;
1125 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1126 #address-cells = <1>;
1128 status = "disabled";
1132 compatible = "qcom,geni-spi";
1133 reg = <0 0x00a8c000 0 0x4000>;
1135 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1136 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cells = <1>;
1139 power-domains = <&rpmhpd SM8250_CX>;
1140 operating-points-v2 = <&qup_opp_table>;
1141 status = "disabled";
1145 compatible = "qcom,geni-i2c";
1146 reg = <0 0x00a90000 0 0x4000>;
1148 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1149 pinctrl-names = "default";
1150 pinctrl-0 = <&qup_i2c12_default>;
1151 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1152 #address-cells = <1>;
1154 status = "disabled";
1158 compatible = "qcom,geni-spi";
1159 reg = <0 0x00a90000 0 0x4000>;
1161 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1162 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1163 #address-cells = <1>;
1165 power-domains = <&rpmhpd SM8250_CX>;
1166 operating-points-v2 = <&qup_opp_table>;
1167 status = "disabled";
1170 uart12: serial@a90000 {
1171 compatible = "qcom,geni-debug-uart";
1172 reg = <0x0 0x00a90000 0x0 0x4000>;
1174 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&qup_uart12_default>;
1177 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1178 power-domains = <&rpmhpd SM8250_CX>;
1179 operating-points-v2 = <&qup_opp_table>;
1180 status = "disabled";
1184 compatible = "qcom,geni-i2c";
1185 reg = <0 0x00a94000 0 0x4000>;
1187 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1188 pinctrl-names = "default";
1189 pinctrl-0 = <&qup_i2c13_default>;
1190 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1191 #address-cells = <1>;
1193 status = "disabled";
1197 compatible = "qcom,geni-spi";
1198 reg = <0 0x00a94000 0 0x4000>;
1200 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1201 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1202 #address-cells = <1>;
1204 power-domains = <&rpmhpd SM8250_CX>;
1205 operating-points-v2 = <&qup_opp_table>;
1206 status = "disabled";
1210 config_noc: interconnect@1500000 {
1211 compatible = "qcom,sm8250-config-noc";
1212 reg = <0 0x01500000 0 0xa580>;
1213 #interconnect-cells = <1>;
1214 qcom,bcm-voters = <&apps_bcm_voter>;
1217 system_noc: interconnect@1620000 {
1218 compatible = "qcom,sm8250-system-noc";
1219 reg = <0 0x01620000 0 0x1c200>;
1220 #interconnect-cells = <1>;
1221 qcom,bcm-voters = <&apps_bcm_voter>;
1224 mc_virt: interconnect@163d000 {
1225 compatible = "qcom,sm8250-mc-virt";
1226 reg = <0 0x0163d000 0 0x1000>;
1227 #interconnect-cells = <1>;
1228 qcom,bcm-voters = <&apps_bcm_voter>;
1231 aggre1_noc: interconnect@16e0000 {
1232 compatible = "qcom,sm8250-aggre1-noc";
1233 reg = <0 0x016e0000 0 0x1f180>;
1234 #interconnect-cells = <1>;
1235 qcom,bcm-voters = <&apps_bcm_voter>;
1238 aggre2_noc: interconnect@1700000 {
1239 compatible = "qcom,sm8250-aggre2-noc";
1240 reg = <0 0x01700000 0 0x33000>;
1241 #interconnect-cells = <1>;
1242 qcom,bcm-voters = <&apps_bcm_voter>;
1245 compute_noc: interconnect@1733000 {
1246 compatible = "qcom,sm8250-compute-noc";
1247 reg = <0 0x01733000 0 0xa180>;
1248 #interconnect-cells = <1>;
1249 qcom,bcm-voters = <&apps_bcm_voter>;
1252 mmss_noc: interconnect@1740000 {
1253 compatible = "qcom,sm8250-mmss-noc";
1254 reg = <0 0x01740000 0 0x1f080>;
1255 #interconnect-cells = <1>;
1256 qcom,bcm-voters = <&apps_bcm_voter>;
1259 pcie0: pci@1c00000 {
1260 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1261 reg = <0 0x01c00000 0 0x3000>,
1262 <0 0x60000000 0 0xf1d>,
1263 <0 0x60000f20 0 0xa8>,
1264 <0 0x60001000 0 0x1000>,
1265 <0 0x60100000 0 0x100000>;
1266 reg-names = "parf", "dbi", "elbi", "atu", "config";
1267 device_type = "pci";
1268 linux,pci-domain = <0>;
1269 bus-range = <0x00 0xff>;
1272 #address-cells = <3>;
1275 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1276 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1278 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1279 interrupt-names = "msi";
1280 #interrupt-cells = <1>;
1281 interrupt-map-mask = <0 0 0 0x7>;
1282 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1283 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1284 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1285 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1287 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1288 <&gcc GCC_PCIE_0_AUX_CLK>,
1289 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1290 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1291 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1292 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1293 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1294 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1295 clock-names = "pipe",
1304 iommus = <&apps_smmu 0x1c00 0x7f>;
1305 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1306 <0x100 &apps_smmu 0x1c01 0x1>;
1308 resets = <&gcc GCC_PCIE_0_BCR>;
1309 reset-names = "pci";
1311 power-domains = <&gcc PCIE_0_GDSC>;
1313 phys = <&pcie0_lane>;
1314 phy-names = "pciephy";
1316 status = "disabled";
1319 pcie0_phy: phy@1c06000 {
1320 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1321 reg = <0 0x01c06000 0 0x1c0>;
1322 #address-cells = <2>;
1325 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1326 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1327 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1328 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1329 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1331 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1332 reset-names = "phy";
1334 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1335 assigned-clock-rates = <100000000>;
1337 status = "disabled";
1339 pcie0_lane: lanes@1c06200 {
1340 reg = <0 0x1c06200 0 0x170>, /* tx */
1341 <0 0x1c06400 0 0x200>, /* rx */
1342 <0 0x1c06800 0 0x1f0>, /* pcs */
1343 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1344 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1345 clock-names = "pipe0";
1348 clock-output-names = "pcie_0_pipe_clk";
1352 pcie1: pci@1c08000 {
1353 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1354 reg = <0 0x01c08000 0 0x3000>,
1355 <0 0x40000000 0 0xf1d>,
1356 <0 0x40000f20 0 0xa8>,
1357 <0 0x40001000 0 0x1000>,
1358 <0 0x40100000 0 0x100000>;
1359 reg-names = "parf", "dbi", "elbi", "atu", "config";
1360 device_type = "pci";
1361 linux,pci-domain = <1>;
1362 bus-range = <0x00 0xff>;
1365 #address-cells = <3>;
1368 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1369 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1371 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
1372 interrupt-names = "msi";
1373 #interrupt-cells = <1>;
1374 interrupt-map-mask = <0 0 0 0x7>;
1375 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1376 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1377 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1378 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1380 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1381 <&gcc GCC_PCIE_1_AUX_CLK>,
1382 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1383 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1384 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1385 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1386 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1387 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1388 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1389 clock-names = "pipe",
1399 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1400 assigned-clock-rates = <19200000>;
1402 iommus = <&apps_smmu 0x1c80 0x7f>;
1403 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1404 <0x100 &apps_smmu 0x1c81 0x1>;
1406 resets = <&gcc GCC_PCIE_1_BCR>;
1407 reset-names = "pci";
1409 power-domains = <&gcc PCIE_1_GDSC>;
1411 phys = <&pcie1_lane>;
1412 phy-names = "pciephy";
1414 status = "disabled";
1417 pcie1_phy: phy@1c0e000 {
1418 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1419 reg = <0 0x01c0e000 0 0x1c0>;
1420 #address-cells = <2>;
1423 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1424 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1425 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1426 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1427 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1429 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1430 reset-names = "phy";
1432 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1433 assigned-clock-rates = <100000000>;
1435 status = "disabled";
1437 pcie1_lane: lanes@1c0e200 {
1438 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1439 <0 0x1c0e400 0 0x200>, /* rx0 */
1440 <0 0x1c0ea00 0 0x1f0>, /* pcs */
1441 <0 0x1c0e600 0 0x170>, /* tx1 */
1442 <0 0x1c0e800 0 0x200>, /* rx1 */
1443 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1444 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1445 clock-names = "pipe0";
1448 clock-output-names = "pcie_1_pipe_clk";
1452 pcie2: pci@1c10000 {
1453 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
1454 reg = <0 0x01c10000 0 0x3000>,
1455 <0 0x64000000 0 0xf1d>,
1456 <0 0x64000f20 0 0xa8>,
1457 <0 0x64001000 0 0x1000>,
1458 <0 0x64100000 0 0x100000>;
1459 reg-names = "parf", "dbi", "elbi", "atu", "config";
1460 device_type = "pci";
1461 linux,pci-domain = <2>;
1462 bus-range = <0x00 0xff>;
1465 #address-cells = <3>;
1468 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
1469 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
1471 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
1472 interrupt-names = "msi";
1473 #interrupt-cells = <1>;
1474 interrupt-map-mask = <0 0 0 0x7>;
1475 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1476 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1477 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1478 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1480 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1481 <&gcc GCC_PCIE_2_AUX_CLK>,
1482 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1483 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1484 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
1485 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
1486 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1487 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1488 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1489 clock-names = "pipe",
1499 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
1500 assigned-clock-rates = <19200000>;
1502 iommus = <&apps_smmu 0x1d00 0x7f>;
1503 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
1504 <0x100 &apps_smmu 0x1d01 0x1>;
1506 resets = <&gcc GCC_PCIE_2_BCR>;
1507 reset-names = "pci";
1509 power-domains = <&gcc PCIE_2_GDSC>;
1511 phys = <&pcie2_lane>;
1512 phy-names = "pciephy";
1514 status = "disabled";
1517 pcie2_phy: phy@1c16000 {
1518 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
1519 reg = <0 0x1c16000 0 0x1c0>;
1520 #address-cells = <2>;
1523 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1524 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1525 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
1526 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1527 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1529 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
1530 reset-names = "phy";
1532 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1533 assigned-clock-rates = <100000000>;
1535 status = "disabled";
1537 pcie2_lane: lanes@1c16200 {
1538 reg = <0 0x1c16200 0 0x170>, /* tx0 */
1539 <0 0x1c16400 0 0x200>, /* rx0 */
1540 <0 0x1c16a00 0 0x1f0>, /* pcs */
1541 <0 0x1c16600 0 0x170>, /* tx1 */
1542 <0 0x1c16800 0 0x200>, /* rx1 */
1543 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1544 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
1545 clock-names = "pipe0";
1548 clock-output-names = "pcie_2_pipe_clk";
1552 ufs_mem_hc: ufshc@1d84000 {
1553 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1555 reg = <0 0x01d84000 0 0x3000>;
1556 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1557 phys = <&ufs_mem_phy_lanes>;
1558 phy-names = "ufsphy";
1559 lanes-per-direction = <2>;
1561 resets = <&gcc GCC_UFS_PHY_BCR>;
1562 reset-names = "rst";
1564 power-domains = <&gcc UFS_PHY_GDSC>;
1566 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
1574 "tx_lane0_sync_clk",
1575 "rx_lane0_sync_clk",
1576 "rx_lane1_sync_clk";
1578 <&gcc GCC_UFS_PHY_AXI_CLK>,
1579 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1580 <&gcc GCC_UFS_PHY_AHB_CLK>,
1581 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1582 <&rpmhcc RPMH_CXO_CLK>,
1583 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1584 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1585 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1587 <37500000 300000000>,
1590 <37500000 300000000>,
1596 status = "disabled";
1599 ufs_mem_phy: phy@1d87000 {
1600 compatible = "qcom,sm8250-qmp-ufs-phy";
1601 reg = <0 0x01d87000 0 0x1c0>;
1602 #address-cells = <2>;
1605 clock-names = "ref",
1607 clocks = <&rpmhcc RPMH_CXO_CLK>,
1608 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1610 resets = <&ufs_mem_hc 0>;
1611 reset-names = "ufsphy";
1612 status = "disabled";
1614 ufs_mem_phy_lanes: lanes@1d87400 {
1615 reg = <0 0x01d87400 0 0x108>,
1616 <0 0x01d87600 0 0x1e0>,
1617 <0 0x01d87c00 0 0x1dc>,
1618 <0 0x01d87800 0 0x108>,
1619 <0 0x01d87a00 0 0x1e0>;
1624 ipa_virt: interconnect@1e00000 {
1625 compatible = "qcom,sm8250-ipa-virt";
1626 reg = <0 0x01e00000 0 0x1000>;
1627 #interconnect-cells = <1>;
1628 qcom,bcm-voters = <&apps_bcm_voter>;
1631 tcsr_mutex: hwlock@1f40000 {
1632 compatible = "qcom,tcsr-mutex";
1633 reg = <0x0 0x01f40000 0x0 0x40000>;
1634 #hwlock-cells = <1>;
1637 wsamacro: codec@3240000 {
1638 compatible = "qcom,sm8250-lpass-wsa-macro";
1639 reg = <0 0x03240000 0 0x1000>;
1640 clocks = <&audiocc 1>,
1642 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1643 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1647 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
1650 clock-frequency = <9600000>;
1651 clock-output-names = "mclk";
1652 #sound-dai-cells = <1>;
1654 pinctrl-names = "default";
1655 pinctrl-0 = <&wsa_swr_active>;
1658 swr0: soundwire-controller@3250000 {
1659 reg = <0 0x03250000 0 0x2000>;
1660 compatible = "qcom,soundwire-v1.5.1";
1661 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1662 clocks = <&wsamacro>;
1663 clock-names = "iface";
1665 qcom,din-ports = <2>;
1666 qcom,dout-ports = <6>;
1668 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
1669 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
1670 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
1671 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
1673 #sound-dai-cells = <1>;
1674 #address-cells = <2>;
1678 audiocc: clock-controller@3300000 {
1679 compatible = "qcom,sm8250-lpass-audiocc";
1680 reg = <0 0x03300000 0 0x30000>;
1682 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1683 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1684 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1685 clock-names = "core", "audio", "bus";
1688 vamacro: codec@3370000 {
1689 compatible = "qcom,sm8250-lpass-va-macro";
1690 reg = <0 0x03370000 0 0x1000>;
1691 clocks = <&aoncc 0>,
1692 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1693 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1695 clock-names = "mclk", "macro", "dcodec";
1698 clock-frequency = <9600000>;
1699 clock-output-names = "fsgen";
1700 #sound-dai-cells = <1>;
1703 aoncc: clock-controller@3380000 {
1704 compatible = "qcom,sm8250-lpass-aoncc";
1705 reg = <0 0x03380000 0 0x40000>;
1707 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1708 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1709 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1710 clock-names = "core", "audio", "bus";
1713 lpass_tlmm: pinctrl@33c0000{
1714 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
1715 reg = <0 0x033c0000 0x0 0x20000>,
1716 <0 0x03550000 0x0 0x10000>;
1719 gpio-ranges = <&lpass_tlmm 0 0 14>;
1721 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
1722 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
1723 clock-names = "core", "audio";
1725 wsa_swr_active: wsa-swr-active-pins {
1728 function = "wsa_swr_clk";
1729 drive-strength = <2>;
1736 function = "wsa_swr_data";
1737 drive-strength = <2>;
1744 wsa_swr_sleep: wsa-swr-sleep-pins {
1747 function = "wsa_swr_clk";
1748 drive-strength = <2>;
1755 function = "wsa_swr_data";
1756 drive-strength = <2>;
1763 dmic01_active: dmic01-active-pins {
1766 function = "dmic1_clk";
1767 drive-strength = <8>;
1772 function = "dmic1_data";
1773 drive-strength = <8>;
1778 dmic01_sleep: dmic01-sleep-pins {
1781 function = "dmic1_clk";
1782 drive-strength = <2>;
1789 function = "dmic1_data";
1790 drive-strength = <2>;
1798 compatible = "qcom,adreno-650.2",
1800 #stream-id-cells = <16>;
1802 reg = <0 0x03d00000 0 0x40000>;
1803 reg-names = "kgsl_3d0_reg_memory";
1805 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1807 iommus = <&adreno_smmu 0 0x401>;
1809 operating-points-v2 = <&gpu_opp_table>;
1813 status = "disabled";
1816 memory-region = <&gpu_mem>;
1819 /* note: downstream checks gpu binning for 670 Mhz */
1820 gpu_opp_table: opp-table {
1821 compatible = "operating-points-v2";
1824 opp-hz = /bits/ 64 <670000000>;
1825 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1829 opp-hz = /bits/ 64 <587000000>;
1830 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1834 opp-hz = /bits/ 64 <525000000>;
1835 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1839 opp-hz = /bits/ 64 <490000000>;
1840 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1844 opp-hz = /bits/ 64 <441600000>;
1845 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1849 opp-hz = /bits/ 64 <400000000>;
1850 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1854 opp-hz = /bits/ 64 <305000000>;
1855 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1861 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1863 reg = <0 0x03d6a000 0 0x30000>,
1864 <0 0x3de0000 0 0x10000>,
1865 <0 0xb290000 0 0x10000>,
1866 <0 0xb490000 0 0x10000>;
1867 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1869 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1870 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1871 interrupt-names = "hfi", "gmu";
1873 clocks = <&gpucc GPU_CC_AHB_CLK>,
1874 <&gpucc GPU_CC_CX_GMU_CLK>,
1875 <&gpucc GPU_CC_CXO_CLK>,
1876 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1877 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1878 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1880 power-domains = <&gpucc GPU_CX_GDSC>,
1881 <&gpucc GPU_GX_GDSC>;
1882 power-domain-names = "cx", "gx";
1884 iommus = <&adreno_smmu 5 0x400>;
1886 operating-points-v2 = <&gmu_opp_table>;
1888 status = "disabled";
1890 gmu_opp_table: opp-table {
1891 compatible = "operating-points-v2";
1894 opp-hz = /bits/ 64 <200000000>;
1895 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1900 gpucc: clock-controller@3d90000 {
1901 compatible = "qcom,sm8250-gpucc";
1902 reg = <0 0x03d90000 0 0x9000>;
1903 clocks = <&rpmhcc RPMH_CXO_CLK>,
1904 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1905 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1906 clock-names = "bi_tcxo",
1907 "gcc_gpu_gpll0_clk_src",
1908 "gcc_gpu_gpll0_div_clk_src";
1911 #power-domain-cells = <1>;
1914 adreno_smmu: iommu@3da0000 {
1915 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1916 reg = <0 0x03da0000 0 0x10000>;
1918 #global-interrupts = <2>;
1919 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1920 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1921 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1922 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1923 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1924 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1925 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1926 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1927 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1928 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
1929 clocks = <&gpucc GPU_CC_AHB_CLK>,
1930 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1931 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1932 clock-names = "ahb", "bus", "iface";
1934 power-domains = <&gpucc GPU_CX_GDSC>;
1937 slpi: remoteproc@5c00000 {
1938 compatible = "qcom,sm8250-slpi-pas";
1939 reg = <0 0x05c00000 0 0x4000>;
1941 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1942 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1943 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1944 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1945 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1946 interrupt-names = "wdog", "fatal", "ready",
1947 "handover", "stop-ack";
1949 clocks = <&rpmhcc RPMH_CXO_CLK>;
1952 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1953 <&rpmhpd SM8250_LCX>,
1954 <&rpmhpd SM8250_LMX>;
1955 power-domain-names = "load_state", "lcx", "lmx";
1957 memory-region = <&slpi_mem>;
1959 qcom,smem-states = <&smp2p_slpi_out 0>;
1960 qcom,smem-state-names = "stop";
1962 status = "disabled";
1965 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1966 IPCC_MPROC_SIGNAL_GLINK_QMP
1967 IRQ_TYPE_EDGE_RISING>;
1968 mboxes = <&ipcc IPCC_CLIENT_SLPI
1969 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1972 qcom,remote-pid = <3>;
1975 compatible = "qcom,fastrpc";
1976 qcom,glink-channels = "fastrpcglink-apps-dsp";
1978 #address-cells = <1>;
1982 compatible = "qcom,fastrpc-compute-cb";
1984 iommus = <&apps_smmu 0x0541 0x0>;
1988 compatible = "qcom,fastrpc-compute-cb";
1990 iommus = <&apps_smmu 0x0542 0x0>;
1994 compatible = "qcom,fastrpc-compute-cb";
1996 iommus = <&apps_smmu 0x0543 0x0>;
1997 /* note: shared-cb = <4> in downstream */
2003 cdsp: remoteproc@8300000 {
2004 compatible = "qcom,sm8250-cdsp-pas";
2005 reg = <0 0x08300000 0 0x10000>;
2007 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2008 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2009 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2010 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2011 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2012 interrupt-names = "wdog", "fatal", "ready",
2013 "handover", "stop-ack";
2015 clocks = <&rpmhcc RPMH_CXO_CLK>;
2018 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
2019 <&rpmhpd SM8250_CX>;
2020 power-domain-names = "load_state", "cx";
2022 memory-region = <&cdsp_mem>;
2024 qcom,smem-states = <&smp2p_cdsp_out 0>;
2025 qcom,smem-state-names = "stop";
2027 status = "disabled";
2030 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2031 IPCC_MPROC_SIGNAL_GLINK_QMP
2032 IRQ_TYPE_EDGE_RISING>;
2033 mboxes = <&ipcc IPCC_CLIENT_CDSP
2034 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2037 qcom,remote-pid = <5>;
2040 compatible = "qcom,fastrpc";
2041 qcom,glink-channels = "fastrpcglink-apps-dsp";
2043 #address-cells = <1>;
2047 compatible = "qcom,fastrpc-compute-cb";
2049 iommus = <&apps_smmu 0x1001 0x0460>;
2053 compatible = "qcom,fastrpc-compute-cb";
2055 iommus = <&apps_smmu 0x1002 0x0460>;
2059 compatible = "qcom,fastrpc-compute-cb";
2061 iommus = <&apps_smmu 0x1003 0x0460>;
2065 compatible = "qcom,fastrpc-compute-cb";
2067 iommus = <&apps_smmu 0x1004 0x0460>;
2071 compatible = "qcom,fastrpc-compute-cb";
2073 iommus = <&apps_smmu 0x1005 0x0460>;
2077 compatible = "qcom,fastrpc-compute-cb";
2079 iommus = <&apps_smmu 0x1006 0x0460>;
2083 compatible = "qcom,fastrpc-compute-cb";
2085 iommus = <&apps_smmu 0x1007 0x0460>;
2089 compatible = "qcom,fastrpc-compute-cb";
2091 iommus = <&apps_smmu 0x1008 0x0460>;
2094 /* note: secure cb9 in downstream */
2102 usb_1_hsphy: phy@88e3000 {
2103 compatible = "qcom,sm8250-usb-hs-phy",
2104 "qcom,usb-snps-hs-7nm-phy";
2105 reg = <0 0x088e3000 0 0x400>;
2106 status = "disabled";
2109 clocks = <&rpmhcc RPMH_CXO_CLK>;
2110 clock-names = "ref";
2112 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2115 usb_2_hsphy: phy@88e4000 {
2116 compatible = "qcom,sm8250-usb-hs-phy",
2117 "qcom,usb-snps-hs-7nm-phy";
2118 reg = <0 0x088e4000 0 0x400>;
2119 status = "disabled";
2122 clocks = <&rpmhcc RPMH_CXO_CLK>;
2123 clock-names = "ref";
2125 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2128 usb_1_qmpphy: phy@88e9000 {
2129 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
2130 reg = <0 0x088e9000 0 0x200>,
2131 <0 0x088e8000 0 0x40>,
2132 <0 0x088ea000 0 0x200>;
2133 status = "disabled";
2134 #address-cells = <2>;
2138 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2139 <&rpmhcc RPMH_CXO_CLK>,
2140 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2141 clock-names = "aux", "ref_clk_src", "com_aux";
2143 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2144 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2145 reset-names = "phy", "common";
2147 usb_1_ssphy: usb3-phy@88e9200 {
2148 reg = <0 0x088e9200 0 0x200>,
2149 <0 0x088e9400 0 0x200>,
2150 <0 0x088e9c00 0 0x400>,
2151 <0 0x088e9600 0 0x200>,
2152 <0 0x088e9800 0 0x200>,
2153 <0 0x088e9a00 0 0x100>;
2156 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2157 clock-names = "pipe0";
2158 clock-output-names = "usb3_phy_pipe_clk_src";
2161 dp_phy: dp-phy@88ea200 {
2162 reg = <0 0x088ea200 0 0x200>,
2163 <0 0x088ea400 0 0x200>,
2164 <0 0x088eac00 0 0x400>,
2165 <0 0x088ea600 0 0x200>,
2166 <0 0x088ea800 0 0x200>,
2167 <0 0x088eaa00 0 0x100>;
2170 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2171 clock-names = "pipe0";
2172 clock-output-names = "usb3_phy_pipe_clk_src";
2176 usb_2_qmpphy: phy@88eb000 {
2177 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2178 reg = <0 0x088eb000 0 0x200>;
2179 status = "disabled";
2180 #address-cells = <2>;
2184 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2185 <&rpmhcc RPMH_CXO_CLK>,
2186 <&gcc GCC_USB3_SEC_CLKREF_EN>,
2187 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2188 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2190 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2191 <&gcc GCC_USB3_PHY_SEC_BCR>;
2192 reset-names = "phy", "common";
2194 usb_2_ssphy: lane@88eb200 {
2195 reg = <0 0x088eb200 0 0x200>,
2196 <0 0x088eb400 0 0x200>,
2197 <0 0x088eb800 0 0x800>;
2200 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2201 clock-names = "pipe0";
2202 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2206 sdhc_2: sdhci@8804000 {
2207 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2208 reg = <0 0x08804000 0 0x1000>;
2210 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2211 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2212 interrupt-names = "hc_irq", "pwr_irq";
2214 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2215 <&gcc GCC_SDCC2_APPS_CLK>,
2216 <&rpmhcc RPMH_CXO_CLK>;
2217 clock-names = "iface", "core", "xo";
2218 iommus = <&apps_smmu 0x4a0 0x0>;
2219 qcom,dll-config = <0x0007642c>;
2220 qcom,ddr-config = <0x80040868>;
2221 power-domains = <&rpmhpd SM8250_CX>;
2222 operating-points-v2 = <&sdhc2_opp_table>;
2224 status = "disabled";
2226 sdhc2_opp_table: sdhc2-opp-table {
2227 compatible = "operating-points-v2";
2230 opp-hz = /bits/ 64 <19200000>;
2231 required-opps = <&rpmhpd_opp_min_svs>;
2235 opp-hz = /bits/ 64 <50000000>;
2236 required-opps = <&rpmhpd_opp_low_svs>;
2240 opp-hz = /bits/ 64 <100000000>;
2241 required-opps = <&rpmhpd_opp_svs>;
2245 opp-hz = /bits/ 64 <202000000>;
2246 required-opps = <&rpmhpd_opp_svs_l1>;
2251 dc_noc: interconnect@90c0000 {
2252 compatible = "qcom,sm8250-dc-noc";
2253 reg = <0 0x090c0000 0 0x4200>;
2254 #interconnect-cells = <1>;
2255 qcom,bcm-voters = <&apps_bcm_voter>;
2258 gem_noc: interconnect@9100000 {
2259 compatible = "qcom,sm8250-gem-noc";
2260 reg = <0 0x09100000 0 0xb4000>;
2261 #interconnect-cells = <1>;
2262 qcom,bcm-voters = <&apps_bcm_voter>;
2265 npu_noc: interconnect@9990000 {
2266 compatible = "qcom,sm8250-npu-noc";
2267 reg = <0 0x09990000 0 0x1600>;
2268 #interconnect-cells = <1>;
2269 qcom,bcm-voters = <&apps_bcm_voter>;
2272 usb_1: usb@a6f8800 {
2273 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2274 reg = <0 0x0a6f8800 0 0x400>;
2275 status = "disabled";
2276 #address-cells = <2>;
2281 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2282 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2283 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2284 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2285 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2286 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2287 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2290 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2291 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2292 assigned-clock-rates = <19200000>, <200000000>;
2294 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2295 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2296 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2297 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2298 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2299 "dm_hs_phy_irq", "ss_phy_irq";
2301 power-domains = <&gcc USB30_PRIM_GDSC>;
2303 resets = <&gcc GCC_USB30_PRIM_BCR>;
2305 usb_1_dwc3: dwc3@a600000 {
2306 compatible = "snps,dwc3";
2307 reg = <0 0x0a600000 0 0xcd00>;
2308 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2309 iommus = <&apps_smmu 0x0 0x0>;
2310 snps,dis_u2_susphy_quirk;
2311 snps,dis_enblslpm_quirk;
2312 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2313 phy-names = "usb2-phy", "usb3-phy";
2317 system-cache-controller@9200000 {
2318 compatible = "qcom,sm8250-llcc";
2319 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2320 reg-names = "llcc_base", "llcc_broadcast_base";
2323 usb_2: usb@a8f8800 {
2324 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
2325 reg = <0 0x0a8f8800 0 0x400>;
2326 status = "disabled";
2327 #address-cells = <2>;
2332 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2333 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2334 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2335 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2336 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2337 <&gcc GCC_USB3_SEC_CLKREF_EN>;
2338 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2341 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2342 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2343 assigned-clock-rates = <19200000>, <200000000>;
2345 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2346 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2347 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2348 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2349 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2350 "dm_hs_phy_irq", "ss_phy_irq";
2352 power-domains = <&gcc USB30_SEC_GDSC>;
2354 resets = <&gcc GCC_USB30_SEC_BCR>;
2356 usb_2_dwc3: dwc3@a800000 {
2357 compatible = "snps,dwc3";
2358 reg = <0 0x0a800000 0 0xcd00>;
2359 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2360 iommus = <&apps_smmu 0x20 0>;
2361 snps,dis_u2_susphy_quirk;
2362 snps,dis_enblslpm_quirk;
2363 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2364 phy-names = "usb2-phy", "usb3-phy";
2368 venus: video-codec@aa00000 {
2369 compatible = "qcom,sm8250-venus";
2370 reg = <0 0x0aa00000 0 0x100000>;
2371 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2372 power-domains = <&videocc MVS0C_GDSC>,
2373 <&videocc MVS0_GDSC>,
2374 <&rpmhpd SM8250_MX>;
2375 power-domain-names = "venus", "vcodec0", "mx";
2376 operating-points-v2 = <&venus_opp_table>;
2378 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
2379 <&videocc VIDEO_CC_MVS0C_CLK>,
2380 <&videocc VIDEO_CC_MVS0_CLK>;
2381 clock-names = "iface", "core", "vcodec0_core";
2383 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
2384 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
2385 interconnect-names = "cpu-cfg", "video-mem";
2387 iommus = <&apps_smmu 0x2100 0x0400>;
2388 memory-region = <&video_mem>;
2390 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
2391 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
2392 reset-names = "bus", "core";
2394 status = "disabled";
2397 compatible = "venus-decoder";
2401 compatible = "venus-encoder";
2404 venus_opp_table: venus-opp-table {
2405 compatible = "operating-points-v2";
2408 opp-hz = /bits/ 64 <720000000>;
2409 required-opps = <&rpmhpd_opp_low_svs>;
2413 opp-hz = /bits/ 64 <1014000000>;
2414 required-opps = <&rpmhpd_opp_svs>;
2418 opp-hz = /bits/ 64 <1098000000>;
2419 required-opps = <&rpmhpd_opp_svs_l1>;
2423 opp-hz = /bits/ 64 <1332000000>;
2424 required-opps = <&rpmhpd_opp_nom>;
2429 videocc: clock-controller@abf0000 {
2430 compatible = "qcom,sm8250-videocc";
2431 reg = <0 0x0abf0000 0 0x10000>;
2432 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
2433 <&rpmhcc RPMH_CXO_CLK>,
2434 <&rpmhcc RPMH_CXO_CLK_A>;
2435 mmcx-supply = <&mmcx_reg>;
2436 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
2439 #power-domain-cells = <1>;
2442 mdss: mdss@ae00000 {
2443 compatible = "qcom,sm8250-mdss";
2444 reg = <0 0x0ae00000 0 0x1000>;
2447 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
2448 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
2449 interconnect-names = "mdp0-mem", "mdp1-mem";
2451 power-domains = <&dispcc MDSS_GDSC>;
2453 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2454 <&gcc GCC_DISP_HF_AXI_CLK>,
2455 <&gcc GCC_DISP_SF_AXI_CLK>,
2456 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2457 clock-names = "iface", "bus", "nrt_bus", "core";
2459 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2460 assigned-clock-rates = <460000000>;
2462 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2463 interrupt-controller;
2464 #interrupt-cells = <1>;
2466 iommus = <&apps_smmu 0x820 0x402>;
2468 status = "disabled";
2470 #address-cells = <2>;
2474 mdss_mdp: mdp@ae01000 {
2475 compatible = "qcom,sm8250-dpu";
2476 reg = <0 0x0ae01000 0 0x8f000>,
2477 <0 0x0aeb0000 0 0x2008>;
2478 reg-names = "mdp", "vbif";
2480 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2481 <&gcc GCC_DISP_HF_AXI_CLK>,
2482 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2483 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2484 clock-names = "iface", "bus", "core", "vsync";
2486 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2487 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2488 assigned-clock-rates = <460000000>,
2491 operating-points-v2 = <&mdp_opp_table>;
2492 power-domains = <&rpmhpd SM8250_MMCX>;
2494 interrupt-parent = <&mdss>;
2495 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2498 #address-cells = <1>;
2503 dpu_intf1_out: endpoint {
2504 remote-endpoint = <&dsi0_in>;
2510 dpu_intf2_out: endpoint {
2511 remote-endpoint = <&dsi1_in>;
2516 mdp_opp_table: mdp-opp-table {
2517 compatible = "operating-points-v2";
2520 opp-hz = /bits/ 64 <200000000>;
2521 required-opps = <&rpmhpd_opp_low_svs>;
2525 opp-hz = /bits/ 64 <300000000>;
2526 required-opps = <&rpmhpd_opp_svs>;
2530 opp-hz = /bits/ 64 <345000000>;
2531 required-opps = <&rpmhpd_opp_svs_l1>;
2535 opp-hz = /bits/ 64 <460000000>;
2536 required-opps = <&rpmhpd_opp_nom>;
2542 compatible = "qcom,mdss-dsi-ctrl";
2543 reg = <0 0x0ae94000 0 0x400>;
2544 reg-names = "dsi_ctrl";
2546 interrupt-parent = <&mdss>;
2547 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
2549 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2550 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2551 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2552 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2553 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2554 <&gcc GCC_DISP_HF_AXI_CLK>;
2555 clock-names = "byte",
2562 operating-points-v2 = <&dsi_opp_table>;
2563 power-domains = <&rpmhpd SM8250_MMCX>;
2568 status = "disabled";
2570 #address-cells = <1>;
2574 #address-cells = <1>;
2580 remote-endpoint = <&dpu_intf1_out>;
2586 dsi0_out: endpoint {
2592 dsi0_phy: dsi-phy@ae94400 {
2593 compatible = "qcom,dsi-phy-7nm";
2594 reg = <0 0x0ae94400 0 0x200>,
2595 <0 0x0ae94600 0 0x280>,
2596 <0 0x0ae94900 0 0x260>;
2597 reg-names = "dsi_phy",
2604 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2605 <&rpmhcc RPMH_CXO_CLK>;
2606 clock-names = "iface", "ref";
2608 status = "disabled";
2612 compatible = "qcom,mdss-dsi-ctrl";
2613 reg = <0 0x0ae96000 0 0x400>;
2614 reg-names = "dsi_ctrl";
2616 interrupt-parent = <&mdss>;
2617 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2619 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2620 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2621 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2622 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2623 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2624 <&gcc GCC_DISP_HF_AXI_CLK>;
2625 clock-names = "byte",
2632 operating-points-v2 = <&dsi_opp_table>;
2633 power-domains = <&rpmhpd SM8250_MMCX>;
2638 status = "disabled";
2640 #address-cells = <1>;
2644 #address-cells = <1>;
2650 remote-endpoint = <&dpu_intf2_out>;
2656 dsi1_out: endpoint {
2662 dsi1_phy: dsi-phy@ae96400 {
2663 compatible = "qcom,dsi-phy-7nm";
2664 reg = <0 0x0ae96400 0 0x200>,
2665 <0 0x0ae96600 0 0x280>,
2666 <0 0x0ae96900 0 0x260>;
2667 reg-names = "dsi_phy",
2674 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2675 <&rpmhcc RPMH_CXO_CLK>;
2676 clock-names = "iface", "ref";
2678 status = "disabled";
2680 dsi_opp_table: dsi-opp-table {
2681 compatible = "operating-points-v2";
2684 opp-hz = /bits/ 64 <187500000>;
2685 required-opps = <&rpmhpd_opp_low_svs>;
2689 opp-hz = /bits/ 64 <300000000>;
2690 required-opps = <&rpmhpd_opp_svs>;
2694 opp-hz = /bits/ 64 <358000000>;
2695 required-opps = <&rpmhpd_opp_svs_l1>;
2701 dispcc: clock-controller@af00000 {
2702 compatible = "qcom,sm8250-dispcc";
2703 reg = <0 0x0af00000 0 0x10000>;
2704 mmcx-supply = <&mmcx_reg>;
2705 clocks = <&rpmhcc RPMH_CXO_CLK>,
2712 clock-names = "bi_tcxo",
2713 "dsi0_phy_pll_out_byteclk",
2714 "dsi0_phy_pll_out_dsiclk",
2715 "dsi1_phy_pll_out_byteclk",
2716 "dsi1_phy_pll_out_dsiclk",
2717 "dp_phy_pll_link_clk",
2718 "dp_phy_pll_vco_div_clk";
2721 #power-domain-cells = <1>;
2724 pdc: interrupt-controller@b220000 {
2725 compatible = "qcom,sm8250-pdc", "qcom,pdc";
2726 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
2727 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2728 <125 63 1>, <126 716 12>;
2729 #interrupt-cells = <2>;
2730 interrupt-parent = <&intc>;
2731 interrupt-controller;
2734 tsens0: thermal-sensor@c263000 {
2735 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2736 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2737 <0 0x0c222000 0 0x1ff>; /* SROT */
2738 #qcom,sensors = <16>;
2739 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2740 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2741 interrupt-names = "uplow", "critical";
2742 #thermal-sensor-cells = <1>;
2745 tsens1: thermal-sensor@c265000 {
2746 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
2747 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2748 <0 0x0c223000 0 0x1ff>; /* SROT */
2749 #qcom,sensors = <9>;
2750 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2751 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2752 interrupt-names = "uplow", "critical";
2753 #thermal-sensor-cells = <1>;
2756 aoss_qmp: power-controller@c300000 {
2757 compatible = "qcom,sm8250-aoss-qmp";
2758 reg = <0 0x0c300000 0 0x100000>;
2759 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
2760 IPCC_MPROC_SIGNAL_GLINK_QMP
2761 IRQ_TYPE_EDGE_RISING>;
2762 mboxes = <&ipcc IPCC_CLIENT_AOP
2763 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2766 #power-domain-cells = <1>;
2769 spmi_bus: spmi@c440000 {
2770 compatible = "qcom,spmi-pmic-arb";
2771 reg = <0x0 0x0c440000 0x0 0x0001100>,
2772 <0x0 0x0c600000 0x0 0x2000000>,
2773 <0x0 0x0e600000 0x0 0x0100000>,
2774 <0x0 0x0e700000 0x0 0x00a0000>,
2775 <0x0 0x0c40a000 0x0 0x0026000>;
2776 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2777 interrupt-names = "periph_irq";
2778 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2781 #address-cells = <2>;
2783 interrupt-controller;
2784 #interrupt-cells = <4>;
2787 tlmm: pinctrl@f100000 {
2788 compatible = "qcom,sm8250-pinctrl";
2789 reg = <0 0x0f100000 0 0x300000>,
2790 <0 0x0f500000 0 0x300000>,
2791 <0 0x0f900000 0 0x300000>;
2792 reg-names = "west", "south", "north";
2793 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2796 interrupt-controller;
2797 #interrupt-cells = <2>;
2798 gpio-ranges = <&tlmm 0 0 181>;
2799 wakeup-parent = <&pdc>;
2801 pri_mi2s_active: pri-mi2s-active {
2804 function = "mi2s0_sck";
2805 drive-strength = <8>;
2811 function = "mi2s0_ws";
2812 drive-strength = <8>;
2818 function = "mi2s0_data0";
2819 drive-strength = <8>;
2826 function = "mi2s0_data1";
2827 drive-strength = <8>;
2832 qup_i2c0_default: qup-i2c0-default {
2834 pins = "gpio28", "gpio29";
2839 pins = "gpio28", "gpio29";
2840 drive-strength = <2>;
2845 qup_i2c1_default: qup-i2c1-default {
2847 pins = "gpio4", "gpio5";
2852 pins = "gpio4", "gpio5";
2853 drive-strength = <2>;
2858 qup_i2c2_default: qup-i2c2-default {
2860 pins = "gpio115", "gpio116";
2865 pins = "gpio115", "gpio116";
2866 drive-strength = <2>;
2871 qup_i2c3_default: qup-i2c3-default {
2873 pins = "gpio119", "gpio120";
2878 pins = "gpio119", "gpio120";
2879 drive-strength = <2>;
2884 qup_i2c4_default: qup-i2c4-default {
2886 pins = "gpio8", "gpio9";
2891 pins = "gpio8", "gpio9";
2892 drive-strength = <2>;
2897 qup_i2c5_default: qup-i2c5-default {
2899 pins = "gpio12", "gpio13";
2904 pins = "gpio12", "gpio13";
2905 drive-strength = <2>;
2910 qup_i2c6_default: qup-i2c6-default {
2912 pins = "gpio16", "gpio17";
2917 pins = "gpio16", "gpio17";
2918 drive-strength = <2>;
2923 qup_i2c7_default: qup-i2c7-default {
2925 pins = "gpio20", "gpio21";
2930 pins = "gpio20", "gpio21";
2931 drive-strength = <2>;
2936 qup_i2c8_default: qup-i2c8-default {
2938 pins = "gpio24", "gpio25";
2943 pins = "gpio24", "gpio25";
2944 drive-strength = <2>;
2949 qup_i2c9_default: qup-i2c9-default {
2951 pins = "gpio125", "gpio126";
2956 pins = "gpio125", "gpio126";
2957 drive-strength = <2>;
2962 qup_i2c10_default: qup-i2c10-default {
2964 pins = "gpio129", "gpio130";
2969 pins = "gpio129", "gpio130";
2970 drive-strength = <2>;
2975 qup_i2c11_default: qup-i2c11-default {
2977 pins = "gpio60", "gpio61";
2982 pins = "gpio60", "gpio61";
2983 drive-strength = <2>;
2988 qup_i2c12_default: qup-i2c12-default {
2990 pins = "gpio32", "gpio33";
2995 pins = "gpio32", "gpio33";
2996 drive-strength = <2>;
3001 qup_i2c13_default: qup-i2c13-default {
3003 pins = "gpio36", "gpio37";
3008 pins = "gpio36", "gpio37";
3009 drive-strength = <2>;
3014 qup_i2c14_default: qup-i2c14-default {
3016 pins = "gpio40", "gpio41";
3021 pins = "gpio40", "gpio41";
3022 drive-strength = <2>;
3027 qup_i2c15_default: qup-i2c15-default {
3029 pins = "gpio44", "gpio45";
3034 pins = "gpio44", "gpio45";
3035 drive-strength = <2>;
3040 qup_i2c16_default: qup-i2c16-default {
3042 pins = "gpio48", "gpio49";
3047 pins = "gpio48", "gpio49";
3048 drive-strength = <2>;
3053 qup_i2c17_default: qup-i2c17-default {
3055 pins = "gpio52", "gpio53";
3060 pins = "gpio52", "gpio53";
3061 drive-strength = <2>;
3066 qup_i2c18_default: qup-i2c18-default {
3068 pins = "gpio56", "gpio57";
3073 pins = "gpio56", "gpio57";
3074 drive-strength = <2>;
3079 qup_i2c19_default: qup-i2c19-default {
3081 pins = "gpio0", "gpio1";
3086 pins = "gpio0", "gpio1";
3087 drive-strength = <2>;
3092 qup_spi0_cs: qup-spi0-cs {
3097 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
3102 qup_spi0_data_clk: qup-spi0-data-clk {
3103 pins = "gpio28", "gpio29",
3108 qup_spi1_cs: qup-spi1-cs {
3113 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
3118 qup_spi1_data_clk: qup-spi1-data-clk {
3119 pins = "gpio4", "gpio5",
3124 qup_spi2_cs: qup-spi2-cs {
3129 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
3134 qup_spi2_data_clk: qup-spi2-data-clk {
3135 pins = "gpio115", "gpio116",
3140 qup_spi3_cs: qup-spi3-cs {
3145 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
3150 qup_spi3_data_clk: qup-spi3-data-clk {
3151 pins = "gpio119", "gpio120",
3156 qup_spi4_cs: qup-spi4-cs {
3161 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
3166 qup_spi4_data_clk: qup-spi4-data-clk {
3167 pins = "gpio8", "gpio9",
3172 qup_spi5_cs: qup-spi5-cs {
3177 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
3182 qup_spi5_data_clk: qup-spi5-data-clk {
3183 pins = "gpio12", "gpio13",
3188 qup_spi6_cs: qup-spi6-cs {
3193 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
3198 qup_spi6_data_clk: qup-spi6-data-clk {
3199 pins = "gpio16", "gpio17",
3204 qup_spi7_cs: qup-spi7-cs {
3209 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
3214 qup_spi7_data_clk: qup-spi7-data-clk {
3215 pins = "gpio20", "gpio21",
3220 qup_spi8_cs: qup-spi8-cs {
3225 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
3230 qup_spi8_data_clk: qup-spi8-data-clk {
3231 pins = "gpio24", "gpio25",
3236 qup_spi9_cs: qup-spi9-cs {
3241 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
3246 qup_spi9_data_clk: qup-spi9-data-clk {
3247 pins = "gpio125", "gpio126",
3252 qup_spi10_cs: qup-spi10-cs {
3257 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
3262 qup_spi10_data_clk: qup-spi10-data-clk {
3263 pins = "gpio129", "gpio130",
3268 qup_spi11_cs: qup-spi11-cs {
3273 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
3278 qup_spi11_data_clk: qup-spi11-data-clk {
3279 pins = "gpio60", "gpio61",
3284 qup_spi12_cs: qup-spi12-cs {
3289 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
3294 qup_spi12_data_clk: qup-spi12-data-clk {
3295 pins = "gpio32", "gpio33",
3300 qup_spi13_cs: qup-spi13-cs {
3305 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
3310 qup_spi13_data_clk: qup-spi13-data-clk {
3311 pins = "gpio36", "gpio37",
3316 qup_spi14_cs: qup-spi14-cs {
3321 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
3326 qup_spi14_data_clk: qup-spi14-data-clk {
3327 pins = "gpio40", "gpio41",
3332 qup_spi15_cs: qup-spi15-cs {
3337 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
3342 qup_spi15_data_clk: qup-spi15-data-clk {
3343 pins = "gpio44", "gpio45",
3348 qup_spi16_cs: qup-spi16-cs {
3353 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
3358 qup_spi16_data_clk: qup-spi16-data-clk {
3359 pins = "gpio48", "gpio49",
3364 qup_spi17_cs: qup-spi17-cs {
3369 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
3374 qup_spi17_data_clk: qup-spi17-data-clk {
3375 pins = "gpio52", "gpio53",
3380 qup_spi18_cs: qup-spi18-cs {
3385 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
3390 qup_spi18_data_clk: qup-spi18-data-clk {
3391 pins = "gpio56", "gpio57",
3396 qup_spi19_cs: qup-spi19-cs {
3401 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
3406 qup_spi19_data_clk: qup-spi19-data-clk {
3407 pins = "gpio0", "gpio1",
3412 qup_uart2_default: qup-uart2-default {
3414 pins = "gpio117", "gpio118";
3419 qup_uart6_default: qup-uart6-default {
3421 pins = "gpio16", "gpio17",
3427 qup_uart12_default: qup-uart12-default {
3429 pins = "gpio34", "gpio35";
3434 qup_uart17_default: qup-uart17-default {
3436 pins = "gpio52", "gpio53",
3442 qup_uart18_default: qup-uart18-default {
3444 pins = "gpio58", "gpio59";
3449 tert_mi2s_active: tert-mi2s-active {
3452 function = "mi2s2_sck";
3453 drive-strength = <8>;
3459 function = "mi2s2_data0";
3460 drive-strength = <8>;
3467 function = "mi2s2_ws";
3468 drive-strength = <8>;
3474 apps_smmu: iommu@15000000 {
3475 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3476 reg = <0 0x15000000 0 0x100000>;
3478 #global-interrupts = <2>;
3479 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
3480 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3481 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3482 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3483 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3484 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3485 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3486 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3487 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3488 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3489 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3490 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3491 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3492 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3493 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3494 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3495 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3496 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3497 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3498 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3499 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3500 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3501 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3502 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3503 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3504 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3505 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3506 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3507 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3508 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3509 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3510 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3511 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3512 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3513 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3514 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3515 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3516 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3517 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3518 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3519 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3520 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3521 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3522 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3523 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3524 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3525 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3526 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3527 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3528 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3529 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3530 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3531 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3532 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3533 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3534 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3535 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3536 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3537 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3538 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3539 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3540 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3541 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3542 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3543 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3544 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3545 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3546 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3547 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3548 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3549 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3556 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3557 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3558 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3559 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3560 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3561 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3562 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3563 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3564 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
3579 adsp: remoteproc@17300000 {
3580 compatible = "qcom,sm8250-adsp-pas";
3581 reg = <0 0x17300000 0 0x100>;
3583 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3584 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3585 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3586 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
3587 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
3588 interrupt-names = "wdog", "fatal", "ready",
3589 "handover", "stop-ack";
3591 clocks = <&rpmhcc RPMH_CXO_CLK>;
3594 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
3595 <&rpmhpd SM8250_LCX>,
3596 <&rpmhpd SM8250_LMX>;
3597 power-domain-names = "load_state", "lcx", "lmx";
3599 memory-region = <&adsp_mem>;
3601 qcom,smem-states = <&smp2p_adsp_out 0>;
3602 qcom,smem-state-names = "stop";
3604 status = "disabled";
3607 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3608 IPCC_MPROC_SIGNAL_GLINK_QMP
3609 IRQ_TYPE_EDGE_RISING>;
3610 mboxes = <&ipcc IPCC_CLIENT_LPASS
3611 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3614 qcom,remote-pid = <2>;
3617 compatible = "qcom,apr-v2";
3618 qcom,glink-channels = "apr_audio_svc";
3619 qcom,apr-domain = <APR_DOMAIN_ADSP>;
3620 #address-cells = <1>;
3624 reg = <APR_SVC_ADSP_CORE>;
3625 compatible = "qcom,q6core";
3626 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3629 q6afe: apr-service@4 {
3630 compatible = "qcom,q6afe";
3631 reg = <APR_SVC_AFE>;
3632 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3634 compatible = "qcom,q6afe-dais";
3635 #address-cells = <1>;
3637 #sound-dai-cells = <1>;
3641 compatible = "qcom,q6afe-clocks";
3646 q6asm: apr-service@7 {
3647 compatible = "qcom,q6asm";
3648 reg = <APR_SVC_ASM>;
3649 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3651 compatible = "qcom,q6asm-dais";
3652 #address-cells = <1>;
3654 #sound-dai-cells = <1>;
3655 iommus = <&apps_smmu 0x1801 0x0>;
3659 q6adm: apr-service@8 {
3660 compatible = "qcom,q6adm";
3661 reg = <APR_SVC_ADM>;
3662 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3663 q6routing: routing {
3664 compatible = "qcom,q6adm-routing";
3665 #sound-dai-cells = <0>;
3671 compatible = "qcom,fastrpc";
3672 qcom,glink-channels = "fastrpcglink-apps-dsp";
3674 #address-cells = <1>;
3678 compatible = "qcom,fastrpc-compute-cb";
3680 iommus = <&apps_smmu 0x1803 0x0>;
3684 compatible = "qcom,fastrpc-compute-cb";
3686 iommus = <&apps_smmu 0x1804 0x0>;
3690 compatible = "qcom,fastrpc-compute-cb";
3692 iommus = <&apps_smmu 0x1805 0x0>;
3698 intc: interrupt-controller@17a00000 {
3699 compatible = "arm,gic-v3";
3700 #interrupt-cells = <3>;
3701 interrupt-controller;
3702 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3703 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3704 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3708 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
3709 reg = <0 0x17c10000 0 0x1000>;
3710 clocks = <&sleep_clk>;
3711 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3715 #address-cells = <2>;
3718 compatible = "arm,armv7-timer-mem";
3719 reg = <0x0 0x17c20000 0x0 0x1000>;
3720 clock-frequency = <19200000>;
3724 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3725 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3726 reg = <0x0 0x17c21000 0x0 0x1000>,
3727 <0x0 0x17c22000 0x0 0x1000>;
3732 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3733 reg = <0x0 0x17c23000 0x0 0x1000>;
3734 status = "disabled";
3739 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3740 reg = <0x0 0x17c25000 0x0 0x1000>;
3741 status = "disabled";
3746 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3747 reg = <0x0 0x17c27000 0x0 0x1000>;
3748 status = "disabled";
3753 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3754 reg = <0x0 0x17c29000 0x0 0x1000>;
3755 status = "disabled";
3760 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3761 reg = <0x0 0x17c2b000 0x0 0x1000>;
3762 status = "disabled";
3767 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3768 reg = <0x0 0x17c2d000 0x0 0x1000>;
3769 status = "disabled";
3773 apps_rsc: rsc@18200000 {
3775 compatible = "qcom,rpmh-rsc";
3776 reg = <0x0 0x18200000 0x0 0x10000>,
3777 <0x0 0x18210000 0x0 0x10000>,
3778 <0x0 0x18220000 0x0 0x10000>;
3779 reg-names = "drv-0", "drv-1", "drv-2";
3780 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3781 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3782 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3783 qcom,tcs-offset = <0xd00>;
3785 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
3786 <WAKE_TCS 3>, <CONTROL_TCS 1>;
3788 rpmhcc: clock-controller {
3789 compatible = "qcom,sm8250-rpmh-clk";
3792 clocks = <&xo_board>;
3795 rpmhpd: power-controller {
3796 compatible = "qcom,sm8250-rpmhpd";
3797 #power-domain-cells = <1>;
3798 operating-points-v2 = <&rpmhpd_opp_table>;
3800 rpmhpd_opp_table: opp-table {
3801 compatible = "operating-points-v2";
3803 rpmhpd_opp_ret: opp1 {
3804 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3807 rpmhpd_opp_min_svs: opp2 {
3808 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3811 rpmhpd_opp_low_svs: opp3 {
3812 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3815 rpmhpd_opp_svs: opp4 {
3816 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3819 rpmhpd_opp_svs_l1: opp5 {
3820 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3823 rpmhpd_opp_nom: opp6 {
3824 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3827 rpmhpd_opp_nom_l1: opp7 {
3828 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3831 rpmhpd_opp_nom_l2: opp8 {
3832 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3835 rpmhpd_opp_turbo: opp9 {
3836 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3839 rpmhpd_opp_turbo_l1: opp10 {
3840 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3845 apps_bcm_voter: bcm_voter {
3846 compatible = "qcom,bcm-voter";
3850 epss_l3: interconnect@18591000 {
3851 compatible = "qcom,sm8250-epss-l3";
3852 reg = <0 0x18590000 0 0x1000>;
3854 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3855 clock-names = "xo", "alternate";
3857 #interconnect-cells = <1>;
3860 cpufreq_hw: cpufreq@18591000 {
3861 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
3862 reg = <0 0x18591000 0 0x1000>,
3863 <0 0x18592000 0 0x1000>,
3864 <0 0x18593000 0 0x1000>;
3865 reg-names = "freq-domain0", "freq-domain1",
3868 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3869 clock-names = "xo", "alternate";
3871 #freq-domain-cells = <1>;
3876 compatible = "arm,armv8-timer";
3877 interrupts = <GIC_PPI 13
3878 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3880 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3882 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3884 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3889 polling-delay-passive = <250>;
3890 polling-delay = <1000>;
3892 thermal-sensors = <&tsens0 1>;
3895 cpu0_alert0: trip-point0 {
3896 temperature = <90000>;
3897 hysteresis = <2000>;
3901 cpu0_alert1: trip-point1 {
3902 temperature = <95000>;
3903 hysteresis = <2000>;
3907 cpu0_crit: cpu_crit {
3908 temperature = <110000>;
3909 hysteresis = <1000>;
3916 trip = <&cpu0_alert0>;
3917 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3918 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3919 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3920 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3923 trip = <&cpu0_alert1>;
3924 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3925 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3926 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3927 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3933 polling-delay-passive = <250>;
3934 polling-delay = <1000>;
3936 thermal-sensors = <&tsens0 2>;
3939 cpu1_alert0: trip-point0 {
3940 temperature = <90000>;
3941 hysteresis = <2000>;
3945 cpu1_alert1: trip-point1 {
3946 temperature = <95000>;
3947 hysteresis = <2000>;
3951 cpu1_crit: cpu_crit {
3952 temperature = <110000>;
3953 hysteresis = <1000>;
3960 trip = <&cpu1_alert0>;
3961 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3962 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3963 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3964 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3967 trip = <&cpu1_alert1>;
3968 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3969 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3970 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3971 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3977 polling-delay-passive = <250>;
3978 polling-delay = <1000>;
3980 thermal-sensors = <&tsens0 3>;
3983 cpu2_alert0: trip-point0 {
3984 temperature = <90000>;
3985 hysteresis = <2000>;
3989 cpu2_alert1: trip-point1 {
3990 temperature = <95000>;
3991 hysteresis = <2000>;
3995 cpu2_crit: cpu_crit {
3996 temperature = <110000>;
3997 hysteresis = <1000>;
4004 trip = <&cpu2_alert0>;
4005 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4006 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4007 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4008 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4011 trip = <&cpu2_alert1>;
4012 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4013 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4014 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4015 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4021 polling-delay-passive = <250>;
4022 polling-delay = <1000>;
4024 thermal-sensors = <&tsens0 4>;
4027 cpu3_alert0: trip-point0 {
4028 temperature = <90000>;
4029 hysteresis = <2000>;
4033 cpu3_alert1: trip-point1 {
4034 temperature = <95000>;
4035 hysteresis = <2000>;
4039 cpu3_crit: cpu_crit {
4040 temperature = <110000>;
4041 hysteresis = <1000>;
4048 trip = <&cpu3_alert0>;
4049 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4050 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4051 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4052 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4055 trip = <&cpu3_alert1>;
4056 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4057 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4058 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4059 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4065 polling-delay-passive = <250>;
4066 polling-delay = <1000>;
4068 thermal-sensors = <&tsens0 7>;
4071 cpu4_top_alert0: trip-point0 {
4072 temperature = <90000>;
4073 hysteresis = <2000>;
4077 cpu4_top_alert1: trip-point1 {
4078 temperature = <95000>;
4079 hysteresis = <2000>;
4083 cpu4_top_crit: cpu_crit {
4084 temperature = <110000>;
4085 hysteresis = <1000>;
4092 trip = <&cpu4_top_alert0>;
4093 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4094 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4095 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4096 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4099 trip = <&cpu4_top_alert1>;
4100 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4101 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4102 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4103 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4109 polling-delay-passive = <250>;
4110 polling-delay = <1000>;
4112 thermal-sensors = <&tsens0 8>;
4115 cpu5_top_alert0: trip-point0 {
4116 temperature = <90000>;
4117 hysteresis = <2000>;
4121 cpu5_top_alert1: trip-point1 {
4122 temperature = <95000>;
4123 hysteresis = <2000>;
4127 cpu5_top_crit: cpu_crit {
4128 temperature = <110000>;
4129 hysteresis = <1000>;
4136 trip = <&cpu5_top_alert0>;
4137 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4138 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4139 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4140 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4143 trip = <&cpu5_top_alert1>;
4144 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4145 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4146 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4147 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4153 polling-delay-passive = <250>;
4154 polling-delay = <1000>;
4156 thermal-sensors = <&tsens0 9>;
4159 cpu6_top_alert0: trip-point0 {
4160 temperature = <90000>;
4161 hysteresis = <2000>;
4165 cpu6_top_alert1: trip-point1 {
4166 temperature = <95000>;
4167 hysteresis = <2000>;
4171 cpu6_top_crit: cpu_crit {
4172 temperature = <110000>;
4173 hysteresis = <1000>;
4180 trip = <&cpu6_top_alert0>;
4181 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4182 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4183 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4184 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4187 trip = <&cpu6_top_alert1>;
4188 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4189 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4190 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4191 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4197 polling-delay-passive = <250>;
4198 polling-delay = <1000>;
4200 thermal-sensors = <&tsens0 10>;
4203 cpu7_top_alert0: trip-point0 {
4204 temperature = <90000>;
4205 hysteresis = <2000>;
4209 cpu7_top_alert1: trip-point1 {
4210 temperature = <95000>;
4211 hysteresis = <2000>;
4215 cpu7_top_crit: cpu_crit {
4216 temperature = <110000>;
4217 hysteresis = <1000>;
4224 trip = <&cpu7_top_alert0>;
4225 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4226 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4227 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4228 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4231 trip = <&cpu7_top_alert1>;
4232 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4233 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4234 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4235 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4240 cpu4-bottom-thermal {
4241 polling-delay-passive = <250>;
4242 polling-delay = <1000>;
4244 thermal-sensors = <&tsens0 11>;
4247 cpu4_bottom_alert0: trip-point0 {
4248 temperature = <90000>;
4249 hysteresis = <2000>;
4253 cpu4_bottom_alert1: trip-point1 {
4254 temperature = <95000>;
4255 hysteresis = <2000>;
4259 cpu4_bottom_crit: cpu_crit {
4260 temperature = <110000>;
4261 hysteresis = <1000>;
4268 trip = <&cpu4_bottom_alert0>;
4269 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4270 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4271 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4272 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4275 trip = <&cpu4_bottom_alert1>;
4276 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4277 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4278 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4279 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4284 cpu5-bottom-thermal {
4285 polling-delay-passive = <250>;
4286 polling-delay = <1000>;
4288 thermal-sensors = <&tsens0 12>;
4291 cpu5_bottom_alert0: trip-point0 {
4292 temperature = <90000>;
4293 hysteresis = <2000>;
4297 cpu5_bottom_alert1: trip-point1 {
4298 temperature = <95000>;
4299 hysteresis = <2000>;
4303 cpu5_bottom_crit: cpu_crit {
4304 temperature = <110000>;
4305 hysteresis = <1000>;
4312 trip = <&cpu5_bottom_alert0>;
4313 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4314 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4315 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4316 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4319 trip = <&cpu5_bottom_alert1>;
4320 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4321 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4322 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4323 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4328 cpu6-bottom-thermal {
4329 polling-delay-passive = <250>;
4330 polling-delay = <1000>;
4332 thermal-sensors = <&tsens0 13>;
4335 cpu6_bottom_alert0: trip-point0 {
4336 temperature = <90000>;
4337 hysteresis = <2000>;
4341 cpu6_bottom_alert1: trip-point1 {
4342 temperature = <95000>;
4343 hysteresis = <2000>;
4347 cpu6_bottom_crit: cpu_crit {
4348 temperature = <110000>;
4349 hysteresis = <1000>;
4356 trip = <&cpu6_bottom_alert0>;
4357 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4358 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4359 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4360 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4363 trip = <&cpu6_bottom_alert1>;
4364 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4365 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4366 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4367 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4372 cpu7-bottom-thermal {
4373 polling-delay-passive = <250>;
4374 polling-delay = <1000>;
4376 thermal-sensors = <&tsens0 14>;
4379 cpu7_bottom_alert0: trip-point0 {
4380 temperature = <90000>;
4381 hysteresis = <2000>;
4385 cpu7_bottom_alert1: trip-point1 {
4386 temperature = <95000>;
4387 hysteresis = <2000>;
4391 cpu7_bottom_crit: cpu_crit {
4392 temperature = <110000>;
4393 hysteresis = <1000>;
4400 trip = <&cpu7_bottom_alert0>;
4401 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4402 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4403 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4404 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4407 trip = <&cpu7_bottom_alert1>;
4408 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4409 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4410 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4411 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4417 polling-delay-passive = <250>;
4418 polling-delay = <1000>;
4420 thermal-sensors = <&tsens0 0>;
4423 aoss0_alert0: trip-point0 {
4424 temperature = <90000>;
4425 hysteresis = <2000>;
4432 polling-delay-passive = <250>;
4433 polling-delay = <1000>;
4435 thermal-sensors = <&tsens0 5>;
4438 cluster0_alert0: trip-point0 {
4439 temperature = <90000>;
4440 hysteresis = <2000>;
4443 cluster0_crit: cluster0_crit {
4444 temperature = <110000>;
4445 hysteresis = <2000>;
4452 polling-delay-passive = <250>;
4453 polling-delay = <1000>;
4455 thermal-sensors = <&tsens0 6>;
4458 cluster1_alert0: trip-point0 {
4459 temperature = <90000>;
4460 hysteresis = <2000>;
4463 cluster1_crit: cluster1_crit {
4464 temperature = <110000>;
4465 hysteresis = <2000>;
4472 polling-delay-passive = <250>;
4473 polling-delay = <1000>;
4475 thermal-sensors = <&tsens0 15>;
4478 gpu1_alert0: trip-point0 {
4479 temperature = <90000>;
4480 hysteresis = <2000>;
4487 polling-delay-passive = <250>;
4488 polling-delay = <1000>;
4490 thermal-sensors = <&tsens1 0>;
4493 aoss1_alert0: trip-point0 {
4494 temperature = <90000>;
4495 hysteresis = <2000>;
4502 polling-delay-passive = <250>;
4503 polling-delay = <1000>;
4505 thermal-sensors = <&tsens1 1>;
4508 wlan_alert0: trip-point0 {
4509 temperature = <90000>;
4510 hysteresis = <2000>;
4517 polling-delay-passive = <250>;
4518 polling-delay = <1000>;
4520 thermal-sensors = <&tsens1 2>;
4523 video_alert0: trip-point0 {
4524 temperature = <90000>;
4525 hysteresis = <2000>;
4532 polling-delay-passive = <250>;
4533 polling-delay = <1000>;
4535 thermal-sensors = <&tsens1 3>;
4538 mem_alert0: trip-point0 {
4539 temperature = <90000>;
4540 hysteresis = <2000>;
4547 polling-delay-passive = <250>;
4548 polling-delay = <1000>;
4550 thermal-sensors = <&tsens1 4>;
4553 q6_hvx_alert0: trip-point0 {
4554 temperature = <90000>;
4555 hysteresis = <2000>;
4562 polling-delay-passive = <250>;
4563 polling-delay = <1000>;
4565 thermal-sensors = <&tsens1 5>;
4568 camera_alert0: trip-point0 {
4569 temperature = <90000>;
4570 hysteresis = <2000>;
4577 polling-delay-passive = <250>;
4578 polling-delay = <1000>;
4580 thermal-sensors = <&tsens1 6>;
4583 compute_alert0: trip-point0 {
4584 temperature = <90000>;
4585 hysteresis = <2000>;
4592 polling-delay-passive = <250>;
4593 polling-delay = <1000>;
4595 thermal-sensors = <&tsens1 7>;
4598 npu_alert0: trip-point0 {
4599 temperature = <90000>;
4600 hysteresis = <2000>;
4606 gpu-thermal-bottom {
4607 polling-delay-passive = <250>;
4608 polling-delay = <1000>;
4610 thermal-sensors = <&tsens1 8>;
4613 gpu2_alert0: trip-point0 {
4614 temperature = <90000>;
4615 hysteresis = <2000>;