arch/arm64/boot/dts/qcom/sm8150.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2019, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/dma/qcom-gpi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/power/qcom-rpmpd.h>
  10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  11 #include <dt-bindings/clock/qcom,rpmh.h>
  12 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
  13 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  14 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
  15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  16 #include <dt-bindings/interconnect/qcom,sm8150.h>
  17 #include <dt-bindings/thermal/thermal.h>
  18
  19 / {
  20         interrupt-parent = <&intc>;
  21
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         chosen { };
  26
  27         clocks {
  28                 xo_board: xo-board {
  29                         compatible = "fixed-clock";
  30                         #clock-cells = <0>;
  31                         clock-frequency = <38400000>;
  32                         clock-output-names = "xo_board";
  33                 };
  34
  35                 sleep_clk: sleep-clk {
  36                         compatible = "fixed-clock";
  37                         #clock-cells = <0>;
  38                         clock-frequency = <32764>;
  39                         clock-output-names = "sleep_clk";
  40                 };
  41         };
  42
  43         cpus {
  44                 #address-cells = <2>;
  45                 #size-cells = <0>;
  46
  47                 CPU0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "qcom,kryo485";
  50                         reg = <0x0 0x0>;
  51                         clocks = <&cpufreq_hw 0>;
  52                         enable-method = "psci";
  53                         capacity-dmips-mhz = <488>;
  54                         dynamic-power-coefficient = <232>;
  55                         next-level-cache = <&L2_0>;
  56                         qcom,freq-domain = <&cpufreq_hw 0>;
  57                         operating-points-v2 = <&cpu0_opp_table>;
  58                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
  59                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  60                         power-domains = <&CPU_PD0>;
  61                         power-domain-names = "psci";
  62                         #cooling-cells = <2>;
  63                         L2_0: l2-cache {
  64                                 compatible = "cache";
  65                                 cache-level = <2>;
  66                                 cache-unified;
  67                                 next-level-cache = <&L3_0>;
  68                                 L3_0: l3-cache {
  69                                         compatible = "cache";
  70                                         cache-level = <3>;
  71                                         cache-unified;
  72                                 };
  73                         };
  74                 };
  75
  76                 CPU1: cpu@100 {
  77                         device_type = "cpu";
  78                         compatible = "qcom,kryo485";
  79                         reg = <0x0 0x100>;
  80                         clocks = <&cpufreq_hw 0>;
  81                         enable-method = "psci";
  82                         capacity-dmips-mhz = <488>;
  83                         dynamic-power-coefficient = <232>;
  84                         next-level-cache = <&L2_100>;
  85                         qcom,freq-domain = <&cpufreq_hw 0>;
  86                         operating-points-v2 = <&cpu0_opp_table>;
  87                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
  88                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  89                         power-domains = <&CPU_PD1>;
  90                         power-domain-names = "psci";
  91                         #cooling-cells = <2>;
  92                         L2_100: l2-cache {
  93                                 compatible = "cache";
  94                                 cache-level = <2>;
  95                                 cache-unified;
  96                                 next-level-cache = <&L3_0>;
  97                         };
  98                 };
  99
 100                 CPU2: cpu@200 {
 101                         device_type = "cpu";
 102                         compatible = "qcom,kryo485";
 103                         reg = <0x0 0x200>;
 104                         clocks = <&cpufreq_hw 0>;
 105                         enable-method = "psci";
 106                         capacity-dmips-mhz = <488>;
 107                         dynamic-power-coefficient = <232>;
 108                         next-level-cache = <&L2_200>;
 109                         qcom,freq-domain = <&cpufreq_hw 0>;
 110                         operating-points-v2 = <&cpu0_opp_table>;
 111                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 112                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 113                         power-domains = <&CPU_PD2>;
 114                         power-domain-names = "psci";
 115                         #cooling-cells = <2>;
 116                         L2_200: l2-cache {
 117                                 compatible = "cache";
 118                                 cache-level = <2>;
 119                                 cache-unified;
 120                                 next-level-cache = <&L3_0>;
 121                         };
 122                 };
 123
 124                 CPU3: cpu@300 {
 125                         device_type = "cpu";
 126                         compatible = "qcom,kryo485";
 127                         reg = <0x0 0x300>;
 128                         clocks = <&cpufreq_hw 0>;
 129                         enable-method = "psci";
 130                         capacity-dmips-mhz = <488>;
 131                         dynamic-power-coefficient = <232>;
 132                         next-level-cache = <&L2_300>;
 133                         qcom,freq-domain = <&cpufreq_hw 0>;
 134                         operating-points-v2 = <&cpu0_opp_table>;
 135                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 136                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 137                         power-domains = <&CPU_PD3>;
 138                         power-domain-names = "psci";
 139                         #cooling-cells = <2>;
 140                         L2_300: l2-cache {
 141                                 compatible = "cache";
 142                                 cache-level = <2>;
 143                                 cache-unified;
 144                                 next-level-cache = <&L3_0>;
 145                         };
 146                 };
 147
 148                 CPU4: cpu@400 {
 149                         device_type = "cpu";
 150                         compatible = "qcom,kryo485";
 151                         reg = <0x0 0x400>;
 152                         clocks = <&cpufreq_hw 1>;
 153                         enable-method = "psci";
 154                         capacity-dmips-mhz = <1024>;
 155                         dynamic-power-coefficient = <369>;
 156                         next-level-cache = <&L2_400>;
 157                         qcom,freq-domain = <&cpufreq_hw 1>;
 158                         operating-points-v2 = <&cpu4_opp_table>;
 159                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 160                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 161                         power-domains = <&CPU_PD4>;
 162                         power-domain-names = "psci";
 163                         #cooling-cells = <2>;
 164                         L2_400: l2-cache {
 165                                 compatible = "cache";
 166                                 cache-level = <2>;
 167                                 cache-unified;
 168                                 next-level-cache = <&L3_0>;
 169                         };
 170                 };
 171
 172                 CPU5: cpu@500 {
 173                         device_type = "cpu";
 174                         compatible = "qcom,kryo485";
 175                         reg = <0x0 0x500>;
 176                         clocks = <&cpufreq_hw 1>;
 177                         enable-method = "psci";
 178                         capacity-dmips-mhz = <1024>;
 179                         dynamic-power-coefficient = <369>;
 180                         next-level-cache = <&L2_500>;
 181                         qcom,freq-domain = <&cpufreq_hw 1>;
 182                         operating-points-v2 = <&cpu4_opp_table>;
 183                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 184                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 185                         power-domains = <&CPU_PD5>;
 186                         power-domain-names = "psci";
 187                         #cooling-cells = <2>;
 188                         L2_500: l2-cache {
 189                                 compatible = "cache";
 190                                 cache-level = <2>;
 191                                 cache-unified;
 192                                 next-level-cache = <&L3_0>;
 193                         };
 194                 };
 195
 196                 CPU6: cpu@600 {
 197                         device_type = "cpu";
 198                         compatible = "qcom,kryo485";
 199                         reg = <0x0 0x600>;
 200                         clocks = <&cpufreq_hw 1>;
 201                         enable-method = "psci";
 202                         capacity-dmips-mhz = <1024>;
 203                         dynamic-power-coefficient = <369>;
 204                         next-level-cache = <&L2_600>;
 205                         qcom,freq-domain = <&cpufreq_hw 1>;
 206                         operating-points-v2 = <&cpu4_opp_table>;
 207                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 208                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 209                         power-domains = <&CPU_PD6>;
 210                         power-domain-names = "psci";
 211                         #cooling-cells = <2>;
 212                         L2_600: l2-cache {
 213                                 compatible = "cache";
 214                                 cache-level = <2>;
 215                                 cache-unified;
 216                                 next-level-cache = <&L3_0>;
 217                         };
 218                 };
 219
 220                 CPU7: cpu@700 {
 221                         device_type = "cpu";
 222                         compatible = "qcom,kryo485";
 223                         reg = <0x0 0x700>;
 224                         clocks = <&cpufreq_hw 2>;
 225                         enable-method = "psci";
 226                         capacity-dmips-mhz = <1024>;
 227                         dynamic-power-coefficient = <421>;
 228                         next-level-cache = <&L2_700>;
 229                         qcom,freq-domain = <&cpufreq_hw 2>;
 230                         operating-points-v2 = <&cpu7_opp_table>;
 231                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 232                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 233                         power-domains = <&CPU_PD7>;
 234                         power-domain-names = "psci";
 235                         #cooling-cells = <2>;
 236                         L2_700: l2-cache {
 237                                 compatible = "cache";
 238                                 cache-level = <2>;
 239                                 cache-unified;
 240                                 next-level-cache = <&L3_0>;
 241                         };
 242                 };
 243
 244                 cpu-map {
 245                         cluster0 {
 246                                 core0 {
 247                                         cpu = <&CPU0>;
 248                                 };
 249
 250                                 core1 {
 251                                         cpu = <&CPU1>;
 252                                 };
 253
 254                                 core2 {
 255                                         cpu = <&CPU2>;
 256                                 };
 257
 258                                 core3 {
 259                                         cpu = <&CPU3>;
 260                                 };
 261
 262                                 core4 {
 263                                         cpu = <&CPU4>;
 264                                 };
 265
 266                                 core5 {
 267                                         cpu = <&CPU5>;
 268                                 };
 269
 270                                 core6 {
 271                                         cpu = <&CPU6>;
 272                                 };
 273
 274                                 core7 {
 275                                         cpu = <&CPU7>;
 276                                 };
 277                         };
 278                 };
 279
 280                 idle-states {
 281                         entry-method = "psci";
 282
 283                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 284                                 compatible = "arm,idle-state";
 285                                 idle-state-name = "little-rail-power-collapse";
 286                                 arm,psci-suspend-param = <0x40000004>;
 287                                 entry-latency-us = <355>;
 288                                 exit-latency-us = <909>;
 289                                 min-residency-us = <3934>;
 290                                 local-timer-stop;
 291                         };
 292
 293                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 294                                 compatible = "arm,idle-state";
 295                                 idle-state-name = "big-rail-power-collapse";
 296                                 arm,psci-suspend-param = <0x40000004>;
 297                                 entry-latency-us = <241>;
 298                                 exit-latency-us = <1461>;
 299                                 min-residency-us = <4488>;
 300                                 local-timer-stop;
 301                         };
 302                 };
 303
 304                 domain-idle-states {
 305                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 306                                 compatible = "domain-idle-state";
 307                                 arm,psci-suspend-param = <0x4100c244>;
 308                                 entry-latency-us = <3263>;
 309                                 exit-latency-us = <6562>;
 310                                 min-residency-us = <9987>;
 311                         };
 312                 };
 313         };
 314
 315         cpu0_opp_table: opp-table-cpu0 {
 316                 compatible = "operating-points-v2";
 317                 opp-shared;
 318
 319                 cpu0_opp1: opp-300000000 {
 320                         opp-hz = /bits/ 64 <300000000>;
 321                         opp-peak-kBps = <800000 9600000>;
 322                 };
 323
 324                 cpu0_opp2: opp-403200000 {
 325                         opp-hz = /bits/ 64 <403200000>;
 326                         opp-peak-kBps = <800000 9600000>;
 327                 };
 328
 329                 cpu0_opp3: opp-499200000 {
 330                         opp-hz = /bits/ 64 <499200000>;
 331                         opp-peak-kBps = <800000 12902400>;
 332                 };
 333
 334                 cpu0_opp4: opp-576000000 {
 335                         opp-hz = /bits/ 64 <576000000>;
 336                         opp-peak-kBps = <800000 12902400>;
 337                 };
 338
 339                 cpu0_opp5: opp-672000000 {
 340                         opp-hz = /bits/ 64 <672000000>;
 341                         opp-peak-kBps = <800000 15974400>;
 342                 };
 343
 344                 cpu0_opp6: opp-768000000 {
 345                         opp-hz = /bits/ 64 <768000000>;
 346                         opp-peak-kBps = <1804000 19660800>;
 347                 };
 348
 349                 cpu0_opp7: opp-844800000 {
 350                         opp-hz = /bits/ 64 <844800000>;
 351                         opp-peak-kBps = <1804000 19660800>;
 352                 };
 353
 354                 cpu0_opp8: opp-940800000 {
 355                         opp-hz = /bits/ 64 <940800000>;
 356                         opp-peak-kBps = <1804000 22732800>;
 357                 };
 358
 359                 cpu0_opp9: opp-1036800000 {
 360                         opp-hz = /bits/ 64 <1036800000>;
 361                         opp-peak-kBps = <1804000 22732800>;
 362                 };
 363
 364                 cpu0_opp10: opp-1113600000 {
 365                         opp-hz = /bits/ 64 <1113600000>;
 366                         opp-peak-kBps = <2188000 25804800>;
 367                 };
 368
 369                 cpu0_opp11: opp-1209600000 {
 370                         opp-hz = /bits/ 64 <1209600000>;
 371                         opp-peak-kBps = <2188000 31948800>;
 372                 };
 373
 374                 cpu0_opp12: opp-1305600000 {
 375                         opp-hz = /bits/ 64 <1305600000>;
 376                         opp-peak-kBps = <3072000 31948800>;
 377                 };
 378
 379                 cpu0_opp13: opp-1382400000 {
 380                         opp-hz = /bits/ 64 <1382400000>;
 381                         opp-peak-kBps = <3072000 31948800>;
 382                 };
 383
 384                 cpu0_opp14: opp-1478400000 {
 385                         opp-hz = /bits/ 64 <1478400000>;
 386                         opp-peak-kBps = <3072000 31948800>;
 387                 };
 388
 389                 cpu0_opp15: opp-1555200000 {
 390                         opp-hz = /bits/ 64 <1555200000>;
 391                         opp-peak-kBps = <3072000 40550400>;
 392                 };
 393
 394                 cpu0_opp16: opp-1632000000 {
 395                         opp-hz = /bits/ 64 <1632000000>;
 396                         opp-peak-kBps = <3072000 40550400>;
 397                 };
 398
 399                 cpu0_opp17: opp-1708800000 {
 400                         opp-hz = /bits/ 64 <1708800000>;
 401                         opp-peak-kBps = <3072000 43008000>;
 402                 };
 403
 404                 cpu0_opp18: opp-1785600000 {
 405                         opp-hz = /bits/ 64 <1785600000>;
 406                         opp-peak-kBps = <3072000 43008000>;
 407                 };
 408         };
 409
 410         cpu4_opp_table: opp-table-cpu4 {
 411                 compatible = "operating-points-v2";
 412                 opp-shared;
 413
 414                 cpu4_opp1: opp-710400000 {
 415                         opp-hz = /bits/ 64 <710400000>;
 416                         opp-peak-kBps = <1804000 15974400>;
 417                 };
 418
 419                 cpu4_opp2: opp-825600000 {
 420                         opp-hz = /bits/ 64 <825600000>;
 421                         opp-peak-kBps = <2188000 19660800>;
 422                 };
 423
 424                 cpu4_opp3: opp-940800000 {
 425                         opp-hz = /bits/ 64 <940800000>;
 426                         opp-peak-kBps = <2188000 22732800>;
 427                 };
 428
 429                 cpu4_opp4: opp-1056000000 {
 430                         opp-hz = /bits/ 64 <1056000000>;
 431                         opp-peak-kBps = <3072000 25804800>;
 432                 };
 433
 434                 cpu4_opp5: opp-1171200000 {
 435                         opp-hz = /bits/ 64 <1171200000>;
 436                         opp-peak-kBps = <3072000 31948800>;
 437                 };
 438
 439                 cpu4_opp6: opp-1286400000 {
 440                         opp-hz = /bits/ 64 <1286400000>;
 441                         opp-peak-kBps = <4068000 31948800>;
 442                 };
 443
 444                 cpu4_opp7: opp-1401600000 {
 445                         opp-hz = /bits/ 64 <1401600000>;
 446                         opp-peak-kBps = <4068000 31948800>;
 447                 };
 448
 449                 cpu4_opp8: opp-1497600000 {
 450                         opp-hz = /bits/ 64 <1497600000>;
 451                         opp-peak-kBps = <4068000 40550400>;
 452                 };
 453
 454                 cpu4_opp9: opp-1612800000 {
 455                         opp-hz = /bits/ 64 <1612800000>;
 456                         opp-peak-kBps = <4068000 40550400>;
 457                 };
 458
 459                 cpu4_opp10: opp-1708800000 {
 460                         opp-hz = /bits/ 64 <1708800000>;
 461                         opp-peak-kBps = <4068000 43008000>;
 462                 };
 463
 464                 cpu4_opp11: opp-1804800000 {
 465                         opp-hz = /bits/ 64 <1804800000>;
 466                         opp-peak-kBps = <6220000 43008000>;
 467                 };
 468
 469                 cpu4_opp12: opp-1920000000 {
 470                         opp-hz = /bits/ 64 <1920000000>;
 471                         opp-peak-kBps = <6220000 49152000>;
 472                 };
 473
 474                 cpu4_opp13: opp-2016000000 {
 475                         opp-hz = /bits/ 64 <2016000000>;
 476                         opp-peak-kBps = <7216000 49152000>;
 477                 };
 478
 479                 cpu4_opp14: opp-2131200000 {
 480                         opp-hz = /bits/ 64 <2131200000>;
 481                         opp-peak-kBps = <8368000 49152000>;
 482                 };
 483
 484                 cpu4_opp15: opp-2227200000 {
 485                         opp-hz = /bits/ 64 <2227200000>;
 486                         opp-peak-kBps = <8368000 51609600>;
 487                 };
 488
 489                 cpu4_opp16: opp-2323200000 {
 490                         opp-hz = /bits/ 64 <2323200000>;
 491                         opp-peak-kBps = <8368000 51609600>;
 492                 };
 493
 494                 cpu4_opp17: opp-2419200000 {
 495                         opp-hz = /bits/ 64 <2419200000>;
 496                         opp-peak-kBps = <8368000 51609600>;
 497                 };
 498         };
 499
 500         cpu7_opp_table: opp-table-cpu7 {
 501                 compatible = "operating-points-v2";
 502                 opp-shared;
 503
 504                 cpu7_opp1: opp-825600000 {
 505                         opp-hz = /bits/ 64 <825600000>;
 506                         opp-peak-kBps = <2188000 19660800>;
 507                 };
 508
 509                 cpu7_opp2: opp-940800000 {
 510                         opp-hz = /bits/ 64 <940800000>;
 511                         opp-peak-kBps = <2188000 22732800>;
 512                 };
 513
 514                 cpu7_opp3: opp-1056000000 {
 515                         opp-hz = /bits/ 64 <1056000000>;
 516                         opp-peak-kBps = <3072000 25804800>;
 517                 };
 518
 519                 cpu7_opp4: opp-1171200000 {
 520                         opp-hz = /bits/ 64 <1171200000>;
 521                         opp-peak-kBps = <3072000 31948800>;
 522                 };
 523
 524                 cpu7_opp5: opp-1286400000 {
 525                         opp-hz = /bits/ 64 <1286400000>;
 526                         opp-peak-kBps = <4068000 31948800>;
 527                 };
 528
 529                 cpu7_opp6: opp-1401600000 {
 530                         opp-hz = /bits/ 64 <1401600000>;
 531                         opp-peak-kBps = <4068000 31948800>;
 532                 };
 533
 534                 cpu7_opp7: opp-1497600000 {
 535                         opp-hz = /bits/ 64 <1497600000>;
 536                         opp-peak-kBps = <4068000 40550400>;
 537                 };
 538
 539                 cpu7_opp8: opp-1612800000 {
 540                         opp-hz = /bits/ 64 <1612800000>;
 541                         opp-peak-kBps = <4068000 40550400>;
 542                 };
 543
 544                 cpu7_opp9: opp-1708800000 {
 545                         opp-hz = /bits/ 64 <1708800000>;
 546                         opp-peak-kBps = <4068000 43008000>;
 547                 };
 548
 549                 cpu7_opp10: opp-1804800000 {
 550                         opp-hz = /bits/ 64 <1804800000>;
 551                         opp-peak-kBps = <6220000 43008000>;
 552                 };
 553
 554                 cpu7_opp11: opp-1920000000 {
 555                         opp-hz = /bits/ 64 <1920000000>;
 556                         opp-peak-kBps = <6220000 49152000>;
 557                 };
 558
 559                 cpu7_opp12: opp-2016000000 {
 560                         opp-hz = /bits/ 64 <2016000000>;
 561                         opp-peak-kBps = <7216000 49152000>;
 562                 };
 563
 564                 cpu7_opp13: opp-2131200000 {
 565                         opp-hz = /bits/ 64 <2131200000>;
 566                         opp-peak-kBps = <8368000 49152000>;
 567                 };
 568
 569                 cpu7_opp14: opp-2227200000 {
 570                         opp-hz = /bits/ 64 <2227200000>;
 571                         opp-peak-kBps = <8368000 51609600>;
 572                 };
 573
 574                 cpu7_opp15: opp-2323200000 {
 575                         opp-hz = /bits/ 64 <2323200000>;
 576                         opp-peak-kBps = <8368000 51609600>;
 577                 };
 578
 579                 cpu7_opp16: opp-2419200000 {
 580                         opp-hz = /bits/ 64 <2419200000>;
 581                         opp-peak-kBps = <8368000 51609600>;
 582                 };
 583
 584                 cpu7_opp17: opp-2534400000 {
 585                         opp-hz = /bits/ 64 <2534400000>;
 586                         opp-peak-kBps = <8368000 51609600>;
 587                 };
 588
 589                 cpu7_opp18: opp-2649600000 {
 590                         opp-hz = /bits/ 64 <2649600000>;
 591                         opp-peak-kBps = <8368000 51609600>;
 592                 };
 593
 594                 cpu7_opp19: opp-2745600000 {
 595                         opp-hz = /bits/ 64 <2745600000>;
 596                         opp-peak-kBps = <8368000 51609600>;
 597                 };
 598
 599                 cpu7_opp20: opp-2841600000 {
 600                         opp-hz = /bits/ 64 <2841600000>;
 601                         opp-peak-kBps = <8368000 51609600>;
 602                 };
 603         };
 604
 605         firmware {
 606                 scm: scm {
 607                         compatible = "qcom,scm-sm8150", "qcom,scm";
 608                         #reset-cells = <1>;
 609                 };
 610         };
 611
 612         memory@80000000 {
 613                 device_type = "memory";
 614                 /* We expect the bootloader to fill in the size */
 615                 reg = <0x0 0x80000000 0x0 0x0>;
 616         };
 617
 618         pmu {
 619                 compatible = "arm,armv8-pmuv3";
 620                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 621         };
 622
 623         psci {
 624                 compatible = "arm,psci-1.0";
 625                 method = "smc";
 626
 627                 CPU_PD0: power-domain-cpu0 {
 628                         #power-domain-cells = <0>;
 629                         power-domains = <&CLUSTER_PD>;
 630                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 631                 };
 632
 633                 CPU_PD1: power-domain-cpu1 {
 634                         #power-domain-cells = <0>;
 635                         power-domains = <&CLUSTER_PD>;
 636                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 637                 };
 638
 639                 CPU_PD2: power-domain-cpu2 {
 640                         #power-domain-cells = <0>;
 641                         power-domains = <&CLUSTER_PD>;
 642                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 643                 };
 644
 645                 CPU_PD3: power-domain-cpu3 {
 646                         #power-domain-cells = <0>;
 647                         power-domains = <&CLUSTER_PD>;
 648                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 649                 };
 650
 651                 CPU_PD4: power-domain-cpu4 {
 652                         #power-domain-cells = <0>;
 653                         power-domains = <&CLUSTER_PD>;
 654                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 655                 };
 656
 657                 CPU_PD5: power-domain-cpu5 {
 658                         #power-domain-cells = <0>;
 659                         power-domains = <&CLUSTER_PD>;
 660                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 661                 };
 662
 663                 CPU_PD6: power-domain-cpu6 {
 664                         #power-domain-cells = <0>;
 665                         power-domains = <&CLUSTER_PD>;
 666                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 667                 };
 668
 669                 CPU_PD7: power-domain-cpu7 {
 670                         #power-domain-cells = <0>;
 671                         power-domains = <&CLUSTER_PD>;
 672                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 673                 };
 674
 675                 CLUSTER_PD: power-domain-cpu-cluster0 {
 676                         #power-domain-cells = <0>;
 677                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 678                 };
 679         };
 680
 681         reserved-memory {
 682                 #address-cells = <2>;
 683                 #size-cells = <2>;
 684                 ranges;
 685
 686                 hyp_mem: memory@85700000 {
 687                         reg = <0x0 0x85700000 0x0 0x600000>;
 688                         no-map;
 689                 };
 690
 691                 xbl_mem: memory@85d00000 {
 692                         reg = <0x0 0x85d00000 0x0 0x140000>;
 693                         no-map;
 694                 };
 695
 696                 aop_mem: memory@85f00000 {
 697                         reg = <0x0 0x85f00000 0x0 0x20000>;
 698                         no-map;
 699                 };
 700
 701                 aop_cmd_db: memory@85f20000 {
 702                         compatible = "qcom,cmd-db";
 703                         reg = <0x0 0x85f20000 0x0 0x20000>;
 704                         no-map;
 705                 };
 706
 707                 smem_mem: memory@86000000 {
 708                         reg = <0x0 0x86000000 0x0 0x200000>;
 709                         no-map;
 710                 };
 711
 712                 tz_mem: memory@86200000 {
 713                         reg = <0x0 0x86200000 0x0 0x3900000>;
 714                         no-map;
 715                 };
 716
 717                 rmtfs_mem: memory@89b00000 {
 718                         compatible = "qcom,rmtfs-mem";
 719                         reg = <0x0 0x89b00000 0x0 0x200000>;
 720                         no-map;
 721
 722                         qcom,client-id = <1>;
 723                         qcom,vmid = <15>;
 724                 };
 725
 726                 camera_mem: memory@8b700000 {
 727                         reg = <0x0 0x8b700000 0x0 0x500000>;
 728                         no-map;
 729                 };
 730
 731                 wlan_mem: memory@8bc00000 {
 732                         reg = <0x0 0x8bc00000 0x0 0x180000>;
 733                         no-map;
 734                 };
 735
 736                 npu_mem: memory@8bd80000 {
 737                         reg = <0x0 0x8bd80000 0x0 0x80000>;
 738                         no-map;
 739                 };
 740
 741                 adsp_mem: memory@8be00000 {
 742                         reg = <0x0 0x8be00000 0x0 0x1a00000>;
 743                         no-map;
 744                 };
 745
 746                 mpss_mem: memory@8d800000 {
 747                         reg = <0x0 0x8d800000 0x0 0x9600000>;
 748                         no-map;
 749                 };
 750
 751                 venus_mem: memory@96e00000 {
 752                         reg = <0x0 0x96e00000 0x0 0x500000>;
 753                         no-map;
 754                 };
 755
 756                 slpi_mem: memory@97300000 {
 757                         reg = <0x0 0x97300000 0x0 0x1400000>;
 758                         no-map;
 759                 };
 760
 761                 ipa_fw_mem: memory@98700000 {
 762                         reg = <0x0 0x98700000 0x0 0x10000>;
 763                         no-map;
 764                 };
 765
 766                 ipa_gsi_mem: memory@98710000 {
 767                         reg = <0x0 0x98710000 0x0 0x5000>;
 768                         no-map;
 769                 };
 770
 771                 gpu_mem: memory@98715000 {
 772                         reg = <0x0 0x98715000 0x0 0x2000>;
 773                         no-map;
 774                 };
 775
 776                 spss_mem: memory@98800000 {
 777                         reg = <0x0 0x98800000 0x0 0x100000>;
 778                         no-map;
 779                 };
 780
 781                 cdsp_mem: memory@98900000 {
 782                         reg = <0x0 0x98900000 0x0 0x1400000>;
 783                         no-map;
 784                 };
 785
 786                 qseecom_mem: memory@9e400000 {
 787                         reg = <0x0 0x9e400000 0x0 0x1400000>;
 788                         no-map;
 789                 };
 790         };
 791
 792         smem {
 793                 compatible = "qcom,smem";
 794                 memory-region = <&smem_mem>;
 795                 hwlocks = <&tcsr_mutex 3>;
 796         };
 797
 798         smp2p-cdsp {
 799                 compatible = "qcom,smp2p";
 800                 qcom,smem = <94>, <432>;
 801
 802                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 803
 804                 mboxes = <&apss_shared 6>;
 805
 806                 qcom,local-pid = <0>;
 807                 qcom,remote-pid = <5>;
 808
 809                 cdsp_smp2p_out: master-kernel {
 810                         qcom,entry-name = "master-kernel";
 811                         #qcom,smem-state-cells = <1>;
 812                 };
 813
 814                 cdsp_smp2p_in: slave-kernel {
 815                         qcom,entry-name = "slave-kernel";
 816
 817                         interrupt-controller;
 818                         #interrupt-cells = <2>;
 819                 };
 820         };
 821
 822         smp2p-lpass {
 823                 compatible = "qcom,smp2p";
 824                 qcom,smem = <443>, <429>;
 825
 826                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 827
 828                 mboxes = <&apss_shared 10>;
 829
 830                 qcom,local-pid = <0>;
 831                 qcom,remote-pid = <2>;
 832
 833                 adsp_smp2p_out: master-kernel {
 834                         qcom,entry-name = "master-kernel";
 835                         #qcom,smem-state-cells = <1>;
 836                 };
 837
 838                 adsp_smp2p_in: slave-kernel {
 839                         qcom,entry-name = "slave-kernel";
 840
 841                         interrupt-controller;
 842                         #interrupt-cells = <2>;
 843                 };
 844         };
 845
 846         smp2p-mpss {
 847                 compatible = "qcom,smp2p";
 848                 qcom,smem = <435>, <428>;
 849
 850                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 851
 852                 mboxes = <&apss_shared 14>;
 853
 854                 qcom,local-pid = <0>;
 855                 qcom,remote-pid = <1>;
 856
 857                 modem_smp2p_out: master-kernel {
 858                         qcom,entry-name = "master-kernel";
 859                         #qcom,smem-state-cells = <1>;
 860                 };
 861
 862                 modem_smp2p_in: slave-kernel {
 863                         qcom,entry-name = "slave-kernel";
 864
 865                         interrupt-controller;
 866                         #interrupt-cells = <2>;
 867                 };
 868         };
 869
 870         smp2p-slpi {
 871                 compatible = "qcom,smp2p";
 872                 qcom,smem = <481>, <430>;
 873
 874                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 875
 876                 mboxes = <&apss_shared 26>;
 877
 878                 qcom,local-pid = <0>;
 879                 qcom,remote-pid = <3>;
 880
 881                 slpi_smp2p_out: master-kernel {
 882                         qcom,entry-name = "master-kernel";
 883                         #qcom,smem-state-cells = <1>;
 884                 };
 885
 886                 slpi_smp2p_in: slave-kernel {
 887                         qcom,entry-name = "slave-kernel";
 888
 889                         interrupt-controller;
 890                         #interrupt-cells = <2>;
 891                 };
 892         };
 893
 894         soc: soc@0 {
 895                 #address-cells = <2>;
 896                 #size-cells = <2>;
 897                 ranges = <0 0 0 0 0x10 0>;
 898                 dma-ranges = <0 0 0 0 0x10 0>;
 899                 compatible = "simple-bus";
 900
 901                 gcc: clock-controller@100000 {
 902                         compatible = "qcom,gcc-sm8150";
 903                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 904                         #clock-cells = <1>;
 905                         #reset-cells = <1>;
 906                         #power-domain-cells = <1>;
 907                         clock-names = "bi_tcxo",
 908                                       "sleep_clk";
 909                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 910                                  <&sleep_clk>;
 911                 };
 912
 913                 gpi_dma0: dma-controller@800000 {
 914                         compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
 915                         reg = <0 0x00800000 0 0x60000>;
 916                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 917                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 918                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 919                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 920                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 921                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 922                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 923                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 924                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 925                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 926                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 927                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 928                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 929                         dma-channels = <13>;
 930                         dma-channel-mask = <0xfa>;
 931                         iommus = <&apps_smmu 0x00d6 0x0>;
 932                         #dma-cells = <3>;
 933                         status = "disabled";
 934                 };
 935
 936                 ethernet: ethernet@20000 {
 937                         compatible = "qcom,sm8150-ethqos";
 938                         reg = <0x0 0x00020000 0x0 0x10000>,
 939                               <0x0 0x00036000 0x0 0x100>;
 940                         reg-names = "stmmaceth", "rgmii";
 941                         clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
 942                         clocks = <&gcc GCC_EMAC_AXI_CLK>,
 943                                 <&gcc GCC_EMAC_SLV_AHB_CLK>,
 944                                 <&gcc GCC_EMAC_PTP_CLK>,
 945                                 <&gcc GCC_EMAC_RGMII_CLK>;
 946                         interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
 947                                      <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
 948                         interrupt-names = "macirq", "eth_lpi";
 949
 950                         power-domains = <&gcc EMAC_GDSC>;
 951                         resets = <&gcc GCC_EMAC_BCR>;
 952
 953                         iommus = <&apps_smmu 0x3c0 0x0>;
 954
 955                         snps,tso;
 956                         rx-fifo-depth = <4096>;
 957                         tx-fifo-depth = <4096>;
 958
 959                         status = "disabled";
 960                 };
 961
 962                 qfprom: efuse@784000 {
 963                         compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
 964                         reg = <0 0x00784000 0 0x8ff>;
 965                         #address-cells = <1>;
 966                         #size-cells = <1>;
 967
 968                         gpu_speed_bin: gpu_speed_bin@133 {
 969                                 reg = <0x133 0x1>;
 970                                 bits = <5 3>;
 971                         };
 972                 };
 973
 974                 qupv3_id_0: geniqup@8c0000 {
 975                         compatible = "qcom,geni-se-qup";
 976                         reg = <0x0 0x008c0000 0x0 0x6000>;
 977                         clock-names = "m-ahb", "s-ahb";
 978                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 979                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 980                         iommus = <&apps_smmu 0xc3 0x0>;
 981                         #address-cells = <2>;
 982                         #size-cells = <2>;
 983                         ranges;
 984                         status = "disabled";
 985
 986                         i2c0: i2c@880000 {
 987                                 compatible = "qcom,geni-i2c";
 988                                 reg = <0 0x00880000 0 0x4000>;
 989                                 clock-names = "se";
 990                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 991                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 992                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 993                                 dma-names = "tx", "rx";
 994                                 pinctrl-names = "default";
 995                                 pinctrl-0 = <&qup_i2c0_default>;
 996                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 997                                 #address-cells = <1>;
 998                                 #size-cells = <0>;
 999                                 status = "disabled";
1000                         };
1001
1002                         spi0: spi@880000 {
1003                                 compatible = "qcom,geni-spi";
1004                                 reg = <0 0x00880000 0 0x4000>;
1005                                 reg-names = "se";
1006                                 clock-names = "se";
1007                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1008                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1009                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1010                                 dma-names = "tx", "rx";
1011                                 pinctrl-names = "default";
1012                                 pinctrl-0 = <&qup_spi0_default>;
1013                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1014                                 spi-max-frequency = <50000000>;
1015                                 #address-cells = <1>;
1016                                 #size-cells = <0>;
1017                                 status = "disabled";
1018                         };
1019
1020                         i2c1: i2c@884000 {
1021                                 compatible = "qcom,geni-i2c";
1022                                 reg = <0 0x00884000 0 0x4000>;
1023                                 clock-names = "se";
1024                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1025                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1026                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1027                                 dma-names = "tx", "rx";
1028                                 pinctrl-names = "default";
1029                                 pinctrl-0 = <&qup_i2c1_default>;
1030                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1031                                 #address-cells = <1>;
1032                                 #size-cells = <0>;
1033                                 status = "disabled";
1034                         };
1035
1036                         spi1: spi@884000 {
1037                                 compatible = "qcom,geni-spi";
1038                                 reg = <0 0x00884000 0 0x4000>;
1039                                 reg-names = "se";
1040                                 clock-names = "se";
1041                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1042                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1043                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1044                                 dma-names = "tx", "rx";
1045                                 pinctrl-names = "default";
1046                                 pinctrl-0 = <&qup_spi1_default>;
1047                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1048                                 spi-max-frequency = <50000000>;
1049                                 #address-cells = <1>;
1050                                 #size-cells = <0>;
1051                                 status = "disabled";
1052                         };
1053
1054                         i2c2: i2c@888000 {
1055                                 compatible = "qcom,geni-i2c";
1056                                 reg = <0 0x00888000 0 0x4000>;
1057                                 clock-names = "se";
1058                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1059                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1060                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1061                                 dma-names = "tx", "rx";
1062                                 pinctrl-names = "default";
1063                                 pinctrl-0 = <&qup_i2c2_default>;
1064                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1065                                 #address-cells = <1>;
1066                                 #size-cells = <0>;
1067                                 status = "disabled";
1068                         };
1069
1070                         spi2: spi@888000 {
1071                                 compatible = "qcom,geni-spi";
1072                                 reg = <0 0x00888000 0 0x4000>;
1073                                 reg-names = "se";
1074                                 clock-names = "se";
1075                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1076                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1077                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1078                                 dma-names = "tx", "rx";
1079                                 pinctrl-names = "default";
1080                                 pinctrl-0 = <&qup_spi2_default>;
1081                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1082                                 spi-max-frequency = <50000000>;
1083                                 #address-cells = <1>;
1084                                 #size-cells = <0>;
1085                                 status = "disabled";
1086                         };
1087
1088                         i2c3: i2c@88c000 {
1089                                 compatible = "qcom,geni-i2c";
1090                                 reg = <0 0x0088c000 0 0x4000>;
1091                                 clock-names = "se";
1092                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1093                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1094                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1095                                 dma-names = "tx", "rx";
1096                                 pinctrl-names = "default";
1097                                 pinctrl-0 = <&qup_i2c3_default>;
1098                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1099                                 #address-cells = <1>;
1100                                 #size-cells = <0>;
1101                                 status = "disabled";
1102                         };
1103
1104                         spi3: spi@88c000 {
1105                                 compatible = "qcom,geni-spi";
1106                                 reg = <0 0x0088c000 0 0x4000>;
1107                                 reg-names = "se";
1108                                 clock-names = "se";
1109                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1110                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1111                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1112                                 dma-names = "tx", "rx";
1113                                 pinctrl-names = "default";
1114                                 pinctrl-0 = <&qup_spi3_default>;
1115                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1116                                 spi-max-frequency = <50000000>;
1117                                 #address-cells = <1>;
1118                                 #size-cells = <0>;
1119                                 status = "disabled";
1120                         };
1121
1122                         i2c4: i2c@890000 {
1123                                 compatible = "qcom,geni-i2c";
1124                                 reg = <0 0x00890000 0 0x4000>;
1125                                 clock-names = "se";
1126                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1127                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1128                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1129                                 dma-names = "tx", "rx";
1130                                 pinctrl-names = "default";
1131                                 pinctrl-0 = <&qup_i2c4_default>;
1132                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1133                                 #address-cells = <1>;
1134                                 #size-cells = <0>;
1135                                 status = "disabled";
1136                         };
1137
1138                         spi4: spi@890000 {
1139                                 compatible = "qcom,geni-spi";
1140                                 reg = <0 0x00890000 0 0x4000>;
1141                                 reg-names = "se";
1142                                 clock-names = "se";
1143                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1144                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1145                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1146                                 dma-names = "tx", "rx";
1147                                 pinctrl-names = "default";
1148                                 pinctrl-0 = <&qup_spi4_default>;
1149                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1150                                 spi-max-frequency = <50000000>;
1151                                 #address-cells = <1>;
1152                                 #size-cells = <0>;
1153                                 status = "disabled";
1154                         };
1155
1156                         i2c5: i2c@894000 {
1157                                 compatible = "qcom,geni-i2c";
1158                                 reg = <0 0x00894000 0 0x4000>;
1159                                 clock-names = "se";
1160                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1161                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1162                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1163                                 dma-names = "tx", "rx";
1164                                 pinctrl-names = "default";
1165                                 pinctrl-0 = <&qup_i2c5_default>;
1166                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1167                                 #address-cells = <1>;
1168                                 #size-cells = <0>;
1169                                 status = "disabled";
1170                         };
1171
1172                         spi5: spi@894000 {
1173                                 compatible = "qcom,geni-spi";
1174                                 reg = <0 0x00894000 0 0x4000>;
1175                                 reg-names = "se";
1176                                 clock-names = "se";
1177                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1178                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1179                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1180                                 dma-names = "tx", "rx";
1181                                 pinctrl-names = "default";
1182                                 pinctrl-0 = <&qup_spi5_default>;
1183                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1184                                 spi-max-frequency = <50000000>;
1185                                 #address-cells = <1>;
1186                                 #size-cells = <0>;
1187                                 status = "disabled";
1188                         };
1189
1190                         i2c6: i2c@898000 {
1191                                 compatible = "qcom,geni-i2c";
1192                                 reg = <0 0x00898000 0 0x4000>;
1193                                 clock-names = "se";
1194                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1195                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1196                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1197                                 dma-names = "tx", "rx";
1198                                 pinctrl-names = "default";
1199                                 pinctrl-0 = <&qup_i2c6_default>;
1200                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1201                                 #address-cells = <1>;
1202                                 #size-cells = <0>;
1203                                 status = "disabled";
1204                         };
1205
1206                         spi6: spi@898000 {
1207                                 compatible = "qcom,geni-spi";
1208                                 reg = <0 0x00898000 0 0x4000>;
1209                                 reg-names = "se";
1210                                 clock-names = "se";
1211                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1212                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1213                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1214                                 dma-names = "tx", "rx";
1215                                 pinctrl-names = "default";
1216                                 pinctrl-0 = <&qup_spi6_default>;
1217                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1218                                 spi-max-frequency = <50000000>;
1219                                 #address-cells = <1>;
1220                                 #size-cells = <0>;
1221                                 status = "disabled";
1222                         };
1223
1224                         i2c7: i2c@89c000 {
1225                                 compatible = "qcom,geni-i2c";
1226                                 reg = <0 0x0089c000 0 0x4000>;
1227                                 clock-names = "se";
1228                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1229                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1230                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1231                                 dma-names = "tx", "rx";
1232                                 pinctrl-names = "default";
1233                                 pinctrl-0 = <&qup_i2c7_default>;
1234                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1235                                 #address-cells = <1>;
1236                                 #size-cells = <0>;
1237                                 status = "disabled";
1238                         };
1239
1240                         spi7: spi@89c000 {
1241                                 compatible = "qcom,geni-spi";
1242                                 reg = <0 0x0089c000 0 0x4000>;
1243                                 reg-names = "se";
1244                                 clock-names = "se";
1245                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1246                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1247                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1248                                 dma-names = "tx", "rx";
1249                                 pinctrl-names = "default";
1250                                 pinctrl-0 = <&qup_spi7_default>;
1251                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1252                                 spi-max-frequency = <50000000>;
1253                                 #address-cells = <1>;
1254                                 #size-cells = <0>;
1255                                 status = "disabled";
1256                         };
1257                 };
1258
1259                 gpi_dma1: dma-controller@a00000 {
1260                         compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1261                         reg = <0 0x00a00000 0 0x60000>;
1262                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1263                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1264                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1265                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1266                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1267                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1268                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1269                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1270                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1271                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1272                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1273                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1274                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1275                         dma-channels = <13>;
1276                         dma-channel-mask = <0xfa>;
1277                         iommus = <&apps_smmu 0x0616 0x0>;
1278                         #dma-cells = <3>;
1279                         status = "disabled";
1280                 };
1281
1282                 qupv3_id_1: geniqup@ac0000 {
1283                         compatible = "qcom,geni-se-qup";
1284                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1285                         clock-names = "m-ahb", "s-ahb";
1286                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1287                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1288                         iommus = <&apps_smmu 0x603 0x0>;
1289                         #address-cells = <2>;
1290                         #size-cells = <2>;
1291                         ranges;
1292                         status = "disabled";
1293
1294                         i2c8: i2c@a80000 {
1295                                 compatible = "qcom,geni-i2c";
1296                                 reg = <0 0x00a80000 0 0x4000>;
1297                                 clock-names = "se";
1298                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1299                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1300                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1301                                 dma-names = "tx", "rx";
1302                                 pinctrl-names = "default";
1303                                 pinctrl-0 = <&qup_i2c8_default>;
1304                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1305                                 #address-cells = <1>;
1306                                 #size-cells = <0>;
1307                                 status = "disabled";
1308                         };
1309
1310                         spi8: spi@a80000 {
1311                                 compatible = "qcom,geni-spi";
1312                                 reg = <0 0x00a80000 0 0x4000>;
1313                                 reg-names = "se";
1314                                 clock-names = "se";
1315                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1316                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1317                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1318                                 dma-names = "tx", "rx";
1319                                 pinctrl-names = "default";
1320                                 pinctrl-0 = <&qup_spi8_default>;
1321                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1322                                 spi-max-frequency = <50000000>;
1323                                 #address-cells = <1>;
1324                                 #size-cells = <0>;
1325                                 status = "disabled";
1326                         };
1327
1328                         i2c9: i2c@a84000 {
1329                                 compatible = "qcom,geni-i2c";
1330                                 reg = <0 0x00a84000 0 0x4000>;
1331                                 clock-names = "se";
1332                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1333                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1334                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1335                                 dma-names = "tx", "rx";
1336                                 pinctrl-names = "default";
1337                                 pinctrl-0 = <&qup_i2c9_default>;
1338                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1339                                 #address-cells = <1>;
1340                                 #size-cells = <0>;
1341                                 status = "disabled";
1342                         };
1343
1344                         spi9: spi@a84000 {
1345                                 compatible = "qcom,geni-spi";
1346                                 reg = <0 0x00a84000 0 0x4000>;
1347                                 reg-names = "se";
1348                                 clock-names = "se";
1349                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1350                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1351                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1352                                 dma-names = "tx", "rx";
1353                                 pinctrl-names = "default";
1354                                 pinctrl-0 = <&qup_spi9_default>;
1355                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1356                                 spi-max-frequency = <50000000>;
1357                                 #address-cells = <1>;
1358                                 #size-cells = <0>;
1359                                 status = "disabled";
1360                         };
1361
1362                         uart9: serial@a84000 {
1363                                 compatible = "qcom,geni-uart";
1364                                 reg = <0x0 0x00a84000 0x0 0x4000>;
1365                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1366                                 clock-names = "se";
1367                                 pinctrl-0 = <&qup_uart9_default>;
1368                                 pinctrl-names = "default";
1369                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1370                                 status = "disabled";
1371                         };
1372
1373                         i2c10: i2c@a88000 {
1374                                 compatible = "qcom,geni-i2c";
1375                                 reg = <0 0x00a88000 0 0x4000>;
1376                                 clock-names = "se";
1377                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1378                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1379                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1380                                 dma-names = "tx", "rx";
1381                                 pinctrl-names = "default";
1382                                 pinctrl-0 = <&qup_i2c10_default>;
1383                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1384                                 #address-cells = <1>;
1385                                 #size-cells = <0>;
1386                                 status = "disabled";
1387                         };
1388
1389                         spi10: spi@a88000 {
1390                                 compatible = "qcom,geni-spi";
1391                                 reg = <0 0x00a88000 0 0x4000>;
1392                                 reg-names = "se";
1393                                 clock-names = "se";
1394                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1395                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1396                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1397                                 dma-names = "tx", "rx";
1398                                 pinctrl-names = "default";
1399                                 pinctrl-0 = <&qup_spi10_default>;
1400                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1401                                 spi-max-frequency = <50000000>;
1402                                 #address-cells = <1>;
1403                                 #size-cells = <0>;
1404                                 status = "disabled";
1405                         };
1406
1407                         i2c11: i2c@a8c000 {
1408                                 compatible = "qcom,geni-i2c";
1409                                 reg = <0 0x00a8c000 0 0x4000>;
1410                                 clock-names = "se";
1411                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1412                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1413                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1414                                 dma-names = "tx", "rx";
1415                                 pinctrl-names = "default";
1416                                 pinctrl-0 = <&qup_i2c11_default>;
1417                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1418                                 #address-cells = <1>;
1419                                 #size-cells = <0>;
1420                                 status = "disabled";
1421                         };
1422
1423                         spi11: spi@a8c000 {
1424                                 compatible = "qcom,geni-spi";
1425                                 reg = <0 0x00a8c000 0 0x4000>;
1426                                 reg-names = "se";
1427                                 clock-names = "se";
1428                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1429                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1430                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1431                                 dma-names = "tx", "rx";
1432                                 pinctrl-names = "default";
1433                                 pinctrl-0 = <&qup_spi11_default>;
1434                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1435                                 spi-max-frequency = <50000000>;
1436                                 #address-cells = <1>;
1437                                 #size-cells = <0>;
1438                                 status = "disabled";
1439                         };
1440
1441                         uart2: serial@a90000 {
1442                                 compatible = "qcom,geni-debug-uart";
1443                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1444                                 clock-names = "se";
1445                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1446                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1447                                 status = "disabled";
1448                         };
1449
1450                         i2c12: i2c@a90000 {
1451                                 compatible = "qcom,geni-i2c";
1452                                 reg = <0 0x00a90000 0 0x4000>;
1453                                 clock-names = "se";
1454                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1455                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1456                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1457                                 dma-names = "tx", "rx";
1458                                 pinctrl-names = "default";
1459                                 pinctrl-0 = <&qup_i2c12_default>;
1460                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1461                                 #address-cells = <1>;
1462                                 #size-cells = <0>;
1463                                 status = "disabled";
1464                         };
1465
1466                         spi12: spi@a90000 {
1467                                 compatible = "qcom,geni-spi";
1468                                 reg = <0 0x00a90000 0 0x4000>;
1469                                 reg-names = "se";
1470                                 clock-names = "se";
1471                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1472                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1473                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1474                                 dma-names = "tx", "rx";
1475                                 pinctrl-names = "default";
1476                                 pinctrl-0 = <&qup_spi12_default>;
1477                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1478                                 spi-max-frequency = <50000000>;
1479                                 #address-cells = <1>;
1480                                 #size-cells = <0>;
1481                                 status = "disabled";
1482                         };
1483
1484                         i2c16: i2c@94000 {
1485                                 compatible = "qcom,geni-i2c";
1486                                 reg = <0 0x00094000 0 0x4000>;
1487                                 clock-names = "se";
1488                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1489                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1490                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1491                                 dma-names = "tx", "rx";
1492                                 pinctrl-names = "default";
1493                                 pinctrl-0 = <&qup_i2c16_default>;
1494                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1495                                 #address-cells = <1>;
1496                                 #size-cells = <0>;
1497                                 status = "disabled";
1498                         };
1499
1500                         spi16: spi@a94000 {
1501                                 compatible = "qcom,geni-spi";
1502                                 reg = <0 0x00a94000 0 0x4000>;
1503                                 reg-names = "se";
1504                                 clock-names = "se";
1505                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1506                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1507                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1508                                 dma-names = "tx", "rx";
1509                                 pinctrl-names = "default";
1510                                 pinctrl-0 = <&qup_spi16_default>;
1511                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1512                                 spi-max-frequency = <50000000>;
1513                                 #address-cells = <1>;
1514                                 #size-cells = <0>;
1515                                 status = "disabled";
1516                         };
1517                 };
1518
1519                 gpi_dma2: dma-controller@c00000 {
1520                         compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1521                         reg = <0 0x00c00000 0 0x60000>;
1522                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1523                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1524                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1525                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1526                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1527                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1528                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1529                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1530                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1531                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1532                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1533                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1534                                      <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1535                         dma-channels = <13>;
1536                         dma-channel-mask = <0xfa>;
1537                         iommus = <&apps_smmu 0x07b6 0x0>;
1538                         #dma-cells = <3>;
1539                         status = "disabled";
1540                 };
1541
1542                 qupv3_id_2: geniqup@cc0000 {
1543                         compatible = "qcom,geni-se-qup";
1544                         reg = <0x0 0x00cc0000 0x0 0x6000>;
1545
1546                         clock-names = "m-ahb", "s-ahb";
1547                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1548                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1549                         iommus = <&apps_smmu 0x7a3 0x0>;
1550                         #address-cells = <2>;
1551                         #size-cells = <2>;
1552                         ranges;
1553                         status = "disabled";
1554
1555                         i2c17: i2c@c80000 {
1556                                 compatible = "qcom,geni-i2c";
1557                                 reg = <0 0x00c80000 0 0x4000>;
1558                                 clock-names = "se";
1559                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1560                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1561                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1562                                 dma-names = "tx", "rx";
1563                                 pinctrl-names = "default";
1564                                 pinctrl-0 = <&qup_i2c17_default>;
1565                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1566                                 #address-cells = <1>;
1567                                 #size-cells = <0>;
1568                                 status = "disabled";
1569                         };
1570
1571                         spi17: spi@c80000 {
1572                                 compatible = "qcom,geni-spi";
1573                                 reg = <0 0x00c80000 0 0x4000>;
1574                                 reg-names = "se";
1575                                 clock-names = "se";
1576                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1577                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1578                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1579                                 dma-names = "tx", "rx";
1580                                 pinctrl-names = "default";
1581                                 pinctrl-0 = <&qup_spi17_default>;
1582                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1583                                 spi-max-frequency = <50000000>;
1584                                 #address-cells = <1>;
1585                                 #size-cells = <0>;
1586                                 status = "disabled";
1587                         };
1588
1589                         i2c18: i2c@c84000 {
1590                                 compatible = "qcom,geni-i2c";
1591                                 reg = <0 0x00c84000 0 0x4000>;
1592                                 clock-names = "se";
1593                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1594                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1595                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1596                                 dma-names = "tx", "rx";
1597                                 pinctrl-names = "default";
1598                                 pinctrl-0 = <&qup_i2c18_default>;
1599                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1600                                 #address-cells = <1>;
1601                                 #size-cells = <0>;
1602                                 status = "disabled";
1603                         };
1604
1605                         spi18: spi@c84000 {
1606                                 compatible = "qcom,geni-spi";
1607                                 reg = <0 0x00c84000 0 0x4000>;
1608                                 reg-names = "se";
1609                                 clock-names = "se";
1610                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1611                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1612                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1613                                 dma-names = "tx", "rx";
1614                                 pinctrl-names = "default";
1615                                 pinctrl-0 = <&qup_spi18_default>;
1616                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1617                                 spi-max-frequency = <50000000>;
1618                                 #address-cells = <1>;
1619                                 #size-cells = <0>;
1620                                 status = "disabled";
1621                         };
1622
1623                         i2c19: i2c@c88000 {
1624                                 compatible = "qcom,geni-i2c";
1625                                 reg = <0 0x00c88000 0 0x4000>;
1626                                 clock-names = "se";
1627                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1628                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1629                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1630                                 dma-names = "tx", "rx";
1631                                 pinctrl-names = "default";
1632                                 pinctrl-0 = <&qup_i2c19_default>;
1633                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1634                                 #address-cells = <1>;
1635                                 #size-cells = <0>;
1636                                 status = "disabled";
1637                         };
1638
1639                         spi19: spi@c88000 {
1640                                 compatible = "qcom,geni-spi";
1641                                 reg = <0 0x00c88000 0 0x4000>;
1642                                 reg-names = "se";
1643                                 clock-names = "se";
1644                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1645                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1646                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1647                                 dma-names = "tx", "rx";
1648                                 pinctrl-names = "default";
1649                                 pinctrl-0 = <&qup_spi19_default>;
1650                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1651                                 spi-max-frequency = <50000000>;
1652                                 #address-cells = <1>;
1653                                 #size-cells = <0>;
1654                                 status = "disabled";
1655                         };
1656
1657                         i2c13: i2c@c8c000 {
1658                                 compatible = "qcom,geni-i2c";
1659                                 reg = <0 0x00c8c000 0 0x4000>;
1660                                 clock-names = "se";
1661                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1662                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1663                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1664                                 dma-names = "tx", "rx";
1665                                 pinctrl-names = "default";
1666                                 pinctrl-0 = <&qup_i2c13_default>;
1667                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1668                                 #address-cells = <1>;
1669                                 #size-cells = <0>;
1670                                 status = "disabled";
1671                         };
1672
1673                         spi13: spi@c8c000 {
1674                                 compatible = "qcom,geni-spi";
1675                                 reg = <0 0x00c8c000 0 0x4000>;
1676                                 reg-names = "se";
1677                                 clock-names = "se";
1678                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1679                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1680                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1681                                 dma-names = "tx", "rx";
1682                                 pinctrl-names = "default";
1683                                 pinctrl-0 = <&qup_spi13_default>;
1684                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1685                                 spi-max-frequency = <50000000>;
1686                                 #address-cells = <1>;
1687                                 #size-cells = <0>;
1688                                 status = "disabled";
1689                         };
1690
1691                         i2c14: i2c@c90000 {
1692                                 compatible = "qcom,geni-i2c";
1693                                 reg = <0 0x00c90000 0 0x4000>;
1694                                 clock-names = "se";
1695                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1696                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1697                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1698                                 dma-names = "tx", "rx";
1699                                 pinctrl-names = "default";
1700                                 pinctrl-0 = <&qup_i2c14_default>;
1701                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1702                                 #address-cells = <1>;
1703                                 #size-cells = <0>;
1704                                 status = "disabled";
1705                         };
1706
1707                         spi14: spi@c90000 {
1708                                 compatible = "qcom,geni-spi";
1709                                 reg = <0 0x00c90000 0 0x4000>;
1710                                 reg-names = "se";
1711                                 clock-names = "se";
1712                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1713                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1714                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1715                                 dma-names = "tx", "rx";
1716                                 pinctrl-names = "default";
1717                                 pinctrl-0 = <&qup_spi14_default>;
1718                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1719                                 spi-max-frequency = <50000000>;
1720                                 #address-cells = <1>;
1721                                 #size-cells = <0>;
1722                                 status = "disabled";
1723                         };
1724
1725                         i2c15: i2c@c94000 {
1726                                 compatible = "qcom,geni-i2c";
1727                                 reg = <0 0x00c94000 0 0x4000>;
1728                                 clock-names = "se";
1729                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1730                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1731                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1732                                 dma-names = "tx", "rx";
1733                                 pinctrl-names = "default";
1734                                 pinctrl-0 = <&qup_i2c15_default>;
1735                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1736                                 #address-cells = <1>;
1737                                 #size-cells = <0>;
1738                                 status = "disabled";
1739                         };
1740
1741                         spi15: spi@c94000 {
1742                                 compatible = "qcom,geni-spi";
1743                                 reg = <0 0x00c94000 0 0x4000>;
1744                                 reg-names = "se";
1745                                 clock-names = "se";
1746                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1747                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1748                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1749                                 dma-names = "tx", "rx";
1750                                 pinctrl-names = "default";
1751                                 pinctrl-0 = <&qup_spi15_default>;
1752                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1753                                 spi-max-frequency = <50000000>;
1754                                 #address-cells = <1>;
1755                                 #size-cells = <0>;
1756                                 status = "disabled";
1757                         };
1758                 };
1759
1760                 config_noc: interconnect@1500000 {
1761                         compatible = "qcom,sm8150-config-noc";
1762                         reg = <0 0x01500000 0 0x7400>;
1763                         #interconnect-cells = <2>;
1764                         qcom,bcm-voters = <&apps_bcm_voter>;
1765                 };
1766
1767                 system_noc: interconnect@1620000 {
1768                         compatible = "qcom,sm8150-system-noc";
1769                         reg = <0 0x01620000 0 0x19400>;
1770                         #interconnect-cells = <2>;
1771                         qcom,bcm-voters = <&apps_bcm_voter>;
1772                 };
1773
1774                 mc_virt: interconnect@163a000 {
1775                         compatible = "qcom,sm8150-mc-virt";
1776                         reg = <0 0x0163a000 0 0x1000>;
1777                         #interconnect-cells = <2>;
1778                         qcom,bcm-voters = <&apps_bcm_voter>;
1779                 };
1780
1781                 aggre1_noc: interconnect@16e0000 {
1782                         compatible = "qcom,sm8150-aggre1-noc";
1783                         reg = <0 0x016e0000 0 0xd080>;
1784                         #interconnect-cells = <2>;
1785                         qcom,bcm-voters = <&apps_bcm_voter>;
1786                 };
1787
1788                 aggre2_noc: interconnect@1700000 {
1789                         compatible = "qcom,sm8150-aggre2-noc";
1790                         reg = <0 0x01700000 0 0x20000>;
1791                         #interconnect-cells = <2>;
1792                         qcom,bcm-voters = <&apps_bcm_voter>;
1793                 };
1794
1795                 compute_noc: interconnect@1720000 {
1796                         compatible = "qcom,sm8150-compute-noc";
1797                         reg = <0 0x01720000 0 0x7000>;
1798                         #interconnect-cells = <2>;
1799                         qcom,bcm-voters = <&apps_bcm_voter>;
1800                 };
1801
1802                 mmss_noc: interconnect@1740000 {
1803                         compatible = "qcom,sm8150-mmss-noc";
1804                         reg = <0 0x01740000 0 0x1c100>;
1805                         #interconnect-cells = <2>;
1806                         qcom,bcm-voters = <&apps_bcm_voter>;
1807                 };
1808
1809                 system-cache-controller@9200000 {
1810                         compatible = "qcom,sm8150-llcc";
1811                         reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1812                               <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1813                               <0 0x09600000 0 0x50000>;
1814                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1815                                     "llcc3_base", "llcc_broadcast_base";
1816                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1817                 };
1818
1819                 dma@10a2000 {
1820                         compatible = "qcom,sm8150-dcc", "qcom,dcc";
1821                         reg = <0x0 0x010a2000 0x0 0x1000>,
1822                               <0x0 0x010ad000 0x0 0x3000>;
1823                 };
1824
1825                 pcie0: pci@1c00000 {
1826                         compatible = "qcom,pcie-sm8150";
1827                         reg = <0 0x01c00000 0 0x3000>,
1828                               <0 0x60000000 0 0xf1d>,
1829                               <0 0x60000f20 0 0xa8>,
1830                               <0 0x60001000 0 0x1000>,
1831                               <0 0x60100000 0 0x100000>;
1832                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1833                         device_type = "pci";
1834                         linux,pci-domain = <0>;
1835                         bus-range = <0x00 0xff>;
1836                         num-lanes = <1>;
1837
1838                         #address-cells = <3>;
1839                         #size-cells = <2>;
1840
1841                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1842                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1843
1844                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1845                         interrupt-names = "msi";
1846                         #interrupt-cells = <1>;
1847                         interrupt-map-mask = <0 0 0 0x7>;
1848                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1849                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1850                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1851                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1852
1853                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1854                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1855                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1856                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1857                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1858                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1859                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1860                         clock-names = "pipe",
1861                                       "aux",
1862                                       "cfg",
1863                                       "bus_master",
1864                                       "bus_slave",
1865                                       "slave_q2a",
1866                                       "tbu";
1867
1868                         iommu-map = <0x0   &apps_smmu 0x1d80 0x1>,
1869                                     <0x100 &apps_smmu 0x1d81 0x1>;
1870
1871                         resets = <&gcc GCC_PCIE_0_BCR>;
1872                         reset-names = "pci";
1873
1874                         power-domains = <&gcc PCIE_0_GDSC>;
1875
1876                         phys = <&pcie0_lane>;
1877                         phy-names = "pciephy";
1878
1879                         perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1880                         enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1881
1882                         pinctrl-names = "default";
1883                         pinctrl-0 = <&pcie0_default_state>;
1884
1885                         status = "disabled";
1886                 };
1887
1888                 pcie0_phy: phy@1c06000 {
1889                         compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1890                         reg = <0 0x01c06000 0 0x1c0>;
1891                         #address-cells = <2>;
1892                         #size-cells = <2>;
1893                         ranges;
1894                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1895                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1896                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
1897                                  <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1898                         clock-names = "aux",
1899                                       "cfg_ahb",
1900                                       "ref",
1901                                       "refgen";
1902
1903                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1904                         reset-names = "phy";
1905
1906                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1907                         assigned-clock-rates = <100000000>;
1908
1909                         status = "disabled";
1910
1911                         pcie0_lane: phy@1c06200 {
1912                                 reg = <0 0x01c06200 0 0x170>, /* tx */
1913                                       <0 0x01c06400 0 0x200>, /* rx */
1914                                       <0 0x01c06800 0 0x1f0>, /* pcs */
1915                                       <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1916                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1917                                 clock-names = "pipe0";
1918
1919                                 #phy-cells = <0>;
1920                                 clock-output-names = "pcie_0_pipe_clk";
1921                         };
1922                 };
1923
1924                 pcie1: pci@1c08000 {
1925                         compatible = "qcom,pcie-sm8150";
1926                         reg = <0 0x01c08000 0 0x3000>,
1927                               <0 0x40000000 0 0xf1d>,
1928                               <0 0x40000f20 0 0xa8>,
1929                               <0 0x40001000 0 0x1000>,
1930                               <0 0x40100000 0 0x100000>;
1931                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1932                         device_type = "pci";
1933                         linux,pci-domain = <1>;
1934                         bus-range = <0x00 0xff>;
1935                         num-lanes = <2>;
1936
1937                         #address-cells = <3>;
1938                         #size-cells = <2>;
1939
1940                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1941                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1942
1943                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1944                         interrupt-names = "msi";
1945                         #interrupt-cells = <1>;
1946                         interrupt-map-mask = <0 0 0 0x7>;
1947                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1948                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1949                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1950                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1951
1952                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1953                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1954                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1955                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1956                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1957                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1958                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1959                         clock-names = "pipe",
1960                                       "aux",
1961                                       "cfg",
1962                                       "bus_master",
1963                                       "bus_slave",
1964                                       "slave_q2a",
1965                                       "tbu";
1966
1967                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1968                         assigned-clock-rates = <19200000>;
1969
1970                         iommu-map = <0x0   &apps_smmu 0x1e00 0x1>,
1971                                     <0x100 &apps_smmu 0x1e01 0x1>;
1972
1973                         resets = <&gcc GCC_PCIE_1_BCR>;
1974                         reset-names = "pci";
1975
1976                         power-domains = <&gcc PCIE_1_GDSC>;
1977
1978                         phys = <&pcie1_lane>;
1979                         phy-names = "pciephy";
1980
1981                         perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
1982                         enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
1983
1984                         pinctrl-names = "default";
1985                         pinctrl-0 = <&pcie1_default_state>;
1986
1987                         status = "disabled";
1988                 };
1989
1990                 pcie1_phy: phy@1c0e000 {
1991                         compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
1992                         reg = <0 0x01c0e000 0 0x1c0>;
1993                         #address-cells = <2>;
1994                         #size-cells = <2>;
1995                         ranges;
1996                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1997                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1998                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
1999                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2000                         clock-names = "aux",
2001                                       "cfg_ahb",
2002                                       "ref",
2003                                       "refgen";
2004
2005                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2006                         reset-names = "phy";
2007
2008                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2009                         assigned-clock-rates = <100000000>;
2010
2011                         status = "disabled";
2012
2013                         pcie1_lane: phy@1c0e200 {
2014                                 reg = <0 0x01c0e200 0 0x170>, /* tx0 */
2015                                       <0 0x01c0e400 0 0x200>, /* rx0 */
2016                                       <0 0x01c0ea00 0 0x1f0>, /* pcs */
2017                                       <0 0x01c0e600 0 0x170>, /* tx1 */
2018                                       <0 0x01c0e800 0 0x200>, /* rx1 */
2019                                       <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2020                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2021                                 clock-names = "pipe0";
2022
2023                                 #phy-cells = <0>;
2024                                 clock-output-names = "pcie_1_pipe_clk";
2025                         };
2026                 };
2027
2028                 ufs_mem_hc: ufshc@1d84000 {
2029                         compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2030                                      "jedec,ufs-2.0";
2031                         reg = <0 0x01d84000 0 0x2500>,
2032                               <0 0x01d90000 0 0x8000>;
2033                         reg-names = "std", "ice";
2034                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2035                         phys = <&ufs_mem_phy_lanes>;
2036                         phy-names = "ufsphy";
2037                         lanes-per-direction = <2>;
2038                         #reset-cells = <1>;
2039                         resets = <&gcc GCC_UFS_PHY_BCR>;
2040                         reset-names = "rst";
2041
2042                         iommus = <&apps_smmu 0x300 0>;
2043
2044                         clock-names =
2045                                 "core_clk",
2046                                 "bus_aggr_clk",
2047                                 "iface_clk",
2048                                 "core_clk_unipro",
2049                                 "ref_clk",
2050                                 "tx_lane0_sync_clk",
2051                                 "rx_lane0_sync_clk",
2052                                 "rx_lane1_sync_clk",
2053                                 "ice_core_clk";
2054                         clocks =
2055                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2056                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2057                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2058                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2059                                 <&rpmhcc RPMH_CXO_CLK>,
2060                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2061                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2062                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2063                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2064                         freq-table-hz =
2065                                 <37500000 300000000>,
2066                                 <0 0>,
2067                                 <0 0>,
2068                                 <37500000 300000000>,
2069                                 <0 0>,
2070                                 <0 0>,
2071                                 <0 0>,
2072                                 <0 0>,
2073                                 <0 300000000>;
2074
2075                         status = "disabled";
2076                 };
2077
2078                 ufs_mem_phy: phy@1d87000 {
2079                         compatible = "qcom,sm8150-qmp-ufs-phy";
2080                         reg = <0 0x01d87000 0 0x1c0>;
2081                         #address-cells = <2>;
2082                         #size-cells = <2>;
2083                         ranges;
2084                         clock-names = "ref",
2085                                       "ref_aux";
2086                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2087                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2088
2089                         power-domains = <&gcc UFS_PHY_GDSC>;
2090
2091                         resets = <&ufs_mem_hc 0>;
2092                         reset-names = "ufsphy";
2093                         status = "disabled";
2094
2095                         ufs_mem_phy_lanes: phy@1d87400 {
2096                                 reg = <0 0x01d87400 0 0x16c>,
2097                                       <0 0x01d87600 0 0x200>,
2098                                       <0 0x01d87c00 0 0x200>,
2099                                       <0 0x01d87800 0 0x16c>,
2100                                       <0 0x01d87a00 0 0x200>;
2101                                 #phy-cells = <0>;
2102                         };
2103                 };
2104
2105                 cryptobam: dma-controller@1dc4000 {
2106                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2107                         reg = <0 0x01dc4000 0 0x24000>;
2108                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2109                         #dma-cells = <1>;
2110                         qcom,ee = <0>;
2111                         qcom,controlled-remotely;
2112                         num-channels = <8>;
2113                         qcom,num-ees = <2>;
2114                         iommus = <&apps_smmu 0x502 0x0641>,
2115                                  <&apps_smmu 0x504 0x0011>,
2116                                  <&apps_smmu 0x506 0x0011>,
2117                                  <&apps_smmu 0x508 0x0011>,
2118                                  <&apps_smmu 0x512 0x0000>;
2119                 };
2120
2121                 crypto: crypto@1dfa000 {
2122                         compatible = "qcom,sm8150-qce", "qcom,qce";
2123                         reg = <0 0x01dfa000 0 0x6000>;
2124                         dmas = <&cryptobam 4>, <&cryptobam 5>;
2125                         dma-names = "rx", "tx";
2126                         iommus = <&apps_smmu 0x502 0x0641>,
2127                                  <&apps_smmu 0x504 0x0011>,
2128                                  <&apps_smmu 0x506 0x0011>,
2129                                  <&apps_smmu 0x508 0x0011>,
2130                                  <&apps_smmu 0x512 0x0000>;
2131                         interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2132                         interconnect-names = "memory";
2133                 };
2134
2135                 tcsr_mutex: hwlock@1f40000 {
2136                         compatible = "qcom,tcsr-mutex";
2137                         reg = <0x0 0x01f40000 0x0 0x20000>;
2138                         #hwlock-cells = <1>;
2139                 };
2140
2141                 tcsr_regs_1: syscon@1f60000 {
2142                         compatible = "qcom,sm8150-tcsr", "syscon";
2143                         reg = <0x0 0x01f60000 0x0 0x20000>;
2144                 };
2145
2146                 remoteproc_slpi: remoteproc@2400000 {
2147                         compatible = "qcom,sm8150-slpi-pas";
2148                         reg = <0x0 0x02400000 0x0 0x4040>;
2149
2150                         interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2151                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2152                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2153                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2154                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2155                         interrupt-names = "wdog", "fatal", "ready",
2156                                           "handover", "stop-ack";
2157
2158                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2159                         clock-names = "xo";
2160
2161                         power-domains = <&rpmhpd SM8150_LCX>,
2162                                         <&rpmhpd SM8150_LMX>;
2163                         power-domain-names = "lcx", "lmx";
2164
2165                         memory-region = <&slpi_mem>;
2166
2167                         qcom,qmp = <&aoss_qmp>;
2168
2169                         qcom,smem-states = <&slpi_smp2p_out 0>;
2170                         qcom,smem-state-names = "stop";
2171
2172                         status = "disabled";
2173
2174                         glink-edge {
2175                                 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2176                                 label = "dsps";
2177                                 qcom,remote-pid = <3>;
2178                                 mboxes = <&apss_shared 24>;
2179
2180                                 fastrpc {
2181                                         compatible = "qcom,fastrpc";
2182                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2183                                         label = "sdsp";
2184                                         qcom,non-secure-domain;
2185                                         #address-cells = <1>;
2186                                         #size-cells = <0>;
2187
2188                                         compute-cb@1 {
2189                                                 compatible = "qcom,fastrpc-compute-cb";
2190                                                 reg = <1>;
2191                                                 iommus = <&apps_smmu 0x05a1 0x0>;
2192                                         };
2193
2194                                         compute-cb@2 {
2195                                                 compatible = "qcom,fastrpc-compute-cb";
2196                                                 reg = <2>;
2197                                                 iommus = <&apps_smmu 0x05a2 0x0>;
2198                                         };
2199
2200                                         compute-cb@3 {
2201                                                 compatible = "qcom,fastrpc-compute-cb";
2202                                                 reg = <3>;
2203                                                 iommus = <&apps_smmu 0x05a3 0x0>;
2204                                                 /* note: shared-cb = <4> in downstream */
2205                                         };
2206                                 };
2207                         };
2208                 };
2209
2210                 gpu: gpu@2c00000 {
2211                         compatible = "qcom,adreno-640.1", "qcom,adreno";
2212                         reg = <0 0x02c00000 0 0x40000>;
2213                         reg-names = "kgsl_3d0_reg_memory";
2214
2215                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2216
2217                         iommus = <&adreno_smmu 0 0x401>;
2218
2219                         operating-points-v2 = <&gpu_opp_table>;
2220
2221                         qcom,gmu = <&gmu>;
2222
2223                         nvmem-cells = <&gpu_speed_bin>;
2224                         nvmem-cell-names = "speed_bin";
2225
2226                         status = "disabled";
2227
2228                         zap-shader {
2229                                 memory-region = <&gpu_mem>;
2230                         };
2231
2232                         gpu_opp_table: opp-table {
2233                                 compatible = "operating-points-v2";
2234
2235                                 opp-675000000 {
2236                                         opp-hz = /bits/ 64 <675000000>;
2237                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2238                                         opp-supported-hw = <0x2>;
2239                                 };
2240
2241                                 opp-585000000 {
2242                                         opp-hz = /bits/ 64 <585000000>;
2243                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2244                                         opp-supported-hw = <0x3>;
2245                                 };
2246
2247                                 opp-499200000 {
2248                                         opp-hz = /bits/ 64 <499200000>;
2249                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2250                                         opp-supported-hw = <0x3>;
2251                                 };
2252
2253                                 opp-427000000 {
2254                                         opp-hz = /bits/ 64 <427000000>;
2255                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2256                                         opp-supported-hw = <0x3>;
2257                                 };
2258
2259                                 opp-345000000 {
2260                                         opp-hz = /bits/ 64 <345000000>;
2261                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2262                                         opp-supported-hw = <0x3>;
2263                                 };
2264
2265                                 opp-257000000 {
2266                                         opp-hz = /bits/ 64 <257000000>;
2267                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2268                                         opp-supported-hw = <0x3>;
2269                                 };
2270                         };
2271                 };
2272
2273                 gmu: gmu@2c6a000 {
2274                         compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2275
2276                         reg = <0 0x02c6a000 0 0x30000>,
2277                               <0 0x0b290000 0 0x10000>,
2278                               <0 0x0b490000 0 0x10000>;
2279                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2280
2281                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2282                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2283                         interrupt-names = "hfi", "gmu";
2284
2285                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2286                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2287                                  <&gpucc GPU_CC_CXO_CLK>,
2288                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2289                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2290                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2291
2292                         power-domains = <&gpucc GPU_CX_GDSC>,
2293                                         <&gpucc GPU_GX_GDSC>;
2294                         power-domain-names = "cx", "gx";
2295
2296                         iommus = <&adreno_smmu 5 0x400>;
2297
2298                         operating-points-v2 = <&gmu_opp_table>;
2299
2300                         status = "disabled";
2301
2302                         gmu_opp_table: opp-table {
2303                                 compatible = "operating-points-v2";
2304
2305                                 opp-200000000 {
2306                                         opp-hz = /bits/ 64 <200000000>;
2307                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2308                                 };
2309                         };
2310                 };
2311
2312                 gpucc: clock-controller@2c90000 {
2313                         compatible = "qcom,sm8150-gpucc";
2314                         reg = <0 0x02c90000 0 0x9000>;
2315                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2316                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2317                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2318                         clock-names = "bi_tcxo",
2319                                       "gcc_gpu_gpll0_clk_src",
2320                                       "gcc_gpu_gpll0_div_clk_src";
2321                         #clock-cells = <1>;
2322                         #reset-cells = <1>;
2323                         #power-domain-cells = <1>;
2324                 };
2325
2326                 adreno_smmu: iommu@2ca0000 {
2327                         compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2328                                      "qcom,smmu-500", "arm,mmu-500";
2329                         reg = <0 0x02ca0000 0 0x10000>;
2330                         #iommu-cells = <2>;
2331                         #global-interrupts = <1>;
2332                         interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2333                                 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2334                                 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2335                                 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2336                                 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2337                                 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2338                                 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2339                                 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2340                                 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2341                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2342                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2343                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2344                         clock-names = "ahb", "bus", "iface";
2345
2346                         power-domains = <&gpucc GPU_CX_GDSC>;
2347                 };
2348
2349                 tlmm: pinctrl@3100000 {
2350                         compatible = "qcom,sm8150-pinctrl";
2351                         reg = <0x0 0x03100000 0x0 0x300000>,
2352                               <0x0 0x03500000 0x0 0x300000>,
2353                               <0x0 0x03900000 0x0 0x300000>,
2354                               <0x0 0x03D00000 0x0 0x300000>;
2355                         reg-names = "west", "east", "north", "south";
2356                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2357                         gpio-ranges = <&tlmm 0 0 176>;
2358                         gpio-controller;
2359                         #gpio-cells = <2>;
2360                         interrupt-controller;
2361                         #interrupt-cells = <2>;
2362                         wakeup-parent = <&pdc>;
2363
2364                         qup_i2c0_default: qup-i2c0-default-state {
2365                                 pins = "gpio0", "gpio1";
2366                                 function = "qup0";
2367                                 drive-strength = <0x02>;
2368                                 bias-disable;
2369                         };
2370
2371                         qup_spi0_default: qup-spi0-default-state {
2372                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2373                                 function = "qup0";
2374                                 drive-strength = <6>;
2375                                 bias-disable;
2376                         };
2377
2378                         qup_i2c1_default: qup-i2c1-default-state {
2379                                 pins = "gpio114", "gpio115";
2380                                 function = "qup1";
2381                                 drive-strength = <2>;
2382                                 bias-disable;
2383                         };
2384
2385                         qup_spi1_default: qup-spi1-default-state {
2386                                 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2387                                 function = "qup1";
2388                                 drive-strength = <6>;
2389                                 bias-disable;
2390                         };
2391
2392                         qup_i2c2_default: qup-i2c2-default-state {
2393                                 pins = "gpio126", "gpio127";
2394                                 function = "qup2";
2395                                 drive-strength = <2>;
2396                                 bias-disable;
2397                         };
2398
2399                         qup_spi2_default: qup-spi2-default-state {
2400                                 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2401                                 function = "qup2";
2402                                 drive-strength = <6>;
2403                                 bias-disable;
2404                         };
2405
2406                         qup_i2c3_default: qup-i2c3-default-state {
2407                                 pins = "gpio144", "gpio145";
2408                                 function = "qup3";
2409                                 drive-strength = <2>;
2410                                 bias-disable;
2411                         };
2412
2413                         qup_spi3_default: qup-spi3-default-state {
2414                                 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2415                                 function = "qup3";
2416                                 drive-strength = <6>;
2417                                 bias-disable;
2418                         };
2419
2420                         qup_i2c4_default: qup-i2c4-default-state {
2421                                 pins = "gpio51", "gpio52";
2422                                 function = "qup4";
2423                                 drive-strength = <2>;
2424                                 bias-disable;
2425                         };
2426
2427                         qup_spi4_default: qup-spi4-default-state {
2428                                 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2429                                 function = "qup4";
2430                                 drive-strength = <6>;
2431                                 bias-disable;
2432                         };
2433
2434                         qup_i2c5_default: qup-i2c5-default-state {
2435                                 pins = "gpio121", "gpio122";
2436                                 function = "qup5";
2437                                 drive-strength = <2>;
2438                                 bias-disable;
2439                         };
2440
2441                         qup_spi5_default: qup-spi5-default-state {
2442                                 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2443                                 function = "qup5";
2444                                 drive-strength = <6>;
2445                                 bias-disable;
2446                         };
2447
2448                         qup_i2c6_default: qup-i2c6-default-state {
2449                                 pins = "gpio6", "gpio7";
2450                                 function = "qup6";
2451                                 drive-strength = <2>;
2452                                 bias-disable;
2453                         };
2454
2455                         qup_spi6_default: qup-spi6_default-state {
2456                                 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2457                                 function = "qup6";
2458                                 drive-strength = <6>;
2459                                 bias-disable;
2460                         };
2461
2462                         qup_i2c7_default: qup-i2c7-default-state {
2463                                 pins = "gpio98", "gpio99";
2464                                 function = "qup7";
2465                                 drive-strength = <2>;
2466                                 bias-disable;
2467                         };
2468
2469                         qup_spi7_default: qup-spi7_default-state {
2470                                 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2471                                 function = "qup7";
2472                                 drive-strength = <6>;
2473                                 bias-disable;
2474                         };
2475
2476                         qup_i2c8_default: qup-i2c8-default-state {
2477                                 pins = "gpio88", "gpio89";
2478                                 function = "qup8";
2479                                 drive-strength = <2>;
2480                                 bias-disable;
2481                         };
2482
2483                         qup_spi8_default: qup-spi8-default-state {
2484                                 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2485                                 function = "qup8";
2486                                 drive-strength = <6>;
2487                                 bias-disable;
2488                         };
2489
2490                         qup_i2c9_default: qup-i2c9-default-state {
2491                                 pins = "gpio39", "gpio40";
2492                                 function = "qup9";
2493                                 drive-strength = <2>;
2494                                 bias-disable;
2495                         };
2496
2497                         qup_spi9_default: qup-spi9-default-state {
2498                                 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2499                                 function = "qup9";
2500                                 drive-strength = <6>;
2501                                 bias-disable;
2502                         };
2503
2504                         qup_uart9_default: qup-uart9-default-state {
2505                                 pins = "gpio41", "gpio42";
2506                                 function = "qup9";
2507                                 drive-strength = <2>;
2508                                 bias-disable;
2509                         };
2510
2511                         qup_i2c10_default: qup-i2c10-default-state {
2512                                 pins = "gpio9", "gpio10";
2513                                 function = "qup10";
2514                                 drive-strength = <2>;
2515                                 bias-disable;
2516                         };
2517
2518                         qup_spi10_default: qup-spi10-default-state {
2519                                 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2520                                 function = "qup10";
2521                                 drive-strength = <6>;
2522                                 bias-disable;
2523                         };
2524
2525                         qup_i2c11_default: qup-i2c11-default-state {
2526                                 pins = "gpio94", "gpio95";
2527                                 function = "qup11";
2528                                 drive-strength = <2>;
2529                                 bias-disable;
2530                         };
2531
2532                         qup_spi11_default: qup-spi11-default-state {
2533                                 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2534                                 function = "qup11";
2535                                 drive-strength = <6>;
2536                                 bias-disable;
2537                         };
2538
2539                         qup_i2c12_default: qup-i2c12-default-state {
2540                                 pins = "gpio83", "gpio84";
2541                                 function = "qup12";
2542                                 drive-strength = <2>;
2543                                 bias-disable;
2544                         };
2545
2546                         qup_spi12_default: qup-spi12-default-state {
2547                                 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2548                                 function = "qup12";
2549                                 drive-strength = <6>;
2550                                 bias-disable;
2551                         };
2552
2553                         qup_i2c13_default: qup-i2c13-default-state {
2554                                 pins = "gpio43", "gpio44";
2555                                 function = "qup13";
2556                                 drive-strength = <2>;
2557                                 bias-disable;
2558                         };
2559
2560                         qup_spi13_default: qup-spi13-default-state {
2561                                 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2562                                 function = "qup13";
2563                                 drive-strength = <6>;
2564                                 bias-disable;
2565                         };
2566
2567                         qup_i2c14_default: qup-i2c14-default-state {
2568                                 pins = "gpio47", "gpio48";
2569                                 function = "qup14";
2570                                 drive-strength = <2>;
2571                                 bias-disable;
2572                         };
2573
2574                         qup_spi14_default: qup-spi14-default-state {
2575                                 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2576                                 function = "qup14";
2577                                 drive-strength = <6>;
2578                                 bias-disable;
2579                         };
2580
2581                         qup_i2c15_default: qup-i2c15-default-state {
2582                                 pins = "gpio27", "gpio28";
2583                                 function = "qup15";
2584                                 drive-strength = <2>;
2585                                 bias-disable;
2586                         };
2587
2588                         qup_spi15_default: qup-spi15-default-state {
2589                                 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2590                                 function = "qup15";
2591                                 drive-strength = <6>;
2592                                 bias-disable;
2593                         };
2594
2595                         qup_i2c16_default: qup-i2c16-default-state {
2596                                 pins = "gpio86", "gpio85";
2597                                 function = "qup16";
2598                                 drive-strength = <2>;
2599                                 bias-disable;
2600                         };
2601
2602                         qup_spi16_default: qup-spi16-default-state {
2603                                 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2604                                 function = "qup16";
2605                                 drive-strength = <6>;
2606                                 bias-disable;
2607                         };
2608
2609                         qup_i2c17_default: qup-i2c17-default-state {
2610                                 pins = "gpio55", "gpio56";
2611                                 function = "qup17";
2612                                 drive-strength = <2>;
2613                                 bias-disable;
2614                         };
2615
2616                         qup_spi17_default: qup-spi17-default-state {
2617                                 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2618                                 function = "qup17";
2619                                 drive-strength = <6>;
2620                                 bias-disable;
2621                         };
2622
2623                         qup_i2c18_default: qup-i2c18-default-state {
2624                                 pins = "gpio23", "gpio24";
2625                                 function = "qup18";
2626                                 drive-strength = <2>;
2627                                 bias-disable;
2628                         };
2629
2630                         qup_spi18_default: qup-spi18-default-state {
2631                                 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2632                                 function = "qup18";
2633                                 drive-strength = <6>;
2634                                 bias-disable;
2635                         };
2636
2637                         qup_i2c19_default: qup-i2c19-default-state {
2638                                 pins = "gpio57", "gpio58";
2639                                 function = "qup19";
2640                                 drive-strength = <2>;
2641                                 bias-disable;
2642                         };
2643
2644                         qup_spi19_default: qup-spi19-default-state {
2645                                 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2646                                 function = "qup19";
2647                                 drive-strength = <6>;
2648                                 bias-disable;
2649                         };
2650
2651                         pcie0_default_state: pcie0-default-state {
2652                                 perst-pins {
2653                                         pins = "gpio35";
2654                                         function = "gpio";
2655                                         drive-strength = <2>;
2656                                         bias-pull-down;
2657                                 };
2658
2659                                 clkreq-pins {
2660                                         pins = "gpio36";
2661                                         function = "pci_e0";
2662                                         drive-strength = <2>;
2663                                         bias-pull-up;
2664                                 };
2665
2666                                 wake-pins {
2667                                         pins = "gpio37";
2668                                         function = "gpio";
2669                                         drive-strength = <2>;
2670                                         bias-pull-up;
2671                                 };
2672                         };
2673
2674                         pcie1_default_state: pcie1-default-state {
2675                                 perst-pins {
2676                                         pins = "gpio102";
2677                                         function = "gpio";
2678                                         drive-strength = <2>;
2679                                         bias-pull-down;
2680                                 };
2681
2682                                 clkreq-pins {
2683                                         pins = "gpio103";
2684                                         function = "pci_e1";
2685                                         drive-strength = <2>;
2686                                         bias-pull-up;
2687                                 };
2688
2689                                 wake-pins {
2690                                         pins = "gpio104";
2691                                         function = "gpio";
2692                                         drive-strength = <2>;
2693                                         bias-pull-up;
2694                                 };
2695                         };
2696                 };
2697
2698                 remoteproc_mpss: remoteproc@4080000 {
2699                         compatible = "qcom,sm8150-mpss-pas";
2700                         reg = <0x0 0x04080000 0x0 0x4040>;
2701
2702                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2703                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2704                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2705                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2706                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2707                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2708                         interrupt-names = "wdog", "fatal", "ready", "handover",
2709                                           "stop-ack", "shutdown-ack";
2710
2711                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2712                         clock-names = "xo";
2713
2714                         power-domains = <&rpmhpd SM8150_CX>,
2715                                         <&rpmhpd SM8150_MSS>;
2716                         power-domain-names = "cx", "mss";
2717
2718                         memory-region = <&mpss_mem>;
2719
2720                         qcom,qmp = <&aoss_qmp>;
2721
2722                         qcom,smem-states = <&modem_smp2p_out 0>;
2723                         qcom,smem-state-names = "stop";
2724
2725                         status = "disabled";
2726
2727                         glink-edge {
2728                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2729                                 label = "modem";
2730                                 qcom,remote-pid = <1>;
2731                                 mboxes = <&apss_shared 12>;
2732                         };
2733                 };
2734
2735                 stm@6002000 {
2736                         compatible = "arm,coresight-stm", "arm,primecell";
2737                         reg = <0 0x06002000 0 0x1000>,
2738                               <0 0x16280000 0 0x180000>;
2739                         reg-names = "stm-base", "stm-stimulus-base";
2740
2741                         clocks = <&aoss_qmp>;
2742                         clock-names = "apb_pclk";
2743
2744                         out-ports {
2745                                 port {
2746                                         stm_out: endpoint {
2747                                                 remote-endpoint = <&funnel0_in7>;
2748                                         };
2749                                 };
2750                         };
2751                 };
2752
2753                 funnel@6041000 {
2754                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2755                         reg = <0 0x06041000 0 0x1000>;
2756
2757                         clocks = <&aoss_qmp>;
2758                         clock-names = "apb_pclk";
2759
2760                         out-ports {
2761                                 port {
2762                                         funnel0_out: endpoint {
2763                                                 remote-endpoint = <&merge_funnel_in0>;
2764                                         };
2765                                 };
2766                         };
2767
2768                         in-ports {
2769                                 #address-cells = <1>;
2770                                 #size-cells = <0>;
2771
2772                                 port@7 {
2773                                         reg = <7>;
2774                                         funnel0_in7: endpoint {
2775                                                 remote-endpoint = <&stm_out>;
2776                                         };
2777                                 };
2778                         };
2779                 };
2780
2781                 funnel@6042000 {
2782                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2783                         reg = <0 0x06042000 0 0x1000>;
2784
2785                         clocks = <&aoss_qmp>;
2786                         clock-names = "apb_pclk";
2787
2788                         out-ports {
2789                                 port {
2790                                         funnel1_out: endpoint {
2791                                                 remote-endpoint = <&merge_funnel_in1>;
2792                                         };
2793                                 };
2794                         };
2795
2796                         in-ports {
2797                                 #address-cells = <1>;
2798                                 #size-cells = <0>;
2799
2800                                 port@4 {
2801                                         reg = <4>;
2802                                         funnel1_in4: endpoint {
2803                                                 remote-endpoint = <&swao_replicator_out>;
2804                                         };
2805                                 };
2806                         };
2807                 };
2808
2809                 funnel@6043000 {
2810                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2811                         reg = <0 0x06043000 0 0x1000>;
2812
2813                         clocks = <&aoss_qmp>;
2814                         clock-names = "apb_pclk";
2815
2816                         out-ports {
2817                                 port {
2818                                         funnel2_out: endpoint {
2819                                                 remote-endpoint = <&merge_funnel_in2>;
2820                                         };
2821                                 };
2822                         };
2823
2824                         in-ports {
2825                                 #address-cells = <1>;
2826                                 #size-cells = <0>;
2827
2828                                 port@2 {
2829                                         reg = <2>;
2830                                         funnel2_in2: endpoint {
2831                                                 remote-endpoint = <&apss_merge_funnel_out>;
2832                                         };
2833                                 };
2834                         };
2835                 };
2836
2837                 funnel@6045000 {
2838                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2839                         reg = <0 0x06045000 0 0x1000>;
2840
2841                         clocks = <&aoss_qmp>;
2842                         clock-names = "apb_pclk";
2843
2844                         out-ports {
2845                                 port {
2846                                         merge_funnel_out: endpoint {
2847                                                 remote-endpoint = <&etf_in>;
2848                                         };
2849                                 };
2850                         };
2851
2852                         in-ports {
2853                                 #address-cells = <1>;
2854                                 #size-cells = <0>;
2855
2856                                 port@0 {
2857                                         reg = <0>;
2858                                         merge_funnel_in0: endpoint {
2859                                                 remote-endpoint = <&funnel0_out>;
2860                                         };
2861                                 };
2862
2863                                 port@1 {
2864                                         reg = <1>;
2865                                         merge_funnel_in1: endpoint {
2866                                                 remote-endpoint = <&funnel1_out>;
2867                                         };
2868                                 };
2869
2870                                 port@2 {
2871                                         reg = <2>;
2872                                         merge_funnel_in2: endpoint {
2873                                                 remote-endpoint = <&funnel2_out>;
2874                                         };
2875                                 };
2876                         };
2877                 };
2878
2879                 replicator@6046000 {
2880                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2881                         reg = <0 0x06046000 0 0x1000>;
2882
2883                         clocks = <&aoss_qmp>;
2884                         clock-names = "apb_pclk";
2885
2886                         out-ports {
2887                                 #address-cells = <1>;
2888                                 #size-cells = <0>;
2889
2890                                 port@0 {
2891                                         reg = <0>;
2892                                         replicator_out0: endpoint {
2893                                                 remote-endpoint = <&etr_in>;
2894                                         };
2895                                 };
2896
2897                                 port@1 {
2898                                         reg = <1>;
2899                                         replicator_out1: endpoint {
2900                                                 remote-endpoint = <&replicator1_in>;
2901                                         };
2902                                 };
2903                         };
2904
2905                         in-ports {
2906                                 port {
2907                                         replicator_in0: endpoint {
2908                                                 remote-endpoint = <&etf_out>;
2909                                         };
2910                                 };
2911                         };
2912                 };
2913
2914                 etf@6047000 {
2915                         compatible = "arm,coresight-tmc", "arm,primecell";
2916                         reg = <0 0x06047000 0 0x1000>;
2917
2918                         clocks = <&aoss_qmp>;
2919                         clock-names = "apb_pclk";
2920
2921                         out-ports {
2922                                 port {
2923                                         etf_out: endpoint {
2924                                                 remote-endpoint = <&replicator_in0>;
2925                                         };
2926                                 };
2927                         };
2928
2929                         in-ports {
2930                                 port {
2931                                         etf_in: endpoint {
2932                                                 remote-endpoint = <&merge_funnel_out>;
2933                                         };
2934                                 };
2935                         };
2936                 };
2937
2938                 etr@6048000 {
2939                         compatible = "arm,coresight-tmc", "arm,primecell";
2940                         reg = <0 0x06048000 0 0x1000>;
2941                         iommus = <&apps_smmu 0x05e0 0x0>;
2942
2943                         clocks = <&aoss_qmp>;
2944                         clock-names = "apb_pclk";
2945                         arm,scatter-gather;
2946
2947                         in-ports {
2948                                 port {
2949                                         etr_in: endpoint {
2950                                                 remote-endpoint = <&replicator_out0>;
2951                                         };
2952                                 };
2953                         };
2954                 };
2955
2956                 replicator@604a000 {
2957                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2958                         reg = <0 0x0604a000 0 0x1000>;
2959
2960                         clocks = <&aoss_qmp>;
2961                         clock-names = "apb_pclk";
2962
2963                         out-ports {
2964                                 #address-cells = <1>;
2965                                 #size-cells = <0>;
2966
2967                                 port@1 {
2968                                         reg = <1>;
2969                                         replicator1_out: endpoint {
2970                                                 remote-endpoint = <&swao_funnel_in>;
2971                                         };
2972                                 };
2973                         };
2974
2975                         in-ports {
2976                                 #address-cells = <1>;
2977                                 #size-cells = <0>;
2978
2979                                 port@1 {
2980                                         reg = <1>;
2981                                         replicator1_in: endpoint {
2982                                                 remote-endpoint = <&replicator_out1>;
2983                                         };
2984                                 };
2985                         };
2986                 };
2987
2988                 funnel@6b08000 {
2989                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2990                         reg = <0 0x06b08000 0 0x1000>;
2991
2992                         clocks = <&aoss_qmp>;
2993                         clock-names = "apb_pclk";
2994
2995                         out-ports {
2996                                 port {
2997                                         swao_funnel_out: endpoint {
2998                                                 remote-endpoint = <&swao_etf_in>;
2999                                         };
3000                                 };
3001                         };
3002
3003                         in-ports {
3004                                 #address-cells = <1>;
3005                                 #size-cells = <0>;
3006
3007                                 port@6 {
3008                                         reg = <6>;
3009                                         swao_funnel_in: endpoint {
3010                                                 remote-endpoint = <&replicator1_out>;
3011                                         };
3012                                 };
3013                         };
3014                 };
3015
3016                 etf@6b09000 {
3017                         compatible = "arm,coresight-tmc", "arm,primecell";
3018                         reg = <0 0x06b09000 0 0x1000>;
3019
3020                         clocks = <&aoss_qmp>;
3021                         clock-names = "apb_pclk";
3022
3023                         out-ports {
3024                                 port {
3025                                         swao_etf_out: endpoint {
3026                                                 remote-endpoint = <&swao_replicator_in>;
3027                                         };
3028                                 };
3029                         };
3030
3031                         in-ports {
3032                                 port {
3033                                         swao_etf_in: endpoint {
3034                                                 remote-endpoint = <&swao_funnel_out>;
3035                                         };
3036                                 };
3037                         };
3038                 };
3039
3040                 replicator@6b0a000 {
3041                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3042                         reg = <0 0x06b0a000 0 0x1000>;
3043
3044                         clocks = <&aoss_qmp>;
3045                         clock-names = "apb_pclk";
3046                         qcom,replicator-loses-context;
3047
3048                         out-ports {
3049                                 port {
3050                                         swao_replicator_out: endpoint {
3051                                                 remote-endpoint = <&funnel1_in4>;
3052                                         };
3053                                 };
3054                         };
3055
3056                         in-ports {
3057                                 port {
3058                                         swao_replicator_in: endpoint {
3059                                                 remote-endpoint = <&swao_etf_out>;
3060                                         };
3061                                 };
3062                         };
3063                 };
3064
3065                 etm@7040000 {
3066                         compatible = "arm,coresight-etm4x", "arm,primecell";
3067                         reg = <0 0x07040000 0 0x1000>;
3068
3069                         cpu = <&CPU0>;
3070
3071                         clocks = <&aoss_qmp>;
3072                         clock-names = "apb_pclk";
3073                         arm,coresight-loses-context-with-cpu;
3074                         qcom,skip-power-up;
3075
3076                         out-ports {
3077                                 port {
3078                                         etm0_out: endpoint {
3079                                                 remote-endpoint = <&apss_funnel_in0>;
3080                                         };
3081                                 };
3082                         };
3083                 };
3084
3085                 etm@7140000 {
3086                         compatible = "arm,coresight-etm4x", "arm,primecell";
3087                         reg = <0 0x07140000 0 0x1000>;
3088
3089                         cpu = <&CPU1>;
3090
3091                         clocks = <&aoss_qmp>;
3092                         clock-names = "apb_pclk";
3093                         arm,coresight-loses-context-with-cpu;
3094                         qcom,skip-power-up;
3095
3096                         out-ports {
3097                                 port {
3098                                         etm1_out: endpoint {
3099                                                 remote-endpoint = <&apss_funnel_in1>;
3100                                         };
3101                                 };
3102                         };
3103                 };
3104
3105                 etm@7240000 {
3106                         compatible = "arm,coresight-etm4x", "arm,primecell";
3107                         reg = <0 0x07240000 0 0x1000>;
3108
3109                         cpu = <&CPU2>;
3110
3111                         clocks = <&aoss_qmp>;
3112                         clock-names = "apb_pclk";
3113                         arm,coresight-loses-context-with-cpu;
3114                         qcom,skip-power-up;
3115
3116                         out-ports {
3117                                 port {
3118                                         etm2_out: endpoint {
3119                                                 remote-endpoint = <&apss_funnel_in2>;
3120                                         };
3121                                 };
3122                         };
3123                 };
3124
3125                 etm@7340000 {
3126                         compatible = "arm,coresight-etm4x", "arm,primecell";
3127                         reg = <0 0x07340000 0 0x1000>;
3128
3129                         cpu = <&CPU3>;
3130
3131                         clocks = <&aoss_qmp>;
3132                         clock-names = "apb_pclk";
3133                         arm,coresight-loses-context-with-cpu;
3134                         qcom,skip-power-up;
3135
3136                         out-ports {
3137                                 port {
3138                                         etm3_out: endpoint {
3139                                                 remote-endpoint = <&apss_funnel_in3>;
3140                                         };
3141                                 };
3142                         };
3143                 };
3144
3145                 etm@7440000 {
3146                         compatible = "arm,coresight-etm4x", "arm,primecell";
3147                         reg = <0 0x07440000 0 0x1000>;
3148
3149                         cpu = <&CPU4>;
3150
3151                         clocks = <&aoss_qmp>;
3152                         clock-names = "apb_pclk";
3153                         arm,coresight-loses-context-with-cpu;
3154                         qcom,skip-power-up;
3155
3156                         out-ports {
3157                                 port {
3158                                         etm4_out: endpoint {
3159                                                 remote-endpoint = <&apss_funnel_in4>;
3160                                         };
3161                                 };
3162                         };
3163                 };
3164
3165                 etm@7540000 {
3166                         compatible = "arm,coresight-etm4x", "arm,primecell";
3167                         reg = <0 0x07540000 0 0x1000>;
3168
3169                         cpu = <&CPU5>;
3170
3171                         clocks = <&aoss_qmp>;
3172                         clock-names = "apb_pclk";
3173                         arm,coresight-loses-context-with-cpu;
3174                         qcom,skip-power-up;
3175
3176                         out-ports {
3177                                 port {
3178                                         etm5_out: endpoint {
3179                                                 remote-endpoint = <&apss_funnel_in5>;
3180                                         };
3181                                 };
3182                         };
3183                 };
3184
3185                 etm@7640000 {
3186                         compatible = "arm,coresight-etm4x", "arm,primecell";
3187                         reg = <0 0x07640000 0 0x1000>;
3188
3189                         cpu = <&CPU6>;
3190
3191                         clocks = <&aoss_qmp>;
3192                         clock-names = "apb_pclk";
3193                         arm,coresight-loses-context-with-cpu;
3194                         qcom,skip-power-up;
3195
3196                         out-ports {
3197                                 port {
3198                                         etm6_out: endpoint {
3199                                                 remote-endpoint = <&apss_funnel_in6>;
3200                                         };
3201                                 };
3202                         };
3203                 };
3204
3205                 etm@7740000 {
3206                         compatible = "arm,coresight-etm4x", "arm,primecell";
3207                         reg = <0 0x07740000 0 0x1000>;
3208
3209                         cpu = <&CPU7>;
3210
3211                         clocks = <&aoss_qmp>;
3212                         clock-names = "apb_pclk";
3213                         arm,coresight-loses-context-with-cpu;
3214                         qcom,skip-power-up;
3215
3216                         out-ports {
3217                                 port {
3218                                         etm7_out: endpoint {
3219                                                 remote-endpoint = <&apss_funnel_in7>;
3220                                         };
3221                                 };
3222                         };
3223                 };
3224
3225                 funnel@7800000 { /* APSS Funnel */
3226                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3227                         reg = <0 0x07800000 0 0x1000>;
3228
3229                         clocks = <&aoss_qmp>;
3230                         clock-names = "apb_pclk";
3231
3232                         out-ports {
3233                                 port {
3234                                         apss_funnel_out: endpoint {
3235                                                 remote-endpoint = <&apss_merge_funnel_in>;
3236                                         };
3237                                 };
3238                         };
3239
3240                         in-ports {
3241                                 #address-cells = <1>;
3242                                 #size-cells = <0>;
3243
3244                                 port@0 {
3245                                         reg = <0>;
3246                                         apss_funnel_in0: endpoint {
3247                                                 remote-endpoint = <&etm0_out>;
3248                                         };
3249                                 };
3250
3251                                 port@1 {
3252                                         reg = <1>;
3253                                         apss_funnel_in1: endpoint {
3254                                                 remote-endpoint = <&etm1_out>;
3255                                         };
3256                                 };
3257
3258                                 port@2 {
3259                                         reg = <2>;
3260                                         apss_funnel_in2: endpoint {
3261                                                 remote-endpoint = <&etm2_out>;
3262                                         };
3263                                 };
3264
3265                                 port@3 {
3266                                         reg = <3>;
3267                                         apss_funnel_in3: endpoint {
3268                                                 remote-endpoint = <&etm3_out>;
3269                                         };
3270                                 };
3271
3272                                 port@4 {
3273                                         reg = <4>;
3274                                         apss_funnel_in4: endpoint {
3275                                                 remote-endpoint = <&etm4_out>;
3276                                         };
3277                                 };
3278
3279                                 port@5 {
3280                                         reg = <5>;
3281                                         apss_funnel_in5: endpoint {
3282                                                 remote-endpoint = <&etm5_out>;
3283                                         };
3284                                 };
3285
3286                                 port@6 {
3287                                         reg = <6>;
3288                                         apss_funnel_in6: endpoint {
3289                                                 remote-endpoint = <&etm6_out>;
3290                                         };
3291                                 };
3292
3293                                 port@7 {
3294                                         reg = <7>;
3295                                         apss_funnel_in7: endpoint {
3296                                                 remote-endpoint = <&etm7_out>;
3297                                         };
3298                                 };
3299                         };
3300                 };
3301
3302                 funnel@7810000 {
3303                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3304                         reg = <0 0x07810000 0 0x1000>;
3305
3306                         clocks = <&aoss_qmp>;
3307                         clock-names = "apb_pclk";
3308
3309                         out-ports {
3310                                 port {
3311                                         apss_merge_funnel_out: endpoint {
3312                                                 remote-endpoint = <&funnel2_in2>;
3313                                         };
3314                                 };
3315                         };
3316
3317                         in-ports {
3318                                 port {
3319                                         apss_merge_funnel_in: endpoint {
3320                                                 remote-endpoint = <&apss_funnel_out>;
3321                                         };
3322                                 };
3323                         };
3324                 };
3325
3326                 remoteproc_cdsp: remoteproc@8300000 {
3327                         compatible = "qcom,sm8150-cdsp-pas";
3328                         reg = <0x0 0x08300000 0x0 0x4040>;
3329
3330                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3331                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3332                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3333                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3334                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3335                         interrupt-names = "wdog", "fatal", "ready",
3336                                           "handover", "stop-ack";
3337
3338                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3339                         clock-names = "xo";
3340
3341                         power-domains = <&rpmhpd SM8150_CX>;
3342
3343                         memory-region = <&cdsp_mem>;
3344
3345                         qcom,qmp = <&aoss_qmp>;
3346
3347                         qcom,smem-states = <&cdsp_smp2p_out 0>;
3348                         qcom,smem-state-names = "stop";
3349
3350                         status = "disabled";
3351
3352                         glink-edge {
3353                                 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3354                                 label = "cdsp";
3355                                 qcom,remote-pid = <5>;
3356                                 mboxes = <&apss_shared 4>;
3357
3358                                 fastrpc {
3359                                         compatible = "qcom,fastrpc";
3360                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3361                                         label = "cdsp";
3362                                         qcom,non-secure-domain;
3363                                         #address-cells = <1>;
3364                                         #size-cells = <0>;
3365
3366                                         compute-cb@1 {
3367                                                 compatible = "qcom,fastrpc-compute-cb";
3368                                                 reg = <1>;
3369                                                 iommus = <&apps_smmu 0x1001 0x0460>;
3370                                         };
3371
3372                                         compute-cb@2 {
3373                                                 compatible = "qcom,fastrpc-compute-cb";
3374                                                 reg = <2>;
3375                                                 iommus = <&apps_smmu 0x1002 0x0460>;
3376                                         };
3377
3378                                         compute-cb@3 {
3379                                                 compatible = "qcom,fastrpc-compute-cb";
3380                                                 reg = <3>;
3381                                                 iommus = <&apps_smmu 0x1003 0x0460>;
3382                                         };
3383
3384                                         compute-cb@4 {
3385                                                 compatible = "qcom,fastrpc-compute-cb";
3386                                                 reg = <4>;
3387                                                 iommus = <&apps_smmu 0x1004 0x0460>;
3388                                         };
3389
3390                                         compute-cb@5 {
3391                                                 compatible = "qcom,fastrpc-compute-cb";
3392                                                 reg = <5>;
3393                                                 iommus = <&apps_smmu 0x1005 0x0460>;
3394                                         };
3395
3396                                         compute-cb@6 {
3397                                                 compatible = "qcom,fastrpc-compute-cb";
3398                                                 reg = <6>;
3399                                                 iommus = <&apps_smmu 0x1006 0x0460>;
3400                                         };
3401
3402                                         compute-cb@7 {
3403                                                 compatible = "qcom,fastrpc-compute-cb";
3404                                                 reg = <7>;
3405                                                 iommus = <&apps_smmu 0x1007 0x0460>;
3406                                         };
3407
3408                                         compute-cb@8 {
3409                                                 compatible = "qcom,fastrpc-compute-cb";
3410                                                 reg = <8>;
3411                                                 iommus = <&apps_smmu 0x1008 0x0460>;
3412                                         };
3413
3414                                         /* note: secure cb9 in downstream */
3415                                 };
3416                         };
3417                 };
3418
3419                 usb_1_hsphy: phy@88e2000 {
3420                         compatible = "qcom,sm8150-usb-hs-phy",
3421                                      "qcom,usb-snps-hs-7nm-phy";
3422                         reg = <0 0x088e2000 0 0x400>;
3423                         status = "disabled";
3424                         #phy-cells = <0>;
3425
3426                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3427                         clock-names = "ref";
3428
3429                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3430                 };
3431
3432                 usb_2_hsphy: phy@88e3000 {
3433                         compatible = "qcom,sm8150-usb-hs-phy",
3434                                      "qcom,usb-snps-hs-7nm-phy";
3435                         reg = <0 0x088e3000 0 0x400>;
3436                         status = "disabled";
3437                         #phy-cells = <0>;
3438
3439                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3440                         clock-names = "ref";
3441
3442                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3443                 };
3444
3445                 usb_1_qmpphy: phy@88e9000 {
3446                         compatible = "qcom,sm8150-qmp-usb3-phy";
3447                         reg = <0 0x088e9000 0 0x18c>,
3448                               <0 0x088e8000 0 0x10>;
3449                         status = "disabled";
3450                         #address-cells = <2>;
3451                         #size-cells = <2>;
3452                         ranges;
3453
3454                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3455                                  <&rpmhcc RPMH_CXO_CLK>,
3456                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3457                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3458                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3459
3460                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3461                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3462                         reset-names = "phy", "common";
3463
3464                         usb_1_ssphy: phy@88e9200 {
3465                                 reg = <0 0x088e9200 0 0x200>,
3466                                       <0 0x088e9400 0 0x200>,
3467                                       <0 0x088e9c00 0 0x218>,
3468                                       <0 0x088e9600 0 0x200>,
3469                                       <0 0x088e9800 0 0x200>,
3470                                       <0 0x088e9a00 0 0x100>;
3471                                 #clock-cells = <0>;
3472                                 #phy-cells = <0>;
3473                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3474                                 clock-names = "pipe0";
3475                                 clock-output-names = "usb3_phy_pipe_clk_src";
3476                         };
3477                 };
3478
3479                 usb_2_qmpphy: phy@88eb000 {
3480                         compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3481                         reg = <0 0x088eb000 0 0x200>;
3482                         status = "disabled";
3483                         #address-cells = <2>;
3484                         #size-cells = <2>;
3485                         ranges;
3486
3487                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3488                                  <&rpmhcc RPMH_CXO_CLK>,
3489                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3490                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3491                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3492
3493                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3494                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3495                         reset-names = "phy", "common";
3496
3497                         usb_2_ssphy: phy@88eb200 {
3498                                 reg = <0 0x088eb200 0 0x200>,
3499                                       <0 0x088eb400 0 0x200>,
3500                                       <0 0x088eb800 0 0x800>,
3501                                       <0 0x088eb600 0 0x200>;
3502                                 #clock-cells = <0>;
3503                                 #phy-cells = <0>;
3504                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3505                                 clock-names = "pipe0";
3506                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3507                         };
3508                 };
3509
3510                 sdhc_2: mmc@8804000 {
3511                         compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3512                         reg = <0 0x08804000 0 0x1000>;
3513
3514                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3515                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3516                         interrupt-names = "hc_irq", "pwr_irq";
3517
3518                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3519                                  <&gcc GCC_SDCC2_APPS_CLK>,
3520                                  <&rpmhcc RPMH_CXO_CLK>;
3521                         clock-names = "iface", "core", "xo";
3522                         iommus = <&apps_smmu 0x6a0 0x0>;
3523                         qcom,dll-config = <0x0007642c>;
3524                         qcom,ddr-config = <0x80040868>;
3525                         power-domains = <&rpmhpd 0>;
3526                         operating-points-v2 = <&sdhc2_opp_table>;
3527
3528                         status = "disabled";
3529
3530                         sdhc2_opp_table: opp-table {
3531                                 compatible = "operating-points-v2";
3532
3533                                 opp-19200000 {
3534                                         opp-hz = /bits/ 64 <19200000>;
3535                                         required-opps = <&rpmhpd_opp_min_svs>;
3536                                 };
3537
3538                                 opp-50000000 {
3539                                         opp-hz = /bits/ 64 <50000000>;
3540                                         required-opps = <&rpmhpd_opp_low_svs>;
3541                                 };
3542
3543                                 opp-100000000 {
3544                                         opp-hz = /bits/ 64 <100000000>;
3545                                         required-opps = <&rpmhpd_opp_svs>;
3546                                 };
3547
3548                                 opp-202000000 {
3549                                         opp-hz = /bits/ 64 <202000000>;
3550                                         required-opps = <&rpmhpd_opp_svs_l1>;
3551                                 };
3552                         };
3553                 };
3554
3555                 dc_noc: interconnect@9160000 {
3556                         compatible = "qcom,sm8150-dc-noc";
3557                         reg = <0 0x09160000 0 0x3200>;
3558                         #interconnect-cells = <2>;
3559                         qcom,bcm-voters = <&apps_bcm_voter>;
3560                 };
3561
3562                 gem_noc: interconnect@9680000 {
3563                         compatible = "qcom,sm8150-gem-noc";
3564                         reg = <0 0x09680000 0 0x3e200>;
3565                         #interconnect-cells = <2>;
3566                         qcom,bcm-voters = <&apps_bcm_voter>;
3567                 };
3568
3569                 usb_1: usb@a6f8800 {
3570                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3571                         reg = <0 0x0a6f8800 0 0x400>;
3572                         status = "disabled";
3573                         #address-cells = <2>;
3574                         #size-cells = <2>;
3575                         ranges;
3576                         dma-ranges;
3577
3578                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3579                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3580                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3581                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3582                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3583                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3584                         clock-names = "cfg_noc",
3585                                       "core",
3586                                       "iface",
3587                                       "sleep",
3588                                       "mock_utmi",
3589                                       "xo";
3590
3591                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3592                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3593                         assigned-clock-rates = <19200000>, <200000000>;
3594
3595                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3596                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3597                                      <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
3598                                      <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
3599                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3600                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3601
3602                         power-domains = <&gcc USB30_PRIM_GDSC>;
3603
3604                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3605
3606                         interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3607                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3608                         interconnect-names = "usb-ddr", "apps-usb";
3609
3610                         usb_1_dwc3: usb@a600000 {
3611                                 compatible = "snps,dwc3";
3612                                 reg = <0 0x0a600000 0 0xcd00>;
3613                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3614                                 iommus = <&apps_smmu 0x140 0>;
3615                                 snps,dis_u2_susphy_quirk;
3616                                 snps,dis_enblslpm_quirk;
3617                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3618                                 phy-names = "usb2-phy", "usb3-phy";
3619                         };
3620                 };
3621
3622                 usb_2: usb@a8f8800 {
3623                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3624                         reg = <0 0x0a8f8800 0 0x400>;
3625                         status = "disabled";
3626                         #address-cells = <2>;
3627                         #size-cells = <2>;
3628                         ranges;
3629                         dma-ranges;
3630
3631                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3632                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3633                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3634                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3635                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3636                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3637                         clock-names = "cfg_noc",
3638                                       "core",
3639                                       "iface",
3640                                       "sleep",
3641                                       "mock_utmi",
3642                                       "xo";
3643
3644                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3645                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3646                         assigned-clock-rates = <19200000>, <200000000>;
3647
3648                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3649                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3650                                      <GIC_SPI 490 IRQ_TYPE_EDGE_BOTH>,
3651                                      <GIC_SPI 491 IRQ_TYPE_EDGE_BOTH>;
3652                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3653                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3654
3655                         power-domains = <&gcc USB30_SEC_GDSC>;
3656
3657                         resets = <&gcc GCC_USB30_SEC_BCR>;
3658
3659                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3660                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3661                         interconnect-names = "usb-ddr", "apps-usb";
3662
3663                         usb_2_dwc3: usb@a800000 {
3664                                 compatible = "snps,dwc3";
3665                                 reg = <0 0x0a800000 0 0xcd00>;
3666                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3667                                 iommus = <&apps_smmu 0x160 0>;
3668                                 snps,dis_u2_susphy_quirk;
3669                                 snps,dis_enblslpm_quirk;
3670                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3671                                 phy-names = "usb2-phy", "usb3-phy";
3672                         };
3673                 };
3674
3675                 camnoc_virt: interconnect@ac00000 {
3676                         compatible = "qcom,sm8150-camnoc-virt";
3677                         reg = <0 0x0ac00000 0 0x1000>;
3678                         #interconnect-cells = <2>;
3679                         qcom,bcm-voters = <&apps_bcm_voter>;
3680                 };
3681
3682                 mdss: display-subsystem@ae00000 {
3683                         compatible = "qcom,sm8150-mdss";
3684                         reg = <0 0x0ae00000 0 0x1000>;
3685                         reg-names = "mdss";
3686
3687                         interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3688                                         <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3689                         interconnect-names = "mdp0-mem", "mdp1-mem";
3690
3691                         power-domains = <&dispcc MDSS_GDSC>;
3692
3693                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3694                                  <&gcc GCC_DISP_HF_AXI_CLK>,
3695                                  <&gcc GCC_DISP_SF_AXI_CLK>,
3696                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
3697                         clock-names = "iface", "bus", "nrt_bus", "core";
3698
3699                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3700                         interrupt-controller;
3701                         #interrupt-cells = <1>;
3702
3703                         iommus = <&apps_smmu 0x800 0x420>;
3704
3705                         status = "disabled";
3706
3707                         #address-cells = <2>;
3708                         #size-cells = <2>;
3709                         ranges;
3710
3711                         mdss_mdp: display-controller@ae01000 {
3712                                 compatible = "qcom,sm8150-dpu";
3713                                 reg = <0 0x0ae01000 0 0x8f000>,
3714                                       <0 0x0aeb0000 0 0x2008>;
3715                                 reg-names = "mdp", "vbif";
3716
3717                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3718                                          <&gcc GCC_DISP_HF_AXI_CLK>,
3719                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3720                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3721                                 clock-names = "iface", "bus", "core", "vsync";
3722
3723                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3724                                 assigned-clock-rates = <19200000>;
3725
3726                                 operating-points-v2 = <&mdp_opp_table>;
3727                                 power-domains = <&rpmhpd SM8150_MMCX>;
3728
3729                                 interrupt-parent = <&mdss>;
3730                                 interrupts = <0>;
3731
3732                                 ports {
3733                                         #address-cells = <1>;
3734                                         #size-cells = <0>;
3735
3736                                         port@0 {
3737                                                 reg = <0>;
3738                                                 dpu_intf1_out: endpoint {
3739                                                         remote-endpoint = <&mdss_dsi0_in>;
3740                                                 };
3741                                         };
3742
3743                                         port@1 {
3744                                                 reg = <1>;
3745                                                 dpu_intf2_out: endpoint {
3746                                                         remote-endpoint = <&mdss_dsi1_in>;
3747                                                 };
3748                                         };
3749                                 };
3750
3751                                 mdp_opp_table: opp-table {
3752                                         compatible = "operating-points-v2";
3753
3754                                         opp-171428571 {
3755                                                 opp-hz = /bits/ 64 <171428571>;
3756                                                 required-opps = <&rpmhpd_opp_low_svs>;
3757                                         };
3758
3759                                         opp-300000000 {
3760                                                 opp-hz = /bits/ 64 <300000000>;
3761                                                 required-opps = <&rpmhpd_opp_svs>;
3762                                         };
3763
3764                                         opp-345000000 {
3765                                                 opp-hz = /bits/ 64 <345000000>;
3766                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3767                                         };
3768
3769                                         opp-460000000 {
3770                                                 opp-hz = /bits/ 64 <460000000>;
3771                                                 required-opps = <&rpmhpd_opp_nom>;
3772                                         };
3773                                 };
3774                         };
3775
3776                         mdss_dsi0: dsi@ae94000 {
3777                                 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3778                                 reg = <0 0x0ae94000 0 0x400>;
3779                                 reg-names = "dsi_ctrl";
3780
3781                                 interrupt-parent = <&mdss>;
3782                                 interrupts = <4>;
3783
3784                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3785                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3786                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3787                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3788                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3789                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3790                                 clock-names = "byte",
3791                                               "byte_intf",
3792                                               "pixel",
3793                                               "core",
3794                                               "iface",
3795                                               "bus";
3796
3797                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3798                                                   <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3799                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3800                                                          <&mdss_dsi0_phy 1>;
3801
3802                                 operating-points-v2 = <&dsi_opp_table>;
3803                                 power-domains = <&rpmhpd SM8150_MMCX>;
3804
3805                                 phys = <&mdss_dsi0_phy>;
3806
3807                                 status = "disabled";
3808
3809                                 #address-cells = <1>;
3810                                 #size-cells = <0>;
3811
3812                                 ports {
3813                                         #address-cells = <1>;
3814                                         #size-cells = <0>;
3815
3816                                         port@0 {
3817                                                 reg = <0>;
3818                                                 mdss_dsi0_in: endpoint {
3819                                                         remote-endpoint = <&dpu_intf1_out>;
3820                                                 };
3821                                         };
3822
3823                                         port@1 {
3824                                                 reg = <1>;
3825                                                 mdss_dsi0_out: endpoint {
3826                                                 };
3827                                         };
3828                                 };
3829
3830                                 dsi_opp_table: opp-table {
3831                                         compatible = "operating-points-v2";
3832
3833                                         opp-187500000 {
3834                                                 opp-hz = /bits/ 64 <187500000>;
3835                                                 required-opps = <&rpmhpd_opp_low_svs>;
3836                                         };
3837
3838                                         opp-300000000 {
3839                                                 opp-hz = /bits/ 64 <300000000>;
3840                                                 required-opps = <&rpmhpd_opp_svs>;
3841                                         };
3842
3843                                         opp-358000000 {
3844                                                 opp-hz = /bits/ 64 <358000000>;
3845                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3846                                         };
3847                                 };
3848                         };
3849
3850                         mdss_dsi0_phy: phy@ae94400 {
3851                                 compatible = "qcom,dsi-phy-7nm-8150";
3852                                 reg = <0 0x0ae94400 0 0x200>,
3853                                       <0 0x0ae94600 0 0x280>,
3854                                       <0 0x0ae94900 0 0x260>;
3855                                 reg-names = "dsi_phy",
3856                                             "dsi_phy_lane",
3857                                             "dsi_pll";
3858
3859                                 #clock-cells = <1>;
3860                                 #phy-cells = <0>;
3861
3862                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3863                                          <&rpmhcc RPMH_CXO_CLK>;
3864                                 clock-names = "iface", "ref";
3865
3866                                 status = "disabled";
3867                         };
3868
3869                         mdss_dsi1: dsi@ae96000 {
3870                                 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3871                                 reg = <0 0x0ae96000 0 0x400>;
3872                                 reg-names = "dsi_ctrl";
3873
3874                                 interrupt-parent = <&mdss>;
3875                                 interrupts = <5>;
3876
3877                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3878                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3879                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3880                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3881                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3882                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3883                                 clock-names = "byte",
3884                                               "byte_intf",
3885                                               "pixel",
3886                                               "core",
3887                                               "iface",
3888                                               "bus";
3889
3890                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3891                                                   <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3892                                 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3893                                                          <&mdss_dsi1_phy 1>;
3894
3895                                 operating-points-v2 = <&dsi_opp_table>;
3896                                 power-domains = <&rpmhpd SM8150_MMCX>;
3897
3898                                 phys = <&mdss_dsi1_phy>;
3899
3900                                 status = "disabled";
3901
3902                                 #address-cells = <1>;
3903                                 #size-cells = <0>;
3904
3905                                 ports {
3906                                         #address-cells = <1>;
3907                                         #size-cells = <0>;
3908
3909                                         port@0 {
3910                                                 reg = <0>;
3911                                                 mdss_dsi1_in: endpoint {
3912                                                         remote-endpoint = <&dpu_intf2_out>;
3913                                                 };
3914                                         };
3915
3916                                         port@1 {
3917                                                 reg = <1>;
3918                                                 mdss_dsi1_out: endpoint {
3919                                                 };
3920                                         };
3921                                 };
3922                         };
3923
3924                         mdss_dsi1_phy: phy@ae96400 {
3925                                 compatible = "qcom,dsi-phy-7nm-8150";
3926                                 reg = <0 0x0ae96400 0 0x200>,
3927                                       <0 0x0ae96600 0 0x280>,
3928                                       <0 0x0ae96900 0 0x260>;
3929                                 reg-names = "dsi_phy",
3930                                             "dsi_phy_lane",
3931                                             "dsi_pll";
3932
3933                                 #clock-cells = <1>;
3934                                 #phy-cells = <0>;
3935
3936                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3937                                          <&rpmhcc RPMH_CXO_CLK>;
3938                                 clock-names = "iface", "ref";
3939
3940                                 status = "disabled";
3941                         };
3942                 };
3943
3944                 dispcc: clock-controller@af00000 {
3945                         compatible = "qcom,sm8150-dispcc";
3946                         reg = <0 0x0af00000 0 0x10000>;
3947                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3948                                  <&mdss_dsi0_phy 0>,
3949                                  <&mdss_dsi0_phy 1>,
3950                                  <&mdss_dsi1_phy 0>,
3951                                  <&mdss_dsi1_phy 1>,
3952                                  <0>,
3953                                  <0>;
3954                         clock-names = "bi_tcxo",
3955                                       "dsi0_phy_pll_out_byteclk",
3956                                       "dsi0_phy_pll_out_dsiclk",
3957                                       "dsi1_phy_pll_out_byteclk",
3958                                       "dsi1_phy_pll_out_dsiclk",
3959                                       "dp_phy_pll_link_clk",
3960                                       "dp_phy_pll_vco_div_clk";
3961                         power-domains = <&rpmhpd SM8150_MMCX>;
3962                         required-opps = <&rpmhpd_opp_low_svs>;
3963                         #clock-cells = <1>;
3964                         #reset-cells = <1>;
3965                         #power-domain-cells = <1>;
3966                 };
3967
3968                 pdc: interrupt-controller@b220000 {
3969                         compatible = "qcom,sm8150-pdc", "qcom,pdc";
3970                         reg = <0 0x0b220000 0 0x30000>;
3971                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3972                                           <125 63 1>;
3973                         #interrupt-cells = <2>;
3974                         interrupt-parent = <&intc>;
3975                         interrupt-controller;
3976                 };
3977
3978                 aoss_qmp: power-management@c300000 {
3979                         compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
3980                         reg = <0x0 0x0c300000 0x0 0x400>;
3981                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3982                         mboxes = <&apss_shared 0>;
3983
3984                         #clock-cells = <0>;
3985                 };
3986
3987                 sram@c3f0000 {
3988                         compatible = "qcom,rpmh-stats";
3989                         reg = <0 0x0c3f0000 0 0x400>;
3990                 };
3991
3992                 tsens0: thermal-sensor@c263000 {
3993                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3994                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3995                               <0 0x0c222000 0 0x1ff>; /* SROT */
3996                         #qcom,sensors = <16>;
3997                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3998                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3999                         interrupt-names = "uplow", "critical";
4000                         #thermal-sensor-cells = <1>;
4001                 };
4002
4003                 tsens1: thermal-sensor@c265000 {
4004                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4005                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4006                               <0 0x0c223000 0 0x1ff>; /* SROT */
4007                         #qcom,sensors = <8>;
4008                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4009                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4010                         interrupt-names = "uplow", "critical";
4011                         #thermal-sensor-cells = <1>;
4012                 };
4013
4014                 spmi_bus: spmi@c440000 {
4015                         compatible = "qcom,spmi-pmic-arb";
4016                         reg = <0x0 0x0c440000 0x0 0x0001100>,
4017                               <0x0 0x0c600000 0x0 0x2000000>,
4018                               <0x0 0x0e600000 0x0 0x0100000>,
4019                               <0x0 0x0e700000 0x0 0x00a0000>,
4020                               <0x0 0x0c40a000 0x0 0x0026000>;
4021                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4022                         interrupt-names = "periph_irq";
4023                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4024                         qcom,ee = <0>;
4025                         qcom,channel = <0>;
4026                         #address-cells = <2>;
4027                         #size-cells = <0>;
4028                         interrupt-controller;
4029                         #interrupt-cells = <4>;
4030                 };
4031
4032                 apps_smmu: iommu@15000000 {
4033                         compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4034                         reg = <0 0x15000000 0 0x100000>;
4035                         #iommu-cells = <2>;
4036                         #global-interrupts = <1>;
4037                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4038                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4039                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4040                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4041                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4042                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4043                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4044                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4045                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4046                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4047                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4048                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4049                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4050                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4051                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4052                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4053                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4054                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4055                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4056                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4057                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4058                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4059                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4060                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4061                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4062                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4063                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4064                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4065                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4066                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4067                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4068                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4069                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4070                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4071                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4072                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4073                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4074                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4075                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4076                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4077                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4078                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4079                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4080                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4081                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4082                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4083                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4084                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4085                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4086                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4087                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4088                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4089                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4090                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4091                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4092                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4093                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4094                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4095                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4096                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4097                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4098                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4099                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4100                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4101                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4102                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4103                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4104                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4105                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4106                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4107                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4108                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4109                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4110                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4111                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4112                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4113                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4114                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4115                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4116                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4117                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4118                 };
4119
4120                 remoteproc_adsp: remoteproc@17300000 {
4121                         compatible = "qcom,sm8150-adsp-pas";
4122                         reg = <0x0 0x17300000 0x0 0x4040>;
4123
4124                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4125                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4126                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4127                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4128                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4129                         interrupt-names = "wdog", "fatal", "ready",
4130                                           "handover", "stop-ack";
4131
4132                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4133                         clock-names = "xo";
4134
4135                         power-domains = <&rpmhpd SM8150_CX>;
4136
4137                         memory-region = <&adsp_mem>;
4138
4139                         qcom,qmp = <&aoss_qmp>;
4140
4141                         qcom,smem-states = <&adsp_smp2p_out 0>;
4142                         qcom,smem-state-names = "stop";
4143
4144                         status = "disabled";
4145
4146                         glink-edge {
4147                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4148                                 label = "lpass";
4149                                 qcom,remote-pid = <2>;
4150                                 mboxes = <&apss_shared 8>;
4151
4152                                 fastrpc {
4153                                         compatible = "qcom,fastrpc";
4154                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4155                                         label = "adsp";
4156                                         qcom,non-secure-domain;
4157                                         #address-cells = <1>;
4158                                         #size-cells = <0>;
4159
4160                                         compute-cb@3 {
4161                                                 compatible = "qcom,fastrpc-compute-cb";
4162                                                 reg = <3>;
4163                                                 iommus = <&apps_smmu 0x1b23 0x0>;
4164                                         };
4165
4166                                         compute-cb@4 {
4167                                                 compatible = "qcom,fastrpc-compute-cb";
4168                                                 reg = <4>;
4169                                                 iommus = <&apps_smmu 0x1b24 0x0>;
4170                                         };
4171
4172                                         compute-cb@5 {
4173                                                 compatible = "qcom,fastrpc-compute-cb";
4174                                                 reg = <5>;
4175                                                 iommus = <&apps_smmu 0x1b25 0x0>;
4176                                         };
4177                                 };
4178                         };
4179                 };
4180
4181                 intc: interrupt-controller@17a00000 {
4182                         compatible = "arm,gic-v3";
4183                         interrupt-controller;
4184                         #interrupt-cells = <3>;
4185                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
4186                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
4187                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4188                 };
4189
4190                 apss_shared: mailbox@17c00000 {
4191                         compatible = "qcom,sm8150-apss-shared",
4192                                      "qcom,sdm845-apss-shared";
4193                         reg = <0x0 0x17c00000 0x0 0x1000>;
4194                         #mbox-cells = <1>;
4195                 };
4196
4197                 watchdog@17c10000 {
4198                         compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4199                         reg = <0 0x17c10000 0 0x1000>;
4200                         clocks = <&sleep_clk>;
4201                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4202                 };
4203
4204                 timer@17c20000 {
4205                         #address-cells = <1>;
4206                         #size-cells = <1>;
4207                         ranges = <0 0 0 0x20000000>;
4208                         compatible = "arm,armv7-timer-mem";
4209                         reg = <0x0 0x17c20000 0x0 0x1000>;
4210                         clock-frequency = <19200000>;
4211
4212                         frame@17c21000 {
4213                                 frame-number = <0>;
4214                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4215                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4216                                 reg = <0x17c21000 0x1000>,
4217                                       <0x17c22000 0x1000>;
4218                         };
4219
4220                         frame@17c23000 {
4221                                 frame-number = <1>;
4222                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4223                                 reg = <0x17c23000 0x1000>;
4224                                 status = "disabled";
4225                         };
4226
4227                         frame@17c25000 {
4228                                 frame-number = <2>;
4229                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4230                                 reg = <0x17c25000 0x1000>;
4231                                 status = "disabled";
4232                         };
4233
4234                         frame@17c27000 {
4235                                 frame-number = <3>;
4236                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4237                                 reg = <0x17c26000 0x1000>;
4238                                 status = "disabled";
4239                         };
4240
4241                         frame@17c29000 {
4242                                 frame-number = <4>;
4243                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4244                                 reg = <0x17c29000 0x1000>;
4245                                 status = "disabled";
4246                         };
4247
4248                         frame@17c2b000 {
4249                                 frame-number = <5>;
4250                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4251                                 reg = <0x17c2b000 0x1000>;
4252                                 status = "disabled";
4253                         };
4254
4255                         frame@17c2d000 {
4256                                 frame-number = <6>;
4257                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4258                                 reg = <0x17c2d000 0x1000>;
4259                                 status = "disabled";
4260                         };
4261                 };
4262
4263                 apps_rsc: rsc@18200000 {
4264                         label = "apps_rsc";
4265                         compatible = "qcom,rpmh-rsc";
4266                         reg = <0x0 0x18200000 0x0 0x10000>,
4267                               <0x0 0x18210000 0x0 0x10000>,
4268                               <0x0 0x18220000 0x0 0x10000>;
4269                         reg-names = "drv-0", "drv-1", "drv-2";
4270                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4271                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4272                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4273                         qcom,tcs-offset = <0xd00>;
4274                         qcom,drv-id = <2>;
4275                         qcom,tcs-config = <ACTIVE_TCS  2>,
4276                                           <SLEEP_TCS   3>,
4277                                           <WAKE_TCS    3>,
4278                                           <CONTROL_TCS 1>;
4279                         power-domains = <&CLUSTER_PD>;
4280
4281                         rpmhcc: clock-controller {
4282                                 compatible = "qcom,sm8150-rpmh-clk";
4283                                 #clock-cells = <1>;
4284                                 clock-names = "xo";
4285                                 clocks = <&xo_board>;
4286                         };
4287
4288                         rpmhpd: power-controller {
4289                                 compatible = "qcom,sm8150-rpmhpd";
4290                                 #power-domain-cells = <1>;
4291                                 operating-points-v2 = <&rpmhpd_opp_table>;
4292
4293                                 rpmhpd_opp_table: opp-table {
4294                                         compatible = "operating-points-v2";
4295
4296                                         rpmhpd_opp_ret: opp1 {
4297                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4298                                         };
4299
4300                                         rpmhpd_opp_min_svs: opp2 {
4301                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4302                                         };
4303
4304                                         rpmhpd_opp_low_svs: opp3 {
4305                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4306                                         };
4307
4308                                         rpmhpd_opp_svs: opp4 {
4309                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4310                                         };
4311
4312                                         rpmhpd_opp_svs_l1: opp5 {
4313                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4314                                         };
4315
4316                                         rpmhpd_opp_svs_l2: opp6 {
4317                                                 opp-level = <224>;
4318                                         };
4319
4320                                         rpmhpd_opp_nom: opp7 {
4321                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4322                                         };
4323
4324                                         rpmhpd_opp_nom_l1: opp8 {
4325                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4326                                         };
4327
4328                                         rpmhpd_opp_nom_l2: opp9 {
4329                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4330                                         };
4331
4332                                         rpmhpd_opp_turbo: opp10 {
4333                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4334                                         };
4335
4336                                         rpmhpd_opp_turbo_l1: opp11 {
4337                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4338                                         };
4339                                 };
4340                         };
4341
4342                         apps_bcm_voter: bcm-voter {
4343                                 compatible = "qcom,bcm-voter";
4344                         };
4345                 };
4346
4347                 osm_l3: interconnect@18321000 {
4348                         compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4349                         reg = <0 0x18321000 0 0x1400>;
4350
4351                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4352                         clock-names = "xo", "alternate";
4353
4354                         #interconnect-cells = <1>;
4355                 };
4356
4357                 cpufreq_hw: cpufreq@18323000 {
4358                         compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4359                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4360                               <0 0x18327800 0 0x1400>;
4361                         reg-names = "freq-domain0", "freq-domain1",
4362                                     "freq-domain2";
4363
4364                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4365                         clock-names = "xo", "alternate";
4366
4367                         #freq-domain-cells = <1>;
4368                         #clock-cells = <1>;
4369                 };
4370
4371                 lmh_cluster1: lmh@18350800 {
4372                         compatible = "qcom,sm8150-lmh";
4373                         reg = <0 0x18350800 0 0x400>;
4374                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4375                         cpus = <&CPU4>;
4376                         qcom,lmh-temp-arm-millicelsius = <60000>;
4377                         qcom,lmh-temp-low-millicelsius = <84500>;
4378                         qcom,lmh-temp-high-millicelsius = <85000>;
4379                         interrupt-controller;
4380                         #interrupt-cells = <1>;
4381                 };
4382
4383                 lmh_cluster0: lmh@18358800 {
4384                         compatible = "qcom,sm8150-lmh";
4385                         reg = <0 0x18358800 0 0x400>;
4386                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4387                         cpus = <&CPU0>;
4388                         qcom,lmh-temp-arm-millicelsius = <60000>;
4389                         qcom,lmh-temp-low-millicelsius = <84500>;
4390                         qcom,lmh-temp-high-millicelsius = <85000>;
4391                         interrupt-controller;
4392                         #interrupt-cells = <1>;
4393                 };
4394
4395                 wifi: wifi@18800000 {
4396                         compatible = "qcom,wcn3990-wifi";
4397                         reg = <0 0x18800000 0 0x800000>;
4398                         reg-names = "membase";
4399                         memory-region = <&wlan_mem>;
4400                         clock-names = "cxo_ref_clk_pin", "qdss";
4401                         clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4402                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4403                                      <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4404                                      <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4405                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4406                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4407                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4408                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4409                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4410                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4411                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4412                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4413                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4414                         iommus = <&apps_smmu 0x0640 0x1>;
4415                         status = "disabled";
4416                 };
4417         };
4418
4419         timer {
4420                 compatible = "arm,armv8-timer";
4421                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4422                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4423                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4424                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4425         };
4426
4427         thermal-zones {
4428                 cpu0-thermal {
4429                         polling-delay-passive = <250>;
4430                         polling-delay = <1000>;
4431
4432                         thermal-sensors = <&tsens0 1>;
4433
4434                         trips {
4435                                 cpu0_alert0: trip-point0 {
4436                                         temperature = <90000>;
4437                                         hysteresis = <2000>;
4438                                         type = "passive";
4439                                 };
4440
4441                                 cpu0_alert1: trip-point1 {
4442                                         temperature = <95000>;
4443                                         hysteresis = <2000>;
4444                                         type = "passive";
4445                                 };
4446
4447                                 cpu0_crit: cpu-crit {
4448                                         temperature = <110000>;
4449                                         hysteresis = <1000>;
4450                                         type = "critical";
4451                                 };
4452                         };
4453
4454                         cooling-maps {
4455                                 map0 {
4456                                         trip = <&cpu0_alert0>;
4457                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4458                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4459                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4460                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4461                                 };
4462                                 map1 {
4463                                         trip = <&cpu0_alert1>;
4464                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4465                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4466                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4467                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4468                                 };
4469                         };
4470                 };
4471
4472                 cpu1-thermal {
4473                         polling-delay-passive = <250>;
4474                         polling-delay = <1000>;
4475
4476                         thermal-sensors = <&tsens0 2>;
4477
4478                         trips {
4479                                 cpu1_alert0: trip-point0 {
4480                                         temperature = <90000>;
4481                                         hysteresis = <2000>;
4482                                         type = "passive";
4483                                 };
4484
4485                                 cpu1_alert1: trip-point1 {
4486                                         temperature = <95000>;
4487                                         hysteresis = <2000>;
4488                                         type = "passive";
4489                                 };
4490
4491                                 cpu1_crit: cpu-crit {
4492                                         temperature = <110000>;
4493                                         hysteresis = <1000>;
4494                                         type = "critical";
4495                                 };
4496                         };
4497
4498                         cooling-maps {
4499                                 map0 {
4500                                         trip = <&cpu1_alert0>;
4501                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4502                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4503                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4504                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4505                                 };
4506                                 map1 {
4507                                         trip = <&cpu1_alert1>;
4508                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4509                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4510                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4511                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4512                                 };
4513                         };
4514                 };
4515
4516                 cpu2-thermal {
4517                         polling-delay-passive = <250>;
4518                         polling-delay = <1000>;
4519
4520                         thermal-sensors = <&tsens0 3>;
4521
4522                         trips {
4523                                 cpu2_alert0: trip-point0 {
4524                                         temperature = <90000>;
4525                                         hysteresis = <2000>;
4526                                         type = "passive";
4527                                 };
4528
4529                                 cpu2_alert1: trip-point1 {
4530                                         temperature = <95000>;
4531                                         hysteresis = <2000>;
4532                                         type = "passive";
4533                                 };
4534
4535                                 cpu2_crit: cpu-crit {
4536                                         temperature = <110000>;
4537                                         hysteresis = <1000>;
4538                                         type = "critical";
4539                                 };
4540                         };
4541
4542                         cooling-maps {
4543                                 map0 {
4544                                         trip = <&cpu2_alert0>;
4545                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4546                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4547                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4548                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4549                                 };
4550                                 map1 {
4551                                         trip = <&cpu2_alert1>;
4552                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4553                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4554                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4555                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4556                                 };
4557                         };
4558                 };
4559
4560                 cpu3-thermal {
4561                         polling-delay-passive = <250>;
4562                         polling-delay = <1000>;
4563
4564                         thermal-sensors = <&tsens0 4>;
4565
4566                         trips {
4567                                 cpu3_alert0: trip-point0 {
4568                                         temperature = <90000>;
4569                                         hysteresis = <2000>;
4570                                         type = "passive";
4571                                 };
4572
4573                                 cpu3_alert1: trip-point1 {
4574                                         temperature = <95000>;
4575                                         hysteresis = <2000>;
4576                                         type = "passive";
4577                                 };
4578
4579                                 cpu3_crit: cpu-crit {
4580                                         temperature = <110000>;
4581                                         hysteresis = <1000>;
4582                                         type = "critical";
4583                                 };
4584                         };
4585
4586                         cooling-maps {
4587                                 map0 {
4588                                         trip = <&cpu3_alert0>;
4589                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4590                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4591                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4592                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4593                                 };
4594                                 map1 {
4595                                         trip = <&cpu3_alert1>;
4596                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4597                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4598                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4599                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4600                                 };
4601                         };
4602                 };
4603
4604                 cpu4-top-thermal {
4605                         polling-delay-passive = <250>;
4606                         polling-delay = <1000>;
4607
4608                         thermal-sensors = <&tsens0 7>;
4609
4610                         trips {
4611                                 cpu4_top_alert0: trip-point0 {
4612                                         temperature = <90000>;
4613                                         hysteresis = <2000>;
4614                                         type = "passive";
4615                                 };
4616
4617                                 cpu4_top_alert1: trip-point1 {
4618                                         temperature = <95000>;
4619                                         hysteresis = <2000>;
4620                                         type = "passive";
4621                                 };
4622
4623                                 cpu4_top_crit: cpu-crit {
4624                                         temperature = <110000>;
4625                                         hysteresis = <1000>;
4626                                         type = "critical";
4627                                 };
4628                         };
4629
4630                         cooling-maps {
4631                                 map0 {
4632                                         trip = <&cpu4_top_alert0>;
4633                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4634                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4635                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4636                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4637                                 };
4638                                 map1 {
4639                                         trip = <&cpu4_top_alert1>;
4640                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4641                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4642                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4643                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4644                                 };
4645                         };
4646                 };
4647
4648                 cpu5-top-thermal {
4649                         polling-delay-passive = <250>;
4650                         polling-delay = <1000>;
4651
4652                         thermal-sensors = <&tsens0 8>;
4653
4654                         trips {
4655                                 cpu5_top_alert0: trip-point0 {
4656                                         temperature = <90000>;
4657                                         hysteresis = <2000>;
4658                                         type = "passive";
4659                                 };
4660
4661                                 cpu5_top_alert1: trip-point1 {
4662                                         temperature = <95000>;
4663                                         hysteresis = <2000>;
4664                                         type = "passive";
4665                                 };
4666
4667                                 cpu5_top_crit: cpu-crit {
4668                                         temperature = <110000>;
4669                                         hysteresis = <1000>;
4670                                         type = "critical";
4671                                 };
4672                         };
4673
4674                         cooling-maps {
4675                                 map0 {
4676                                         trip = <&cpu5_top_alert0>;
4677                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4678                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4679                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4680                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4681                                 };
4682                                 map1 {
4683                                         trip = <&cpu5_top_alert1>;
4684                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4685                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4686                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4687                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4688                                 };
4689                         };
4690                 };
4691
4692                 cpu6-top-thermal {
4693                         polling-delay-passive = <250>;
4694                         polling-delay = <1000>;
4695
4696                         thermal-sensors = <&tsens0 9>;
4697
4698                         trips {
4699                                 cpu6_top_alert0: trip-point0 {
4700                                         temperature = <90000>;
4701                                         hysteresis = <2000>;
4702                                         type = "passive";
4703                                 };
4704
4705                                 cpu6_top_alert1: trip-point1 {
4706                                         temperature = <95000>;
4707                                         hysteresis = <2000>;
4708                                         type = "passive";
4709                                 };
4710
4711                                 cpu6_top_crit: cpu-crit {
4712                                         temperature = <110000>;
4713                                         hysteresis = <1000>;
4714                                         type = "critical";
4715                                 };
4716                         };
4717
4718                         cooling-maps {
4719                                 map0 {
4720                                         trip = <&cpu6_top_alert0>;
4721                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4722                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4723                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4725                                 };
4726                                 map1 {
4727                                         trip = <&cpu6_top_alert1>;
4728                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4729                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4730                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4732                                 };
4733                         };
4734                 };
4735
4736                 cpu7-top-thermal {
4737                         polling-delay-passive = <250>;
4738                         polling-delay = <1000>;
4739
4740                         thermal-sensors = <&tsens0 10>;
4741
4742                         trips {
4743                                 cpu7_top_alert0: trip-point0 {
4744                                         temperature = <90000>;
4745                                         hysteresis = <2000>;
4746                                         type = "passive";
4747                                 };
4748
4749                                 cpu7_top_alert1: trip-point1 {
4750                                         temperature = <95000>;
4751                                         hysteresis = <2000>;
4752                                         type = "passive";
4753                                 };
4754
4755                                 cpu7_top_crit: cpu-crit {
4756                                         temperature = <110000>;
4757                                         hysteresis = <1000>;
4758                                         type = "critical";
4759                                 };
4760                         };
4761
4762                         cooling-maps {
4763                                 map0 {
4764                                         trip = <&cpu7_top_alert0>;
4765                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4766                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4769                                 };
4770                                 map1 {
4771                                         trip = <&cpu7_top_alert1>;
4772                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4773                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4776                                 };
4777                         };
4778                 };
4779
4780                 cpu4-bottom-thermal {
4781                         polling-delay-passive = <250>;
4782                         polling-delay = <1000>;
4783
4784                         thermal-sensors = <&tsens0 11>;
4785
4786                         trips {
4787                                 cpu4_bottom_alert0: trip-point0 {
4788                                         temperature = <90000>;
4789                                         hysteresis = <2000>;
4790                                         type = "passive";
4791                                 };
4792
4793                                 cpu4_bottom_alert1: trip-point1 {
4794                                         temperature = <95000>;
4795                                         hysteresis = <2000>;
4796                                         type = "passive";
4797                                 };
4798
4799                                 cpu4_bottom_crit: cpu-crit {
4800                                         temperature = <110000>;
4801                                         hysteresis = <1000>;
4802                                         type = "critical";
4803                                 };
4804                         };
4805
4806                         cooling-maps {
4807                                 map0 {
4808                                         trip = <&cpu4_bottom_alert0>;
4809                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813                                 };
4814                                 map1 {
4815                                         trip = <&cpu4_bottom_alert1>;
4816                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820                                 };
4821                         };
4822                 };
4823
4824                 cpu5-bottom-thermal {
4825                         polling-delay-passive = <250>;
4826                         polling-delay = <1000>;
4827
4828                         thermal-sensors = <&tsens0 12>;
4829
4830                         trips {
4831                                 cpu5_bottom_alert0: trip-point0 {
4832                                         temperature = <90000>;
4833                                         hysteresis = <2000>;
4834                                         type = "passive";
4835                                 };
4836
4837                                 cpu5_bottom_alert1: trip-point1 {
4838                                         temperature = <95000>;
4839                                         hysteresis = <2000>;
4840                                         type = "passive";
4841                                 };
4842
4843                                 cpu5_bottom_crit: cpu-crit {
4844                                         temperature = <110000>;
4845                                         hysteresis = <1000>;
4846                                         type = "critical";
4847                                 };
4848                         };
4849
4850                         cooling-maps {
4851                                 map0 {
4852                                         trip = <&cpu5_bottom_alert0>;
4853                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4856                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4857                                 };
4858                                 map1 {
4859                                         trip = <&cpu5_bottom_alert1>;
4860                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4863                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4864                                 };
4865                         };
4866                 };
4867
4868                 cpu6-bottom-thermal {
4869                         polling-delay-passive = <250>;
4870                         polling-delay = <1000>;
4871
4872                         thermal-sensors = <&tsens0 13>;
4873
4874                         trips {
4875                                 cpu6_bottom_alert0: trip-point0 {
4876                                         temperature = <90000>;
4877                                         hysteresis = <2000>;
4878                                         type = "passive";
4879                                 };
4880
4881                                 cpu6_bottom_alert1: trip-point1 {
4882                                         temperature = <95000>;
4883                                         hysteresis = <2000>;
4884                                         type = "passive";
4885                                 };
4886
4887                                 cpu6_bottom_crit: cpu-crit {
4888                                         temperature = <110000>;
4889                                         hysteresis = <1000>;
4890                                         type = "critical";
4891                                 };
4892                         };
4893
4894                         cooling-maps {
4895                                 map0 {
4896                                         trip = <&cpu6_bottom_alert0>;
4897                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4899                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4900                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4901                                 };
4902                                 map1 {
4903                                         trip = <&cpu6_bottom_alert1>;
4904                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4906                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4907                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4908                                 };
4909                         };
4910                 };
4911
4912                 cpu7-bottom-thermal {
4913                         polling-delay-passive = <250>;
4914                         polling-delay = <1000>;
4915
4916                         thermal-sensors = <&tsens0 14>;
4917
4918                         trips {
4919                                 cpu7_bottom_alert0: trip-point0 {
4920                                         temperature = <90000>;
4921                                         hysteresis = <2000>;
4922                                         type = "passive";
4923                                 };
4924
4925                                 cpu7_bottom_alert1: trip-point1 {
4926                                         temperature = <95000>;
4927                                         hysteresis = <2000>;
4928                                         type = "passive";
4929                                 };
4930
4931                                 cpu7_bottom_crit: cpu-crit {
4932                                         temperature = <110000>;
4933                                         hysteresis = <1000>;
4934                                         type = "critical";
4935                                 };
4936                         };
4937
4938                         cooling-maps {
4939                                 map0 {
4940                                         trip = <&cpu7_bottom_alert0>;
4941                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4942                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4943                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4944                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4945                                 };
4946                                 map1 {
4947                                         trip = <&cpu7_bottom_alert1>;
4948                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4949                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4950                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4951                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4952                                 };
4953                         };
4954                 };
4955
4956                 aoss0-thermal {
4957                         polling-delay-passive = <250>;
4958                         polling-delay = <1000>;
4959
4960                         thermal-sensors = <&tsens0 0>;
4961
4962                         trips {
4963                                 aoss0_alert0: trip-point0 {
4964                                         temperature = <90000>;
4965                                         hysteresis = <2000>;
4966                                         type = "hot";
4967                                 };
4968                         };
4969                 };
4970
4971                 cluster0-thermal {
4972                         polling-delay-passive = <250>;
4973                         polling-delay = <1000>;
4974
4975                         thermal-sensors = <&tsens0 5>;
4976
4977                         trips {
4978                                 cluster0_alert0: trip-point0 {
4979                                         temperature = <90000>;
4980                                         hysteresis = <2000>;
4981                                         type = "hot";
4982                                 };
4983                                 cluster0_crit: cluster0_crit {
4984                                         temperature = <110000>;
4985                                         hysteresis = <2000>;
4986                                         type = "critical";
4987                                 };
4988                         };
4989                 };
4990
4991                 cluster1-thermal {
4992                         polling-delay-passive = <250>;
4993                         polling-delay = <1000>;
4994
4995                         thermal-sensors = <&tsens0 6>;
4996
4997                         trips {
4998                                 cluster1_alert0: trip-point0 {
4999                                         temperature = <90000>;
5000                                         hysteresis = <2000>;
5001                                         type = "hot";
5002                                 };
5003                                 cluster1_crit: cluster1_crit {
5004                                         temperature = <110000>;
5005                                         hysteresis = <2000>;
5006                                         type = "critical";
5007                                 };
5008                         };
5009                 };
5010
5011                 gpu-top-thermal {
5012                         polling-delay-passive = <250>;
5013                         polling-delay = <1000>;
5014
5015                         thermal-sensors = <&tsens0 15>;
5016
5017                         trips {
5018                                 gpu1_alert0: trip-point0 {
5019                                         temperature = <90000>;
5020                                         hysteresis = <2000>;
5021                                         type = "hot";
5022                                 };
5023                         };
5024                 };
5025
5026                 aoss1-thermal {
5027                         polling-delay-passive = <250>;
5028                         polling-delay = <1000>;
5029
5030                         thermal-sensors = <&tsens1 0>;
5031
5032                         trips {
5033                                 aoss1_alert0: trip-point0 {
5034                                         temperature = <90000>;
5035                                         hysteresis = <2000>;
5036                                         type = "hot";
5037                                 };
5038                         };
5039                 };
5040
5041                 wlan-thermal {
5042                         polling-delay-passive = <250>;
5043                         polling-delay = <1000>;
5044
5045                         thermal-sensors = <&tsens1 1>;
5046
5047                         trips {
5048                                 wlan_alert0: trip-point0 {
5049                                         temperature = <90000>;
5050                                         hysteresis = <2000>;
5051                                         type = "hot";
5052                                 };
5053                         };
5054                 };
5055
5056                 video-thermal {
5057                         polling-delay-passive = <250>;
5058                         polling-delay = <1000>;
5059
5060                         thermal-sensors = <&tsens1 2>;
5061
5062                         trips {
5063                                 video_alert0: trip-point0 {
5064                                         temperature = <90000>;
5065                                         hysteresis = <2000>;
5066                                         type = "hot";
5067                                 };
5068                         };
5069                 };
5070
5071                 mem-thermal {
5072                         polling-delay-passive = <250>;
5073                         polling-delay = <1000>;
5074
5075                         thermal-sensors = <&tsens1 3>;
5076
5077                         trips {
5078                                 mem_alert0: trip-point0 {
5079                                         temperature = <90000>;
5080                                         hysteresis = <2000>;
5081                                         type = "hot";
5082                                 };
5083                         };
5084                 };
5085
5086                 q6-hvx-thermal {
5087                         polling-delay-passive = <250>;
5088                         polling-delay = <1000>;
5089
5090                         thermal-sensors = <&tsens1 4>;
5091
5092                         trips {
5093                                 q6_hvx_alert0: trip-point0 {
5094                                         temperature = <90000>;
5095                                         hysteresis = <2000>;
5096                                         type = "hot";
5097                                 };
5098                         };
5099                 };
5100
5101                 camera-thermal {
5102                         polling-delay-passive = <250>;
5103                         polling-delay = <1000>;
5104
5105                         thermal-sensors = <&tsens1 5>;
5106
5107                         trips {
5108                                 camera_alert0: trip-point0 {
5109                                         temperature = <90000>;
5110                                         hysteresis = <2000>;
5111                                         type = "hot";
5112                                 };
5113                         };
5114                 };
5115
5116                 compute-thermal {
5117                         polling-delay-passive = <250>;
5118                         polling-delay = <1000>;
5119
5120                         thermal-sensors = <&tsens1 6>;
5121
5122                         trips {
5123                                 compute_alert0: trip-point0 {
5124                                         temperature = <90000>;
5125                                         hysteresis = <2000>;
5126                                         type = "hot";
5127                                 };
5128                         };
5129                 };
5130
5131                 modem-thermal {
5132                         polling-delay-passive = <250>;
5133                         polling-delay = <1000>;
5134
5135                         thermal-sensors = <&tsens1 7>;
5136
5137                         trips {
5138                                 modem_alert0: trip-point0 {
5139                                         temperature = <90000>;
5140                                         hysteresis = <2000>;
5141                                         type = "hot";
5142                                 };
5143                         };
5144                 };
5145
5146                 npu-thermal {
5147                         polling-delay-passive = <250>;
5148                         polling-delay = <1000>;
5149
5150                         thermal-sensors = <&tsens1 8>;
5151
5152                         trips {
5153                                 npu_alert0: trip-point0 {
5154                                         temperature = <90000>;
5155                                         hysteresis = <2000>;
5156                                         type = "hot";
5157                                 };
5158                         };
5159                 };
5160
5161                 modem-vec-thermal {
5162                         polling-delay-passive = <250>;
5163                         polling-delay = <1000>;
5164
5165                         thermal-sensors = <&tsens1 9>;
5166
5167                         trips {
5168                                 modem_vec_alert0: trip-point0 {
5169                                         temperature = <90000>;
5170                                         hysteresis = <2000>;
5171                                         type = "hot";
5172                                 };
5173                         };
5174                 };
5175
5176                 modem-scl-thermal {
5177                         polling-delay-passive = <250>;
5178                         polling-delay = <1000>;
5179
5180                         thermal-sensors = <&tsens1 10>;
5181
5182                         trips {
5183                                 modem_scl_alert0: trip-point0 {
5184                                         temperature = <90000>;
5185                                         hysteresis = <2000>;
5186                                         type = "hot";
5187                                 };
5188                         };
5189                 };
5190
5191                 gpu-bottom-thermal {
5192                         polling-delay-passive = <250>;
5193                         polling-delay = <1000>;
5194
5195                         thermal-sensors = <&tsens1 11>;
5196
5197                         trips {
5198                                 gpu2_alert0: trip-point0 {
5199                                         temperature = <90000>;
5200                                         hysteresis = <2000>;
5201                                         type = "hot";
5202                                 };
5203                         };
5204                 };
5205         };
5206 };