1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
26 compatible = "fixed-clock";
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
42 compatible = "qcom,kryo260";
44 clocks = <&cpufreq_hw 0>;
45 capacity-dmips-mhz = <1024>;
46 dynamic-power-coefficient = <100>;
47 enable-method = "psci";
48 next-level-cache = <&L2_0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
50 power-domains = <&CPU_PD0>;
51 power-domain-names = "psci";
61 compatible = "qcom,kryo260";
63 clocks = <&cpufreq_hw 0>;
64 capacity-dmips-mhz = <1024>;
65 dynamic-power-coefficient = <100>;
66 enable-method = "psci";
67 next-level-cache = <&L2_0>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
69 power-domains = <&CPU_PD1>;
70 power-domain-names = "psci";
75 compatible = "qcom,kryo260";
77 clocks = <&cpufreq_hw 0>;
78 capacity-dmips-mhz = <1024>;
79 dynamic-power-coefficient = <100>;
80 enable-method = "psci";
81 next-level-cache = <&L2_0>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
83 power-domains = <&CPU_PD2>;
84 power-domain-names = "psci";
89 compatible = "qcom,kryo260";
91 clocks = <&cpufreq_hw 0>;
92 capacity-dmips-mhz = <1024>;
93 dynamic-power-coefficient = <100>;
94 enable-method = "psci";
95 next-level-cache = <&L2_0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
97 power-domains = <&CPU_PD3>;
98 power-domain-names = "psci";
103 compatible = "qcom,kryo260";
105 clocks = <&cpufreq_hw 1>;
106 enable-method = "psci";
107 capacity-dmips-mhz = <1638>;
108 dynamic-power-coefficient = <282>;
109 next-level-cache = <&L2_1>;
110 qcom,freq-domain = <&cpufreq_hw 1>;
111 power-domains = <&CPU_PD4>;
112 power-domain-names = "psci";
114 compatible = "cache";
122 compatible = "qcom,kryo260";
124 clocks = <&cpufreq_hw 1>;
125 capacity-dmips-mhz = <1638>;
126 dynamic-power-coefficient = <282>;
127 enable-method = "psci";
128 next-level-cache = <&L2_1>;
129 qcom,freq-domain = <&cpufreq_hw 1>;
130 power-domains = <&CPU_PD5>;
131 power-domain-names = "psci";
136 compatible = "qcom,kryo260";
138 clocks = <&cpufreq_hw 1>;
139 capacity-dmips-mhz = <1638>;
140 dynamic-power-coefficient = <282>;
141 enable-method = "psci";
142 next-level-cache = <&L2_1>;
143 qcom,freq-domain = <&cpufreq_hw 1>;
144 power-domains = <&CPU_PD6>;
145 power-domain-names = "psci";
150 compatible = "qcom,kryo260";
152 clocks = <&cpufreq_hw 1>;
153 capacity-dmips-mhz = <1638>;
154 dynamic-power-coefficient = <282>;
155 enable-method = "psci";
156 next-level-cache = <&L2_1>;
157 qcom,freq-domain = <&cpufreq_hw 1>;
158 power-domains = <&CPU_PD7>;
159 power-domain-names = "psci";
201 entry-method = "psci";
203 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
204 compatible = "arm,idle-state";
205 idle-state-name = "silver-rail-power-collapse";
206 arm,psci-suspend-param = <0x40000003>;
207 entry-latency-us = <290>;
208 exit-latency-us = <376>;
209 min-residency-us = <1182>;
213 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
214 compatible = "arm,idle-state";
215 idle-state-name = "gold-rail-power-collapse";
216 arm,psci-suspend-param = <0x40000003>;
217 entry-latency-us = <297>;
218 exit-latency-us = <324>;
219 min-residency-us = <1110>;
225 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
227 compatible = "domain-idle-state";
228 arm,psci-suspend-param = <0x40000022>;
229 entry-latency-us = <360>;
230 exit-latency-us = <421>;
231 min-residency-us = <782>;
234 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
236 compatible = "domain-idle-state";
237 arm,psci-suspend-param = <0x41000044>;
238 entry-latency-us = <800>;
239 exit-latency-us = <2118>;
240 min-residency-us = <7376>;
243 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
245 compatible = "domain-idle-state";
246 arm,psci-suspend-param = <0x40000042>;
247 entry-latency-us = <314>;
248 exit-latency-us = <345>;
249 min-residency-us = <660>;
252 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 {
254 compatible = "domain-idle-state";
255 arm,psci-suspend-param = <0x41000044>;
256 entry-latency-us = <640>;
257 exit-latency-us = <1654>;
258 min-residency-us = <8094>;
265 compatible = "qcom,scm-sm6115", "qcom,scm";
271 device_type = "memory";
272 /* We expect the bootloader to fill in the size */
273 reg = <0 0x80000000 0 0>;
277 compatible = "arm,armv8-pmuv3";
278 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
282 compatible = "arm,psci-1.0";
285 CPU_PD0: power-domain-cpu0 {
286 #power-domain-cells = <0>;
287 power-domains = <&CLUSTER_0_PD>;
288 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
291 CPU_PD1: power-domain-cpu1 {
292 #power-domain-cells = <0>;
293 power-domains = <&CLUSTER_0_PD>;
294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
297 CPU_PD2: power-domain-cpu2 {
298 #power-domain-cells = <0>;
299 power-domains = <&CLUSTER_0_PD>;
300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
303 CPU_PD3: power-domain-cpu3 {
304 #power-domain-cells = <0>;
305 power-domains = <&CLUSTER_0_PD>;
306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
309 CPU_PD4: power-domain-cpu4 {
310 #power-domain-cells = <0>;
311 power-domains = <&CLUSTER_1_PD>;
312 domain-idle-states = <&BIG_CPU_SLEEP_0>;
315 CPU_PD5: power-domain-cpu5 {
316 #power-domain-cells = <0>;
317 power-domains = <&CLUSTER_1_PD>;
318 domain-idle-states = <&BIG_CPU_SLEEP_0>;
321 CPU_PD6: power-domain-cpu6 {
322 #power-domain-cells = <0>;
323 power-domains = <&CLUSTER_1_PD>;
324 domain-idle-states = <&BIG_CPU_SLEEP_0>;
327 CPU_PD7: power-domain-cpu7 {
328 #power-domain-cells = <0>;
329 power-domains = <&CLUSTER_1_PD>;
330 domain-idle-states = <&BIG_CPU_SLEEP_0>;
333 CLUSTER_0_PD: power-domain-cpu-cluster0 {
334 #power-domain-cells = <0>;
335 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>;
338 CLUSTER_1_PD: power-domain-cpu-cluster1 {
339 #power-domain-cells = <0>;
340 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>;
344 reserved_memory: reserved-memory {
345 #address-cells = <2>;
349 hyp_mem: memory@45700000 {
350 reg = <0x0 0x45700000 0x0 0x600000>;
354 xbl_aop_mem: memory@45e00000 {
355 reg = <0x0 0x45e00000 0x0 0x140000>;
359 sec_apps_mem: memory@45fff000 {
360 reg = <0x0 0x45fff000 0x0 0x1000>;
364 smem_mem: memory@46000000 {
365 compatible = "qcom,smem";
366 reg = <0x0 0x46000000 0x0 0x200000>;
369 hwlocks = <&tcsr_mutex 3>;
370 qcom,rpm-msg-ram = <&rpm_msg_ram>;
373 cdsp_sec_mem: memory@46200000 {
374 reg = <0x0 0x46200000 0x0 0x1e00000>;
378 pil_modem_mem: memory@4ab00000 {
379 reg = <0x0 0x4ab00000 0x0 0x6900000>;
383 pil_video_mem: memory@51400000 {
384 reg = <0x0 0x51400000 0x0 0x500000>;
388 wlan_msa_mem: memory@51900000 {
389 reg = <0x0 0x51900000 0x0 0x100000>;
393 pil_cdsp_mem: memory@51a00000 {
394 reg = <0x0 0x51a00000 0x0 0x1e00000>;
398 pil_adsp_mem: memory@53800000 {
399 reg = <0x0 0x53800000 0x0 0x2800000>;
403 pil_ipa_fw_mem: memory@56100000 {
404 reg = <0x0 0x56100000 0x0 0x10000>;
408 pil_ipa_gsi_mem: memory@56110000 {
409 reg = <0x0 0x56110000 0x0 0x5000>;
413 pil_gpu_mem: memory@56115000 {
414 reg = <0x0 0x56115000 0x0 0x2000>;
418 cont_splash_memory: memory@5c000000 {
419 reg = <0x0 0x5c000000 0x0 0x00f00000>;
423 dfps_data_memory: memory@5cf00000 {
424 reg = <0x0 0x5cf00000 0x0 0x0100000>;
428 removed_mem: memory@60000000 {
429 reg = <0x0 0x60000000 0x0 0x3900000>;
433 rmtfs_mem: memory@89b01000 {
434 compatible = "qcom,rmtfs-mem";
435 reg = <0x0 0x89b01000 0x0 0x200000>;
438 qcom,client-id = <1>;
439 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
444 compatible = "qcom,glink-rpm";
446 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
447 qcom,rpm-msg-ram = <&rpm_msg_ram>;
448 mboxes = <&apcs_glb 0>;
450 rpm_requests: rpm-requests {
451 compatible = "qcom,rpm-sm6115";
452 qcom,glink-channels = "rpm_requests";
454 rpmcc: clock-controller {
455 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
456 clocks = <&xo_board>;
461 rpmpd: power-controller {
462 compatible = "qcom,sm6115-rpmpd";
463 #power-domain-cells = <1>;
464 operating-points-v2 = <&rpmpd_opp_table>;
466 rpmpd_opp_table: opp-table {
467 compatible = "operating-points-v2";
469 rpmpd_opp_min_svs: opp1 {
470 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
473 rpmpd_opp_low_svs: opp2 {
474 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
477 rpmpd_opp_svs: opp3 {
478 opp-level = <RPM_SMD_LEVEL_SVS>;
481 rpmpd_opp_svs_plus: opp4 {
482 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
485 rpmpd_opp_nom: opp5 {
486 opp-level = <RPM_SMD_LEVEL_NOM>;
489 rpmpd_opp_nom_plus: opp6 {
490 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
493 rpmpd_opp_turbo: opp7 {
494 opp-level = <RPM_SMD_LEVEL_TURBO>;
497 rpmpd_opp_turbo_plus: opp8 {
498 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
506 compatible = "qcom,smp2p";
507 qcom,smem = <443>, <429>;
509 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
511 mboxes = <&apcs_glb 10>;
513 qcom,local-pid = <0>;
514 qcom,remote-pid = <2>;
516 adsp_smp2p_out: master-kernel {
517 qcom,entry-name = "master-kernel";
518 #qcom,smem-state-cells = <1>;
521 adsp_smp2p_in: slave-kernel {
522 qcom,entry-name = "slave-kernel";
524 interrupt-controller;
525 #interrupt-cells = <2>;
530 compatible = "qcom,smp2p";
531 qcom,smem = <94>, <432>;
533 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
535 mboxes = <&apcs_glb 30>;
537 qcom,local-pid = <0>;
538 qcom,remote-pid = <5>;
540 cdsp_smp2p_out: master-kernel {
541 qcom,entry-name = "master-kernel";
542 #qcom,smem-state-cells = <1>;
545 cdsp_smp2p_in: slave-kernel {
546 qcom,entry-name = "slave-kernel";
548 interrupt-controller;
549 #interrupt-cells = <2>;
554 compatible = "qcom,smp2p";
555 qcom,smem = <435>, <428>;
557 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
559 mboxes = <&apcs_glb 14>;
561 qcom,local-pid = <0>;
562 qcom,remote-pid = <1>;
564 modem_smp2p_out: master-kernel {
565 qcom,entry-name = "master-kernel";
566 #qcom,smem-state-cells = <1>;
569 modem_smp2p_in: slave-kernel {
570 qcom,entry-name = "slave-kernel";
572 interrupt-controller;
573 #interrupt-cells = <2>;
578 compatible = "simple-bus";
579 #address-cells = <2>;
581 ranges = <0 0 0 0 0x10 0>;
582 dma-ranges = <0 0 0 0 0x10 0>;
584 tcsr_mutex: hwlock@340000 {
585 compatible = "qcom,tcsr-mutex";
586 reg = <0x0 0x00340000 0x0 0x20000>;
590 tlmm: pinctrl@500000 {
591 compatible = "qcom,sm6115-tlmm";
592 reg = <0x0 0x00500000 0x0 0x400000>,
593 <0x0 0x00900000 0x0 0x400000>,
594 <0x0 0x00d00000 0x0 0x400000>;
595 reg-names = "west", "south", "east";
596 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
598 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
600 interrupt-controller;
601 #interrupt-cells = <2>;
603 qup_i2c0_default: qup-i2c0-default-state {
604 pins = "gpio0", "gpio1";
606 drive-strength = <2>;
610 qup_i2c1_default: qup-i2c1-default-state {
611 pins = "gpio4", "gpio5";
613 drive-strength = <2>;
617 qup_i2c2_default: qup-i2c2-default-state {
618 pins = "gpio6", "gpio7";
620 drive-strength = <2>;
624 qup_i2c3_default: qup-i2c3-default-state {
625 pins = "gpio8", "gpio9";
627 drive-strength = <2>;
631 qup_i2c4_default: qup-i2c4-default-state {
632 pins = "gpio12", "gpio13";
634 drive-strength = <2>;
638 qup_i2c5_default: qup-i2c5-default-state {
639 pins = "gpio14", "gpio15";
641 drive-strength = <2>;
645 qup_spi0_default: qup-spi0-default-state {
646 pins = "gpio0", "gpio1","gpio2", "gpio3";
648 drive-strength = <2>;
652 qup_spi1_default: qup-spi1-default-state {
653 pins = "gpio4", "gpio5", "gpio69", "gpio70";
655 drive-strength = <2>;
659 qup_spi2_default: qup-spi2-default-state {
660 pins = "gpio6", "gpio7", "gpio71", "gpio80";
662 drive-strength = <2>;
666 qup_spi3_default: qup-spi3-default-state {
667 pins = "gpio8", "gpio9", "gpio10", "gpio11";
669 drive-strength = <2>;
673 qup_spi4_default: qup-spi4-default-state {
674 pins = "gpio12", "gpio13", "gpio96", "gpio97";
676 drive-strength = <2>;
680 qup_spi5_default: qup-spi5-default-state {
681 pins = "gpio14", "gpio15", "gpio16", "gpio17";
683 drive-strength = <2>;
687 sdc1_state_on: sdc1-on-state {
691 drive-strength = <16>;
697 drive-strength = <10>;
703 drive-strength = <10>;
712 sdc1_state_off: sdc1-off-state {
716 drive-strength = <2>;
722 drive-strength = <2>;
728 drive-strength = <2>;
737 sdc2_state_on: sdc2-on-state {
741 drive-strength = <16>;
747 drive-strength = <10>;
753 drive-strength = <10>;
757 sdc2_state_off: sdc2-off-state {
761 drive-strength = <2>;
767 drive-strength = <2>;
773 drive-strength = <2>;
778 gcc: clock-controller@1400000 {
779 compatible = "qcom,gcc-sm6115";
780 reg = <0x0 0x01400000 0x0 0x1f0000>;
781 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
782 clock-names = "bi_tcxo", "sleep_clk";
785 #power-domain-cells = <1>;
788 usb_hsphy: phy@1613000 {
789 compatible = "qcom,sm6115-qusb2-phy";
790 reg = <0x0 0x01613000 0x0 0x180>;
793 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
794 clock-names = "cfg_ahb", "ref";
796 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
797 nvmem-cells = <&qusb2_hstx_trim>;
802 cryptobam: dma-controller@1b04000 {
803 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
804 reg = <0x0 0x01b04000 0x0 0x24000>;
805 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&rpmcc RPM_SMD_CE1_CLK>;
807 clock-names = "bam_clk";
810 qcom,controlled-remotely;
811 iommus = <&apps_smmu 0x92 0>,
812 <&apps_smmu 0x94 0x11>,
813 <&apps_smmu 0x96 0x11>,
814 <&apps_smmu 0x98 0x1>,
818 crypto: crypto@1b3a000 {
819 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
820 reg = <0x0 0x01b3a000 0x0 0x6000>;
821 clocks = <&rpmcc RPM_SMD_CE1_CLK>;
822 clock-names = "core";
824 dmas = <&cryptobam 6>, <&cryptobam 7>;
825 dma-names = "rx", "tx";
826 iommus = <&apps_smmu 0x92 0>,
827 <&apps_smmu 0x94 0x11>,
828 <&apps_smmu 0x96 0x11>,
829 <&apps_smmu 0x98 0x1>,
833 usb_qmpphy: phy@1615000 {
834 compatible = "qcom,sm6115-qmp-usb3-phy";
835 reg = <0x0 0x01615000 0x0 0x1000>;
837 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
838 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
839 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
840 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
841 clock-names = "cfg_ahb",
846 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
847 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
848 reset-names = "phy", "phy_phy";
851 clock-output-names = "usb3_phy_pipe_clk_src";
859 compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
860 reg = <0x0 0x01b40000 0x0 0x7000>;
861 #address-cells = <1>;
864 qusb2_hstx_trim: hstx-trim@25b {
871 compatible = "qcom,prng-ee";
872 reg = <0x0 0x01b53000 0x0 0x1000>;
873 clocks = <&gcc GCC_PRNG_AHB_CLK>;
874 clock-names = "core";
877 spmi_bus: spmi@1c40000 {
878 compatible = "qcom,spmi-pmic-arb";
879 reg = <0x0 0x01c40000 0x0 0x1100>,
880 <0x0 0x01e00000 0x0 0x2000000>,
881 <0x0 0x03e00000 0x0 0x100000>,
882 <0x0 0x03f00000 0x0 0xa0000>,
883 <0x0 0x01c0a000 0x0 0x26000>;
884 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
885 interrupt-names = "periph_irq";
886 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
889 #address-cells = <2>;
891 interrupt-controller;
892 #interrupt-cells = <4>;
895 tsens0: thermal-sensor@4411000 {
896 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
897 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */
898 <0x0 0x04410000 0x0 0x8>; /* SROT */
899 #qcom,sensors = <16>;
900 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
902 interrupt-names = "uplow", "critical";
903 #thermal-sensor-cells = <1>;
906 rpm_msg_ram: sram@45f0000 {
907 compatible = "qcom,rpm-msg-ram";
908 reg = <0x0 0x045f0000 0x0 0x7000>;
912 compatible = "qcom,rpm-stats";
913 reg = <0x0 0x04690000 0x0 0x10000>;
916 sdhc_1: mmc@4744000 {
917 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
918 reg = <0x0 0x04744000 0x0 0x1000>,
919 <0x0 0x04745000 0x0 0x1000>,
920 <0x0 0x04748000 0x0 0x8000>;
921 reg-names = "hc", "cqhci", "ice";
923 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
925 interrupt-names = "hc_irq", "pwr_irq";
927 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
928 <&gcc GCC_SDCC1_APPS_CLK>,
929 <&rpmcc RPM_SMD_XO_CLK_SRC>,
930 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
931 clock-names = "iface", "core", "xo", "ice";
937 sdhc_2: mmc@4784000 {
938 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
939 reg = <0x0 0x04784000 0x0 0x1000>;
942 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
944 interrupt-names = "hc_irq", "pwr_irq";
946 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
947 <&gcc GCC_SDCC2_APPS_CLK>,
948 <&rpmcc RPM_SMD_XO_CLK_SRC>;
949 clock-names = "iface", "core", "xo";
951 power-domains = <&rpmpd SM6115_VDDCX>;
952 operating-points-v2 = <&sdhc2_opp_table>;
953 iommus = <&apps_smmu 0x00a0 0x0>;
954 resets = <&gcc GCC_SDCC2_BCR>;
957 qcom,dll-config = <0x0007642c>;
958 qcom,ddr-config = <0x80040868>;
961 sdhc2_opp_table: opp-table {
962 compatible = "operating-points-v2";
965 opp-hz = /bits/ 64 <100000000>;
966 required-opps = <&rpmpd_opp_low_svs>;
970 opp-hz = /bits/ 64 <202000000>;
971 required-opps = <&rpmpd_opp_nom>;
976 ufs_mem_hc: ufs@4804000 {
977 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
978 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
979 reg-names = "std", "ice";
980 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
981 phys = <&ufs_mem_phy_lanes>;
982 phy-names = "ufsphy";
983 lanes-per-direction = <1>;
985 resets = <&gcc GCC_UFS_PHY_BCR>;
988 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
989 iommus = <&apps_smmu 0x100 0>;
991 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
992 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
993 <&gcc GCC_UFS_PHY_AHB_CLK>,
994 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
995 <&rpmcc RPM_SMD_XO_CLK_SRC>,
996 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
997 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
998 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
999 clock-names = "core_clk",
1004 "tx_lane0_sync_clk",
1005 "rx_lane0_sync_clk",
1008 freq-table-hz = <50000000 200000000>,
1011 <37500000 150000000>,
1015 <75000000 300000000>;
1017 status = "disabled";
1020 ufs_mem_phy: phy@4807000 {
1021 compatible = "qcom,sm6115-qmp-ufs-phy";
1022 reg = <0x0 0x04807000 0x0 0x1c4>;
1023 #address-cells = <2>;
1027 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1028 clock-names = "ref", "ref_aux";
1030 resets = <&ufs_mem_hc 0>;
1031 reset-names = "ufsphy";
1032 status = "disabled";
1034 ufs_mem_phy_lanes: phy@4807400 {
1035 reg = <0x0 0x04807400 0x0 0x098>,
1036 <0x0 0x04807600 0x0 0x130>,
1037 <0x0 0x04807c00 0x0 0x16c>;
1042 gpi_dma0: dma-controller@4a00000 {
1043 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1044 reg = <0x0 0x04a00000 0x0 0x60000>;
1045 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1046 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1048 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1049 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1050 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1051 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1052 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1053 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1054 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1055 dma-channels = <10>;
1056 dma-channel-mask = <0xf>;
1057 iommus = <&apps_smmu 0xf6 0x0>;
1059 status = "disabled";
1062 qupv3_id_0: geniqup@4ac0000 {
1063 compatible = "qcom,geni-se-qup";
1064 reg = <0x0 0x04ac0000 0x0 0x2000>;
1065 clock-names = "m-ahb", "s-ahb";
1066 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1067 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1068 #address-cells = <2>;
1070 iommus = <&apps_smmu 0xe3 0x0>;
1072 status = "disabled";
1075 compatible = "qcom,geni-i2c";
1076 reg = <0x0 0x04a80000 0x0 0x4000>;
1078 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&qup_i2c0_default>;
1081 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1082 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1083 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1084 dma-names = "tx", "rx";
1085 #address-cells = <1>;
1087 status = "disabled";
1091 compatible = "qcom,geni-spi";
1092 reg = <0x0 0x04a80000 0x0 0x4000>;
1094 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&qup_spi0_default>;
1097 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1098 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1099 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1100 dma-names = "tx", "rx";
1101 #address-cells = <1>;
1103 status = "disabled";
1107 compatible = "qcom,geni-i2c";
1108 reg = <0x0 0x04a84000 0x0 0x4000>;
1110 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1111 pinctrl-names = "default";
1112 pinctrl-0 = <&qup_i2c1_default>;
1113 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1114 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1115 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1116 dma-names = "tx", "rx";
1117 #address-cells = <1>;
1119 status = "disabled";
1123 compatible = "qcom,geni-spi";
1124 reg = <0x0 0x04a84000 0x0 0x4000>;
1126 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1127 pinctrl-names = "default";
1128 pinctrl-0 = <&qup_spi1_default>;
1129 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1130 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1131 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1132 dma-names = "tx", "rx";
1133 #address-cells = <1>;
1135 status = "disabled";
1139 compatible = "qcom,geni-i2c";
1140 reg = <0x0 0x04a88000 0x0 0x4000>;
1142 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1143 pinctrl-names = "default";
1144 pinctrl-0 = <&qup_i2c2_default>;
1145 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1146 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1147 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1148 dma-names = "tx", "rx";
1149 #address-cells = <1>;
1151 status = "disabled";
1155 compatible = "qcom,geni-spi";
1156 reg = <0x0 0x04a88000 0x0 0x4000>;
1158 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1159 pinctrl-names = "default";
1160 pinctrl-0 = <&qup_spi2_default>;
1161 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1162 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1163 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1164 dma-names = "tx", "rx";
1165 #address-cells = <1>;
1167 status = "disabled";
1171 compatible = "qcom,geni-i2c";
1172 reg = <0x0 0x04a8c000 0x0 0x4000>;
1174 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&qup_i2c3_default>;
1177 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1178 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1179 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1180 dma-names = "tx", "rx";
1181 #address-cells = <1>;
1183 status = "disabled";
1187 compatible = "qcom,geni-spi";
1188 reg = <0x0 0x04a8c000 0x0 0x4000>;
1190 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1191 pinctrl-names = "default";
1192 pinctrl-0 = <&qup_spi3_default>;
1193 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1194 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1195 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1196 dma-names = "tx", "rx";
1197 #address-cells = <1>;
1199 status = "disabled";
1203 compatible = "qcom,geni-i2c";
1204 reg = <0x0 0x04a90000 0x0 0x4000>;
1206 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1207 pinctrl-names = "default";
1208 pinctrl-0 = <&qup_i2c4_default>;
1209 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1210 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1211 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1212 dma-names = "tx", "rx";
1213 #address-cells = <1>;
1215 status = "disabled";
1219 compatible = "qcom,geni-spi";
1220 reg = <0x0 0x04a90000 0x0 0x4000>;
1222 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1223 pinctrl-names = "default";
1224 pinctrl-0 = <&qup_spi4_default>;
1225 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1227 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1228 dma-names = "tx", "rx";
1229 #address-cells = <1>;
1231 status = "disabled";
1234 uart4: serial@4a90000 {
1235 compatible = "qcom,geni-debug-uart";
1236 reg = <0x0 0x04a90000 0x0 0x4000>;
1238 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1239 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1240 status = "disabled";
1244 compatible = "qcom,geni-i2c";
1245 reg = <0x0 0x04a94000 0x0 0x4000>;
1247 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1248 pinctrl-names = "default";
1249 pinctrl-0 = <&qup_i2c5_default>;
1250 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1251 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1252 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1253 dma-names = "tx", "rx";
1254 #address-cells = <1>;
1256 status = "disabled";
1260 compatible = "qcom,geni-spi";
1261 reg = <0x0 0x04a94000 0x0 0x4000>;
1263 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1264 pinctrl-names = "default";
1265 pinctrl-0 = <&qup_spi5_default>;
1266 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1267 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1268 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1269 dma-names = "tx", "rx";
1270 #address-cells = <1>;
1272 status = "disabled";
1277 compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1278 reg = <0x0 0x04ef8800 0x0 0x400>;
1279 #address-cells = <2>;
1283 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1284 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1285 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1286 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1287 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1288 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1289 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1291 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1292 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1293 assigned-clock-rates = <19200000>, <66666667>;
1295 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1296 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1297 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1299 resets = <&gcc GCC_USB30_PRIM_BCR>;
1300 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1301 qcom,select-utmi-as-pipe-clk;
1302 status = "disabled";
1304 usb_dwc3: usb@4e00000 {
1305 compatible = "snps,dwc3";
1306 reg = <0x0 0x04e00000 0x0 0xcd00>;
1307 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1308 phys = <&usb_hsphy>, <&usb_qmpphy>;
1309 phy-names = "usb2-phy", "usb3-phy";
1310 iommus = <&apps_smmu 0x120 0x0>;
1311 snps,dis_u2_susphy_quirk;
1312 snps,dis_enblslpm_quirk;
1313 snps,has-lpm-erratum;
1314 snps,hird-threshold = /bits/ 8 <0x10>;
1315 snps,usb3_lpm_capable;
1319 gpucc: clock-controller@5990000 {
1320 compatible = "qcom,sm6115-gpucc";
1321 reg = <0x0 0x05990000 0x0 0x9000>;
1322 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1323 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1324 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1327 #power-domain-cells = <1>;
1330 adreno_smmu: iommu@59a0000 {
1331 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1332 "qcom,smmu-500", "arm,mmu-500";
1333 reg = <0x0 0x059a0000 0x0 0x10000>;
1334 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1344 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1345 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1346 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1347 clock-names = "mem",
1350 power-domains = <&gpucc GPU_CX_GDSC>;
1352 #global-interrupts = <1>;
1356 mdss: display-subsystem@5e00000 {
1357 compatible = "qcom,sm6115-mdss";
1358 reg = <0x0 0x05e00000 0x0 0x1000>;
1361 power-domains = <&dispcc MDSS_GDSC>;
1363 clocks = <&gcc GCC_DISP_AHB_CLK>,
1364 <&gcc GCC_DISP_HF_AXI_CLK>,
1365 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1367 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1368 interrupt-controller;
1369 #interrupt-cells = <1>;
1371 iommus = <&apps_smmu 0x420 0x2>,
1372 <&apps_smmu 0x421 0x0>;
1374 #address-cells = <2>;
1378 status = "disabled";
1380 mdp: display-controller@5e01000 {
1381 compatible = "qcom,sm6115-dpu";
1382 reg = <0x0 0x05e01000 0x0 0x8f000>,
1383 <0x0 0x05eb0000 0x0 0x2008>;
1384 reg-names = "mdp", "vbif";
1386 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1387 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1388 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1389 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1390 <&dispcc DISP_CC_MDSS_ROT_CLK>,
1391 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1392 clock-names = "bus",
1399 operating-points-v2 = <&mdp_opp_table>;
1400 power-domains = <&rpmpd SM6115_VDDCX>;
1402 interrupt-parent = <&mdss>;
1406 #address-cells = <1>;
1411 dpu_intf1_out: endpoint {
1412 remote-endpoint = <&mdss_dsi0_in>;
1417 mdp_opp_table: opp-table {
1418 compatible = "operating-points-v2";
1421 opp-hz = /bits/ 64 <19200000>;
1422 required-opps = <&rpmpd_opp_min_svs>;
1426 opp-hz = /bits/ 64 <192000000>;
1427 required-opps = <&rpmpd_opp_low_svs>;
1431 opp-hz = /bits/ 64 <256000000>;
1432 required-opps = <&rpmpd_opp_svs>;
1436 opp-hz = /bits/ 64 <307200000>;
1437 required-opps = <&rpmpd_opp_svs_plus>;
1441 opp-hz = /bits/ 64 <384000000>;
1442 required-opps = <&rpmpd_opp_nom>;
1447 mdss_dsi0: dsi@5e94000 {
1448 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1449 reg = <0x0 0x05e94000 0x0 0x400>;
1450 reg-names = "dsi_ctrl";
1452 interrupt-parent = <&mdss>;
1455 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1456 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1457 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1458 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1459 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1460 <&gcc GCC_DISP_HF_AXI_CLK>;
1461 clock-names = "byte",
1468 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1469 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1470 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1472 operating-points-v2 = <&dsi_opp_table>;
1473 power-domains = <&rpmpd SM6115_VDDCX>;
1474 phys = <&mdss_dsi0_phy>;
1476 #address-cells = <1>;
1479 status = "disabled";
1482 #address-cells = <1>;
1487 mdss_dsi0_in: endpoint {
1488 remote-endpoint = <&dpu_intf1_out>;
1494 mdss_dsi0_out: endpoint {
1499 dsi_opp_table: opp-table {
1500 compatible = "operating-points-v2";
1503 opp-hz = /bits/ 64 <19200000>;
1504 required-opps = <&rpmpd_opp_min_svs>;
1508 opp-hz = /bits/ 64 <164000000>;
1509 required-opps = <&rpmpd_opp_low_svs>;
1513 opp-hz = /bits/ 64 <187500000>;
1514 required-opps = <&rpmpd_opp_svs>;
1519 mdss_dsi0_phy: phy@5e94400 {
1520 compatible = "qcom,dsi-phy-14nm-2290";
1521 reg = <0x0 0x05e94400 0x0 0x100>,
1522 <0x0 0x05e94500 0x0 0x300>,
1523 <0x0 0x05e94800 0x0 0x188>;
1524 reg-names = "dsi_phy",
1531 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1532 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1533 clock-names = "iface", "ref";
1535 status = "disabled";
1539 dispcc: clock-controller@5f00000 {
1540 compatible = "qcom,sm6115-dispcc";
1541 reg = <0x0 0x05f00000 0 0x20000>;
1542 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1546 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
1549 #power-domain-cells = <1>;
1552 remoteproc_mpss: remoteproc@6080000 {
1553 compatible = "qcom,sm6115-mpss-pas";
1554 reg = <0x0 0x06080000 0x0 0x100>;
1556 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1557 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1558 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1559 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1560 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1561 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1562 interrupt-names = "wdog", "fatal", "ready", "handover",
1563 "stop-ack", "shutdown-ack";
1565 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1568 power-domains = <&rpmpd SM6115_VDDCX>;
1570 memory-region = <&pil_modem_mem>;
1572 qcom,smem-states = <&modem_smp2p_out 0>;
1573 qcom,smem-state-names = "stop";
1575 status = "disabled";
1578 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
1580 qcom,remote-pid = <1>;
1581 mboxes = <&apcs_glb 12>;
1586 compatible = "arm,coresight-stm", "arm,primecell";
1587 reg = <0x0 0x08002000 0x0 0x1000>,
1588 <0x0 0x0e280000 0x0 0x180000>;
1589 reg-names = "stm-base", "stm-stimulus-base";
1591 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1592 clock-names = "apb_pclk";
1594 status = "disabled";
1599 remote-endpoint = <&funnel_in0_in>;
1606 compatible = "arm,coresight-cti", "arm,primecell";
1607 reg = <0x0 0x08010000 0x0 0x1000>;
1609 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1610 clock-names = "apb_pclk";
1612 status = "disabled";
1616 compatible = "arm,coresight-cti", "arm,primecell";
1617 reg = <0x0 0x08011000 0x0 0x1000>;
1619 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1620 clock-names = "apb_pclk";
1622 status = "disabled";
1626 compatible = "arm,coresight-cti", "arm,primecell";
1627 reg = <0x0 0x08012000 0x0 0x1000>;
1629 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1630 clock-names = "apb_pclk";
1632 status = "disabled";
1636 compatible = "arm,coresight-cti", "arm,primecell";
1637 reg = <0x0 0x08013000 0x0 0x1000>;
1639 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1640 clock-names = "apb_pclk";
1642 status = "disabled";
1646 compatible = "arm,coresight-cti", "arm,primecell";
1647 reg = <0x0 0x08014000 0x0 0x1000>;
1649 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1650 clock-names = "apb_pclk";
1652 status = "disabled";
1656 compatible = "arm,coresight-cti", "arm,primecell";
1657 reg = <0x0 0x08015000 0x0 0x1000>;
1659 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1660 clock-names = "apb_pclk";
1662 status = "disabled";
1666 compatible = "arm,coresight-cti", "arm,primecell";
1667 reg = <0x0 0x08016000 0x0 0x1000>;
1669 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1670 clock-names = "apb_pclk";
1672 status = "disabled";
1676 compatible = "arm,coresight-cti", "arm,primecell";
1677 reg = <0x0 0x08017000 0x0 0x1000>;
1679 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1680 clock-names = "apb_pclk";
1682 status = "disabled";
1686 compatible = "arm,coresight-cti", "arm,primecell";
1687 reg = <0x0 0x08018000 0x0 0x1000>;
1689 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1690 clock-names = "apb_pclk";
1692 status = "disabled";
1696 compatible = "arm,coresight-cti", "arm,primecell";
1697 reg = <0x0 0x08019000 0x0 0x1000>;
1699 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1700 clock-names = "apb_pclk";
1702 status = "disabled";
1705 cti10: cti@801a000 {
1706 compatible = "arm,coresight-cti", "arm,primecell";
1707 reg = <0x0 0x0801a000 0x0 0x1000>;
1709 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1710 clock-names = "apb_pclk";
1712 status = "disabled";
1715 cti11: cti@801b000 {
1716 compatible = "arm,coresight-cti", "arm,primecell";
1717 reg = <0x0 0x0801b000 0x0 0x1000>;
1719 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1720 clock-names = "apb_pclk";
1722 status = "disabled";
1725 cti12: cti@801c000 {
1726 compatible = "arm,coresight-cti", "arm,primecell";
1727 reg = <0x0 0x0801c000 0x0 0x1000>;
1729 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1730 clock-names = "apb_pclk";
1732 status = "disabled";
1735 cti13: cti@801d000 {
1736 compatible = "arm,coresight-cti", "arm,primecell";
1737 reg = <0x0 0x0801d000 0x0 0x1000>;
1739 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1740 clock-names = "apb_pclk";
1742 status = "disabled";
1745 cti14: cti@801e000 {
1746 compatible = "arm,coresight-cti", "arm,primecell";
1747 reg = <0x0 0x0801e000 0x0 0x1000>;
1749 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1750 clock-names = "apb_pclk";
1752 status = "disabled";
1755 cti15: cti@801f000 {
1756 compatible = "arm,coresight-cti", "arm,primecell";
1757 reg = <0x0 0x0801f000 0x0 0x1000>;
1759 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1760 clock-names = "apb_pclk";
1762 status = "disabled";
1765 replicator@8046000 {
1766 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1767 reg = <0x0 0x08046000 0x0 0x1000>;
1769 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1770 clock-names = "apb_pclk";
1772 status = "disabled";
1776 replicator_out: endpoint {
1777 remote-endpoint = <&etr_in>;
1784 replicator_in: endpoint {
1785 remote-endpoint = <&etf_out>;
1792 compatible = "arm,coresight-tmc", "arm,primecell";
1793 reg = <0x0 0x08047000 0x0 0x1000>;
1795 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1796 clock-names = "apb_pclk";
1798 status = "disabled";
1803 remote-endpoint = <&merge_funnel_out>;
1811 remote-endpoint = <&replicator_in>;
1818 compatible = "arm,coresight-tmc", "arm,primecell";
1819 reg = <0x0 0x08048000 0x0 0x1000>;
1821 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1822 clock-names = "apb_pclk";
1824 status = "disabled";
1829 remote-endpoint = <&replicator_out>;
1836 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1837 reg = <0x0 0x08041000 0x0 0x1000>;
1839 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1840 clock-names = "apb_pclk";
1842 status = "disabled";
1846 funnel_in0_out: endpoint {
1847 remote-endpoint = <&merge_funnel_in0>;
1854 funnel_in0_in: endpoint {
1855 remote-endpoint = <&stm_out>;
1862 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1863 reg = <0x0 0x08042000 0x0 0x1000>;
1865 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1866 clock-names = "apb_pclk";
1868 status = "disabled";
1872 funnel_in1_out: endpoint {
1873 remote-endpoint = <&merge_funnel_in1>;
1880 funnel_in1_in: endpoint {
1881 remote-endpoint = <&funnel_apss1_out>;
1888 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1889 reg = <0x0 0x08045000 0x0 0x1000>;
1891 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1892 clock-names = "apb_pclk";
1894 status = "disabled";
1898 merge_funnel_out: endpoint {
1899 remote-endpoint = <&etf_in>;
1905 #address-cells = <1>;
1910 merge_funnel_in0: endpoint {
1911 remote-endpoint = <&funnel_in0_out>;
1917 merge_funnel_in1: endpoint {
1918 remote-endpoint = <&funnel_in1_out>;
1925 compatible = "arm,coresight-etm4x", "arm,primecell";
1926 reg = <0x0 0x09040000 0x0 0x1000>;
1928 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1929 clock-names = "apb_pclk";
1930 arm,coresight-loses-context-with-cpu;
1934 status = "disabled";
1938 etm0_out: endpoint {
1939 remote-endpoint = <&funnel_apss0_in0>;
1946 compatible = "arm,coresight-etm4x", "arm,primecell";
1947 reg = <0x0 0x09140000 0x0 0x1000>;
1949 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1950 clock-names = "apb_pclk";
1951 arm,coresight-loses-context-with-cpu;
1955 status = "disabled";
1959 etm1_out: endpoint {
1960 remote-endpoint = <&funnel_apss0_in1>;
1967 compatible = "arm,coresight-etm4x", "arm,primecell";
1968 reg = <0x0 0x09240000 0x0 0x1000>;
1970 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1971 clock-names = "apb_pclk";
1972 arm,coresight-loses-context-with-cpu;
1976 status = "disabled";
1980 etm2_out: endpoint {
1981 remote-endpoint = <&funnel_apss0_in2>;
1988 compatible = "arm,coresight-etm4x", "arm,primecell";
1989 reg = <0x0 0x09340000 0x0 0x1000>;
1991 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1992 clock-names = "apb_pclk";
1993 arm,coresight-loses-context-with-cpu;
1997 status = "disabled";
2001 etm3_out: endpoint {
2002 remote-endpoint = <&funnel_apss0_in3>;
2009 compatible = "arm,coresight-etm4x", "arm,primecell";
2010 reg = <0x0 0x09440000 0x0 0x1000>;
2012 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2013 clock-names = "apb_pclk";
2014 arm,coresight-loses-context-with-cpu;
2018 status = "disabled";
2022 etm4_out: endpoint {
2023 remote-endpoint = <&funnel_apss0_in4>;
2030 compatible = "arm,coresight-etm4x", "arm,primecell";
2031 reg = <0x0 0x09540000 0x0 0x1000>;
2033 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2034 clock-names = "apb_pclk";
2035 arm,coresight-loses-context-with-cpu;
2039 status = "disabled";
2043 etm5_out: endpoint {
2044 remote-endpoint = <&funnel_apss0_in5>;
2051 compatible = "arm,coresight-etm4x", "arm,primecell";
2052 reg = <0x0 0x09640000 0x0 0x1000>;
2054 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2055 clock-names = "apb_pclk";
2056 arm,coresight-loses-context-with-cpu;
2060 status = "disabled";
2064 etm6_out: endpoint {
2065 remote-endpoint = <&funnel_apss0_in6>;
2072 compatible = "arm,coresight-etm4x", "arm,primecell";
2073 reg = <0x0 0x09740000 0x0 0x1000>;
2075 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2076 clock-names = "apb_pclk";
2077 arm,coresight-loses-context-with-cpu;
2081 status = "disabled";
2085 etm7_out: endpoint {
2086 remote-endpoint = <&funnel_apss0_in7>;
2093 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2094 reg = <0x0 0x09800000 0x0 0x1000>;
2096 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2097 clock-names = "apb_pclk";
2099 status = "disabled";
2103 funnel_apss0_out: endpoint {
2104 remote-endpoint = <&funnel_apss1_in>;
2110 #address-cells = <1>;
2115 funnel_apss0_in0: endpoint {
2116 remote-endpoint = <&etm0_out>;
2122 funnel_apss0_in1: endpoint {
2123 remote-endpoint = <&etm1_out>;
2129 funnel_apss0_in2: endpoint {
2130 remote-endpoint = <&etm2_out>;
2136 funnel_apss0_in3: endpoint {
2137 remote-endpoint = <&etm3_out>;
2143 funnel_apss0_in4: endpoint {
2144 remote-endpoint = <&etm4_out>;
2150 funnel_apss0_in5: endpoint {
2151 remote-endpoint = <&etm5_out>;
2157 funnel_apss0_in6: endpoint {
2158 remote-endpoint = <&etm6_out>;
2164 funnel_apss0_in7: endpoint {
2165 remote-endpoint = <&etm7_out>;
2172 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2173 reg = <0x0 0x09810000 0x0 0x1000>;
2175 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2176 clock-names = "apb_pclk";
2178 status = "disabled";
2182 funnel_apss1_out: endpoint {
2183 remote-endpoint = <&funnel_in1_in>;
2190 funnel_apss1_in: endpoint {
2191 remote-endpoint = <&funnel_apss0_out>;
2197 remoteproc_adsp: remoteproc@ab00000 {
2198 compatible = "qcom,sm6115-adsp-pas";
2199 reg = <0x0 0x0ab00000 0x0 0x100>;
2201 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2202 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2203 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2204 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2205 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2206 interrupt-names = "wdog", "fatal", "ready",
2207 "handover", "stop-ack";
2209 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2212 power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2213 <&rpmpd SM6115_VDD_LPI_MX>;
2215 memory-region = <&pil_adsp_mem>;
2217 qcom,smem-states = <&adsp_smp2p_out 0>;
2218 qcom,smem-state-names = "stop";
2220 status = "disabled";
2223 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
2225 qcom,remote-pid = <2>;
2226 mboxes = <&apcs_glb 8>;
2229 compatible = "qcom,fastrpc";
2230 qcom,glink-channels = "fastrpcglink-apps-dsp";
2232 qcom,non-secure-domain;
2233 #address-cells = <1>;
2237 compatible = "qcom,fastrpc-compute-cb";
2239 iommus = <&apps_smmu 0x01c3 0x0>;
2243 compatible = "qcom,fastrpc-compute-cb";
2245 iommus = <&apps_smmu 0x01c4 0x0>;
2249 compatible = "qcom,fastrpc-compute-cb";
2251 iommus = <&apps_smmu 0x01c5 0x0>;
2255 compatible = "qcom,fastrpc-compute-cb";
2257 iommus = <&apps_smmu 0x01c6 0x0>;
2261 compatible = "qcom,fastrpc-compute-cb";
2263 iommus = <&apps_smmu 0x01c7 0x0>;
2269 remoteproc_cdsp: remoteproc@b300000 {
2270 compatible = "qcom,sm6115-cdsp-pas";
2271 reg = <0x0 0x0b300000 0x0 0x100000>;
2273 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2274 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2275 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2276 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2277 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2278 interrupt-names = "wdog", "fatal", "ready",
2279 "handover", "stop-ack";
2281 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2284 power-domains = <&rpmpd SM6115_VDDCX>;
2286 memory-region = <&pil_cdsp_mem>;
2288 qcom,smem-states = <&cdsp_smp2p_out 0>;
2289 qcom,smem-state-names = "stop";
2291 status = "disabled";
2294 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
2296 qcom,remote-pid = <5>;
2297 mboxes = <&apcs_glb 28>;
2300 compatible = "qcom,fastrpc";
2301 qcom,glink-channels = "fastrpcglink-apps-dsp";
2303 qcom,non-secure-domain;
2304 #address-cells = <1>;
2308 compatible = "qcom,fastrpc-compute-cb";
2310 iommus = <&apps_smmu 0x0c01 0x0>;
2314 compatible = "qcom,fastrpc-compute-cb";
2316 iommus = <&apps_smmu 0x0c02 0x0>;
2320 compatible = "qcom,fastrpc-compute-cb";
2322 iommus = <&apps_smmu 0x0c03 0x0>;
2326 compatible = "qcom,fastrpc-compute-cb";
2328 iommus = <&apps_smmu 0x0c04 0x0>;
2332 compatible = "qcom,fastrpc-compute-cb";
2334 iommus = <&apps_smmu 0x0c05 0x0>;
2338 compatible = "qcom,fastrpc-compute-cb";
2340 iommus = <&apps_smmu 0x0c06 0x0>;
2343 /* note: secure cb9 in downstream */
2348 apps_smmu: iommu@c600000 {
2349 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2350 reg = <0x0 0x0c600000 0x0 0x80000>;
2352 #global-interrupts = <1>;
2354 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
2355 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
2356 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
2357 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
2358 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
2359 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
2360 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
2361 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
2362 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
2363 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
2364 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2365 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2374 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2375 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2376 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2377 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2378 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2379 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2380 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2381 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2382 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2383 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2384 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2385 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2386 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
2387 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
2388 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
2389 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
2390 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
2391 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2392 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2393 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2394 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2395 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
2396 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
2397 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2398 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2399 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
2400 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2401 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2402 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2403 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
2405 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
2406 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2407 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
2408 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2409 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2410 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2411 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2412 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2413 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2414 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2415 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2416 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2417 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
2418 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
2421 wifi: wifi@c800000 {
2422 compatible = "qcom,wcn3990-wifi";
2423 reg = <0x0 0x0c800000 0x0 0x800000>;
2424 reg-names = "membase";
2425 memory-region = <&wlan_msa_mem>;
2426 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
2427 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
2428 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
2429 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
2430 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
2431 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
2432 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
2433 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
2434 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
2435 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
2436 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
2438 iommus = <&apps_smmu 0x1a0 0x1>;
2439 qcom,msa-fixed-perm;
2440 status = "disabled";
2444 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
2445 reg = <0x0 0x0f017000 0x0 0x1000>;
2446 clocks = <&sleep_clk>;
2447 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2450 apcs_glb: mailbox@f111000 {
2451 compatible = "qcom,sm6115-apcs-hmss-global",
2452 "qcom,msm8994-apcs-kpss-global";
2453 reg = <0x0 0x0f111000 0x0 0x1000>;
2459 compatible = "arm,armv7-timer-mem";
2460 reg = <0x0 0x0f120000 0x0 0x1000>;
2461 #address-cells = <2>;
2464 clock-frequency = <19200000>;
2467 reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>;
2469 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2470 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2474 reg = <0x0 0x0f123000 0x0 0x1000>;
2476 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2477 status = "disabled";
2481 reg = <0x0 0x0f124000 0x0 0x1000>;
2483 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2484 status = "disabled";
2488 reg = <0x0 0x0f125000 0x0 0x1000>;
2490 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2491 status = "disabled";
2495 reg = <0x0 0x0f126000 0x0 0x1000>;
2497 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2498 status = "disabled";
2502 reg = <0x0 0x0f127000 0x0 0x1000>;
2504 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2505 status = "disabled";
2509 reg = <0x0 0x0f128000 0x0 0x1000>;
2511 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2512 status = "disabled";
2516 intc: interrupt-controller@f200000 {
2517 compatible = "arm,gic-v3";
2518 reg = <0x0 0x0f200000 0x0 0x10000>,
2519 <0x0 0x0f300000 0x0 0x100000>;
2520 #interrupt-cells = <3>;
2521 interrupt-controller;
2522 interrupt-parent = <&intc>;
2523 #redistributor-regions = <1>;
2524 redistributor-stride = <0x0 0x20000>;
2525 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2528 cpufreq_hw: cpufreq@f521000 {
2529 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
2530 reg = <0x0 0x0f521000 0x0 0x1000>,
2531 <0x0 0x0f523000 0x0 0x1000>;
2533 reg-names = "freq-domain0", "freq-domain1";
2534 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
2535 clock-names = "xo", "alternate";
2537 #freq-domain-cells = <1>;
2544 polling-delay-passive = <0>;
2545 polling-delay = <0>;
2546 thermal-sensors = <&tsens0 0>;
2550 temperature = <115000>;
2551 hysteresis = <5000>;
2556 temperature = <125000>;
2557 hysteresis = <1000>;
2564 polling-delay-passive = <0>;
2565 polling-delay = <0>;
2566 thermal-sensors = <&tsens0 1>;
2570 temperature = <115000>;
2571 hysteresis = <5000>;
2576 temperature = <125000>;
2577 hysteresis = <1000>;
2584 polling-delay-passive = <0>;
2585 polling-delay = <0>;
2586 thermal-sensors = <&tsens0 2>;
2590 temperature = <115000>;
2591 hysteresis = <5000>;
2596 temperature = <125000>;
2597 hysteresis = <1000>;
2604 polling-delay-passive = <0>;
2605 polling-delay = <0>;
2606 thermal-sensors = <&tsens0 3>;
2610 temperature = <115000>;
2611 hysteresis = <5000>;
2616 temperature = <125000>;
2617 hysteresis = <1000>;
2624 polling-delay-passive = <0>;
2625 polling-delay = <0>;
2626 thermal-sensors = <&tsens0 4>;
2630 temperature = <115000>;
2631 hysteresis = <5000>;
2636 temperature = <125000>;
2637 hysteresis = <1000>;
2644 polling-delay-passive = <0>;
2645 polling-delay = <0>;
2646 thermal-sensors = <&tsens0 5>;
2650 temperature = <115000>;
2651 hysteresis = <5000>;
2656 temperature = <125000>;
2657 hysteresis = <1000>;
2664 polling-delay-passive = <0>;
2665 polling-delay = <0>;
2666 thermal-sensors = <&tsens0 6>;
2669 cpu4_alert0: trip-point0 {
2670 temperature = <90000>;
2671 hysteresis = <2000>;
2675 cpu4_alert1: trip-point1 {
2676 temperature = <95000>;
2677 hysteresis = <2000>;
2681 cpu4_crit: cpu_crit {
2682 temperature = <110000>;
2683 hysteresis = <1000>;
2690 polling-delay-passive = <0>;
2691 polling-delay = <0>;
2692 thermal-sensors = <&tsens0 7>;
2695 cpu5_alert0: trip-point0 {
2696 temperature = <90000>;
2697 hysteresis = <2000>;
2701 cpu5_alert1: trip-point1 {
2702 temperature = <95000>;
2703 hysteresis = <2000>;
2707 cpu5_crit: cpu_crit {
2708 temperature = <110000>;
2709 hysteresis = <1000>;
2716 polling-delay-passive = <0>;
2717 polling-delay = <0>;
2718 thermal-sensors = <&tsens0 8>;
2721 cpu6_alert0: trip-point0 {
2722 temperature = <90000>;
2723 hysteresis = <2000>;
2727 cpu6_alert1: trip-point1 {
2728 temperature = <95000>;
2729 hysteresis = <2000>;
2733 cpu6_crit: cpu_crit {
2734 temperature = <110000>;
2735 hysteresis = <1000>;
2742 polling-delay-passive = <0>;
2743 polling-delay = <0>;
2744 thermal-sensors = <&tsens0 9>;
2747 cpu7_alert0: trip-point0 {
2748 temperature = <90000>;
2749 hysteresis = <2000>;
2753 cpu7_alert1: trip-point1 {
2754 temperature = <95000>;
2755 hysteresis = <2000>;
2759 cpu7_crit: cpu_crit {
2760 temperature = <110000>;
2761 hysteresis = <1000>;
2768 polling-delay-passive = <0>;
2769 polling-delay = <0>;
2770 thermal-sensors = <&tsens0 10>;
2773 cpu45_alert0: trip-point0 {
2774 temperature = <90000>;
2775 hysteresis = <2000>;
2779 cpu45_alert1: trip-point1 {
2780 temperature = <95000>;
2781 hysteresis = <2000>;
2785 cpu45_crit: cpu_crit {
2786 temperature = <110000>;
2787 hysteresis = <1000>;
2794 polling-delay-passive = <0>;
2795 polling-delay = <0>;
2796 thermal-sensors = <&tsens0 11>;
2799 cpu67_alert0: trip-point0 {
2800 temperature = <90000>;
2801 hysteresis = <2000>;
2805 cpu67_alert1: trip-point1 {
2806 temperature = <95000>;
2807 hysteresis = <2000>;
2811 cpu67_crit: cpu_crit {
2812 temperature = <110000>;
2813 hysteresis = <1000>;
2820 polling-delay-passive = <0>;
2821 polling-delay = <0>;
2822 thermal-sensors = <&tsens0 12>;
2825 cpu0123_alert0: trip-point0 {
2826 temperature = <90000>;
2827 hysteresis = <2000>;
2831 cpu0123_alert1: trip-point1 {
2832 temperature = <95000>;
2833 hysteresis = <2000>;
2837 cpu0123_crit: cpu_crit {
2838 temperature = <110000>;
2839 hysteresis = <1000>;
2846 polling-delay-passive = <0>;
2847 polling-delay = <0>;
2848 thermal-sensors = <&tsens0 13>;
2852 temperature = <115000>;
2853 hysteresis = <5000>;
2858 temperature = <125000>;
2859 hysteresis = <1000>;
2866 polling-delay-passive = <0>;
2867 polling-delay = <0>;
2868 thermal-sensors = <&tsens0 14>;
2872 temperature = <115000>;
2873 hysteresis = <5000>;
2878 temperature = <125000>;
2879 hysteresis = <1000>;
2886 polling-delay-passive = <0>;
2887 polling-delay = <0>;
2888 thermal-sensors = <&tsens0 15>;
2892 temperature = <115000>;
2893 hysteresis = <5000>;
2898 temperature = <125000>;
2899 hysteresis = <1000>;
2907 compatible = "arm,armv8-timer";
2908 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2909 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2910 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2911 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;