1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sdm845.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/phy/phy-qcom-qusb2.h>
22 #include <dt-bindings/power/qcom-rpmpd.h>
23 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
24 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
25 #include <dt-bindings/soc/qcom,apr.h>
26 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
27 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
28 #include <dt-bindings/thermal/thermal.h>
31 interrupt-parent = <&intc>;
75 compatible = "fixed-clock";
77 clock-frequency = <38400000>;
78 clock-output-names = "xo_board";
81 sleep_clk: sleep-clk {
82 compatible = "fixed-clock";
84 clock-frequency = <32764>;
94 compatible = "qcom,kryo385";
96 clocks = <&cpufreq_hw 0>;
97 enable-method = "psci";
98 capacity-dmips-mhz = <611>;
99 dynamic-power-coefficient = <154>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
101 operating-points-v2 = <&cpu0_opp_table>;
102 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
104 power-domains = <&CPU_PD0>;
105 power-domain-names = "psci";
106 #cooling-cells = <2>;
107 next-level-cache = <&L2_0>;
109 compatible = "cache";
112 next-level-cache = <&L3_0>;
114 compatible = "cache";
123 compatible = "qcom,kryo385";
125 clocks = <&cpufreq_hw 0>;
126 enable-method = "psci";
127 capacity-dmips-mhz = <611>;
128 dynamic-power-coefficient = <154>;
129 qcom,freq-domain = <&cpufreq_hw 0>;
130 operating-points-v2 = <&cpu0_opp_table>;
131 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
132 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
133 power-domains = <&CPU_PD1>;
134 power-domain-names = "psci";
135 #cooling-cells = <2>;
136 next-level-cache = <&L2_100>;
138 compatible = "cache";
141 next-level-cache = <&L3_0>;
147 compatible = "qcom,kryo385";
149 clocks = <&cpufreq_hw 0>;
150 enable-method = "psci";
151 capacity-dmips-mhz = <611>;
152 dynamic-power-coefficient = <154>;
153 qcom,freq-domain = <&cpufreq_hw 0>;
154 operating-points-v2 = <&cpu0_opp_table>;
155 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
156 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
157 power-domains = <&CPU_PD2>;
158 power-domain-names = "psci";
159 #cooling-cells = <2>;
160 next-level-cache = <&L2_200>;
162 compatible = "cache";
165 next-level-cache = <&L3_0>;
171 compatible = "qcom,kryo385";
173 clocks = <&cpufreq_hw 0>;
174 enable-method = "psci";
175 capacity-dmips-mhz = <611>;
176 dynamic-power-coefficient = <154>;
177 qcom,freq-domain = <&cpufreq_hw 0>;
178 operating-points-v2 = <&cpu0_opp_table>;
179 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
180 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
181 #cooling-cells = <2>;
182 power-domains = <&CPU_PD3>;
183 power-domain-names = "psci";
184 next-level-cache = <&L2_300>;
186 compatible = "cache";
189 next-level-cache = <&L3_0>;
195 compatible = "qcom,kryo385";
197 clocks = <&cpufreq_hw 1>;
198 enable-method = "psci";
199 capacity-dmips-mhz = <1024>;
200 dynamic-power-coefficient = <442>;
201 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = <&cpu4_opp_table>;
203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
205 power-domains = <&CPU_PD4>;
206 power-domain-names = "psci";
207 #cooling-cells = <2>;
208 next-level-cache = <&L2_400>;
210 compatible = "cache";
213 next-level-cache = <&L3_0>;
219 compatible = "qcom,kryo385";
221 clocks = <&cpufreq_hw 1>;
222 enable-method = "psci";
223 capacity-dmips-mhz = <1024>;
224 dynamic-power-coefficient = <442>;
225 qcom,freq-domain = <&cpufreq_hw 1>;
226 operating-points-v2 = <&cpu4_opp_table>;
227 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
228 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
229 power-domains = <&CPU_PD5>;
230 power-domain-names = "psci";
231 #cooling-cells = <2>;
232 next-level-cache = <&L2_500>;
234 compatible = "cache";
237 next-level-cache = <&L3_0>;
243 compatible = "qcom,kryo385";
245 clocks = <&cpufreq_hw 1>;
246 enable-method = "psci";
247 capacity-dmips-mhz = <1024>;
248 dynamic-power-coefficient = <442>;
249 qcom,freq-domain = <&cpufreq_hw 1>;
250 operating-points-v2 = <&cpu4_opp_table>;
251 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
252 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
253 power-domains = <&CPU_PD6>;
254 power-domain-names = "psci";
255 #cooling-cells = <2>;
256 next-level-cache = <&L2_600>;
258 compatible = "cache";
261 next-level-cache = <&L3_0>;
267 compatible = "qcom,kryo385";
269 clocks = <&cpufreq_hw 1>;
270 enable-method = "psci";
271 capacity-dmips-mhz = <1024>;
272 dynamic-power-coefficient = <442>;
273 qcom,freq-domain = <&cpufreq_hw 1>;
274 operating-points-v2 = <&cpu4_opp_table>;
275 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
276 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
277 power-domains = <&CPU_PD7>;
278 power-domain-names = "psci";
279 #cooling-cells = <2>;
280 next-level-cache = <&L2_700>;
282 compatible = "cache";
285 next-level-cache = <&L3_0>;
325 cpu_idle_states: idle-states {
326 entry-method = "psci";
328 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
329 compatible = "arm,idle-state";
330 idle-state-name = "little-rail-power-collapse";
331 arm,psci-suspend-param = <0x40000004>;
332 entry-latency-us = <350>;
333 exit-latency-us = <461>;
334 min-residency-us = <1890>;
338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
339 compatible = "arm,idle-state";
340 idle-state-name = "big-rail-power-collapse";
341 arm,psci-suspend-param = <0x40000004>;
342 entry-latency-us = <264>;
343 exit-latency-us = <621>;
344 min-residency-us = <952>;
350 CLUSTER_SLEEP_0: cluster-sleep-0 {
351 compatible = "domain-idle-state";
352 arm,psci-suspend-param = <0x4100c244>;
353 entry-latency-us = <3263>;
354 exit-latency-us = <6562>;
355 min-residency-us = <9987>;
362 compatible = "qcom,scm-sdm845", "qcom,scm";
367 device_type = "memory";
368 /* We expect the bootloader to fill in the size */
369 reg = <0 0x80000000 0 0>;
372 cpu0_opp_table: opp-table-cpu0 {
373 compatible = "operating-points-v2";
376 cpu0_opp1: opp-300000000 {
377 opp-hz = /bits/ 64 <300000000>;
378 opp-peak-kBps = <800000 4800000>;
381 cpu0_opp2: opp-403200000 {
382 opp-hz = /bits/ 64 <403200000>;
383 opp-peak-kBps = <800000 4800000>;
386 cpu0_opp3: opp-480000000 {
387 opp-hz = /bits/ 64 <480000000>;
388 opp-peak-kBps = <800000 6451200>;
391 cpu0_opp4: opp-576000000 {
392 opp-hz = /bits/ 64 <576000000>;
393 opp-peak-kBps = <800000 6451200>;
396 cpu0_opp5: opp-652800000 {
397 opp-hz = /bits/ 64 <652800000>;
398 opp-peak-kBps = <800000 7680000>;
401 cpu0_opp6: opp-748800000 {
402 opp-hz = /bits/ 64 <748800000>;
403 opp-peak-kBps = <1804000 9216000>;
406 cpu0_opp7: opp-825600000 {
407 opp-hz = /bits/ 64 <825600000>;
408 opp-peak-kBps = <1804000 9216000>;
411 cpu0_opp8: opp-902400000 {
412 opp-hz = /bits/ 64 <902400000>;
413 opp-peak-kBps = <1804000 10444800>;
416 cpu0_opp9: opp-979200000 {
417 opp-hz = /bits/ 64 <979200000>;
418 opp-peak-kBps = <1804000 11980800>;
421 cpu0_opp10: opp-1056000000 {
422 opp-hz = /bits/ 64 <1056000000>;
423 opp-peak-kBps = <1804000 11980800>;
426 cpu0_opp11: opp-1132800000 {
427 opp-hz = /bits/ 64 <1132800000>;
428 opp-peak-kBps = <2188000 13516800>;
431 cpu0_opp12: opp-1228800000 {
432 opp-hz = /bits/ 64 <1228800000>;
433 opp-peak-kBps = <2188000 15052800>;
436 cpu0_opp13: opp-1324800000 {
437 opp-hz = /bits/ 64 <1324800000>;
438 opp-peak-kBps = <2188000 16588800>;
441 cpu0_opp14: opp-1420800000 {
442 opp-hz = /bits/ 64 <1420800000>;
443 opp-peak-kBps = <3072000 18124800>;
446 cpu0_opp15: opp-1516800000 {
447 opp-hz = /bits/ 64 <1516800000>;
448 opp-peak-kBps = <3072000 19353600>;
451 cpu0_opp16: opp-1612800000 {
452 opp-hz = /bits/ 64 <1612800000>;
453 opp-peak-kBps = <4068000 19353600>;
456 cpu0_opp17: opp-1689600000 {
457 opp-hz = /bits/ 64 <1689600000>;
458 opp-peak-kBps = <4068000 20889600>;
461 cpu0_opp18: opp-1766400000 {
462 opp-hz = /bits/ 64 <1766400000>;
463 opp-peak-kBps = <4068000 22425600>;
467 cpu4_opp_table: opp-table-cpu4 {
468 compatible = "operating-points-v2";
471 cpu4_opp1: opp-300000000 {
472 opp-hz = /bits/ 64 <300000000>;
473 opp-peak-kBps = <800000 4800000>;
476 cpu4_opp2: opp-403200000 {
477 opp-hz = /bits/ 64 <403200000>;
478 opp-peak-kBps = <800000 4800000>;
481 cpu4_opp3: opp-480000000 {
482 opp-hz = /bits/ 64 <480000000>;
483 opp-peak-kBps = <1804000 4800000>;
486 cpu4_opp4: opp-576000000 {
487 opp-hz = /bits/ 64 <576000000>;
488 opp-peak-kBps = <1804000 4800000>;
491 cpu4_opp5: opp-652800000 {
492 opp-hz = /bits/ 64 <652800000>;
493 opp-peak-kBps = <1804000 4800000>;
496 cpu4_opp6: opp-748800000 {
497 opp-hz = /bits/ 64 <748800000>;
498 opp-peak-kBps = <1804000 4800000>;
501 cpu4_opp7: opp-825600000 {
502 opp-hz = /bits/ 64 <825600000>;
503 opp-peak-kBps = <2188000 9216000>;
506 cpu4_opp8: opp-902400000 {
507 opp-hz = /bits/ 64 <902400000>;
508 opp-peak-kBps = <2188000 9216000>;
511 cpu4_opp9: opp-979200000 {
512 opp-hz = /bits/ 64 <979200000>;
513 opp-peak-kBps = <2188000 9216000>;
516 cpu4_opp10: opp-1056000000 {
517 opp-hz = /bits/ 64 <1056000000>;
518 opp-peak-kBps = <3072000 9216000>;
521 cpu4_opp11: opp-1132800000 {
522 opp-hz = /bits/ 64 <1132800000>;
523 opp-peak-kBps = <3072000 11980800>;
526 cpu4_opp12: opp-1209600000 {
527 opp-hz = /bits/ 64 <1209600000>;
528 opp-peak-kBps = <4068000 11980800>;
531 cpu4_opp13: opp-1286400000 {
532 opp-hz = /bits/ 64 <1286400000>;
533 opp-peak-kBps = <4068000 11980800>;
536 cpu4_opp14: opp-1363200000 {
537 opp-hz = /bits/ 64 <1363200000>;
538 opp-peak-kBps = <4068000 15052800>;
541 cpu4_opp15: opp-1459200000 {
542 opp-hz = /bits/ 64 <1459200000>;
543 opp-peak-kBps = <4068000 15052800>;
546 cpu4_opp16: opp-1536000000 {
547 opp-hz = /bits/ 64 <1536000000>;
548 opp-peak-kBps = <5412000 15052800>;
551 cpu4_opp17: opp-1612800000 {
552 opp-hz = /bits/ 64 <1612800000>;
553 opp-peak-kBps = <5412000 15052800>;
556 cpu4_opp18: opp-1689600000 {
557 opp-hz = /bits/ 64 <1689600000>;
558 opp-peak-kBps = <5412000 19353600>;
561 cpu4_opp19: opp-1766400000 {
562 opp-hz = /bits/ 64 <1766400000>;
563 opp-peak-kBps = <6220000 19353600>;
566 cpu4_opp20: opp-1843200000 {
567 opp-hz = /bits/ 64 <1843200000>;
568 opp-peak-kBps = <6220000 19353600>;
571 cpu4_opp21: opp-1920000000 {
572 opp-hz = /bits/ 64 <1920000000>;
573 opp-peak-kBps = <7216000 19353600>;
576 cpu4_opp22: opp-1996800000 {
577 opp-hz = /bits/ 64 <1996800000>;
578 opp-peak-kBps = <7216000 20889600>;
581 cpu4_opp23: opp-2092800000 {
582 opp-hz = /bits/ 64 <2092800000>;
583 opp-peak-kBps = <7216000 20889600>;
586 cpu4_opp24: opp-2169600000 {
587 opp-hz = /bits/ 64 <2169600000>;
588 opp-peak-kBps = <7216000 20889600>;
591 cpu4_opp25: opp-2246400000 {
592 opp-hz = /bits/ 64 <2246400000>;
593 opp-peak-kBps = <7216000 20889600>;
596 cpu4_opp26: opp-2323200000 {
597 opp-hz = /bits/ 64 <2323200000>;
598 opp-peak-kBps = <7216000 20889600>;
601 cpu4_opp27: opp-2400000000 {
602 opp-hz = /bits/ 64 <2400000000>;
603 opp-peak-kBps = <7216000 22425600>;
606 cpu4_opp28: opp-2476800000 {
607 opp-hz = /bits/ 64 <2476800000>;
608 opp-peak-kBps = <7216000 22425600>;
611 cpu4_opp29: opp-2553600000 {
612 opp-hz = /bits/ 64 <2553600000>;
613 opp-peak-kBps = <7216000 22425600>;
616 cpu4_opp30: opp-2649600000 {
617 opp-hz = /bits/ 64 <2649600000>;
618 opp-peak-kBps = <7216000 22425600>;
621 cpu4_opp31: opp-2745600000 {
622 opp-hz = /bits/ 64 <2745600000>;
623 opp-peak-kBps = <7216000 25497600>;
626 cpu4_opp32: opp-2803200000 {
627 opp-hz = /bits/ 64 <2803200000>;
628 opp-peak-kBps = <7216000 25497600>;
632 dsi_opp_table: opp-table-dsi {
633 compatible = "operating-points-v2";
636 opp-hz = /bits/ 64 <19200000>;
637 required-opps = <&rpmhpd_opp_min_svs>;
641 opp-hz = /bits/ 64 <180000000>;
642 required-opps = <&rpmhpd_opp_low_svs>;
646 opp-hz = /bits/ 64 <275000000>;
647 required-opps = <&rpmhpd_opp_svs>;
651 opp-hz = /bits/ 64 <328580000>;
652 required-opps = <&rpmhpd_opp_svs_l1>;
656 opp-hz = /bits/ 64 <358000000>;
657 required-opps = <&rpmhpd_opp_nom>;
661 qspi_opp_table: opp-table-qspi {
662 compatible = "operating-points-v2";
665 opp-hz = /bits/ 64 <19200000>;
666 required-opps = <&rpmhpd_opp_min_svs>;
670 opp-hz = /bits/ 64 <100000000>;
671 required-opps = <&rpmhpd_opp_low_svs>;
675 opp-hz = /bits/ 64 <150000000>;
676 required-opps = <&rpmhpd_opp_svs>;
680 opp-hz = /bits/ 64 <300000000>;
681 required-opps = <&rpmhpd_opp_nom>;
685 qup_opp_table: opp-table-qup {
686 compatible = "operating-points-v2";
689 opp-hz = /bits/ 64 <50000000>;
690 required-opps = <&rpmhpd_opp_min_svs>;
694 opp-hz = /bits/ 64 <75000000>;
695 required-opps = <&rpmhpd_opp_low_svs>;
699 opp-hz = /bits/ 64 <100000000>;
700 required-opps = <&rpmhpd_opp_svs>;
704 opp-hz = /bits/ 64 <128000000>;
705 required-opps = <&rpmhpd_opp_nom>;
710 compatible = "arm,armv8-pmuv3";
711 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
715 compatible = "arm,psci-1.0";
718 CPU_PD0: power-domain-cpu0 {
719 #power-domain-cells = <0>;
720 power-domains = <&CLUSTER_PD>;
721 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
724 CPU_PD1: power-domain-cpu1 {
725 #power-domain-cells = <0>;
726 power-domains = <&CLUSTER_PD>;
727 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
730 CPU_PD2: power-domain-cpu2 {
731 #power-domain-cells = <0>;
732 power-domains = <&CLUSTER_PD>;
733 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
736 CPU_PD3: power-domain-cpu3 {
737 #power-domain-cells = <0>;
738 power-domains = <&CLUSTER_PD>;
739 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
742 CPU_PD4: power-domain-cpu4 {
743 #power-domain-cells = <0>;
744 power-domains = <&CLUSTER_PD>;
745 domain-idle-states = <&BIG_CPU_SLEEP_0>;
748 CPU_PD5: power-domain-cpu5 {
749 #power-domain-cells = <0>;
750 power-domains = <&CLUSTER_PD>;
751 domain-idle-states = <&BIG_CPU_SLEEP_0>;
754 CPU_PD6: power-domain-cpu6 {
755 #power-domain-cells = <0>;
756 power-domains = <&CLUSTER_PD>;
757 domain-idle-states = <&BIG_CPU_SLEEP_0>;
760 CPU_PD7: power-domain-cpu7 {
761 #power-domain-cells = <0>;
762 power-domains = <&CLUSTER_PD>;
763 domain-idle-states = <&BIG_CPU_SLEEP_0>;
766 CLUSTER_PD: power-domain-cluster {
767 #power-domain-cells = <0>;
768 domain-idle-states = <&CLUSTER_SLEEP_0>;
773 #address-cells = <2>;
777 hyp_mem: hyp-mem@85700000 {
778 reg = <0 0x85700000 0 0x600000>;
782 xbl_mem: xbl-mem@85e00000 {
783 reg = <0 0x85e00000 0 0x100000>;
787 aop_mem: aop-mem@85fc0000 {
788 reg = <0 0x85fc0000 0 0x20000>;
792 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
793 compatible = "qcom,cmd-db";
794 reg = <0x0 0x85fe0000 0 0x20000>;
799 compatible = "qcom,smem";
800 reg = <0x0 0x86000000 0 0x200000>;
802 hwlocks = <&tcsr_mutex 3>;
805 tz_mem: tz@86200000 {
806 reg = <0 0x86200000 0 0x2d00000>;
810 rmtfs_mem: rmtfs@88f00000 {
811 compatible = "qcom,rmtfs-mem";
812 reg = <0 0x88f00000 0 0x200000>;
815 qcom,client-id = <1>;
819 qseecom_mem: qseecom@8ab00000 {
820 reg = <0 0x8ab00000 0 0x1400000>;
824 camera_mem: camera-mem@8bf00000 {
825 reg = <0 0x8bf00000 0 0x500000>;
829 ipa_fw_mem: ipa-fw@8c400000 {
830 reg = <0 0x8c400000 0 0x10000>;
834 ipa_gsi_mem: ipa-gsi@8c410000 {
835 reg = <0 0x8c410000 0 0x5000>;
839 gpu_mem: gpu@8c415000 {
840 reg = <0 0x8c415000 0 0x2000>;
844 adsp_mem: adsp@8c500000 {
845 reg = <0 0x8c500000 0 0x1a00000>;
849 wlan_msa_mem: wlan-msa@8df00000 {
850 reg = <0 0x8df00000 0 0x100000>;
854 mpss_region: mpss@8e000000 {
855 reg = <0 0x8e000000 0 0x7800000>;
859 venus_mem: venus@95800000 {
860 reg = <0 0x95800000 0 0x500000>;
864 cdsp_mem: cdsp@95d00000 {
865 reg = <0 0x95d00000 0 0x800000>;
869 mba_region: mba@96500000 {
870 reg = <0 0x96500000 0 0x200000>;
874 slpi_mem: slpi@96700000 {
875 reg = <0 0x96700000 0 0x1400000>;
879 spss_mem: spss@97b00000 {
880 reg = <0 0x97b00000 0 0x100000>;
884 mdata_mem: mpss-metadata {
885 alloc-ranges = <0 0xa0000000 0 0x20000000>;
890 fastrpc_mem: fastrpc {
891 compatible = "shared-dma-pool";
892 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
893 alignment = <0x0 0x400000>;
894 size = <0x0 0x1000000>;
899 adsp_pas: remoteproc-adsp {
900 compatible = "qcom,sdm845-adsp-pas";
902 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
903 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
904 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
907 interrupt-names = "wdog", "fatal", "ready",
908 "handover", "stop-ack";
910 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 memory-region = <&adsp_mem>;
915 qcom,qmp = <&aoss_qmp>;
917 qcom,smem-states = <&adsp_smp2p_out 0>;
918 qcom,smem-state-names = "stop";
923 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
925 qcom,remote-pid = <2>;
926 mboxes = <&apss_shared 8>;
929 compatible = "qcom,apr-v2";
930 qcom,glink-channels = "apr_audio_svc";
931 qcom,domain = <APR_DOMAIN_ADSP>;
932 #address-cells = <1>;
934 qcom,intents = <512 20>;
937 reg = <APR_SVC_ADSP_CORE>;
938 compatible = "qcom,q6core";
939 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
943 compatible = "qcom,q6afe";
945 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
947 compatible = "qcom,q6afe-dais";
948 #address-cells = <1>;
950 #sound-dai-cells = <1>;
955 compatible = "qcom,q6asm";
957 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
959 compatible = "qcom,q6asm-dais";
960 #address-cells = <1>;
962 #sound-dai-cells = <1>;
963 iommus = <&apps_smmu 0x1821 0x0>;
968 compatible = "qcom,q6adm";
970 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
972 compatible = "qcom,q6adm-routing";
973 #sound-dai-cells = <0>;
979 compatible = "qcom,fastrpc";
980 qcom,glink-channels = "fastrpcglink-apps-dsp";
982 qcom,non-secure-domain;
983 #address-cells = <1>;
987 compatible = "qcom,fastrpc-compute-cb";
989 iommus = <&apps_smmu 0x1823 0x0>;
993 compatible = "qcom,fastrpc-compute-cb";
995 iommus = <&apps_smmu 0x1824 0x0>;
1001 cdsp_pas: remoteproc-cdsp {
1002 compatible = "qcom,sdm845-cdsp-pas";
1004 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1005 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1006 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1009 interrupt-names = "wdog", "fatal", "ready",
1010 "handover", "stop-ack";
1012 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 memory-region = <&cdsp_mem>;
1017 qcom,qmp = <&aoss_qmp>;
1019 qcom,smem-states = <&cdsp_smp2p_out 0>;
1020 qcom,smem-state-names = "stop";
1022 status = "disabled";
1025 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1027 qcom,remote-pid = <5>;
1028 mboxes = <&apss_shared 4>;
1030 compatible = "qcom,fastrpc";
1031 qcom,glink-channels = "fastrpcglink-apps-dsp";
1033 qcom,non-secure-domain;
1034 #address-cells = <1>;
1038 compatible = "qcom,fastrpc-compute-cb";
1040 iommus = <&apps_smmu 0x1401 0x30>;
1044 compatible = "qcom,fastrpc-compute-cb";
1046 iommus = <&apps_smmu 0x1402 0x30>;
1050 compatible = "qcom,fastrpc-compute-cb";
1052 iommus = <&apps_smmu 0x1403 0x30>;
1056 compatible = "qcom,fastrpc-compute-cb";
1058 iommus = <&apps_smmu 0x1404 0x30>;
1062 compatible = "qcom,fastrpc-compute-cb";
1064 iommus = <&apps_smmu 0x1405 0x30>;
1068 compatible = "qcom,fastrpc-compute-cb";
1070 iommus = <&apps_smmu 0x1406 0x30>;
1074 compatible = "qcom,fastrpc-compute-cb";
1076 iommus = <&apps_smmu 0x1407 0x30>;
1080 compatible = "qcom,fastrpc-compute-cb";
1082 iommus = <&apps_smmu 0x1408 0x30>;
1089 compatible = "qcom,smp2p";
1090 qcom,smem = <94>, <432>;
1092 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1094 mboxes = <&apss_shared 6>;
1096 qcom,local-pid = <0>;
1097 qcom,remote-pid = <5>;
1099 cdsp_smp2p_out: master-kernel {
1100 qcom,entry-name = "master-kernel";
1101 #qcom,smem-state-cells = <1>;
1104 cdsp_smp2p_in: slave-kernel {
1105 qcom,entry-name = "slave-kernel";
1107 interrupt-controller;
1108 #interrupt-cells = <2>;
1113 compatible = "qcom,smp2p";
1114 qcom,smem = <443>, <429>;
1116 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1118 mboxes = <&apss_shared 10>;
1120 qcom,local-pid = <0>;
1121 qcom,remote-pid = <2>;
1123 adsp_smp2p_out: master-kernel {
1124 qcom,entry-name = "master-kernel";
1125 #qcom,smem-state-cells = <1>;
1128 adsp_smp2p_in: slave-kernel {
1129 qcom,entry-name = "slave-kernel";
1131 interrupt-controller;
1132 #interrupt-cells = <2>;
1137 compatible = "qcom,smp2p";
1138 qcom,smem = <435>, <428>;
1139 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1140 mboxes = <&apss_shared 14>;
1141 qcom,local-pid = <0>;
1142 qcom,remote-pid = <1>;
1144 modem_smp2p_out: master-kernel {
1145 qcom,entry-name = "master-kernel";
1146 #qcom,smem-state-cells = <1>;
1149 modem_smp2p_in: slave-kernel {
1150 qcom,entry-name = "slave-kernel";
1151 interrupt-controller;
1152 #interrupt-cells = <2>;
1155 ipa_smp2p_out: ipa-ap-to-modem {
1156 qcom,entry-name = "ipa";
1157 #qcom,smem-state-cells = <1>;
1160 ipa_smp2p_in: ipa-modem-to-ap {
1161 qcom,entry-name = "ipa";
1162 interrupt-controller;
1163 #interrupt-cells = <2>;
1168 compatible = "qcom,smp2p";
1169 qcom,smem = <481>, <430>;
1170 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1171 mboxes = <&apss_shared 26>;
1172 qcom,local-pid = <0>;
1173 qcom,remote-pid = <3>;
1175 slpi_smp2p_out: master-kernel {
1176 qcom,entry-name = "master-kernel";
1177 #qcom,smem-state-cells = <1>;
1180 slpi_smp2p_in: slave-kernel {
1181 qcom,entry-name = "slave-kernel";
1182 interrupt-controller;
1183 #interrupt-cells = <2>;
1188 #address-cells = <2>;
1190 ranges = <0 0 0 0 0x10 0>;
1191 dma-ranges = <0 0 0 0 0x10 0>;
1192 compatible = "simple-bus";
1194 gcc: clock-controller@100000 {
1195 compatible = "qcom,gcc-sdm845";
1196 reg = <0 0x00100000 0 0x1f0000>;
1197 clocks = <&rpmhcc RPMH_CXO_CLK>,
1198 <&rpmhcc RPMH_CXO_CLK_A>,
1202 clock-names = "bi_tcxo",
1209 #power-domain-cells = <1>;
1213 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1214 reg = <0 0x00784000 0 0x8ff>;
1215 #address-cells = <1>;
1218 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1223 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1230 compatible = "qcom,prng-ee";
1231 reg = <0 0x00793000 0 0x1000>;
1232 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1233 clock-names = "core";
1236 gpi_dma0: dma-controller@800000 {
1238 compatible = "qcom,sdm845-gpi-dma";
1239 reg = <0 0x00800000 0 0x60000>;
1240 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1253 dma-channels = <13>;
1254 dma-channel-mask = <0xfa>;
1255 iommus = <&apps_smmu 0x0016 0x0>;
1256 status = "disabled";
1259 qupv3_id_0: geniqup@8c0000 {
1260 compatible = "qcom,geni-se-qup";
1261 reg = <0 0x008c0000 0 0x6000>;
1262 clock-names = "m-ahb", "s-ahb";
1263 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1264 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1265 iommus = <&apps_smmu 0x3 0x0>;
1266 #address-cells = <2>;
1269 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1270 interconnect-names = "qup-core";
1271 status = "disabled";
1274 compatible = "qcom,geni-i2c";
1275 reg = <0 0x00880000 0 0x4000>;
1277 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&qup_i2c0_default>;
1280 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1281 #address-cells = <1>;
1283 power-domains = <&rpmhpd SDM845_CX>;
1284 operating-points-v2 = <&qup_opp_table>;
1285 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1286 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1287 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1288 interconnect-names = "qup-core", "qup-config", "qup-memory";
1289 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1290 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1291 dma-names = "tx", "rx";
1292 status = "disabled";
1296 compatible = "qcom,geni-spi";
1297 reg = <0 0x00880000 0 0x4000>;
1299 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1300 pinctrl-names = "default";
1301 pinctrl-0 = <&qup_spi0_default>;
1302 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1303 #address-cells = <1>;
1305 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1306 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1307 interconnect-names = "qup-core", "qup-config";
1308 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1309 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1310 dma-names = "tx", "rx";
1311 status = "disabled";
1314 uart0: serial@880000 {
1315 compatible = "qcom,geni-uart";
1316 reg = <0 0x00880000 0 0x4000>;
1318 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1319 pinctrl-names = "default";
1320 pinctrl-0 = <&qup_uart0_default>;
1321 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1322 power-domains = <&rpmhpd SDM845_CX>;
1323 operating-points-v2 = <&qup_opp_table>;
1324 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1325 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1326 interconnect-names = "qup-core", "qup-config";
1327 status = "disabled";
1331 compatible = "qcom,geni-i2c";
1332 reg = <0 0x00884000 0 0x4000>;
1334 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1335 pinctrl-names = "default";
1336 pinctrl-0 = <&qup_i2c1_default>;
1337 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1338 #address-cells = <1>;
1340 power-domains = <&rpmhpd SDM845_CX>;
1341 operating-points-v2 = <&qup_opp_table>;
1342 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1343 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1344 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1345 interconnect-names = "qup-core", "qup-config", "qup-memory";
1346 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1347 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1348 dma-names = "tx", "rx";
1349 status = "disabled";
1353 compatible = "qcom,geni-spi";
1354 reg = <0 0x00884000 0 0x4000>;
1356 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&qup_spi1_default>;
1359 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1360 #address-cells = <1>;
1362 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1363 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1364 interconnect-names = "qup-core", "qup-config";
1365 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1366 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1367 dma-names = "tx", "rx";
1368 status = "disabled";
1371 uart1: serial@884000 {
1372 compatible = "qcom,geni-uart";
1373 reg = <0 0x00884000 0 0x4000>;
1375 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1376 pinctrl-names = "default";
1377 pinctrl-0 = <&qup_uart1_default>;
1378 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1379 power-domains = <&rpmhpd SDM845_CX>;
1380 operating-points-v2 = <&qup_opp_table>;
1381 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1382 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1383 interconnect-names = "qup-core", "qup-config";
1384 status = "disabled";
1388 compatible = "qcom,geni-i2c";
1389 reg = <0 0x00888000 0 0x4000>;
1391 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1392 pinctrl-names = "default";
1393 pinctrl-0 = <&qup_i2c2_default>;
1394 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1395 #address-cells = <1>;
1397 power-domains = <&rpmhpd SDM845_CX>;
1398 operating-points-v2 = <&qup_opp_table>;
1399 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1400 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1401 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1402 interconnect-names = "qup-core", "qup-config", "qup-memory";
1403 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1404 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1405 dma-names = "tx", "rx";
1406 status = "disabled";
1410 compatible = "qcom,geni-spi";
1411 reg = <0 0x00888000 0 0x4000>;
1413 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1414 pinctrl-names = "default";
1415 pinctrl-0 = <&qup_spi2_default>;
1416 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1417 #address-cells = <1>;
1419 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1420 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1421 interconnect-names = "qup-core", "qup-config";
1422 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1423 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1424 dma-names = "tx", "rx";
1425 status = "disabled";
1428 uart2: serial@888000 {
1429 compatible = "qcom,geni-uart";
1430 reg = <0 0x00888000 0 0x4000>;
1432 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1433 pinctrl-names = "default";
1434 pinctrl-0 = <&qup_uart2_default>;
1435 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1436 power-domains = <&rpmhpd SDM845_CX>;
1437 operating-points-v2 = <&qup_opp_table>;
1438 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1439 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1440 interconnect-names = "qup-core", "qup-config";
1441 status = "disabled";
1445 compatible = "qcom,geni-i2c";
1446 reg = <0 0x0088c000 0 0x4000>;
1448 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1449 pinctrl-names = "default";
1450 pinctrl-0 = <&qup_i2c3_default>;
1451 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1452 #address-cells = <1>;
1454 power-domains = <&rpmhpd SDM845_CX>;
1455 operating-points-v2 = <&qup_opp_table>;
1456 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1457 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1458 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1459 interconnect-names = "qup-core", "qup-config", "qup-memory";
1460 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1461 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1462 dma-names = "tx", "rx";
1463 status = "disabled";
1467 compatible = "qcom,geni-spi";
1468 reg = <0 0x0088c000 0 0x4000>;
1470 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1471 pinctrl-names = "default";
1472 pinctrl-0 = <&qup_spi3_default>;
1473 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1474 #address-cells = <1>;
1476 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1477 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1478 interconnect-names = "qup-core", "qup-config";
1479 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1480 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1481 dma-names = "tx", "rx";
1482 status = "disabled";
1485 uart3: serial@88c000 {
1486 compatible = "qcom,geni-uart";
1487 reg = <0 0x0088c000 0 0x4000>;
1489 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1490 pinctrl-names = "default";
1491 pinctrl-0 = <&qup_uart3_default>;
1492 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1493 power-domains = <&rpmhpd SDM845_CX>;
1494 operating-points-v2 = <&qup_opp_table>;
1495 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1496 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1497 interconnect-names = "qup-core", "qup-config";
1498 status = "disabled";
1502 compatible = "qcom,geni-i2c";
1503 reg = <0 0x00890000 0 0x4000>;
1505 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1506 pinctrl-names = "default";
1507 pinctrl-0 = <&qup_i2c4_default>;
1508 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1509 #address-cells = <1>;
1511 power-domains = <&rpmhpd SDM845_CX>;
1512 operating-points-v2 = <&qup_opp_table>;
1513 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1514 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1515 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1516 interconnect-names = "qup-core", "qup-config", "qup-memory";
1517 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1518 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1519 dma-names = "tx", "rx";
1520 status = "disabled";
1524 compatible = "qcom,geni-spi";
1525 reg = <0 0x00890000 0 0x4000>;
1527 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1528 pinctrl-names = "default";
1529 pinctrl-0 = <&qup_spi4_default>;
1530 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1531 #address-cells = <1>;
1533 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1534 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1535 interconnect-names = "qup-core", "qup-config";
1536 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1537 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1538 dma-names = "tx", "rx";
1539 status = "disabled";
1542 uart4: serial@890000 {
1543 compatible = "qcom,geni-uart";
1544 reg = <0 0x00890000 0 0x4000>;
1546 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1547 pinctrl-names = "default";
1548 pinctrl-0 = <&qup_uart4_default>;
1549 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1550 power-domains = <&rpmhpd SDM845_CX>;
1551 operating-points-v2 = <&qup_opp_table>;
1552 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1553 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1554 interconnect-names = "qup-core", "qup-config";
1555 status = "disabled";
1559 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00894000 0 0x4000>;
1562 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1563 pinctrl-names = "default";
1564 pinctrl-0 = <&qup_i2c5_default>;
1565 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1566 #address-cells = <1>;
1568 power-domains = <&rpmhpd SDM845_CX>;
1569 operating-points-v2 = <&qup_opp_table>;
1570 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1571 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1572 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1573 interconnect-names = "qup-core", "qup-config", "qup-memory";
1574 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1575 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1576 dma-names = "tx", "rx";
1577 status = "disabled";
1581 compatible = "qcom,geni-spi";
1582 reg = <0 0x00894000 0 0x4000>;
1584 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1585 pinctrl-names = "default";
1586 pinctrl-0 = <&qup_spi5_default>;
1587 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1588 #address-cells = <1>;
1590 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1591 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1592 interconnect-names = "qup-core", "qup-config";
1593 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1594 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1595 dma-names = "tx", "rx";
1596 status = "disabled";
1599 uart5: serial@894000 {
1600 compatible = "qcom,geni-uart";
1601 reg = <0 0x00894000 0 0x4000>;
1603 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1604 pinctrl-names = "default";
1605 pinctrl-0 = <&qup_uart5_default>;
1606 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1607 power-domains = <&rpmhpd SDM845_CX>;
1608 operating-points-v2 = <&qup_opp_table>;
1609 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1610 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1611 interconnect-names = "qup-core", "qup-config";
1612 status = "disabled";
1616 compatible = "qcom,geni-i2c";
1617 reg = <0 0x00898000 0 0x4000>;
1619 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1620 pinctrl-names = "default";
1621 pinctrl-0 = <&qup_i2c6_default>;
1622 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1623 #address-cells = <1>;
1625 power-domains = <&rpmhpd SDM845_CX>;
1626 operating-points-v2 = <&qup_opp_table>;
1627 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1628 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1629 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1630 interconnect-names = "qup-core", "qup-config", "qup-memory";
1631 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1632 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1633 dma-names = "tx", "rx";
1634 status = "disabled";
1638 compatible = "qcom,geni-spi";
1639 reg = <0 0x00898000 0 0x4000>;
1641 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1642 pinctrl-names = "default";
1643 pinctrl-0 = <&qup_spi6_default>;
1644 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1645 #address-cells = <1>;
1647 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1648 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1649 interconnect-names = "qup-core", "qup-config";
1650 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1651 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1652 dma-names = "tx", "rx";
1653 status = "disabled";
1656 uart6: serial@898000 {
1657 compatible = "qcom,geni-uart";
1658 reg = <0 0x00898000 0 0x4000>;
1660 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1661 pinctrl-names = "default";
1662 pinctrl-0 = <&qup_uart6_default>;
1663 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1664 power-domains = <&rpmhpd SDM845_CX>;
1665 operating-points-v2 = <&qup_opp_table>;
1666 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1667 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1668 interconnect-names = "qup-core", "qup-config";
1669 status = "disabled";
1673 compatible = "qcom,geni-i2c";
1674 reg = <0 0x0089c000 0 0x4000>;
1676 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1677 pinctrl-names = "default";
1678 pinctrl-0 = <&qup_i2c7_default>;
1679 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1680 #address-cells = <1>;
1682 power-domains = <&rpmhpd SDM845_CX>;
1683 operating-points-v2 = <&qup_opp_table>;
1684 status = "disabled";
1688 compatible = "qcom,geni-spi";
1689 reg = <0 0x0089c000 0 0x4000>;
1691 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1692 pinctrl-names = "default";
1693 pinctrl-0 = <&qup_spi7_default>;
1694 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1695 #address-cells = <1>;
1697 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1698 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1699 interconnect-names = "qup-core", "qup-config";
1700 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1701 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1702 dma-names = "tx", "rx";
1703 status = "disabled";
1706 uart7: serial@89c000 {
1707 compatible = "qcom,geni-uart";
1708 reg = <0 0x0089c000 0 0x4000>;
1710 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1711 pinctrl-names = "default";
1712 pinctrl-0 = <&qup_uart7_default>;
1713 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1714 power-domains = <&rpmhpd SDM845_CX>;
1715 operating-points-v2 = <&qup_opp_table>;
1716 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1717 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1718 interconnect-names = "qup-core", "qup-config";
1719 status = "disabled";
1723 gpi_dma1: dma-controller@a00000 {
1725 compatible = "qcom,sdm845-gpi-dma";
1726 reg = <0 0x00a00000 0 0x60000>;
1727 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1728 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1729 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1730 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1740 dma-channels = <13>;
1741 dma-channel-mask = <0xfa>;
1742 iommus = <&apps_smmu 0x06d6 0x0>;
1743 status = "disabled";
1746 qupv3_id_1: geniqup@ac0000 {
1747 compatible = "qcom,geni-se-qup";
1748 reg = <0 0x00ac0000 0 0x6000>;
1749 clock-names = "m-ahb", "s-ahb";
1750 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1751 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1752 iommus = <&apps_smmu 0x6c3 0x0>;
1753 #address-cells = <2>;
1756 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1757 interconnect-names = "qup-core";
1758 status = "disabled";
1761 compatible = "qcom,geni-i2c";
1762 reg = <0 0x00a80000 0 0x4000>;
1764 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1765 pinctrl-names = "default";
1766 pinctrl-0 = <&qup_i2c8_default>;
1767 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1768 #address-cells = <1>;
1770 power-domains = <&rpmhpd SDM845_CX>;
1771 operating-points-v2 = <&qup_opp_table>;
1772 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1773 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1774 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1775 interconnect-names = "qup-core", "qup-config", "qup-memory";
1776 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1777 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1778 dma-names = "tx", "rx";
1779 status = "disabled";
1783 compatible = "qcom,geni-spi";
1784 reg = <0 0x00a80000 0 0x4000>;
1786 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1787 pinctrl-names = "default";
1788 pinctrl-0 = <&qup_spi8_default>;
1789 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1790 #address-cells = <1>;
1792 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1793 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1794 interconnect-names = "qup-core", "qup-config";
1795 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1796 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1797 dma-names = "tx", "rx";
1798 status = "disabled";
1801 uart8: serial@a80000 {
1802 compatible = "qcom,geni-uart";
1803 reg = <0 0x00a80000 0 0x4000>;
1805 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1806 pinctrl-names = "default";
1807 pinctrl-0 = <&qup_uart8_default>;
1808 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1809 power-domains = <&rpmhpd SDM845_CX>;
1810 operating-points-v2 = <&qup_opp_table>;
1811 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1812 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1813 interconnect-names = "qup-core", "qup-config";
1814 status = "disabled";
1818 compatible = "qcom,geni-i2c";
1819 reg = <0 0x00a84000 0 0x4000>;
1821 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1822 pinctrl-names = "default";
1823 pinctrl-0 = <&qup_i2c9_default>;
1824 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1825 #address-cells = <1>;
1827 power-domains = <&rpmhpd SDM845_CX>;
1828 operating-points-v2 = <&qup_opp_table>;
1829 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1830 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1831 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1832 interconnect-names = "qup-core", "qup-config", "qup-memory";
1833 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1834 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1835 dma-names = "tx", "rx";
1836 status = "disabled";
1840 compatible = "qcom,geni-spi";
1841 reg = <0 0x00a84000 0 0x4000>;
1843 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1844 pinctrl-names = "default";
1845 pinctrl-0 = <&qup_spi9_default>;
1846 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1847 #address-cells = <1>;
1849 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1850 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1851 interconnect-names = "qup-core", "qup-config";
1852 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1853 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1854 dma-names = "tx", "rx";
1855 status = "disabled";
1858 uart9: serial@a84000 {
1859 compatible = "qcom,geni-debug-uart";
1860 reg = <0 0x00a84000 0 0x4000>;
1862 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1863 pinctrl-names = "default";
1864 pinctrl-0 = <&qup_uart9_default>;
1865 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1866 power-domains = <&rpmhpd SDM845_CX>;
1867 operating-points-v2 = <&qup_opp_table>;
1868 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1869 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1870 interconnect-names = "qup-core", "qup-config";
1871 status = "disabled";
1875 compatible = "qcom,geni-i2c";
1876 reg = <0 0x00a88000 0 0x4000>;
1878 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1879 pinctrl-names = "default";
1880 pinctrl-0 = <&qup_i2c10_default>;
1881 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1882 #address-cells = <1>;
1884 power-domains = <&rpmhpd SDM845_CX>;
1885 operating-points-v2 = <&qup_opp_table>;
1886 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1887 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1888 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1889 interconnect-names = "qup-core", "qup-config", "qup-memory";
1890 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1891 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1892 dma-names = "tx", "rx";
1893 status = "disabled";
1897 compatible = "qcom,geni-spi";
1898 reg = <0 0x00a88000 0 0x4000>;
1900 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1901 pinctrl-names = "default";
1902 pinctrl-0 = <&qup_spi10_default>;
1903 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1904 #address-cells = <1>;
1906 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1907 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1908 interconnect-names = "qup-core", "qup-config";
1909 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1910 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1911 dma-names = "tx", "rx";
1912 status = "disabled";
1915 uart10: serial@a88000 {
1916 compatible = "qcom,geni-uart";
1917 reg = <0 0x00a88000 0 0x4000>;
1919 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1920 pinctrl-names = "default";
1921 pinctrl-0 = <&qup_uart10_default>;
1922 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1923 power-domains = <&rpmhpd SDM845_CX>;
1924 operating-points-v2 = <&qup_opp_table>;
1925 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1926 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1927 interconnect-names = "qup-core", "qup-config";
1928 status = "disabled";
1932 compatible = "qcom,geni-i2c";
1933 reg = <0 0x00a8c000 0 0x4000>;
1935 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1936 pinctrl-names = "default";
1937 pinctrl-0 = <&qup_i2c11_default>;
1938 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1939 #address-cells = <1>;
1941 power-domains = <&rpmhpd SDM845_CX>;
1942 operating-points-v2 = <&qup_opp_table>;
1943 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1944 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1945 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1946 interconnect-names = "qup-core", "qup-config", "qup-memory";
1947 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1948 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1949 dma-names = "tx", "rx";
1950 status = "disabled";
1954 compatible = "qcom,geni-spi";
1955 reg = <0 0x00a8c000 0 0x4000>;
1957 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1958 pinctrl-names = "default";
1959 pinctrl-0 = <&qup_spi11_default>;
1960 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1961 #address-cells = <1>;
1963 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1964 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1965 interconnect-names = "qup-core", "qup-config";
1966 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1967 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1968 dma-names = "tx", "rx";
1969 status = "disabled";
1972 uart11: serial@a8c000 {
1973 compatible = "qcom,geni-uart";
1974 reg = <0 0x00a8c000 0 0x4000>;
1976 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1977 pinctrl-names = "default";
1978 pinctrl-0 = <&qup_uart11_default>;
1979 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1980 power-domains = <&rpmhpd SDM845_CX>;
1981 operating-points-v2 = <&qup_opp_table>;
1982 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1983 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1984 interconnect-names = "qup-core", "qup-config";
1985 status = "disabled";
1989 compatible = "qcom,geni-i2c";
1990 reg = <0 0x00a90000 0 0x4000>;
1992 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1993 pinctrl-names = "default";
1994 pinctrl-0 = <&qup_i2c12_default>;
1995 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1996 #address-cells = <1>;
1998 power-domains = <&rpmhpd SDM845_CX>;
1999 operating-points-v2 = <&qup_opp_table>;
2000 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2001 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2002 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2003 interconnect-names = "qup-core", "qup-config", "qup-memory";
2004 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2005 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
2006 dma-names = "tx", "rx";
2007 status = "disabled";
2011 compatible = "qcom,geni-spi";
2012 reg = <0 0x00a90000 0 0x4000>;
2014 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2015 pinctrl-names = "default";
2016 pinctrl-0 = <&qup_spi12_default>;
2017 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2018 #address-cells = <1>;
2020 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2021 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2022 interconnect-names = "qup-core", "qup-config";
2023 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2024 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2025 dma-names = "tx", "rx";
2026 status = "disabled";
2029 uart12: serial@a90000 {
2030 compatible = "qcom,geni-uart";
2031 reg = <0 0x00a90000 0 0x4000>;
2033 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2034 pinctrl-names = "default";
2035 pinctrl-0 = <&qup_uart12_default>;
2036 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2037 power-domains = <&rpmhpd SDM845_CX>;
2038 operating-points-v2 = <&qup_opp_table>;
2039 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2040 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2041 interconnect-names = "qup-core", "qup-config";
2042 status = "disabled";
2046 compatible = "qcom,geni-i2c";
2047 reg = <0 0x00a94000 0 0x4000>;
2049 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2050 pinctrl-names = "default";
2051 pinctrl-0 = <&qup_i2c13_default>;
2052 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2053 #address-cells = <1>;
2055 power-domains = <&rpmhpd SDM845_CX>;
2056 operating-points-v2 = <&qup_opp_table>;
2057 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2058 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2059 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2060 interconnect-names = "qup-core", "qup-config", "qup-memory";
2061 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2062 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2063 dma-names = "tx", "rx";
2064 status = "disabled";
2068 compatible = "qcom,geni-spi";
2069 reg = <0 0x00a94000 0 0x4000>;
2071 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2072 pinctrl-names = "default";
2073 pinctrl-0 = <&qup_spi13_default>;
2074 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2075 #address-cells = <1>;
2077 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2078 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2079 interconnect-names = "qup-core", "qup-config";
2080 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2081 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2082 dma-names = "tx", "rx";
2083 status = "disabled";
2086 uart13: serial@a94000 {
2087 compatible = "qcom,geni-uart";
2088 reg = <0 0x00a94000 0 0x4000>;
2090 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2091 pinctrl-names = "default";
2092 pinctrl-0 = <&qup_uart13_default>;
2093 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2094 power-domains = <&rpmhpd SDM845_CX>;
2095 operating-points-v2 = <&qup_opp_table>;
2096 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2097 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2098 interconnect-names = "qup-core", "qup-config";
2099 status = "disabled";
2103 compatible = "qcom,geni-i2c";
2104 reg = <0 0x00a98000 0 0x4000>;
2106 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2107 pinctrl-names = "default";
2108 pinctrl-0 = <&qup_i2c14_default>;
2109 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2110 #address-cells = <1>;
2112 power-domains = <&rpmhpd SDM845_CX>;
2113 operating-points-v2 = <&qup_opp_table>;
2114 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2115 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2116 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2117 interconnect-names = "qup-core", "qup-config", "qup-memory";
2118 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2119 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2120 dma-names = "tx", "rx";
2121 status = "disabled";
2125 compatible = "qcom,geni-spi";
2126 reg = <0 0x00a98000 0 0x4000>;
2128 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2129 pinctrl-names = "default";
2130 pinctrl-0 = <&qup_spi14_default>;
2131 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2132 #address-cells = <1>;
2134 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2135 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2136 interconnect-names = "qup-core", "qup-config";
2137 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2138 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2139 dma-names = "tx", "rx";
2140 status = "disabled";
2143 uart14: serial@a98000 {
2144 compatible = "qcom,geni-uart";
2145 reg = <0 0x00a98000 0 0x4000>;
2147 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2148 pinctrl-names = "default";
2149 pinctrl-0 = <&qup_uart14_default>;
2150 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2151 power-domains = <&rpmhpd SDM845_CX>;
2152 operating-points-v2 = <&qup_opp_table>;
2153 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2154 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2155 interconnect-names = "qup-core", "qup-config";
2156 status = "disabled";
2160 compatible = "qcom,geni-i2c";
2161 reg = <0 0x00a9c000 0 0x4000>;
2163 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2164 pinctrl-names = "default";
2165 pinctrl-0 = <&qup_i2c15_default>;
2166 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2167 #address-cells = <1>;
2169 power-domains = <&rpmhpd SDM845_CX>;
2170 operating-points-v2 = <&qup_opp_table>;
2171 status = "disabled";
2172 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2173 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2174 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2175 interconnect-names = "qup-core", "qup-config", "qup-memory";
2176 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2177 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2178 dma-names = "tx", "rx";
2182 compatible = "qcom,geni-spi";
2183 reg = <0 0x00a9c000 0 0x4000>;
2185 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2186 pinctrl-names = "default";
2187 pinctrl-0 = <&qup_spi15_default>;
2188 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2189 #address-cells = <1>;
2191 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2192 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2193 interconnect-names = "qup-core", "qup-config";
2194 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2195 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2196 dma-names = "tx", "rx";
2197 status = "disabled";
2200 uart15: serial@a9c000 {
2201 compatible = "qcom,geni-uart";
2202 reg = <0 0x00a9c000 0 0x4000>;
2204 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2205 pinctrl-names = "default";
2206 pinctrl-0 = <&qup_uart15_default>;
2207 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2208 power-domains = <&rpmhpd SDM845_CX>;
2209 operating-points-v2 = <&qup_opp_table>;
2210 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2211 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2212 interconnect-names = "qup-core", "qup-config";
2213 status = "disabled";
2217 llcc: system-cache-controller@1100000 {
2218 compatible = "qcom,sdm845-llcc";
2219 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2220 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2221 <0 0x01300000 0 0x50000>;
2222 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2223 "llcc3_base", "llcc_broadcast_base";
2224 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 compatible = "qcom,sdm845-dcc", "qcom,dcc";
2229 reg = <0x0 0x010a2000 0x0 0x1000>,
2230 <0x0 0x010ae000 0x0 0x2000>;
2234 compatible = "qcom,sdm845-llcc-bwmon";
2235 reg = <0 0x0114a000 0 0x1000>;
2236 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2237 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2239 operating-points-v2 = <&llcc_bwmon_opp_table>;
2241 llcc_bwmon_opp_table: opp-table {
2242 compatible = "operating-points-v2";
2245 * The interconnect path bandwidth taken from
2246 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2247 * interconnect. This also matches the
2248 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2249 * bus width: 4 bytes) from msm-4.9 downstream
2253 opp-peak-kBps = <800000>;
2256 opp-peak-kBps = <1804000>;
2259 opp-peak-kBps = <3072000>;
2262 opp-peak-kBps = <5412000>;
2265 opp-peak-kBps = <7216000>;
2271 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2272 reg = <0 0x01436400 0 0x600>;
2273 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2274 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
2276 operating-points-v2 = <&cpu_bwmon_opp_table>;
2278 cpu_bwmon_opp_table: opp-table {
2279 compatible = "operating-points-v2";
2282 * The interconnect path bandwidth taken from
2283 * cpu4_opp_table bandwidth for OSM L3
2284 * interconnect. This also matches the OSM L3
2285 * from bandwidth table of qcom,cpu4-l3lat-mon
2286 * (qcom,core-dev-table, bus width: 16 bytes)
2287 * from msm-4.9 downstream kernel.
2290 opp-peak-kBps = <4800000>;
2293 opp-peak-kBps = <9216000>;
2296 opp-peak-kBps = <15052800>;
2299 opp-peak-kBps = <20889600>;
2302 opp-peak-kBps = <25497600>;
2307 pcie0: pci@1c00000 {
2308 compatible = "qcom,pcie-sdm845";
2309 reg = <0 0x01c00000 0 0x2000>,
2310 <0 0x60000000 0 0xf1d>,
2311 <0 0x60000f20 0 0xa8>,
2312 <0 0x60100000 0 0x100000>,
2313 <0 0x01c07000 0 0x1000>;
2314 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2315 device_type = "pci";
2316 linux,pci-domain = <0>;
2317 bus-range = <0x00 0xff>;
2320 #address-cells = <3>;
2323 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2324 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2326 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2327 interrupt-names = "msi";
2328 #interrupt-cells = <1>;
2329 interrupt-map-mask = <0 0 0 0x7>;
2330 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2331 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2332 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2333 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2335 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2336 <&gcc GCC_PCIE_0_AUX_CLK>,
2337 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2338 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2339 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2340 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2341 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2342 clock-names = "pipe",
2350 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2351 <0x100 &apps_smmu 0x1c11 0x1>,
2352 <0x200 &apps_smmu 0x1c12 0x1>,
2353 <0x300 &apps_smmu 0x1c13 0x1>,
2354 <0x400 &apps_smmu 0x1c14 0x1>,
2355 <0x500 &apps_smmu 0x1c15 0x1>,
2356 <0x600 &apps_smmu 0x1c16 0x1>,
2357 <0x700 &apps_smmu 0x1c17 0x1>,
2358 <0x800 &apps_smmu 0x1c18 0x1>,
2359 <0x900 &apps_smmu 0x1c19 0x1>,
2360 <0xa00 &apps_smmu 0x1c1a 0x1>,
2361 <0xb00 &apps_smmu 0x1c1b 0x1>,
2362 <0xc00 &apps_smmu 0x1c1c 0x1>,
2363 <0xd00 &apps_smmu 0x1c1d 0x1>,
2364 <0xe00 &apps_smmu 0x1c1e 0x1>,
2365 <0xf00 &apps_smmu 0x1c1f 0x1>;
2367 resets = <&gcc GCC_PCIE_0_BCR>;
2368 reset-names = "pci";
2370 power-domains = <&gcc PCIE_0_GDSC>;
2372 phys = <&pcie0_lane>;
2373 phy-names = "pciephy";
2375 status = "disabled";
2378 pcie0_phy: phy@1c06000 {
2379 compatible = "qcom,sdm845-qmp-pcie-phy";
2380 reg = <0 0x01c06000 0 0x18c>;
2381 #address-cells = <2>;
2384 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2385 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2386 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2387 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2388 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2390 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2391 reset-names = "phy";
2393 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2394 assigned-clock-rates = <100000000>;
2396 status = "disabled";
2398 pcie0_lane: phy@1c06200 {
2399 reg = <0 0x01c06200 0 0x128>,
2400 <0 0x01c06400 0 0x1fc>,
2401 <0 0x01c06800 0 0x218>,
2402 <0 0x01c06600 0 0x70>;
2403 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
2404 clock-names = "pipe0";
2408 clock-output-names = "pcie_0_pipe_clk";
2412 pcie1: pci@1c08000 {
2413 compatible = "qcom,pcie-sdm845";
2414 reg = <0 0x01c08000 0 0x2000>,
2415 <0 0x40000000 0 0xf1d>,
2416 <0 0x40000f20 0 0xa8>,
2417 <0 0x40100000 0 0x100000>,
2418 <0 0x01c0c000 0 0x1000>;
2419 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2420 device_type = "pci";
2421 linux,pci-domain = <1>;
2422 bus-range = <0x00 0xff>;
2425 #address-cells = <3>;
2428 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2429 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2431 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2432 interrupt-names = "msi";
2433 #interrupt-cells = <1>;
2434 interrupt-map-mask = <0 0 0 0x7>;
2435 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2436 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2437 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2438 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2440 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2441 <&gcc GCC_PCIE_1_AUX_CLK>,
2442 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2443 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2444 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2445 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2446 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2447 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2448 clock-names = "pipe",
2457 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2458 assigned-clock-rates = <19200000>;
2460 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2461 <0x100 &apps_smmu 0x1c01 0x1>,
2462 <0x200 &apps_smmu 0x1c02 0x1>,
2463 <0x300 &apps_smmu 0x1c03 0x1>,
2464 <0x400 &apps_smmu 0x1c04 0x1>,
2465 <0x500 &apps_smmu 0x1c05 0x1>,
2466 <0x600 &apps_smmu 0x1c06 0x1>,
2467 <0x700 &apps_smmu 0x1c07 0x1>,
2468 <0x800 &apps_smmu 0x1c08 0x1>,
2469 <0x900 &apps_smmu 0x1c09 0x1>,
2470 <0xa00 &apps_smmu 0x1c0a 0x1>,
2471 <0xb00 &apps_smmu 0x1c0b 0x1>,
2472 <0xc00 &apps_smmu 0x1c0c 0x1>,
2473 <0xd00 &apps_smmu 0x1c0d 0x1>,
2474 <0xe00 &apps_smmu 0x1c0e 0x1>,
2475 <0xf00 &apps_smmu 0x1c0f 0x1>;
2477 resets = <&gcc GCC_PCIE_1_BCR>;
2478 reset-names = "pci";
2480 power-domains = <&gcc PCIE_1_GDSC>;
2482 phys = <&pcie1_lane>;
2483 phy-names = "pciephy";
2485 status = "disabled";
2488 pcie1_phy: phy@1c0a000 {
2489 compatible = "qcom,sdm845-qhp-pcie-phy";
2490 reg = <0 0x01c0a000 0 0x800>;
2491 #address-cells = <2>;
2494 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2495 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2496 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2497 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2498 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2500 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2501 reset-names = "phy";
2503 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2504 assigned-clock-rates = <100000000>;
2506 status = "disabled";
2508 pcie1_lane: phy@1c06200 {
2509 reg = <0 0x01c0a800 0 0x800>,
2510 <0 0x01c0a800 0 0x800>,
2511 <0 0x01c0b800 0 0x400>;
2512 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2513 clock-names = "pipe0";
2517 clock-output-names = "pcie_1_pipe_clk";
2521 mem_noc: interconnect@1380000 {
2522 compatible = "qcom,sdm845-mem-noc";
2523 reg = <0 0x01380000 0 0x27200>;
2524 #interconnect-cells = <2>;
2525 qcom,bcm-voters = <&apps_bcm_voter>;
2528 dc_noc: interconnect@14e0000 {
2529 compatible = "qcom,sdm845-dc-noc";
2530 reg = <0 0x014e0000 0 0x400>;
2531 #interconnect-cells = <2>;
2532 qcom,bcm-voters = <&apps_bcm_voter>;
2535 config_noc: interconnect@1500000 {
2536 compatible = "qcom,sdm845-config-noc";
2537 reg = <0 0x01500000 0 0x5080>;
2538 #interconnect-cells = <2>;
2539 qcom,bcm-voters = <&apps_bcm_voter>;
2542 system_noc: interconnect@1620000 {
2543 compatible = "qcom,sdm845-system-noc";
2544 reg = <0 0x01620000 0 0x18080>;
2545 #interconnect-cells = <2>;
2546 qcom,bcm-voters = <&apps_bcm_voter>;
2549 aggre1_noc: interconnect@16e0000 {
2550 compatible = "qcom,sdm845-aggre1-noc";
2551 reg = <0 0x016e0000 0 0x15080>;
2552 #interconnect-cells = <2>;
2553 qcom,bcm-voters = <&apps_bcm_voter>;
2556 aggre2_noc: interconnect@1700000 {
2557 compatible = "qcom,sdm845-aggre2-noc";
2558 reg = <0 0x01700000 0 0x1f300>;
2559 #interconnect-cells = <2>;
2560 qcom,bcm-voters = <&apps_bcm_voter>;
2563 mmss_noc: interconnect@1740000 {
2564 compatible = "qcom,sdm845-mmss-noc";
2565 reg = <0 0x01740000 0 0x1c100>;
2566 #interconnect-cells = <2>;
2567 qcom,bcm-voters = <&apps_bcm_voter>;
2570 ufs_mem_hc: ufshc@1d84000 {
2571 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2573 reg = <0 0x01d84000 0 0x2500>,
2574 <0 0x01d90000 0 0x8000>;
2575 reg-names = "std", "ice";
2576 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2577 phys = <&ufs_mem_phy_lanes>;
2578 phy-names = "ufsphy";
2579 lanes-per-direction = <2>;
2580 power-domains = <&gcc UFS_PHY_GDSC>;
2582 resets = <&gcc GCC_UFS_PHY_BCR>;
2583 reset-names = "rst";
2585 iommus = <&apps_smmu 0x100 0xf>;
2593 "tx_lane0_sync_clk",
2594 "rx_lane0_sync_clk",
2595 "rx_lane1_sync_clk",
2598 <&gcc GCC_UFS_PHY_AXI_CLK>,
2599 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2600 <&gcc GCC_UFS_PHY_AHB_CLK>,
2601 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2602 <&rpmhcc RPMH_CXO_CLK>,
2603 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2604 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2605 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2606 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2608 <50000000 200000000>,
2611 <37500000 150000000>,
2618 status = "disabled";
2621 ufs_mem_phy: phy@1d87000 {
2622 compatible = "qcom,sdm845-qmp-ufs-phy";
2623 reg = <0 0x01d87000 0 0x18c>;
2624 #address-cells = <2>;
2627 clock-names = "ref",
2629 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2630 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2632 resets = <&ufs_mem_hc 0>;
2633 reset-names = "ufsphy";
2634 status = "disabled";
2636 ufs_mem_phy_lanes: phy@1d87400 {
2637 reg = <0 0x01d87400 0 0x108>,
2638 <0 0x01d87600 0 0x1e0>,
2639 <0 0x01d87c00 0 0x1dc>,
2640 <0 0x01d87800 0 0x108>,
2641 <0 0x01d87a00 0 0x1e0>;
2646 cryptobam: dma-controller@1dc4000 {
2647 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2648 reg = <0 0x01dc4000 0 0x24000>;
2649 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2650 clocks = <&rpmhcc RPMH_CE_CLK>;
2651 clock-names = "bam_clk";
2654 qcom,controlled-remotely;
2655 iommus = <&apps_smmu 0x704 0x1>,
2656 <&apps_smmu 0x706 0x1>,
2657 <&apps_smmu 0x714 0x1>,
2658 <&apps_smmu 0x716 0x1>;
2661 crypto: crypto@1dfa000 {
2662 compatible = "qcom,crypto-v5.4";
2663 reg = <0 0x01dfa000 0 0x6000>;
2664 clocks = <&gcc GCC_CE1_AHB_CLK>,
2665 <&gcc GCC_CE1_AXI_CLK>,
2666 <&rpmhcc RPMH_CE_CLK>;
2667 clock-names = "iface", "bus", "core";
2668 dmas = <&cryptobam 6>, <&cryptobam 7>;
2669 dma-names = "rx", "tx";
2670 iommus = <&apps_smmu 0x704 0x1>,
2671 <&apps_smmu 0x706 0x1>,
2672 <&apps_smmu 0x714 0x1>,
2673 <&apps_smmu 0x716 0x1>;
2677 compatible = "qcom,sdm845-ipa";
2679 iommus = <&apps_smmu 0x720 0x0>,
2680 <&apps_smmu 0x722 0x0>;
2681 reg = <0 0x01e40000 0 0x7000>,
2682 <0 0x01e47000 0 0x2000>,
2683 <0 0x01e04000 0 0x2c000>;
2684 reg-names = "ipa-reg",
2688 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2689 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2690 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2691 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2692 interrupt-names = "ipa",
2697 clocks = <&rpmhcc RPMH_IPA_CLK>;
2698 clock-names = "core";
2700 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2701 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2702 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2703 interconnect-names = "memory",
2707 qcom,smem-states = <&ipa_smp2p_out 0>,
2709 qcom,smem-state-names = "ipa-clock-enabled-valid",
2710 "ipa-clock-enabled";
2712 status = "disabled";
2715 tcsr_mutex: hwlock@1f40000 {
2716 compatible = "qcom,tcsr-mutex";
2717 reg = <0 0x01f40000 0 0x20000>;
2718 #hwlock-cells = <1>;
2721 tcsr_regs_1: syscon@1f60000 {
2722 compatible = "qcom,sdm845-tcsr", "syscon";
2723 reg = <0 0x01f60000 0 0x20000>;
2726 tlmm: pinctrl@3400000 {
2727 compatible = "qcom,sdm845-pinctrl";
2728 reg = <0 0x03400000 0 0xc00000>;
2729 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2732 interrupt-controller;
2733 #interrupt-cells = <2>;
2734 gpio-ranges = <&tlmm 0 0 151>;
2735 wakeup-parent = <&pdc_intc>;
2737 cci0_default: cci0-default-state {
2739 pins = "gpio17", "gpio18";
2740 function = "cci_i2c";
2743 drive-strength = <2>; /* 2 mA */
2746 cci0_sleep: cci0-sleep-state {
2748 pins = "gpio17", "gpio18";
2749 function = "cci_i2c";
2751 drive-strength = <2>; /* 2 mA */
2755 cci1_default: cci1-default-state {
2757 pins = "gpio19", "gpio20";
2758 function = "cci_i2c";
2761 drive-strength = <2>; /* 2 mA */
2764 cci1_sleep: cci1-sleep-state {
2766 pins = "gpio19", "gpio20";
2767 function = "cci_i2c";
2769 drive-strength = <2>; /* 2 mA */
2773 qspi_clk: qspi-clk-state {
2775 function = "qspi_clk";
2778 qspi_cs0: qspi-cs0-state {
2780 function = "qspi_cs";
2783 qspi_cs1: qspi-cs1-state {
2785 function = "qspi_cs";
2788 qspi_data0: qspi-data0-state {
2790 function = "qspi_data";
2793 qspi_data1: qspi-data1-state {
2795 function = "qspi_data";
2798 qspi_data23: qspi-data23-state {
2799 pins = "gpio93", "gpio94";
2800 function = "qspi_data";
2803 qup_i2c0_default: qup-i2c0-default-state {
2804 pins = "gpio0", "gpio1";
2808 qup_i2c1_default: qup-i2c1-default-state {
2809 pins = "gpio17", "gpio18";
2813 qup_i2c2_default: qup-i2c2-default-state {
2814 pins = "gpio27", "gpio28";
2818 qup_i2c3_default: qup-i2c3-default-state {
2819 pins = "gpio41", "gpio42";
2823 qup_i2c4_default: qup-i2c4-default-state {
2824 pins = "gpio89", "gpio90";
2828 qup_i2c5_default: qup-i2c5-default-state {
2829 pins = "gpio85", "gpio86";
2833 qup_i2c6_default: qup-i2c6-default-state {
2834 pins = "gpio45", "gpio46";
2838 qup_i2c7_default: qup-i2c7-default-state {
2839 pins = "gpio93", "gpio94";
2843 qup_i2c8_default: qup-i2c8-default-state {
2844 pins = "gpio65", "gpio66";
2848 qup_i2c9_default: qup-i2c9-default-state {
2849 pins = "gpio6", "gpio7";
2853 qup_i2c10_default: qup-i2c10-default-state {
2854 pins = "gpio55", "gpio56";
2858 qup_i2c11_default: qup-i2c11-default-state {
2859 pins = "gpio31", "gpio32";
2863 qup_i2c12_default: qup-i2c12-default-state {
2864 pins = "gpio49", "gpio50";
2868 qup_i2c13_default: qup-i2c13-default-state {
2869 pins = "gpio105", "gpio106";
2873 qup_i2c14_default: qup-i2c14-default-state {
2874 pins = "gpio33", "gpio34";
2878 qup_i2c15_default: qup-i2c15-default-state {
2879 pins = "gpio81", "gpio82";
2883 qup_spi0_default: qup-spi0-default-state {
2884 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2888 qup_spi1_default: qup-spi1-default-state {
2889 pins = "gpio17", "gpio18", "gpio19", "gpio20";
2893 qup_spi2_default: qup-spi2-default-state {
2894 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2898 qup_spi3_default: qup-spi3-default-state {
2899 pins = "gpio41", "gpio42", "gpio43", "gpio44";
2903 qup_spi4_default: qup-spi4-default-state {
2904 pins = "gpio89", "gpio90", "gpio91", "gpio92";
2908 qup_spi5_default: qup-spi5-default-state {
2909 pins = "gpio85", "gpio86", "gpio87", "gpio88";
2913 qup_spi6_default: qup-spi6-default-state {
2914 pins = "gpio45", "gpio46", "gpio47", "gpio48";
2918 qup_spi7_default: qup-spi7-default-state {
2919 pins = "gpio93", "gpio94", "gpio95", "gpio96";
2923 qup_spi8_default: qup-spi8-default-state {
2924 pins = "gpio65", "gpio66", "gpio67", "gpio68";
2928 qup_spi9_default: qup-spi9-default-state {
2929 pins = "gpio6", "gpio7", "gpio4", "gpio5";
2933 qup_spi10_default: qup-spi10-default-state {
2934 pins = "gpio55", "gpio56", "gpio53", "gpio54";
2938 qup_spi11_default: qup-spi11-default-state {
2939 pins = "gpio31", "gpio32", "gpio33", "gpio34";
2943 qup_spi12_default: qup-spi12-default-state {
2944 pins = "gpio49", "gpio50", "gpio51", "gpio52";
2948 qup_spi13_default: qup-spi13-default-state {
2949 pins = "gpio105", "gpio106", "gpio107", "gpio108";
2953 qup_spi14_default: qup-spi14-default-state {
2954 pins = "gpio33", "gpio34", "gpio31", "gpio32";
2958 qup_spi15_default: qup-spi15-default-state {
2959 pins = "gpio81", "gpio82", "gpio83", "gpio84";
2963 qup_uart0_default: qup-uart0-default-state {
2964 qup_uart0_tx: tx-pins {
2969 qup_uart0_rx: rx-pins {
2975 qup_uart1_default: qup-uart1-default-state {
2976 qup_uart1_tx: tx-pins {
2981 qup_uart1_rx: rx-pins {
2987 qup_uart2_default: qup-uart2-default-state {
2988 qup_uart2_tx: tx-pins {
2993 qup_uart2_rx: rx-pins {
2999 qup_uart3_default: qup-uart3-default-state {
3000 qup_uart3_tx: tx-pins {
3005 qup_uart3_rx: rx-pins {
3011 qup_uart3_4pin: qup-uart3-4pin-state {
3012 qup_uart3_4pin_cts: cts-pins {
3017 qup_uart3_4pin_rts_tx: rts-tx-pins {
3018 pins = "gpio42", "gpio43";
3022 qup_uart3_4pin_rx: rx-pins {
3028 qup_uart4_default: qup-uart4-default-state {
3029 qup_uart4_tx: tx-pins {
3034 qup_uart4_rx: rx-pins {
3040 qup_uart5_default: qup-uart5-default-state {
3041 qup_uart5_tx: tx-pins {
3046 qup_uart5_rx: rx-pins {
3052 qup_uart6_default: qup-uart6-default-state {
3053 qup_uart6_tx: tx-pins {
3058 qup_uart6_rx: rx-pins {
3064 qup_uart6_4pin: qup-uart6-4pin-state {
3065 qup_uart6_4pin_cts: cts-pins {
3071 qup_uart6_4pin_rts_tx: rts-tx-pins {
3072 pins = "gpio46", "gpio47";
3074 drive-strength = <2>;
3078 qup_uart6_4pin_rx: rx-pins {
3085 qup_uart7_default: qup-uart7-default-state {
3086 qup_uart7_tx: tx-pins {
3091 qup_uart7_rx: rx-pins {
3097 qup_uart8_default: qup-uart8-default-state {
3098 qup_uart8_tx: tx-pins {
3103 qup_uart8_rx: rx-pins {
3109 qup_uart9_default: qup-uart9-default-state {
3110 qup_uart9_tx: tx-pins {
3115 qup_uart9_rx: rx-pins {
3121 qup_uart10_default: qup-uart10-default-state {
3122 qup_uart10_tx: tx-pins {
3127 qup_uart10_rx: rx-pins {
3133 qup_uart11_default: qup-uart11-default-state {
3134 qup_uart11_tx: tx-pins {
3139 qup_uart11_rx: rx-pins {
3145 qup_uart12_default: qup-uart12-default-state {
3146 qup_uart12_tx: tx-pins {
3151 qup_uart12_rx: rx-pins {
3157 qup_uart13_default: qup-uart13-default-state {
3158 qup_uart13_tx: tx-pins {
3163 qup_uart13_rx: rx-pins {
3169 qup_uart14_default: qup-uart14-default-state {
3170 qup_uart14_tx: tx-pins {
3175 qup_uart14_rx: rx-pins {
3181 qup_uart15_default: qup-uart15-default-state {
3182 qup_uart15_tx: tx-pins {
3187 qup_uart15_rx: rx-pins {
3193 quat_mi2s_sleep: quat-mi2s-sleep-state {
3194 pins = "gpio58", "gpio59";
3196 drive-strength = <2>;
3200 quat_mi2s_active: quat-mi2s-active-state {
3201 pins = "gpio58", "gpio59";
3202 function = "qua_mi2s";
3203 drive-strength = <8>;
3208 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3211 drive-strength = <2>;
3215 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3217 function = "qua_mi2s";
3218 drive-strength = <8>;
3222 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3225 drive-strength = <2>;
3229 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3231 function = "qua_mi2s";
3232 drive-strength = <8>;
3236 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3239 drive-strength = <2>;
3243 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3245 function = "qua_mi2s";
3246 drive-strength = <8>;
3250 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3253 drive-strength = <2>;
3257 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3259 function = "qua_mi2s";
3260 drive-strength = <8>;
3265 mss_pil: remoteproc@4080000 {
3266 compatible = "qcom,sdm845-mss-pil";
3267 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3268 reg-names = "qdsp6", "rmb";
3270 interrupts-extended =
3271 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3272 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3273 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3274 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3275 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3276 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3277 interrupt-names = "wdog", "fatal", "ready",
3278 "handover", "stop-ack",
3281 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3282 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3283 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3284 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3285 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3286 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3287 <&gcc GCC_PRNG_AHB_CLK>,
3288 <&rpmhcc RPMH_CXO_CLK>;
3289 clock-names = "iface", "bus", "mem", "gpll0_mss",
3290 "snoc_axi", "mnoc_axi", "prng", "xo";
3292 qcom,qmp = <&aoss_qmp>;
3294 qcom,smem-states = <&modem_smp2p_out 0>;
3295 qcom,smem-state-names = "stop";
3297 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3298 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3299 reset-names = "mss_restart", "pdc_reset";
3301 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3303 power-domains = <&rpmhpd SDM845_CX>,
3304 <&rpmhpd SDM845_MX>,
3305 <&rpmhpd SDM845_MSS>;
3306 power-domain-names = "cx", "mx", "mss";
3308 status = "disabled";
3311 memory-region = <&mba_region>;
3315 memory-region = <&mpss_region>;
3319 memory-region = <&mdata_mem>;
3323 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3325 qcom,remote-pid = <1>;
3326 mboxes = <&apss_shared 12>;
3330 gpucc: clock-controller@5090000 {
3331 compatible = "qcom,sdm845-gpucc";
3332 reg = <0 0x05090000 0 0x9000>;
3335 #power-domain-cells = <1>;
3336 clocks = <&rpmhcc RPMH_CXO_CLK>,
3337 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3338 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3339 clock-names = "bi_tcxo",
3340 "gcc_gpu_gpll0_clk_src",
3341 "gcc_gpu_gpll0_div_clk_src";
3344 slpi_pas: remoteproc@5c00000 {
3345 compatible = "qcom,sdm845-slpi-pas";
3346 reg = <0 0x5c00000 0 0x4000>;
3348 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
3349 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3350 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3351 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3352 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3353 interrupt-names = "wdog", "fatal", "ready",
3354 "handover", "stop-ack";
3356 clocks = <&rpmhcc RPMH_CXO_CLK>;
3359 qcom,qmp = <&aoss_qmp>;
3361 power-domains = <&rpmhpd SDM845_CX>,
3362 <&rpmhpd SDM845_MX>;
3363 power-domain-names = "lcx", "lmx";
3365 memory-region = <&slpi_mem>;
3367 qcom,smem-states = <&slpi_smp2p_out 0>;
3368 qcom,smem-state-names = "stop";
3370 status = "disabled";
3373 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
3375 qcom,remote-pid = <3>;
3376 mboxes = <&apss_shared 24>;
3379 compatible = "qcom,fastrpc";
3380 qcom,glink-channels = "fastrpcglink-apps-dsp";
3382 qcom,non-secure-domain;
3383 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA
3384 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>;
3385 memory-region = <&fastrpc_mem>;
3386 #address-cells = <1>;
3390 compatible = "qcom,fastrpc-compute-cb";
3398 compatible = "arm,coresight-stm", "arm,primecell";
3399 reg = <0 0x06002000 0 0x1000>,
3400 <0 0x16280000 0 0x180000>;
3401 reg-names = "stm-base", "stm-stimulus-base";
3403 clocks = <&aoss_qmp>;
3404 clock-names = "apb_pclk";
3417 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3418 reg = <0 0x06041000 0 0x1000>;
3420 clocks = <&aoss_qmp>;
3421 clock-names = "apb_pclk";
3425 funnel0_out: endpoint {
3427 <&merge_funnel_in0>;
3433 #address-cells = <1>;
3438 funnel0_in7: endpoint {
3439 remote-endpoint = <&stm_out>;
3446 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3447 reg = <0 0x06043000 0 0x1000>;
3449 clocks = <&aoss_qmp>;
3450 clock-names = "apb_pclk";
3454 funnel2_out: endpoint {
3456 <&merge_funnel_in2>;
3462 #address-cells = <1>;
3467 funnel2_in5: endpoint {
3469 <&apss_merge_funnel_out>;
3476 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3477 reg = <0 0x06045000 0 0x1000>;
3479 clocks = <&aoss_qmp>;
3480 clock-names = "apb_pclk";
3484 merge_funnel_out: endpoint {
3485 remote-endpoint = <&etf_in>;
3491 #address-cells = <1>;
3496 merge_funnel_in0: endpoint {
3504 merge_funnel_in2: endpoint {
3512 replicator@6046000 {
3513 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3514 reg = <0 0x06046000 0 0x1000>;
3516 clocks = <&aoss_qmp>;
3517 clock-names = "apb_pclk";
3521 replicator_out: endpoint {
3522 remote-endpoint = <&etr_in>;
3529 replicator_in: endpoint {
3530 remote-endpoint = <&etf_out>;
3537 compatible = "arm,coresight-tmc", "arm,primecell";
3538 reg = <0 0x06047000 0 0x1000>;
3540 clocks = <&aoss_qmp>;
3541 clock-names = "apb_pclk";
3553 #address-cells = <1>;
3560 <&merge_funnel_out>;
3567 compatible = "arm,coresight-tmc", "arm,primecell";
3568 reg = <0 0x06048000 0 0x1000>;
3570 clocks = <&aoss_qmp>;
3571 clock-names = "apb_pclk";
3585 compatible = "arm,coresight-etm4x", "arm,primecell";
3586 reg = <0 0x07040000 0 0x1000>;
3590 clocks = <&aoss_qmp>;
3591 clock-names = "apb_pclk";
3592 arm,coresight-loses-context-with-cpu;
3596 etm0_out: endpoint {
3605 compatible = "arm,coresight-etm4x", "arm,primecell";
3606 reg = <0 0x07140000 0 0x1000>;
3610 clocks = <&aoss_qmp>;
3611 clock-names = "apb_pclk";
3612 arm,coresight-loses-context-with-cpu;
3616 etm1_out: endpoint {
3625 compatible = "arm,coresight-etm4x", "arm,primecell";
3626 reg = <0 0x07240000 0 0x1000>;
3630 clocks = <&aoss_qmp>;
3631 clock-names = "apb_pclk";
3632 arm,coresight-loses-context-with-cpu;
3636 etm2_out: endpoint {
3645 compatible = "arm,coresight-etm4x", "arm,primecell";
3646 reg = <0 0x07340000 0 0x1000>;
3650 clocks = <&aoss_qmp>;
3651 clock-names = "apb_pclk";
3652 arm,coresight-loses-context-with-cpu;
3656 etm3_out: endpoint {
3665 compatible = "arm,coresight-etm4x", "arm,primecell";
3666 reg = <0 0x07440000 0 0x1000>;
3670 clocks = <&aoss_qmp>;
3671 clock-names = "apb_pclk";
3672 arm,coresight-loses-context-with-cpu;
3676 etm4_out: endpoint {
3685 compatible = "arm,coresight-etm4x", "arm,primecell";
3686 reg = <0 0x07540000 0 0x1000>;
3690 clocks = <&aoss_qmp>;
3691 clock-names = "apb_pclk";
3692 arm,coresight-loses-context-with-cpu;
3696 etm5_out: endpoint {
3705 compatible = "arm,coresight-etm4x", "arm,primecell";
3706 reg = <0 0x07640000 0 0x1000>;
3710 clocks = <&aoss_qmp>;
3711 clock-names = "apb_pclk";
3712 arm,coresight-loses-context-with-cpu;
3716 etm6_out: endpoint {
3725 compatible = "arm,coresight-etm4x", "arm,primecell";
3726 reg = <0 0x07740000 0 0x1000>;
3730 clocks = <&aoss_qmp>;
3731 clock-names = "apb_pclk";
3732 arm,coresight-loses-context-with-cpu;
3736 etm7_out: endpoint {
3744 funnel@7800000 { /* APSS Funnel */
3745 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3746 reg = <0 0x07800000 0 0x1000>;
3748 clocks = <&aoss_qmp>;
3749 clock-names = "apb_pclk";
3753 apss_funnel_out: endpoint {
3755 <&apss_merge_funnel_in>;
3761 #address-cells = <1>;
3766 apss_funnel_in0: endpoint {
3774 apss_funnel_in1: endpoint {
3782 apss_funnel_in2: endpoint {
3790 apss_funnel_in3: endpoint {
3798 apss_funnel_in4: endpoint {
3806 apss_funnel_in5: endpoint {
3814 apss_funnel_in6: endpoint {
3822 apss_funnel_in7: endpoint {
3831 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3832 reg = <0 0x07810000 0 0x1000>;
3834 clocks = <&aoss_qmp>;
3835 clock-names = "apb_pclk";
3839 apss_merge_funnel_out: endpoint {
3848 apss_merge_funnel_in: endpoint {
3856 sdhc_2: mmc@8804000 {
3857 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3858 reg = <0 0x08804000 0 0x1000>;
3860 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3861 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3862 interrupt-names = "hc_irq", "pwr_irq";
3864 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3865 <&gcc GCC_SDCC2_APPS_CLK>,
3866 <&rpmhcc RPMH_CXO_CLK>;
3867 clock-names = "iface", "core", "xo";
3868 iommus = <&apps_smmu 0xa0 0xf>;
3869 power-domains = <&rpmhpd SDM845_CX>;
3870 operating-points-v2 = <&sdhc2_opp_table>;
3872 status = "disabled";
3874 sdhc2_opp_table: opp-table {
3875 compatible = "operating-points-v2";
3878 opp-hz = /bits/ 64 <9600000>;
3879 required-opps = <&rpmhpd_opp_min_svs>;
3883 opp-hz = /bits/ 64 <19200000>;
3884 required-opps = <&rpmhpd_opp_low_svs>;
3888 opp-hz = /bits/ 64 <100000000>;
3889 required-opps = <&rpmhpd_opp_svs>;
3893 opp-hz = /bits/ 64 <201500000>;
3894 required-opps = <&rpmhpd_opp_svs_l1>;
3900 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3901 reg = <0 0x088df000 0 0x600>;
3902 #address-cells = <1>;
3904 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3905 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3906 <&gcc GCC_QSPI_CORE_CLK>;
3907 clock-names = "iface", "core";
3908 power-domains = <&rpmhpd SDM845_CX>;
3909 operating-points-v2 = <&qspi_opp_table>;
3910 status = "disabled";
3913 slim: slim-ngd@171c0000 {
3914 compatible = "qcom,slim-ngd-v2.1.0";
3915 reg = <0 0x171c0000 0 0x2c000>;
3916 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3918 dmas = <&slimbam 3>, <&slimbam 4>;
3919 dma-names = "rx", "tx";
3921 iommus = <&apps_smmu 0x1806 0x0>;
3922 #address-cells = <1>;
3924 status = "disabled";
3927 lmh_cluster1: lmh@17d70800 {
3928 compatible = "qcom,sdm845-lmh";
3929 reg = <0 0x17d70800 0 0x400>;
3930 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3932 qcom,lmh-temp-arm-millicelsius = <65000>;
3933 qcom,lmh-temp-low-millicelsius = <94500>;
3934 qcom,lmh-temp-high-millicelsius = <95000>;
3935 interrupt-controller;
3936 #interrupt-cells = <1>;
3939 lmh_cluster0: lmh@17d78800 {
3940 compatible = "qcom,sdm845-lmh";
3941 reg = <0 0x17d78800 0 0x400>;
3942 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3944 qcom,lmh-temp-arm-millicelsius = <65000>;
3945 qcom,lmh-temp-low-millicelsius = <94500>;
3946 qcom,lmh-temp-high-millicelsius = <95000>;
3947 interrupt-controller;
3948 #interrupt-cells = <1>;
3951 usb_1_hsphy: phy@88e2000 {
3952 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3953 reg = <0 0x088e2000 0 0x400>;
3954 status = "disabled";
3957 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3958 <&rpmhcc RPMH_CXO_CLK>;
3959 clock-names = "cfg_ahb", "ref";
3961 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3963 nvmem-cells = <&qusb2p_hstx_trim>;
3966 usb_2_hsphy: phy@88e3000 {
3967 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3968 reg = <0 0x088e3000 0 0x400>;
3969 status = "disabled";
3972 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3973 <&rpmhcc RPMH_CXO_CLK>;
3974 clock-names = "cfg_ahb", "ref";
3976 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3978 nvmem-cells = <&qusb2s_hstx_trim>;
3981 usb_1_qmpphy: phy@88e9000 {
3982 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
3983 reg = <0 0x088e9000 0 0x18c>,
3984 <0 0x088e8000 0 0x38>,
3985 <0 0x088ea000 0 0x40>;
3986 status = "disabled";
3987 #address-cells = <2>;
3991 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3992 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3993 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3994 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3995 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3997 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3998 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
3999 reset-names = "phy", "common";
4001 usb_1_ssphy: usb3-phy@88e9200 {
4002 reg = <0 0x088e9200 0 0x128>,
4003 <0 0x088e9400 0 0x200>,
4004 <0 0x088e9c00 0 0x218>,
4005 <0 0x088e9600 0 0x128>,
4006 <0 0x088e9800 0 0x200>,
4007 <0 0x088e9a00 0 0x100>;
4010 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4011 clock-names = "pipe0";
4012 clock-output-names = "usb3_phy_pipe_clk_src";
4015 dp_phy: dp-phy@88ea200 {
4016 reg = <0 0x088ea200 0 0x200>,
4017 <0 0x088ea400 0 0x200>,
4018 <0 0x088eaa00 0 0x200>,
4019 <0 0x088ea600 0 0x200>,
4020 <0 0x088ea800 0 0x200>;
4026 usb_2_qmpphy: phy@88eb000 {
4027 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4028 reg = <0 0x088eb000 0 0x18c>;
4029 status = "disabled";
4030 #address-cells = <2>;
4034 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4035 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4036 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4037 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4038 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4040 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4041 <&gcc GCC_USB3_PHY_SEC_BCR>;
4042 reset-names = "phy", "common";
4044 usb_2_ssphy: phy@88eb200 {
4045 reg = <0 0x088eb200 0 0x128>,
4046 <0 0x088eb400 0 0x1fc>,
4047 <0 0x088eb800 0 0x218>,
4048 <0 0x088eb600 0 0x70>;
4051 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
4052 clock-names = "pipe0";
4053 clock-output-names = "usb3_uni_phy_pipe_clk_src";
4057 usb_1: usb@a6f8800 {
4058 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4059 reg = <0 0x0a6f8800 0 0x400>;
4060 status = "disabled";
4061 #address-cells = <2>;
4066 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4067 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4068 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4069 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4070 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4071 clock-names = "cfg_noc",
4077 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4078 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4079 assigned-clock-rates = <19200000>, <150000000>;
4081 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4082 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4083 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4084 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4085 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4086 "dm_hs_phy_irq", "dp_hs_phy_irq";
4088 power-domains = <&gcc USB30_PRIM_GDSC>;
4090 resets = <&gcc GCC_USB30_PRIM_BCR>;
4092 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4093 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4094 interconnect-names = "usb-ddr", "apps-usb";
4096 usb_1_dwc3: usb@a600000 {
4097 compatible = "snps,dwc3";
4098 reg = <0 0x0a600000 0 0xcd00>;
4099 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4100 iommus = <&apps_smmu 0x740 0>;
4101 snps,dis_u2_susphy_quirk;
4102 snps,dis_enblslpm_quirk;
4103 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4104 phy-names = "usb2-phy", "usb3-phy";
4108 usb_2: usb@a8f8800 {
4109 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4110 reg = <0 0x0a8f8800 0 0x400>;
4111 status = "disabled";
4112 #address-cells = <2>;
4117 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4118 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4119 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4120 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4121 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4122 clock-names = "cfg_noc",
4128 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4129 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4130 assigned-clock-rates = <19200000>, <150000000>;
4132 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4133 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4134 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4135 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4136 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4137 "dm_hs_phy_irq", "dp_hs_phy_irq";
4139 power-domains = <&gcc USB30_SEC_GDSC>;
4141 resets = <&gcc GCC_USB30_SEC_BCR>;
4143 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4144 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4145 interconnect-names = "usb-ddr", "apps-usb";
4147 usb_2_dwc3: usb@a800000 {
4148 compatible = "snps,dwc3";
4149 reg = <0 0x0a800000 0 0xcd00>;
4150 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4151 iommus = <&apps_smmu 0x760 0>;
4152 snps,dis_u2_susphy_quirk;
4153 snps,dis_enblslpm_quirk;
4154 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4155 phy-names = "usb2-phy", "usb3-phy";
4159 venus: video-codec@aa00000 {
4160 compatible = "qcom,sdm845-venus-v2";
4161 reg = <0 0x0aa00000 0 0xff000>;
4162 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4163 power-domains = <&videocc VENUS_GDSC>,
4164 <&videocc VCODEC0_GDSC>,
4165 <&videocc VCODEC1_GDSC>,
4166 <&rpmhpd SDM845_CX>;
4167 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4168 operating-points-v2 = <&venus_opp_table>;
4169 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4170 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4171 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4172 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4173 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4174 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4175 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4176 clock-names = "core", "iface", "bus",
4177 "vcodec0_core", "vcodec0_bus",
4178 "vcodec1_core", "vcodec1_bus";
4179 iommus = <&apps_smmu 0x10a0 0x8>,
4180 <&apps_smmu 0x10b0 0x0>;
4181 memory-region = <&venus_mem>;
4182 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4183 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4184 interconnect-names = "video-mem", "cpu-cfg";
4186 status = "disabled";
4189 compatible = "venus-decoder";
4193 compatible = "venus-encoder";
4196 venus_opp_table: opp-table {
4197 compatible = "operating-points-v2";
4200 opp-hz = /bits/ 64 <100000000>;
4201 required-opps = <&rpmhpd_opp_min_svs>;
4205 opp-hz = /bits/ 64 <200000000>;
4206 required-opps = <&rpmhpd_opp_low_svs>;
4210 opp-hz = /bits/ 64 <320000000>;
4211 required-opps = <&rpmhpd_opp_svs>;
4215 opp-hz = /bits/ 64 <380000000>;
4216 required-opps = <&rpmhpd_opp_svs_l1>;
4220 opp-hz = /bits/ 64 <444000000>;
4221 required-opps = <&rpmhpd_opp_nom>;
4225 opp-hz = /bits/ 64 <533000097>;
4226 required-opps = <&rpmhpd_opp_turbo>;
4231 videocc: clock-controller@ab00000 {
4232 compatible = "qcom,sdm845-videocc";
4233 reg = <0 0x0ab00000 0 0x10000>;
4234 clocks = <&rpmhcc RPMH_CXO_CLK>;
4235 clock-names = "bi_tcxo";
4237 #power-domain-cells = <1>;
4241 camss: camss@a00000 {
4242 compatible = "qcom,sdm845-camss";
4244 reg = <0 0x0acb3000 0 0x1000>,
4245 <0 0x0acba000 0 0x1000>,
4246 <0 0x0acc8000 0 0x1000>,
4247 <0 0x0ac65000 0 0x1000>,
4248 <0 0x0ac66000 0 0x1000>,
4249 <0 0x0ac67000 0 0x1000>,
4250 <0 0x0ac68000 0 0x1000>,
4251 <0 0x0acaf000 0 0x4000>,
4252 <0 0x0acb6000 0 0x4000>,
4253 <0 0x0acc4000 0 0x4000>;
4254 reg-names = "csid0",
4265 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4275 interrupt-names = "csid0",
4286 power-domains = <&clock_camcc IFE_0_GDSC>,
4287 <&clock_camcc IFE_1_GDSC>,
4288 <&clock_camcc TITAN_TOP_GDSC>;
4290 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4291 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4292 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4293 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4294 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4295 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4296 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4297 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4298 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4299 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4300 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4301 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4302 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4303 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4304 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4305 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4306 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4307 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4308 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4309 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4310 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4311 <&gcc GCC_CAMERA_AHB_CLK>,
4312 <&gcc GCC_CAMERA_AXI_CLK>,
4313 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4314 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4315 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4316 <&clock_camcc CAM_CC_IFE_0_CLK>,
4317 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4318 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4319 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4320 <&clock_camcc CAM_CC_IFE_1_CLK>,
4321 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4322 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4323 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4324 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4325 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4326 clock-names = "camnoc_axi",
4337 "csiphy0_timer_src",
4340 "csiphy1_timer_src",
4343 "csiphy2_timer_src",
4346 "csiphy3_timer_src",
4363 iommus = <&apps_smmu 0x0808 0x0>,
4364 <&apps_smmu 0x0810 0x8>,
4365 <&apps_smmu 0x0c08 0x0>,
4366 <&apps_smmu 0x0c10 0x8>;
4368 status = "disabled";
4371 #address-cells = <1>;
4393 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
4394 #address-cells = <1>;
4397 reg = <0 0x0ac4a000 0 0x4000>;
4398 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4399 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4401 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4402 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4403 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4404 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4405 <&clock_camcc CAM_CC_CCI_CLK>,
4406 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4407 clock-names = "camnoc_axi",
4414 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4415 <&clock_camcc CAM_CC_CCI_CLK>;
4416 assigned-clock-rates = <80000000>, <37500000>;
4418 pinctrl-names = "default", "sleep";
4419 pinctrl-0 = <&cci0_default &cci1_default>;
4420 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4422 status = "disabled";
4424 cci_i2c0: i2c-bus@0 {
4426 clock-frequency = <1000000>;
4427 #address-cells = <1>;
4431 cci_i2c1: i2c-bus@1 {
4433 clock-frequency = <1000000>;
4434 #address-cells = <1>;
4439 clock_camcc: clock-controller@ad00000 {
4440 compatible = "qcom,sdm845-camcc";
4441 reg = <0 0x0ad00000 0 0x10000>;
4444 #power-domain-cells = <1>;
4445 clocks = <&rpmhcc RPMH_CXO_CLK>;
4446 clock-names = "bi_tcxo";
4449 mdss: display-subsystem@ae00000 {
4450 compatible = "qcom,sdm845-mdss";
4451 reg = <0 0x0ae00000 0 0x1000>;
4454 power-domains = <&dispcc MDSS_GDSC>;
4456 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4457 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4458 clock-names = "iface", "core";
4460 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4461 interrupt-controller;
4462 #interrupt-cells = <1>;
4464 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4465 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4466 interconnect-names = "mdp0-mem", "mdp1-mem";
4468 iommus = <&apps_smmu 0x880 0x8>,
4469 <&apps_smmu 0xc80 0x8>;
4471 status = "disabled";
4473 #address-cells = <2>;
4477 mdss_mdp: display-controller@ae01000 {
4478 compatible = "qcom,sdm845-dpu";
4479 reg = <0 0x0ae01000 0 0x8f000>,
4480 <0 0x0aeb0000 0 0x2008>;
4481 reg-names = "mdp", "vbif";
4483 clocks = <&gcc GCC_DISP_AXI_CLK>,
4484 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4485 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4486 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4487 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4488 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4490 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4491 assigned-clock-rates = <19200000>;
4492 operating-points-v2 = <&mdp_opp_table>;
4493 power-domains = <&rpmhpd SDM845_CX>;
4495 interrupt-parent = <&mdss>;
4499 #address-cells = <1>;
4504 dpu_intf0_out: endpoint {
4505 remote-endpoint = <&dp_in>;
4511 dpu_intf1_out: endpoint {
4512 remote-endpoint = <&dsi0_in>;
4518 dpu_intf2_out: endpoint {
4519 remote-endpoint = <&dsi1_in>;
4524 mdp_opp_table: opp-table {
4525 compatible = "operating-points-v2";
4528 opp-hz = /bits/ 64 <19200000>;
4529 required-opps = <&rpmhpd_opp_min_svs>;
4533 opp-hz = /bits/ 64 <171428571>;
4534 required-opps = <&rpmhpd_opp_low_svs>;
4538 opp-hz = /bits/ 64 <344000000>;
4539 required-opps = <&rpmhpd_opp_svs_l1>;
4543 opp-hz = /bits/ 64 <430000000>;
4544 required-opps = <&rpmhpd_opp_nom>;
4549 mdss_dp: displayport-controller@ae90000 {
4550 status = "disabled";
4551 compatible = "qcom,sdm845-dp";
4553 reg = <0 0x0ae90000 0 0x200>,
4554 <0 0x0ae90200 0 0x200>,
4555 <0 0x0ae90400 0 0x600>,
4556 <0 0x0ae90a00 0 0x600>,
4557 <0 0x0ae91000 0 0x600>;
4559 interrupt-parent = <&mdss>;
4562 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4563 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4564 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4565 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4566 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4567 clock-names = "core_iface", "core_aux", "ctrl_link",
4568 "ctrl_link_iface", "stream_pixel";
4569 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4570 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4571 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4575 operating-points-v2 = <&dp_opp_table>;
4576 power-domains = <&rpmhpd SDM845_CX>;
4579 #address-cells = <1>;
4584 remote-endpoint = <&dpu_intf0_out>;
4590 dp_out: endpoint { };
4594 dp_opp_table: opp-table {
4595 compatible = "operating-points-v2";
4598 opp-hz = /bits/ 64 <162000000>;
4599 required-opps = <&rpmhpd_opp_low_svs>;
4603 opp-hz = /bits/ 64 <270000000>;
4604 required-opps = <&rpmhpd_opp_svs>;
4608 opp-hz = /bits/ 64 <540000000>;
4609 required-opps = <&rpmhpd_opp_svs_l1>;
4613 opp-hz = /bits/ 64 <810000000>;
4614 required-opps = <&rpmhpd_opp_nom>;
4620 compatible = "qcom,sdm845-dsi-ctrl",
4621 "qcom,mdss-dsi-ctrl";
4622 reg = <0 0x0ae94000 0 0x400>;
4623 reg-names = "dsi_ctrl";
4625 interrupt-parent = <&mdss>;
4628 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4629 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4630 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4631 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4632 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4633 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4634 clock-names = "byte",
4640 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4641 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4643 operating-points-v2 = <&dsi_opp_table>;
4644 power-domains = <&rpmhpd SDM845_CX>;
4648 status = "disabled";
4650 #address-cells = <1>;
4654 #address-cells = <1>;
4660 remote-endpoint = <&dpu_intf1_out>;
4666 dsi0_out: endpoint {
4672 dsi0_phy: phy@ae94400 {
4673 compatible = "qcom,dsi-phy-10nm";
4674 reg = <0 0x0ae94400 0 0x200>,
4675 <0 0x0ae94600 0 0x280>,
4676 <0 0x0ae94a00 0 0x1e0>;
4677 reg-names = "dsi_phy",
4684 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4685 <&rpmhcc RPMH_CXO_CLK>;
4686 clock-names = "iface", "ref";
4688 status = "disabled";
4692 compatible = "qcom,sdm845-dsi-ctrl",
4693 "qcom,mdss-dsi-ctrl";
4694 reg = <0 0x0ae96000 0 0x400>;
4695 reg-names = "dsi_ctrl";
4697 interrupt-parent = <&mdss>;
4700 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4701 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4702 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4703 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4704 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4705 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4706 clock-names = "byte",
4712 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4713 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4715 operating-points-v2 = <&dsi_opp_table>;
4716 power-domains = <&rpmhpd SDM845_CX>;
4720 status = "disabled";
4722 #address-cells = <1>;
4726 #address-cells = <1>;
4732 remote-endpoint = <&dpu_intf2_out>;
4738 dsi1_out: endpoint {
4744 dsi1_phy: phy@ae96400 {
4745 compatible = "qcom,dsi-phy-10nm";
4746 reg = <0 0x0ae96400 0 0x200>,
4747 <0 0x0ae96600 0 0x280>,
4748 <0 0x0ae96a00 0 0x10e>;
4749 reg-names = "dsi_phy",
4756 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4757 <&rpmhcc RPMH_CXO_CLK>;
4758 clock-names = "iface", "ref";
4760 status = "disabled";
4765 compatible = "qcom,adreno-630.2", "qcom,adreno";
4767 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
4768 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4771 * Look ma, no clocks! The GPU clocks and power are
4772 * controlled entirely by the GMU
4775 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4777 iommus = <&adreno_smmu 0>;
4779 operating-points-v2 = <&gpu_opp_table>;
4783 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4784 interconnect-names = "gfx-mem";
4786 status = "disabled";
4788 gpu_opp_table: opp-table {
4789 compatible = "operating-points-v2";
4792 opp-hz = /bits/ 64 <710000000>;
4793 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4794 opp-peak-kBps = <7216000>;
4798 opp-hz = /bits/ 64 <675000000>;
4799 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4800 opp-peak-kBps = <7216000>;
4804 opp-hz = /bits/ 64 <596000000>;
4805 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4806 opp-peak-kBps = <6220000>;
4810 opp-hz = /bits/ 64 <520000000>;
4811 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4812 opp-peak-kBps = <6220000>;
4816 opp-hz = /bits/ 64 <414000000>;
4817 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4818 opp-peak-kBps = <4068000>;
4822 opp-hz = /bits/ 64 <342000000>;
4823 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4824 opp-peak-kBps = <2724000>;
4828 opp-hz = /bits/ 64 <257000000>;
4829 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4830 opp-peak-kBps = <1648000>;
4835 adreno_smmu: iommu@5040000 {
4836 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4837 reg = <0 0x05040000 0 0x10000>;
4839 #global-interrupts = <2>;
4840 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4841 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4842 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4843 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4844 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4845 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4846 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4847 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4848 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4849 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4850 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4851 <&gcc GCC_GPU_CFG_AHB_CLK>;
4852 clock-names = "bus", "iface";
4854 power-domains = <&gpucc GPU_CX_GDSC>;
4858 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4860 reg = <0 0x0506a000 0 0x30000>,
4861 <0 0x0b280000 0 0x10000>,
4862 <0 0x0b480000 0 0x10000>;
4863 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4865 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4866 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4867 interrupt-names = "hfi", "gmu";
4869 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4870 <&gpucc GPU_CC_CXO_CLK>,
4871 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4872 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4873 clock-names = "gmu", "cxo", "axi", "memnoc";
4875 power-domains = <&gpucc GPU_CX_GDSC>,
4876 <&gpucc GPU_GX_GDSC>;
4877 power-domain-names = "cx", "gx";
4879 iommus = <&adreno_smmu 5>;
4881 operating-points-v2 = <&gmu_opp_table>;
4883 status = "disabled";
4885 gmu_opp_table: opp-table {
4886 compatible = "operating-points-v2";
4889 opp-hz = /bits/ 64 <400000000>;
4890 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4894 opp-hz = /bits/ 64 <200000000>;
4895 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4900 dispcc: clock-controller@af00000 {
4901 compatible = "qcom,sdm845-dispcc";
4902 reg = <0 0x0af00000 0 0x10000>;
4903 clocks = <&rpmhcc RPMH_CXO_CLK>,
4904 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4905 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4912 clock-names = "bi_tcxo",
4913 "gcc_disp_gpll0_clk_src",
4914 "gcc_disp_gpll0_div_clk_src",
4915 "dsi0_phy_pll_out_byteclk",
4916 "dsi0_phy_pll_out_dsiclk",
4917 "dsi1_phy_pll_out_byteclk",
4918 "dsi1_phy_pll_out_dsiclk",
4919 "dp_link_clk_divsel_ten",
4920 "dp_vco_divided_clk_src_mux";
4923 #power-domain-cells = <1>;
4926 pdc_intc: interrupt-controller@b220000 {
4927 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4928 reg = <0 0x0b220000 0 0x30000>;
4929 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4930 #interrupt-cells = <2>;
4931 interrupt-parent = <&intc>;
4932 interrupt-controller;
4935 pdc_reset: reset-controller@b2e0000 {
4936 compatible = "qcom,sdm845-pdc-global";
4937 reg = <0 0x0b2e0000 0 0x20000>;
4941 tsens0: thermal-sensor@c263000 {
4942 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4943 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4944 <0 0x0c222000 0 0x1ff>; /* SROT */
4945 #qcom,sensors = <13>;
4946 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4947 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4948 interrupt-names = "uplow", "critical";
4949 #thermal-sensor-cells = <1>;
4952 tsens1: thermal-sensor@c265000 {
4953 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4954 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4955 <0 0x0c223000 0 0x1ff>; /* SROT */
4956 #qcom,sensors = <8>;
4957 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4958 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4959 interrupt-names = "uplow", "critical";
4960 #thermal-sensor-cells = <1>;
4963 aoss_reset: reset-controller@c2a0000 {
4964 compatible = "qcom,sdm845-aoss-cc";
4965 reg = <0 0x0c2a0000 0 0x31000>;
4969 aoss_qmp: power-management@c300000 {
4970 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
4971 reg = <0 0x0c300000 0 0x400>;
4972 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4973 mboxes = <&apss_shared 0>;
4978 #cooling-cells = <2>;
4982 #cooling-cells = <2>;
4987 compatible = "qcom,sdm845-rpmh-stats";
4988 reg = <0 0x0c3f0000 0 0x400>;
4991 spmi_bus: spmi@c440000 {
4992 compatible = "qcom,spmi-pmic-arb";
4993 reg = <0 0x0c440000 0 0x1100>,
4994 <0 0x0c600000 0 0x2000000>,
4995 <0 0x0e600000 0 0x100000>,
4996 <0 0x0e700000 0 0xa0000>,
4997 <0 0x0c40a000 0 0x26000>;
4998 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4999 interrupt-names = "periph_irq";
5000 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5003 #address-cells = <2>;
5005 interrupt-controller;
5006 #interrupt-cells = <4>;
5010 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5011 reg = <0 0x146bf000 0 0x1000>;
5013 #address-cells = <1>;
5016 ranges = <0 0 0x146bf000 0x1000>;
5019 compatible = "qcom,pil-reloc-info";
5024 apps_smmu: iommu@15000000 {
5025 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5026 reg = <0 0x15000000 0 0x80000>;
5028 #global-interrupts = <1>;
5029 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5030 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5031 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5032 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5033 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5034 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5035 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5036 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5037 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5038 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5039 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5040 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5041 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5042 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5043 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5045 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5046 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5047 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5048 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5049 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5050 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5051 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5052 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5053 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5054 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5056 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5057 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5058 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5059 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5060 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5061 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5062 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5063 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5064 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5065 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5066 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5067 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5068 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5069 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5070 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5071 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5072 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5073 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5074 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5075 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5076 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5077 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5078 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5079 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5080 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5081 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5082 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5083 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5084 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5085 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5086 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5087 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5088 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5089 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5090 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5091 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5092 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5093 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5096 lpasscc: clock-controller@17014000 {
5097 compatible = "qcom,sdm845-lpasscc";
5098 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5099 reg-names = "cc", "qdsp6ss";
5101 status = "disabled";
5104 gladiator_noc: interconnect@17900000 {
5105 compatible = "qcom,sdm845-gladiator-noc";
5106 reg = <0 0x17900000 0 0xd080>;
5107 #interconnect-cells = <2>;
5108 qcom,bcm-voters = <&apps_bcm_voter>;
5112 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5113 reg = <0 0x17980000 0 0x1000>;
5114 clocks = <&sleep_clk>;
5115 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5118 apss_shared: mailbox@17990000 {
5119 compatible = "qcom,sdm845-apss-shared";
5120 reg = <0 0x17990000 0 0x1000>;
5124 apps_rsc: rsc@179c0000 {
5126 compatible = "qcom,rpmh-rsc";
5127 reg = <0 0x179c0000 0 0x10000>,
5128 <0 0x179d0000 0 0x10000>,
5129 <0 0x179e0000 0 0x10000>;
5130 reg-names = "drv-0", "drv-1", "drv-2";
5131 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5134 qcom,tcs-offset = <0xd00>;
5136 qcom,tcs-config = <ACTIVE_TCS 2>,
5141 apps_bcm_voter: bcm-voter {
5142 compatible = "qcom,bcm-voter";
5145 rpmhcc: clock-controller {
5146 compatible = "qcom,sdm845-rpmh-clk";
5149 clocks = <&xo_board>;
5152 rpmhpd: power-controller {
5153 compatible = "qcom,sdm845-rpmhpd";
5154 #power-domain-cells = <1>;
5155 operating-points-v2 = <&rpmhpd_opp_table>;
5157 rpmhpd_opp_table: opp-table {
5158 compatible = "operating-points-v2";
5160 rpmhpd_opp_ret: opp1 {
5161 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5164 rpmhpd_opp_min_svs: opp2 {
5165 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5168 rpmhpd_opp_low_svs: opp3 {
5169 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5172 rpmhpd_opp_svs: opp4 {
5173 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5176 rpmhpd_opp_svs_l1: opp5 {
5177 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5180 rpmhpd_opp_nom: opp6 {
5181 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5184 rpmhpd_opp_nom_l1: opp7 {
5185 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5188 rpmhpd_opp_nom_l2: opp8 {
5189 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5192 rpmhpd_opp_turbo: opp9 {
5193 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5196 rpmhpd_opp_turbo_l1: opp10 {
5197 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5203 intc: interrupt-controller@17a00000 {
5204 compatible = "arm,gic-v3";
5205 #address-cells = <2>;
5208 #interrupt-cells = <3>;
5209 interrupt-controller;
5210 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5211 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5212 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5214 msi-controller@17a40000 {
5215 compatible = "arm,gic-v3-its";
5218 reg = <0 0x17a40000 0 0x20000>;
5219 status = "disabled";
5223 slimbam: dma-controller@17184000 {
5224 compatible = "qcom,bam-v1.7.0";
5225 qcom,controlled-remotely;
5226 reg = <0 0x17184000 0 0x2a000>;
5227 num-channels = <31>;
5228 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5232 iommus = <&apps_smmu 0x1806 0x0>;
5236 #address-cells = <1>;
5238 ranges = <0 0 0 0x20000000>;
5239 compatible = "arm,armv7-timer-mem";
5240 reg = <0 0x17c90000 0 0x1000>;
5244 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5245 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5246 reg = <0x17ca0000 0x1000>,
5247 <0x17cb0000 0x1000>;
5252 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5253 reg = <0x17cc0000 0x1000>;
5254 status = "disabled";
5259 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5260 reg = <0x17cd0000 0x1000>;
5261 status = "disabled";
5266 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5267 reg = <0x17ce0000 0x1000>;
5268 status = "disabled";
5273 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5274 reg = <0x17cf0000 0x1000>;
5275 status = "disabled";
5280 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5281 reg = <0x17d00000 0x1000>;
5282 status = "disabled";
5287 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5288 reg = <0x17d10000 0x1000>;
5289 status = "disabled";
5293 osm_l3: interconnect@17d41000 {
5294 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5295 reg = <0 0x17d41000 0 0x1400>;
5297 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5298 clock-names = "xo", "alternate";
5300 #interconnect-cells = <1>;
5303 cpufreq_hw: cpufreq@17d43000 {
5304 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5305 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5306 reg-names = "freq-domain0", "freq-domain1";
5308 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5310 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5311 clock-names = "xo", "alternate";
5313 #freq-domain-cells = <1>;
5317 wifi: wifi@18800000 {
5318 compatible = "qcom,wcn3990-wifi";
5319 status = "disabled";
5320 reg = <0 0x18800000 0 0x800000>;
5321 reg-names = "membase";
5322 memory-region = <&wlan_msa_mem>;
5323 clock-names = "cxo_ref_clk_pin";
5324 clocks = <&rpmhcc RPMH_RF_CLK2>;
5326 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5327 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5328 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5329 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5330 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5331 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5332 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5333 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5334 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5335 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5336 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5337 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5338 iommus = <&apps_smmu 0x0040 0x1>;
5347 polling-delay-passive = <250>;
5348 polling-delay = <1000>;
5350 thermal-sensors = <&tsens0 1>;
5353 cpu0_alert0: trip-point0 {
5354 temperature = <90000>;
5355 hysteresis = <2000>;
5359 cpu0_alert1: trip-point1 {
5360 temperature = <95000>;
5361 hysteresis = <2000>;
5365 cpu0_crit: cpu-crit {
5366 temperature = <110000>;
5367 hysteresis = <1000>;
5374 polling-delay-passive = <250>;
5375 polling-delay = <1000>;
5377 thermal-sensors = <&tsens0 2>;
5380 cpu1_alert0: trip-point0 {
5381 temperature = <90000>;
5382 hysteresis = <2000>;
5386 cpu1_alert1: trip-point1 {
5387 temperature = <95000>;
5388 hysteresis = <2000>;
5392 cpu1_crit: cpu-crit {
5393 temperature = <110000>;
5394 hysteresis = <1000>;
5401 polling-delay-passive = <250>;
5402 polling-delay = <1000>;
5404 thermal-sensors = <&tsens0 3>;
5407 cpu2_alert0: trip-point0 {
5408 temperature = <90000>;
5409 hysteresis = <2000>;
5413 cpu2_alert1: trip-point1 {
5414 temperature = <95000>;
5415 hysteresis = <2000>;
5419 cpu2_crit: cpu-crit {
5420 temperature = <110000>;
5421 hysteresis = <1000>;
5428 polling-delay-passive = <250>;
5429 polling-delay = <1000>;
5431 thermal-sensors = <&tsens0 4>;
5434 cpu3_alert0: trip-point0 {
5435 temperature = <90000>;
5436 hysteresis = <2000>;
5440 cpu3_alert1: trip-point1 {
5441 temperature = <95000>;
5442 hysteresis = <2000>;
5446 cpu3_crit: cpu-crit {
5447 temperature = <110000>;
5448 hysteresis = <1000>;
5455 polling-delay-passive = <250>;
5456 polling-delay = <1000>;
5458 thermal-sensors = <&tsens0 7>;
5461 cpu4_alert0: trip-point0 {
5462 temperature = <90000>;
5463 hysteresis = <2000>;
5467 cpu4_alert1: trip-point1 {
5468 temperature = <95000>;
5469 hysteresis = <2000>;
5473 cpu4_crit: cpu-crit {
5474 temperature = <110000>;
5475 hysteresis = <1000>;
5482 polling-delay-passive = <250>;
5483 polling-delay = <1000>;
5485 thermal-sensors = <&tsens0 8>;
5488 cpu5_alert0: trip-point0 {
5489 temperature = <90000>;
5490 hysteresis = <2000>;
5494 cpu5_alert1: trip-point1 {
5495 temperature = <95000>;
5496 hysteresis = <2000>;
5500 cpu5_crit: cpu-crit {
5501 temperature = <110000>;
5502 hysteresis = <1000>;
5509 polling-delay-passive = <250>;
5510 polling-delay = <1000>;
5512 thermal-sensors = <&tsens0 9>;
5515 cpu6_alert0: trip-point0 {
5516 temperature = <90000>;
5517 hysteresis = <2000>;
5521 cpu6_alert1: trip-point1 {
5522 temperature = <95000>;
5523 hysteresis = <2000>;
5527 cpu6_crit: cpu-crit {
5528 temperature = <110000>;
5529 hysteresis = <1000>;
5536 polling-delay-passive = <250>;
5537 polling-delay = <1000>;
5539 thermal-sensors = <&tsens0 10>;
5542 cpu7_alert0: trip-point0 {
5543 temperature = <90000>;
5544 hysteresis = <2000>;
5548 cpu7_alert1: trip-point1 {
5549 temperature = <95000>;
5550 hysteresis = <2000>;
5554 cpu7_crit: cpu-crit {
5555 temperature = <110000>;
5556 hysteresis = <1000>;
5563 polling-delay-passive = <250>;
5564 polling-delay = <1000>;
5566 thermal-sensors = <&tsens0 0>;
5569 aoss0_alert0: trip-point0 {
5570 temperature = <90000>;
5571 hysteresis = <2000>;
5578 polling-delay-passive = <250>;
5579 polling-delay = <1000>;
5581 thermal-sensors = <&tsens0 5>;
5584 cluster0_alert0: trip-point0 {
5585 temperature = <90000>;
5586 hysteresis = <2000>;
5589 cluster0_crit: cluster0_crit {
5590 temperature = <110000>;
5591 hysteresis = <2000>;
5598 polling-delay-passive = <250>;
5599 polling-delay = <1000>;
5601 thermal-sensors = <&tsens0 6>;
5604 cluster1_alert0: trip-point0 {
5605 temperature = <90000>;
5606 hysteresis = <2000>;
5609 cluster1_crit: cluster1_crit {
5610 temperature = <110000>;
5611 hysteresis = <2000>;
5618 polling-delay-passive = <250>;
5619 polling-delay = <1000>;
5621 thermal-sensors = <&tsens0 11>;
5624 gpu1_alert0: trip-point0 {
5625 temperature = <90000>;
5626 hysteresis = <2000>;
5632 gpu-bottom-thermal {
5633 polling-delay-passive = <250>;
5634 polling-delay = <1000>;
5636 thermal-sensors = <&tsens0 12>;
5639 gpu2_alert0: trip-point0 {
5640 temperature = <90000>;
5641 hysteresis = <2000>;
5648 polling-delay-passive = <250>;
5649 polling-delay = <1000>;
5651 thermal-sensors = <&tsens1 0>;
5654 aoss1_alert0: trip-point0 {
5655 temperature = <90000>;
5656 hysteresis = <2000>;
5663 polling-delay-passive = <250>;
5664 polling-delay = <1000>;
5666 thermal-sensors = <&tsens1 1>;
5669 q6_modem_alert0: trip-point0 {
5670 temperature = <90000>;
5671 hysteresis = <2000>;
5678 polling-delay-passive = <250>;
5679 polling-delay = <1000>;
5681 thermal-sensors = <&tsens1 2>;
5684 mem_alert0: trip-point0 {
5685 temperature = <90000>;
5686 hysteresis = <2000>;
5693 polling-delay-passive = <250>;
5694 polling-delay = <1000>;
5696 thermal-sensors = <&tsens1 3>;
5699 wlan_alert0: trip-point0 {
5700 temperature = <90000>;
5701 hysteresis = <2000>;
5708 polling-delay-passive = <250>;
5709 polling-delay = <1000>;
5711 thermal-sensors = <&tsens1 4>;
5714 q6_hvx_alert0: trip-point0 {
5715 temperature = <90000>;
5716 hysteresis = <2000>;
5723 polling-delay-passive = <250>;
5724 polling-delay = <1000>;
5726 thermal-sensors = <&tsens1 5>;
5729 camera_alert0: trip-point0 {
5730 temperature = <90000>;
5731 hysteresis = <2000>;
5738 polling-delay-passive = <250>;
5739 polling-delay = <1000>;
5741 thermal-sensors = <&tsens1 6>;
5744 video_alert0: trip-point0 {
5745 temperature = <90000>;
5746 hysteresis = <2000>;
5753 polling-delay-passive = <250>;
5754 polling-delay = <1000>;
5756 thermal-sensors = <&tsens1 7>;
5759 modem_alert0: trip-point0 {
5760 temperature = <90000>;
5761 hysteresis = <2000>;
5769 compatible = "arm,armv8-timer";
5770 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
5771 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
5772 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
5773 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;