1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sdm845.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/phy/phy-qcom-qusb2.h>
22 #include <dt-bindings/power/qcom-rpmpd.h>
23 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
24 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
25 #include <dt-bindings/soc/qcom,apr.h>
26 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
27 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
28 #include <dt-bindings/thermal/thermal.h>
31 interrupt-parent = <&intc>;
75 compatible = "fixed-clock";
77 clock-frequency = <38400000>;
78 clock-output-names = "xo_board";
81 sleep_clk: sleep-clk {
82 compatible = "fixed-clock";
84 clock-frequency = <32764>;
94 compatible = "qcom,kryo385";
96 clocks = <&cpufreq_hw 0>;
97 enable-method = "psci";
98 capacity-dmips-mhz = <611>;
99 dynamic-power-coefficient = <154>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
101 operating-points-v2 = <&cpu0_opp_table>;
102 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
104 power-domains = <&CPU_PD0>;
105 power-domain-names = "psci";
106 #cooling-cells = <2>;
107 next-level-cache = <&L2_0>;
109 compatible = "cache";
112 next-level-cache = <&L3_0>;
114 compatible = "cache";
123 compatible = "qcom,kryo385";
125 clocks = <&cpufreq_hw 0>;
126 enable-method = "psci";
127 capacity-dmips-mhz = <611>;
128 dynamic-power-coefficient = <154>;
129 qcom,freq-domain = <&cpufreq_hw 0>;
130 operating-points-v2 = <&cpu0_opp_table>;
131 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
132 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
133 power-domains = <&CPU_PD1>;
134 power-domain-names = "psci";
135 #cooling-cells = <2>;
136 next-level-cache = <&L2_100>;
138 compatible = "cache";
141 next-level-cache = <&L3_0>;
147 compatible = "qcom,kryo385";
149 clocks = <&cpufreq_hw 0>;
150 enable-method = "psci";
151 capacity-dmips-mhz = <611>;
152 dynamic-power-coefficient = <154>;
153 qcom,freq-domain = <&cpufreq_hw 0>;
154 operating-points-v2 = <&cpu0_opp_table>;
155 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
156 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
157 power-domains = <&CPU_PD2>;
158 power-domain-names = "psci";
159 #cooling-cells = <2>;
160 next-level-cache = <&L2_200>;
162 compatible = "cache";
165 next-level-cache = <&L3_0>;
171 compatible = "qcom,kryo385";
173 clocks = <&cpufreq_hw 0>;
174 enable-method = "psci";
175 capacity-dmips-mhz = <611>;
176 dynamic-power-coefficient = <154>;
177 qcom,freq-domain = <&cpufreq_hw 0>;
178 operating-points-v2 = <&cpu0_opp_table>;
179 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
180 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
181 #cooling-cells = <2>;
182 power-domains = <&CPU_PD3>;
183 power-domain-names = "psci";
184 next-level-cache = <&L2_300>;
186 compatible = "cache";
189 next-level-cache = <&L3_0>;
195 compatible = "qcom,kryo385";
197 clocks = <&cpufreq_hw 1>;
198 enable-method = "psci";
199 capacity-dmips-mhz = <1024>;
200 dynamic-power-coefficient = <442>;
201 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = <&cpu4_opp_table>;
203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
205 power-domains = <&CPU_PD4>;
206 power-domain-names = "psci";
207 #cooling-cells = <2>;
208 next-level-cache = <&L2_400>;
210 compatible = "cache";
213 next-level-cache = <&L3_0>;
219 compatible = "qcom,kryo385";
221 clocks = <&cpufreq_hw 1>;
222 enable-method = "psci";
223 capacity-dmips-mhz = <1024>;
224 dynamic-power-coefficient = <442>;
225 qcom,freq-domain = <&cpufreq_hw 1>;
226 operating-points-v2 = <&cpu4_opp_table>;
227 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
228 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
229 power-domains = <&CPU_PD5>;
230 power-domain-names = "psci";
231 #cooling-cells = <2>;
232 next-level-cache = <&L2_500>;
234 compatible = "cache";
237 next-level-cache = <&L3_0>;
243 compatible = "qcom,kryo385";
245 clocks = <&cpufreq_hw 1>;
246 enable-method = "psci";
247 capacity-dmips-mhz = <1024>;
248 dynamic-power-coefficient = <442>;
249 qcom,freq-domain = <&cpufreq_hw 1>;
250 operating-points-v2 = <&cpu4_opp_table>;
251 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
252 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
253 power-domains = <&CPU_PD6>;
254 power-domain-names = "psci";
255 #cooling-cells = <2>;
256 next-level-cache = <&L2_600>;
258 compatible = "cache";
261 next-level-cache = <&L3_0>;
267 compatible = "qcom,kryo385";
269 clocks = <&cpufreq_hw 1>;
270 enable-method = "psci";
271 capacity-dmips-mhz = <1024>;
272 dynamic-power-coefficient = <442>;
273 qcom,freq-domain = <&cpufreq_hw 1>;
274 operating-points-v2 = <&cpu4_opp_table>;
275 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
276 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
277 power-domains = <&CPU_PD7>;
278 power-domain-names = "psci";
279 #cooling-cells = <2>;
280 next-level-cache = <&L2_700>;
282 compatible = "cache";
285 next-level-cache = <&L3_0>;
325 cpu_idle_states: idle-states {
326 entry-method = "psci";
328 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
329 compatible = "arm,idle-state";
330 idle-state-name = "little-rail-power-collapse";
331 arm,psci-suspend-param = <0x40000004>;
332 entry-latency-us = <350>;
333 exit-latency-us = <461>;
334 min-residency-us = <1890>;
338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
339 compatible = "arm,idle-state";
340 idle-state-name = "big-rail-power-collapse";
341 arm,psci-suspend-param = <0x40000004>;
342 entry-latency-us = <264>;
343 exit-latency-us = <621>;
344 min-residency-us = <952>;
350 CLUSTER_SLEEP_0: cluster-sleep-0 {
351 compatible = "domain-idle-state";
352 arm,psci-suspend-param = <0x4100c244>;
353 entry-latency-us = <3263>;
354 exit-latency-us = <6562>;
355 min-residency-us = <9987>;
362 compatible = "qcom,scm-sdm845", "qcom,scm";
367 device_type = "memory";
368 /* We expect the bootloader to fill in the size */
369 reg = <0 0x80000000 0 0>;
372 cpu0_opp_table: opp-table-cpu0 {
373 compatible = "operating-points-v2";
376 cpu0_opp1: opp-300000000 {
377 opp-hz = /bits/ 64 <300000000>;
378 opp-peak-kBps = <800000 4800000>;
381 cpu0_opp2: opp-403200000 {
382 opp-hz = /bits/ 64 <403200000>;
383 opp-peak-kBps = <800000 4800000>;
386 cpu0_opp3: opp-480000000 {
387 opp-hz = /bits/ 64 <480000000>;
388 opp-peak-kBps = <800000 6451200>;
391 cpu0_opp4: opp-576000000 {
392 opp-hz = /bits/ 64 <576000000>;
393 opp-peak-kBps = <800000 6451200>;
396 cpu0_opp5: opp-652800000 {
397 opp-hz = /bits/ 64 <652800000>;
398 opp-peak-kBps = <800000 7680000>;
401 cpu0_opp6: opp-748800000 {
402 opp-hz = /bits/ 64 <748800000>;
403 opp-peak-kBps = <1804000 9216000>;
406 cpu0_opp7: opp-825600000 {
407 opp-hz = /bits/ 64 <825600000>;
408 opp-peak-kBps = <1804000 9216000>;
411 cpu0_opp8: opp-902400000 {
412 opp-hz = /bits/ 64 <902400000>;
413 opp-peak-kBps = <1804000 10444800>;
416 cpu0_opp9: opp-979200000 {
417 opp-hz = /bits/ 64 <979200000>;
418 opp-peak-kBps = <1804000 11980800>;
421 cpu0_opp10: opp-1056000000 {
422 opp-hz = /bits/ 64 <1056000000>;
423 opp-peak-kBps = <1804000 11980800>;
426 cpu0_opp11: opp-1132800000 {
427 opp-hz = /bits/ 64 <1132800000>;
428 opp-peak-kBps = <2188000 13516800>;
431 cpu0_opp12: opp-1228800000 {
432 opp-hz = /bits/ 64 <1228800000>;
433 opp-peak-kBps = <2188000 15052800>;
436 cpu0_opp13: opp-1324800000 {
437 opp-hz = /bits/ 64 <1324800000>;
438 opp-peak-kBps = <2188000 16588800>;
441 cpu0_opp14: opp-1420800000 {
442 opp-hz = /bits/ 64 <1420800000>;
443 opp-peak-kBps = <3072000 18124800>;
446 cpu0_opp15: opp-1516800000 {
447 opp-hz = /bits/ 64 <1516800000>;
448 opp-peak-kBps = <3072000 19353600>;
451 cpu0_opp16: opp-1612800000 {
452 opp-hz = /bits/ 64 <1612800000>;
453 opp-peak-kBps = <4068000 19353600>;
456 cpu0_opp17: opp-1689600000 {
457 opp-hz = /bits/ 64 <1689600000>;
458 opp-peak-kBps = <4068000 20889600>;
461 cpu0_opp18: opp-1766400000 {
462 opp-hz = /bits/ 64 <1766400000>;
463 opp-peak-kBps = <4068000 22425600>;
467 cpu4_opp_table: opp-table-cpu4 {
468 compatible = "operating-points-v2";
471 cpu4_opp1: opp-300000000 {
472 opp-hz = /bits/ 64 <300000000>;
473 opp-peak-kBps = <800000 4800000>;
476 cpu4_opp2: opp-403200000 {
477 opp-hz = /bits/ 64 <403200000>;
478 opp-peak-kBps = <800000 4800000>;
481 cpu4_opp3: opp-480000000 {
482 opp-hz = /bits/ 64 <480000000>;
483 opp-peak-kBps = <1804000 4800000>;
486 cpu4_opp4: opp-576000000 {
487 opp-hz = /bits/ 64 <576000000>;
488 opp-peak-kBps = <1804000 4800000>;
491 cpu4_opp5: opp-652800000 {
492 opp-hz = /bits/ 64 <652800000>;
493 opp-peak-kBps = <1804000 4800000>;
496 cpu4_opp6: opp-748800000 {
497 opp-hz = /bits/ 64 <748800000>;
498 opp-peak-kBps = <1804000 4800000>;
501 cpu4_opp7: opp-825600000 {
502 opp-hz = /bits/ 64 <825600000>;
503 opp-peak-kBps = <2188000 9216000>;
506 cpu4_opp8: opp-902400000 {
507 opp-hz = /bits/ 64 <902400000>;
508 opp-peak-kBps = <2188000 9216000>;
511 cpu4_opp9: opp-979200000 {
512 opp-hz = /bits/ 64 <979200000>;
513 opp-peak-kBps = <2188000 9216000>;
516 cpu4_opp10: opp-1056000000 {
517 opp-hz = /bits/ 64 <1056000000>;
518 opp-peak-kBps = <3072000 9216000>;
521 cpu4_opp11: opp-1132800000 {
522 opp-hz = /bits/ 64 <1132800000>;
523 opp-peak-kBps = <3072000 11980800>;
526 cpu4_opp12: opp-1209600000 {
527 opp-hz = /bits/ 64 <1209600000>;
528 opp-peak-kBps = <4068000 11980800>;
531 cpu4_opp13: opp-1286400000 {
532 opp-hz = /bits/ 64 <1286400000>;
533 opp-peak-kBps = <4068000 11980800>;
536 cpu4_opp14: opp-1363200000 {
537 opp-hz = /bits/ 64 <1363200000>;
538 opp-peak-kBps = <4068000 15052800>;
541 cpu4_opp15: opp-1459200000 {
542 opp-hz = /bits/ 64 <1459200000>;
543 opp-peak-kBps = <4068000 15052800>;
546 cpu4_opp16: opp-1536000000 {
547 opp-hz = /bits/ 64 <1536000000>;
548 opp-peak-kBps = <5412000 15052800>;
551 cpu4_opp17: opp-1612800000 {
552 opp-hz = /bits/ 64 <1612800000>;
553 opp-peak-kBps = <5412000 15052800>;
556 cpu4_opp18: opp-1689600000 {
557 opp-hz = /bits/ 64 <1689600000>;
558 opp-peak-kBps = <5412000 19353600>;
561 cpu4_opp19: opp-1766400000 {
562 opp-hz = /bits/ 64 <1766400000>;
563 opp-peak-kBps = <6220000 19353600>;
566 cpu4_opp20: opp-1843200000 {
567 opp-hz = /bits/ 64 <1843200000>;
568 opp-peak-kBps = <6220000 19353600>;
571 cpu4_opp21: opp-1920000000 {
572 opp-hz = /bits/ 64 <1920000000>;
573 opp-peak-kBps = <7216000 19353600>;
576 cpu4_opp22: opp-1996800000 {
577 opp-hz = /bits/ 64 <1996800000>;
578 opp-peak-kBps = <7216000 20889600>;
581 cpu4_opp23: opp-2092800000 {
582 opp-hz = /bits/ 64 <2092800000>;
583 opp-peak-kBps = <7216000 20889600>;
586 cpu4_opp24: opp-2169600000 {
587 opp-hz = /bits/ 64 <2169600000>;
588 opp-peak-kBps = <7216000 20889600>;
591 cpu4_opp25: opp-2246400000 {
592 opp-hz = /bits/ 64 <2246400000>;
593 opp-peak-kBps = <7216000 20889600>;
596 cpu4_opp26: opp-2323200000 {
597 opp-hz = /bits/ 64 <2323200000>;
598 opp-peak-kBps = <7216000 20889600>;
601 cpu4_opp27: opp-2400000000 {
602 opp-hz = /bits/ 64 <2400000000>;
603 opp-peak-kBps = <7216000 22425600>;
606 cpu4_opp28: opp-2476800000 {
607 opp-hz = /bits/ 64 <2476800000>;
608 opp-peak-kBps = <7216000 22425600>;
611 cpu4_opp29: opp-2553600000 {
612 opp-hz = /bits/ 64 <2553600000>;
613 opp-peak-kBps = <7216000 22425600>;
616 cpu4_opp30: opp-2649600000 {
617 opp-hz = /bits/ 64 <2649600000>;
618 opp-peak-kBps = <7216000 22425600>;
621 cpu4_opp31: opp-2745600000 {
622 opp-hz = /bits/ 64 <2745600000>;
623 opp-peak-kBps = <7216000 25497600>;
626 cpu4_opp32: opp-2803200000 {
627 opp-hz = /bits/ 64 <2803200000>;
628 opp-peak-kBps = <7216000 25497600>;
632 dsi_opp_table: opp-table-dsi {
633 compatible = "operating-points-v2";
636 opp-hz = /bits/ 64 <19200000>;
637 required-opps = <&rpmhpd_opp_min_svs>;
641 opp-hz = /bits/ 64 <180000000>;
642 required-opps = <&rpmhpd_opp_low_svs>;
646 opp-hz = /bits/ 64 <275000000>;
647 required-opps = <&rpmhpd_opp_svs>;
651 opp-hz = /bits/ 64 <328580000>;
652 required-opps = <&rpmhpd_opp_svs_l1>;
656 opp-hz = /bits/ 64 <358000000>;
657 required-opps = <&rpmhpd_opp_nom>;
661 qspi_opp_table: opp-table-qspi {
662 compatible = "operating-points-v2";
665 opp-hz = /bits/ 64 <19200000>;
666 required-opps = <&rpmhpd_opp_min_svs>;
670 opp-hz = /bits/ 64 <100000000>;
671 required-opps = <&rpmhpd_opp_low_svs>;
675 opp-hz = /bits/ 64 <150000000>;
676 required-opps = <&rpmhpd_opp_svs>;
680 opp-hz = /bits/ 64 <300000000>;
681 required-opps = <&rpmhpd_opp_nom>;
685 qup_opp_table: opp-table-qup {
686 compatible = "operating-points-v2";
689 opp-hz = /bits/ 64 <50000000>;
690 required-opps = <&rpmhpd_opp_min_svs>;
694 opp-hz = /bits/ 64 <75000000>;
695 required-opps = <&rpmhpd_opp_low_svs>;
699 opp-hz = /bits/ 64 <100000000>;
700 required-opps = <&rpmhpd_opp_svs>;
704 opp-hz = /bits/ 64 <128000000>;
705 required-opps = <&rpmhpd_opp_nom>;
710 compatible = "arm,armv8-pmuv3";
711 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
715 compatible = "arm,psci-1.0";
718 CPU_PD0: power-domain-cpu0 {
719 #power-domain-cells = <0>;
720 power-domains = <&CLUSTER_PD>;
721 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
724 CPU_PD1: power-domain-cpu1 {
725 #power-domain-cells = <0>;
726 power-domains = <&CLUSTER_PD>;
727 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
730 CPU_PD2: power-domain-cpu2 {
731 #power-domain-cells = <0>;
732 power-domains = <&CLUSTER_PD>;
733 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
736 CPU_PD3: power-domain-cpu3 {
737 #power-domain-cells = <0>;
738 power-domains = <&CLUSTER_PD>;
739 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
742 CPU_PD4: power-domain-cpu4 {
743 #power-domain-cells = <0>;
744 power-domains = <&CLUSTER_PD>;
745 domain-idle-states = <&BIG_CPU_SLEEP_0>;
748 CPU_PD5: power-domain-cpu5 {
749 #power-domain-cells = <0>;
750 power-domains = <&CLUSTER_PD>;
751 domain-idle-states = <&BIG_CPU_SLEEP_0>;
754 CPU_PD6: power-domain-cpu6 {
755 #power-domain-cells = <0>;
756 power-domains = <&CLUSTER_PD>;
757 domain-idle-states = <&BIG_CPU_SLEEP_0>;
760 CPU_PD7: power-domain-cpu7 {
761 #power-domain-cells = <0>;
762 power-domains = <&CLUSTER_PD>;
763 domain-idle-states = <&BIG_CPU_SLEEP_0>;
766 CLUSTER_PD: power-domain-cluster {
767 #power-domain-cells = <0>;
768 domain-idle-states = <&CLUSTER_SLEEP_0>;
773 #address-cells = <2>;
777 hyp_mem: hyp-mem@85700000 {
778 reg = <0 0x85700000 0 0x600000>;
782 xbl_mem: xbl-mem@85e00000 {
783 reg = <0 0x85e00000 0 0x100000>;
787 aop_mem: aop-mem@85fc0000 {
788 reg = <0 0x85fc0000 0 0x20000>;
792 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
793 compatible = "qcom,cmd-db";
794 reg = <0x0 0x85fe0000 0 0x20000>;
799 compatible = "qcom,smem";
800 reg = <0x0 0x86000000 0 0x200000>;
802 hwlocks = <&tcsr_mutex 3>;
805 tz_mem: tz@86200000 {
806 reg = <0 0x86200000 0 0x2d00000>;
810 rmtfs_mem: rmtfs@88f00000 {
811 compatible = "qcom,rmtfs-mem";
812 reg = <0 0x88f00000 0 0x200000>;
815 qcom,client-id = <1>;
819 qseecom_mem: qseecom@8ab00000 {
820 reg = <0 0x8ab00000 0 0x1400000>;
824 camera_mem: camera-mem@8bf00000 {
825 reg = <0 0x8bf00000 0 0x500000>;
829 ipa_fw_mem: ipa-fw@8c400000 {
830 reg = <0 0x8c400000 0 0x10000>;
834 ipa_gsi_mem: ipa-gsi@8c410000 {
835 reg = <0 0x8c410000 0 0x5000>;
839 gpu_mem: gpu@8c415000 {
840 reg = <0 0x8c415000 0 0x2000>;
844 adsp_mem: adsp@8c500000 {
845 reg = <0 0x8c500000 0 0x1a00000>;
849 wlan_msa_mem: wlan-msa@8df00000 {
850 reg = <0 0x8df00000 0 0x100000>;
854 mpss_region: mpss@8e000000 {
855 reg = <0 0x8e000000 0 0x7800000>;
859 venus_mem: venus@95800000 {
860 reg = <0 0x95800000 0 0x500000>;
864 cdsp_mem: cdsp@95d00000 {
865 reg = <0 0x95d00000 0 0x800000>;
869 mba_region: mba@96500000 {
870 reg = <0 0x96500000 0 0x200000>;
874 slpi_mem: slpi@96700000 {
875 reg = <0 0x96700000 0 0x1400000>;
879 spss_mem: spss@97b00000 {
880 reg = <0 0x97b00000 0 0x100000>;
884 mdata_mem: mpss-metadata {
885 alloc-ranges = <0 0xa0000000 0 0x20000000>;
890 fastrpc_mem: fastrpc {
891 compatible = "shared-dma-pool";
892 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
893 alignment = <0x0 0x400000>;
894 size = <0x0 0x1000000>;
899 adsp_pas: remoteproc-adsp {
900 compatible = "qcom,sdm845-adsp-pas";
902 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
903 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
904 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
907 interrupt-names = "wdog", "fatal", "ready",
908 "handover", "stop-ack";
910 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 memory-region = <&adsp_mem>;
915 qcom,qmp = <&aoss_qmp>;
917 qcom,smem-states = <&adsp_smp2p_out 0>;
918 qcom,smem-state-names = "stop";
923 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
925 qcom,remote-pid = <2>;
926 mboxes = <&apss_shared 8>;
929 compatible = "qcom,apr-v2";
930 qcom,glink-channels = "apr_audio_svc";
931 qcom,domain = <APR_DOMAIN_ADSP>;
932 #address-cells = <1>;
934 qcom,intents = <512 20>;
937 reg = <APR_SVC_ADSP_CORE>;
938 compatible = "qcom,q6core";
939 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
943 compatible = "qcom,q6afe";
945 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
947 compatible = "qcom,q6afe-dais";
948 #address-cells = <1>;
950 #sound-dai-cells = <1>;
955 compatible = "qcom,q6asm";
957 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
959 compatible = "qcom,q6asm-dais";
960 #address-cells = <1>;
962 #sound-dai-cells = <1>;
963 iommus = <&apps_smmu 0x1821 0x0>;
968 compatible = "qcom,q6adm";
970 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
972 compatible = "qcom,q6adm-routing";
973 #sound-dai-cells = <0>;
979 compatible = "qcom,fastrpc";
980 qcom,glink-channels = "fastrpcglink-apps-dsp";
982 qcom,non-secure-domain;
983 #address-cells = <1>;
987 compatible = "qcom,fastrpc-compute-cb";
989 iommus = <&apps_smmu 0x1823 0x0>;
993 compatible = "qcom,fastrpc-compute-cb";
995 iommus = <&apps_smmu 0x1824 0x0>;
1001 cdsp_pas: remoteproc-cdsp {
1002 compatible = "qcom,sdm845-cdsp-pas";
1004 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1005 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1006 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1009 interrupt-names = "wdog", "fatal", "ready",
1010 "handover", "stop-ack";
1012 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 memory-region = <&cdsp_mem>;
1017 qcom,qmp = <&aoss_qmp>;
1019 qcom,smem-states = <&cdsp_smp2p_out 0>;
1020 qcom,smem-state-names = "stop";
1022 status = "disabled";
1025 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1027 qcom,remote-pid = <5>;
1028 mboxes = <&apss_shared 4>;
1030 compatible = "qcom,fastrpc";
1031 qcom,glink-channels = "fastrpcglink-apps-dsp";
1033 qcom,non-secure-domain;
1034 #address-cells = <1>;
1038 compatible = "qcom,fastrpc-compute-cb";
1040 iommus = <&apps_smmu 0x1401 0x30>;
1044 compatible = "qcom,fastrpc-compute-cb";
1046 iommus = <&apps_smmu 0x1402 0x30>;
1050 compatible = "qcom,fastrpc-compute-cb";
1052 iommus = <&apps_smmu 0x1403 0x30>;
1056 compatible = "qcom,fastrpc-compute-cb";
1058 iommus = <&apps_smmu 0x1404 0x30>;
1062 compatible = "qcom,fastrpc-compute-cb";
1064 iommus = <&apps_smmu 0x1405 0x30>;
1068 compatible = "qcom,fastrpc-compute-cb";
1070 iommus = <&apps_smmu 0x1406 0x30>;
1074 compatible = "qcom,fastrpc-compute-cb";
1076 iommus = <&apps_smmu 0x1407 0x30>;
1080 compatible = "qcom,fastrpc-compute-cb";
1082 iommus = <&apps_smmu 0x1408 0x30>;
1089 compatible = "qcom,smp2p";
1090 qcom,smem = <94>, <432>;
1092 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1094 mboxes = <&apss_shared 6>;
1096 qcom,local-pid = <0>;
1097 qcom,remote-pid = <5>;
1099 cdsp_smp2p_out: master-kernel {
1100 qcom,entry-name = "master-kernel";
1101 #qcom,smem-state-cells = <1>;
1104 cdsp_smp2p_in: slave-kernel {
1105 qcom,entry-name = "slave-kernel";
1107 interrupt-controller;
1108 #interrupt-cells = <2>;
1113 compatible = "qcom,smp2p";
1114 qcom,smem = <443>, <429>;
1116 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1118 mboxes = <&apss_shared 10>;
1120 qcom,local-pid = <0>;
1121 qcom,remote-pid = <2>;
1123 adsp_smp2p_out: master-kernel {
1124 qcom,entry-name = "master-kernel";
1125 #qcom,smem-state-cells = <1>;
1128 adsp_smp2p_in: slave-kernel {
1129 qcom,entry-name = "slave-kernel";
1131 interrupt-controller;
1132 #interrupt-cells = <2>;
1137 compatible = "qcom,smp2p";
1138 qcom,smem = <435>, <428>;
1139 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1140 mboxes = <&apss_shared 14>;
1141 qcom,local-pid = <0>;
1142 qcom,remote-pid = <1>;
1144 modem_smp2p_out: master-kernel {
1145 qcom,entry-name = "master-kernel";
1146 #qcom,smem-state-cells = <1>;
1149 modem_smp2p_in: slave-kernel {
1150 qcom,entry-name = "slave-kernel";
1151 interrupt-controller;
1152 #interrupt-cells = <2>;
1155 ipa_smp2p_out: ipa-ap-to-modem {
1156 qcom,entry-name = "ipa";
1157 #qcom,smem-state-cells = <1>;
1160 ipa_smp2p_in: ipa-modem-to-ap {
1161 qcom,entry-name = "ipa";
1162 interrupt-controller;
1163 #interrupt-cells = <2>;
1168 compatible = "qcom,smp2p";
1169 qcom,smem = <481>, <430>;
1170 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1171 mboxes = <&apss_shared 26>;
1172 qcom,local-pid = <0>;
1173 qcom,remote-pid = <3>;
1175 slpi_smp2p_out: master-kernel {
1176 qcom,entry-name = "master-kernel";
1177 #qcom,smem-state-cells = <1>;
1180 slpi_smp2p_in: slave-kernel {
1181 qcom,entry-name = "slave-kernel";
1182 interrupt-controller;
1183 #interrupt-cells = <2>;
1188 #address-cells = <2>;
1190 ranges = <0 0 0 0 0x10 0>;
1191 dma-ranges = <0 0 0 0 0x10 0>;
1192 compatible = "simple-bus";
1194 gcc: clock-controller@100000 {
1195 compatible = "qcom,gcc-sdm845";
1196 reg = <0 0x00100000 0 0x1f0000>;
1197 clocks = <&rpmhcc RPMH_CXO_CLK>,
1198 <&rpmhcc RPMH_CXO_CLK_A>,
1202 clock-names = "bi_tcxo",
1209 #power-domain-cells = <1>;
1210 power-domains = <&rpmhpd SDM845_CX>;
1214 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1215 reg = <0 0x00784000 0 0x8ff>;
1216 #address-cells = <1>;
1219 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1224 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1231 compatible = "qcom,prng-ee";
1232 reg = <0 0x00793000 0 0x1000>;
1233 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1234 clock-names = "core";
1237 gpi_dma0: dma-controller@800000 {
1239 compatible = "qcom,sdm845-gpi-dma";
1240 reg = <0 0x00800000 0 0x60000>;
1241 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1254 dma-channels = <13>;
1255 dma-channel-mask = <0xfa>;
1256 iommus = <&apps_smmu 0x0016 0x0>;
1257 status = "disabled";
1260 qupv3_id_0: geniqup@8c0000 {
1261 compatible = "qcom,geni-se-qup";
1262 reg = <0 0x008c0000 0 0x6000>;
1263 clock-names = "m-ahb", "s-ahb";
1264 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1265 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1266 iommus = <&apps_smmu 0x3 0x0>;
1267 #address-cells = <2>;
1270 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1271 interconnect-names = "qup-core";
1272 status = "disabled";
1275 compatible = "qcom,geni-i2c";
1276 reg = <0 0x00880000 0 0x4000>;
1278 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1279 pinctrl-names = "default";
1280 pinctrl-0 = <&qup_i2c0_default>;
1281 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1282 #address-cells = <1>;
1284 power-domains = <&rpmhpd SDM845_CX>;
1285 operating-points-v2 = <&qup_opp_table>;
1286 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1287 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1288 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1289 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1291 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1292 dma-names = "tx", "rx";
1293 status = "disabled";
1297 compatible = "qcom,geni-spi";
1298 reg = <0 0x00880000 0 0x4000>;
1300 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&qup_spi0_default>;
1303 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1304 #address-cells = <1>;
1306 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1307 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1308 interconnect-names = "qup-core", "qup-config";
1309 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1310 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1311 dma-names = "tx", "rx";
1312 status = "disabled";
1315 uart0: serial@880000 {
1316 compatible = "qcom,geni-uart";
1317 reg = <0 0x00880000 0 0x4000>;
1319 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1320 pinctrl-names = "default";
1321 pinctrl-0 = <&qup_uart0_default>;
1322 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1323 power-domains = <&rpmhpd SDM845_CX>;
1324 operating-points-v2 = <&qup_opp_table>;
1325 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1326 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1327 interconnect-names = "qup-core", "qup-config";
1328 status = "disabled";
1332 compatible = "qcom,geni-i2c";
1333 reg = <0 0x00884000 0 0x4000>;
1335 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&qup_i2c1_default>;
1338 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1339 #address-cells = <1>;
1341 power-domains = <&rpmhpd SDM845_CX>;
1342 operating-points-v2 = <&qup_opp_table>;
1343 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1344 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1345 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1346 interconnect-names = "qup-core", "qup-config", "qup-memory";
1347 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1348 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1349 dma-names = "tx", "rx";
1350 status = "disabled";
1354 compatible = "qcom,geni-spi";
1355 reg = <0 0x00884000 0 0x4000>;
1357 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1358 pinctrl-names = "default";
1359 pinctrl-0 = <&qup_spi1_default>;
1360 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1361 #address-cells = <1>;
1363 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1364 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1365 interconnect-names = "qup-core", "qup-config";
1366 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1367 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1368 dma-names = "tx", "rx";
1369 status = "disabled";
1372 uart1: serial@884000 {
1373 compatible = "qcom,geni-uart";
1374 reg = <0 0x00884000 0 0x4000>;
1376 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1377 pinctrl-names = "default";
1378 pinctrl-0 = <&qup_uart1_default>;
1379 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1380 power-domains = <&rpmhpd SDM845_CX>;
1381 operating-points-v2 = <&qup_opp_table>;
1382 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1383 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1384 interconnect-names = "qup-core", "qup-config";
1385 status = "disabled";
1389 compatible = "qcom,geni-i2c";
1390 reg = <0 0x00888000 0 0x4000>;
1392 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1393 pinctrl-names = "default";
1394 pinctrl-0 = <&qup_i2c2_default>;
1395 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1396 #address-cells = <1>;
1398 power-domains = <&rpmhpd SDM845_CX>;
1399 operating-points-v2 = <&qup_opp_table>;
1400 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1401 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1402 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1403 interconnect-names = "qup-core", "qup-config", "qup-memory";
1404 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1405 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1406 dma-names = "tx", "rx";
1407 status = "disabled";
1411 compatible = "qcom,geni-spi";
1412 reg = <0 0x00888000 0 0x4000>;
1414 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&qup_spi2_default>;
1417 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1418 #address-cells = <1>;
1420 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1421 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1422 interconnect-names = "qup-core", "qup-config";
1423 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1424 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1425 dma-names = "tx", "rx";
1426 status = "disabled";
1429 uart2: serial@888000 {
1430 compatible = "qcom,geni-uart";
1431 reg = <0 0x00888000 0 0x4000>;
1433 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1434 pinctrl-names = "default";
1435 pinctrl-0 = <&qup_uart2_default>;
1436 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1437 power-domains = <&rpmhpd SDM845_CX>;
1438 operating-points-v2 = <&qup_opp_table>;
1439 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1440 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1441 interconnect-names = "qup-core", "qup-config";
1442 status = "disabled";
1446 compatible = "qcom,geni-i2c";
1447 reg = <0 0x0088c000 0 0x4000>;
1449 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&qup_i2c3_default>;
1452 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1453 #address-cells = <1>;
1455 power-domains = <&rpmhpd SDM845_CX>;
1456 operating-points-v2 = <&qup_opp_table>;
1457 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1458 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1459 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1460 interconnect-names = "qup-core", "qup-config", "qup-memory";
1461 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1462 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1463 dma-names = "tx", "rx";
1464 status = "disabled";
1468 compatible = "qcom,geni-spi";
1469 reg = <0 0x0088c000 0 0x4000>;
1471 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1472 pinctrl-names = "default";
1473 pinctrl-0 = <&qup_spi3_default>;
1474 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1475 #address-cells = <1>;
1477 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1478 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1479 interconnect-names = "qup-core", "qup-config";
1480 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1481 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1482 dma-names = "tx", "rx";
1483 status = "disabled";
1486 uart3: serial@88c000 {
1487 compatible = "qcom,geni-uart";
1488 reg = <0 0x0088c000 0 0x4000>;
1490 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1491 pinctrl-names = "default";
1492 pinctrl-0 = <&qup_uart3_default>;
1493 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1494 power-domains = <&rpmhpd SDM845_CX>;
1495 operating-points-v2 = <&qup_opp_table>;
1496 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1497 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1498 interconnect-names = "qup-core", "qup-config";
1499 status = "disabled";
1503 compatible = "qcom,geni-i2c";
1504 reg = <0 0x00890000 0 0x4000>;
1506 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1507 pinctrl-names = "default";
1508 pinctrl-0 = <&qup_i2c4_default>;
1509 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1510 #address-cells = <1>;
1512 power-domains = <&rpmhpd SDM845_CX>;
1513 operating-points-v2 = <&qup_opp_table>;
1514 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1515 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1516 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1517 interconnect-names = "qup-core", "qup-config", "qup-memory";
1518 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1519 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1520 dma-names = "tx", "rx";
1521 status = "disabled";
1525 compatible = "qcom,geni-spi";
1526 reg = <0 0x00890000 0 0x4000>;
1528 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1529 pinctrl-names = "default";
1530 pinctrl-0 = <&qup_spi4_default>;
1531 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1532 #address-cells = <1>;
1534 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1535 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1536 interconnect-names = "qup-core", "qup-config";
1537 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1538 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1539 dma-names = "tx", "rx";
1540 status = "disabled";
1543 uart4: serial@890000 {
1544 compatible = "qcom,geni-uart";
1545 reg = <0 0x00890000 0 0x4000>;
1547 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1548 pinctrl-names = "default";
1549 pinctrl-0 = <&qup_uart4_default>;
1550 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1551 power-domains = <&rpmhpd SDM845_CX>;
1552 operating-points-v2 = <&qup_opp_table>;
1553 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1554 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1555 interconnect-names = "qup-core", "qup-config";
1556 status = "disabled";
1560 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00894000 0 0x4000>;
1563 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&qup_i2c5_default>;
1566 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1567 #address-cells = <1>;
1569 power-domains = <&rpmhpd SDM845_CX>;
1570 operating-points-v2 = <&qup_opp_table>;
1571 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1572 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1573 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1574 interconnect-names = "qup-core", "qup-config", "qup-memory";
1575 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1576 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1577 dma-names = "tx", "rx";
1578 status = "disabled";
1582 compatible = "qcom,geni-spi";
1583 reg = <0 0x00894000 0 0x4000>;
1585 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1586 pinctrl-names = "default";
1587 pinctrl-0 = <&qup_spi5_default>;
1588 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1589 #address-cells = <1>;
1591 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1592 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1593 interconnect-names = "qup-core", "qup-config";
1594 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1595 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1596 dma-names = "tx", "rx";
1597 status = "disabled";
1600 uart5: serial@894000 {
1601 compatible = "qcom,geni-uart";
1602 reg = <0 0x00894000 0 0x4000>;
1604 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1605 pinctrl-names = "default";
1606 pinctrl-0 = <&qup_uart5_default>;
1607 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1608 power-domains = <&rpmhpd SDM845_CX>;
1609 operating-points-v2 = <&qup_opp_table>;
1610 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1611 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1612 interconnect-names = "qup-core", "qup-config";
1613 status = "disabled";
1617 compatible = "qcom,geni-i2c";
1618 reg = <0 0x00898000 0 0x4000>;
1620 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&qup_i2c6_default>;
1623 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1624 #address-cells = <1>;
1626 power-domains = <&rpmhpd SDM845_CX>;
1627 operating-points-v2 = <&qup_opp_table>;
1628 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1629 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1630 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1631 interconnect-names = "qup-core", "qup-config", "qup-memory";
1632 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1633 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1634 dma-names = "tx", "rx";
1635 status = "disabled";
1639 compatible = "qcom,geni-spi";
1640 reg = <0 0x00898000 0 0x4000>;
1642 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1643 pinctrl-names = "default";
1644 pinctrl-0 = <&qup_spi6_default>;
1645 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1646 #address-cells = <1>;
1648 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1649 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1650 interconnect-names = "qup-core", "qup-config";
1651 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1652 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1653 dma-names = "tx", "rx";
1654 status = "disabled";
1657 uart6: serial@898000 {
1658 compatible = "qcom,geni-uart";
1659 reg = <0 0x00898000 0 0x4000>;
1661 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1662 pinctrl-names = "default";
1663 pinctrl-0 = <&qup_uart6_default>;
1664 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1665 power-domains = <&rpmhpd SDM845_CX>;
1666 operating-points-v2 = <&qup_opp_table>;
1667 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1668 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1669 interconnect-names = "qup-core", "qup-config";
1670 status = "disabled";
1674 compatible = "qcom,geni-i2c";
1675 reg = <0 0x0089c000 0 0x4000>;
1677 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1678 pinctrl-names = "default";
1679 pinctrl-0 = <&qup_i2c7_default>;
1680 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1681 #address-cells = <1>;
1683 power-domains = <&rpmhpd SDM845_CX>;
1684 operating-points-v2 = <&qup_opp_table>;
1685 status = "disabled";
1689 compatible = "qcom,geni-spi";
1690 reg = <0 0x0089c000 0 0x4000>;
1692 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1693 pinctrl-names = "default";
1694 pinctrl-0 = <&qup_spi7_default>;
1695 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1696 #address-cells = <1>;
1698 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1699 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1700 interconnect-names = "qup-core", "qup-config";
1701 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1702 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1703 dma-names = "tx", "rx";
1704 status = "disabled";
1707 uart7: serial@89c000 {
1708 compatible = "qcom,geni-uart";
1709 reg = <0 0x0089c000 0 0x4000>;
1711 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1712 pinctrl-names = "default";
1713 pinctrl-0 = <&qup_uart7_default>;
1714 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1715 power-domains = <&rpmhpd SDM845_CX>;
1716 operating-points-v2 = <&qup_opp_table>;
1717 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1718 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1719 interconnect-names = "qup-core", "qup-config";
1720 status = "disabled";
1724 gpi_dma1: dma-controller@a00000 {
1726 compatible = "qcom,sdm845-gpi-dma";
1727 reg = <0 0x00a00000 0 0x60000>;
1728 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1729 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1730 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1741 dma-channels = <13>;
1742 dma-channel-mask = <0xfa>;
1743 iommus = <&apps_smmu 0x06d6 0x0>;
1744 status = "disabled";
1747 qupv3_id_1: geniqup@ac0000 {
1748 compatible = "qcom,geni-se-qup";
1749 reg = <0 0x00ac0000 0 0x6000>;
1750 clock-names = "m-ahb", "s-ahb";
1751 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1752 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1753 iommus = <&apps_smmu 0x6c3 0x0>;
1754 #address-cells = <2>;
1757 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1758 interconnect-names = "qup-core";
1759 status = "disabled";
1762 compatible = "qcom,geni-i2c";
1763 reg = <0 0x00a80000 0 0x4000>;
1765 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1766 pinctrl-names = "default";
1767 pinctrl-0 = <&qup_i2c8_default>;
1768 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1769 #address-cells = <1>;
1771 power-domains = <&rpmhpd SDM845_CX>;
1772 operating-points-v2 = <&qup_opp_table>;
1773 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1774 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1775 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1776 interconnect-names = "qup-core", "qup-config", "qup-memory";
1777 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1778 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1779 dma-names = "tx", "rx";
1780 status = "disabled";
1784 compatible = "qcom,geni-spi";
1785 reg = <0 0x00a80000 0 0x4000>;
1787 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1788 pinctrl-names = "default";
1789 pinctrl-0 = <&qup_spi8_default>;
1790 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1791 #address-cells = <1>;
1793 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1794 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1795 interconnect-names = "qup-core", "qup-config";
1796 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1797 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1798 dma-names = "tx", "rx";
1799 status = "disabled";
1802 uart8: serial@a80000 {
1803 compatible = "qcom,geni-uart";
1804 reg = <0 0x00a80000 0 0x4000>;
1806 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1807 pinctrl-names = "default";
1808 pinctrl-0 = <&qup_uart8_default>;
1809 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1810 power-domains = <&rpmhpd SDM845_CX>;
1811 operating-points-v2 = <&qup_opp_table>;
1812 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1813 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1814 interconnect-names = "qup-core", "qup-config";
1815 status = "disabled";
1819 compatible = "qcom,geni-i2c";
1820 reg = <0 0x00a84000 0 0x4000>;
1822 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1823 pinctrl-names = "default";
1824 pinctrl-0 = <&qup_i2c9_default>;
1825 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1826 #address-cells = <1>;
1828 power-domains = <&rpmhpd SDM845_CX>;
1829 operating-points-v2 = <&qup_opp_table>;
1830 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1831 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1832 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1833 interconnect-names = "qup-core", "qup-config", "qup-memory";
1834 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1835 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1836 dma-names = "tx", "rx";
1837 status = "disabled";
1841 compatible = "qcom,geni-spi";
1842 reg = <0 0x00a84000 0 0x4000>;
1844 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1845 pinctrl-names = "default";
1846 pinctrl-0 = <&qup_spi9_default>;
1847 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1848 #address-cells = <1>;
1850 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1851 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1852 interconnect-names = "qup-core", "qup-config";
1853 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1854 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1855 dma-names = "tx", "rx";
1856 status = "disabled";
1859 uart9: serial@a84000 {
1860 compatible = "qcom,geni-debug-uart";
1861 reg = <0 0x00a84000 0 0x4000>;
1863 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1864 pinctrl-names = "default";
1865 pinctrl-0 = <&qup_uart9_default>;
1866 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1867 power-domains = <&rpmhpd SDM845_CX>;
1868 operating-points-v2 = <&qup_opp_table>;
1869 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1870 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1871 interconnect-names = "qup-core", "qup-config";
1872 status = "disabled";
1876 compatible = "qcom,geni-i2c";
1877 reg = <0 0x00a88000 0 0x4000>;
1879 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1880 pinctrl-names = "default";
1881 pinctrl-0 = <&qup_i2c10_default>;
1882 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1883 #address-cells = <1>;
1885 power-domains = <&rpmhpd SDM845_CX>;
1886 operating-points-v2 = <&qup_opp_table>;
1887 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1888 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1889 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1890 interconnect-names = "qup-core", "qup-config", "qup-memory";
1891 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1892 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1893 dma-names = "tx", "rx";
1894 status = "disabled";
1898 compatible = "qcom,geni-spi";
1899 reg = <0 0x00a88000 0 0x4000>;
1901 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1902 pinctrl-names = "default";
1903 pinctrl-0 = <&qup_spi10_default>;
1904 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1905 #address-cells = <1>;
1907 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1908 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1909 interconnect-names = "qup-core", "qup-config";
1910 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1911 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1912 dma-names = "tx", "rx";
1913 status = "disabled";
1916 uart10: serial@a88000 {
1917 compatible = "qcom,geni-uart";
1918 reg = <0 0x00a88000 0 0x4000>;
1920 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1921 pinctrl-names = "default";
1922 pinctrl-0 = <&qup_uart10_default>;
1923 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1924 power-domains = <&rpmhpd SDM845_CX>;
1925 operating-points-v2 = <&qup_opp_table>;
1926 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1927 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1928 interconnect-names = "qup-core", "qup-config";
1929 status = "disabled";
1933 compatible = "qcom,geni-i2c";
1934 reg = <0 0x00a8c000 0 0x4000>;
1936 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1937 pinctrl-names = "default";
1938 pinctrl-0 = <&qup_i2c11_default>;
1939 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1940 #address-cells = <1>;
1942 power-domains = <&rpmhpd SDM845_CX>;
1943 operating-points-v2 = <&qup_opp_table>;
1944 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1945 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1946 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1947 interconnect-names = "qup-core", "qup-config", "qup-memory";
1948 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1949 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1950 dma-names = "tx", "rx";
1951 status = "disabled";
1955 compatible = "qcom,geni-spi";
1956 reg = <0 0x00a8c000 0 0x4000>;
1958 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1959 pinctrl-names = "default";
1960 pinctrl-0 = <&qup_spi11_default>;
1961 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1962 #address-cells = <1>;
1964 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1965 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1966 interconnect-names = "qup-core", "qup-config";
1967 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1968 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1969 dma-names = "tx", "rx";
1970 status = "disabled";
1973 uart11: serial@a8c000 {
1974 compatible = "qcom,geni-uart";
1975 reg = <0 0x00a8c000 0 0x4000>;
1977 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1978 pinctrl-names = "default";
1979 pinctrl-0 = <&qup_uart11_default>;
1980 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1981 power-domains = <&rpmhpd SDM845_CX>;
1982 operating-points-v2 = <&qup_opp_table>;
1983 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1984 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1985 interconnect-names = "qup-core", "qup-config";
1986 status = "disabled";
1990 compatible = "qcom,geni-i2c";
1991 reg = <0 0x00a90000 0 0x4000>;
1993 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1994 pinctrl-names = "default";
1995 pinctrl-0 = <&qup_i2c12_default>;
1996 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 #address-cells = <1>;
1999 power-domains = <&rpmhpd SDM845_CX>;
2000 operating-points-v2 = <&qup_opp_table>;
2001 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2002 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2003 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2004 interconnect-names = "qup-core", "qup-config", "qup-memory";
2005 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2006 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
2007 dma-names = "tx", "rx";
2008 status = "disabled";
2012 compatible = "qcom,geni-spi";
2013 reg = <0 0x00a90000 0 0x4000>;
2015 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2016 pinctrl-names = "default";
2017 pinctrl-0 = <&qup_spi12_default>;
2018 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2019 #address-cells = <1>;
2021 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2022 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2023 interconnect-names = "qup-core", "qup-config";
2024 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2025 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2026 dma-names = "tx", "rx";
2027 status = "disabled";
2030 uart12: serial@a90000 {
2031 compatible = "qcom,geni-uart";
2032 reg = <0 0x00a90000 0 0x4000>;
2034 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2035 pinctrl-names = "default";
2036 pinctrl-0 = <&qup_uart12_default>;
2037 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2038 power-domains = <&rpmhpd SDM845_CX>;
2039 operating-points-v2 = <&qup_opp_table>;
2040 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2041 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2042 interconnect-names = "qup-core", "qup-config";
2043 status = "disabled";
2047 compatible = "qcom,geni-i2c";
2048 reg = <0 0x00a94000 0 0x4000>;
2050 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2051 pinctrl-names = "default";
2052 pinctrl-0 = <&qup_i2c13_default>;
2053 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2054 #address-cells = <1>;
2056 power-domains = <&rpmhpd SDM845_CX>;
2057 operating-points-v2 = <&qup_opp_table>;
2058 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2059 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2060 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2061 interconnect-names = "qup-core", "qup-config", "qup-memory";
2062 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2063 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2064 dma-names = "tx", "rx";
2065 status = "disabled";
2069 compatible = "qcom,geni-spi";
2070 reg = <0 0x00a94000 0 0x4000>;
2072 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2073 pinctrl-names = "default";
2074 pinctrl-0 = <&qup_spi13_default>;
2075 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2076 #address-cells = <1>;
2078 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2079 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2080 interconnect-names = "qup-core", "qup-config";
2081 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2082 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2083 dma-names = "tx", "rx";
2084 status = "disabled";
2087 uart13: serial@a94000 {
2088 compatible = "qcom,geni-uart";
2089 reg = <0 0x00a94000 0 0x4000>;
2091 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2092 pinctrl-names = "default";
2093 pinctrl-0 = <&qup_uart13_default>;
2094 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2095 power-domains = <&rpmhpd SDM845_CX>;
2096 operating-points-v2 = <&qup_opp_table>;
2097 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2098 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2099 interconnect-names = "qup-core", "qup-config";
2100 status = "disabled";
2104 compatible = "qcom,geni-i2c";
2105 reg = <0 0x00a98000 0 0x4000>;
2107 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2108 pinctrl-names = "default";
2109 pinctrl-0 = <&qup_i2c14_default>;
2110 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2111 #address-cells = <1>;
2113 power-domains = <&rpmhpd SDM845_CX>;
2114 operating-points-v2 = <&qup_opp_table>;
2115 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2116 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2117 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2118 interconnect-names = "qup-core", "qup-config", "qup-memory";
2119 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2120 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2121 dma-names = "tx", "rx";
2122 status = "disabled";
2126 compatible = "qcom,geni-spi";
2127 reg = <0 0x00a98000 0 0x4000>;
2129 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2130 pinctrl-names = "default";
2131 pinctrl-0 = <&qup_spi14_default>;
2132 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2133 #address-cells = <1>;
2135 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2136 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2137 interconnect-names = "qup-core", "qup-config";
2138 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2139 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2140 dma-names = "tx", "rx";
2141 status = "disabled";
2144 uart14: serial@a98000 {
2145 compatible = "qcom,geni-uart";
2146 reg = <0 0x00a98000 0 0x4000>;
2148 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2149 pinctrl-names = "default";
2150 pinctrl-0 = <&qup_uart14_default>;
2151 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2152 power-domains = <&rpmhpd SDM845_CX>;
2153 operating-points-v2 = <&qup_opp_table>;
2154 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2155 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2156 interconnect-names = "qup-core", "qup-config";
2157 status = "disabled";
2161 compatible = "qcom,geni-i2c";
2162 reg = <0 0x00a9c000 0 0x4000>;
2164 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2165 pinctrl-names = "default";
2166 pinctrl-0 = <&qup_i2c15_default>;
2167 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2168 #address-cells = <1>;
2170 power-domains = <&rpmhpd SDM845_CX>;
2171 operating-points-v2 = <&qup_opp_table>;
2172 status = "disabled";
2173 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2174 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2175 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2176 interconnect-names = "qup-core", "qup-config", "qup-memory";
2177 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2178 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2179 dma-names = "tx", "rx";
2183 compatible = "qcom,geni-spi";
2184 reg = <0 0x00a9c000 0 0x4000>;
2186 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2187 pinctrl-names = "default";
2188 pinctrl-0 = <&qup_spi15_default>;
2189 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2190 #address-cells = <1>;
2192 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2193 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2194 interconnect-names = "qup-core", "qup-config";
2195 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2196 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2197 dma-names = "tx", "rx";
2198 status = "disabled";
2201 uart15: serial@a9c000 {
2202 compatible = "qcom,geni-uart";
2203 reg = <0 0x00a9c000 0 0x4000>;
2205 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2206 pinctrl-names = "default";
2207 pinctrl-0 = <&qup_uart15_default>;
2208 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2209 power-domains = <&rpmhpd SDM845_CX>;
2210 operating-points-v2 = <&qup_opp_table>;
2211 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2212 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2213 interconnect-names = "qup-core", "qup-config";
2214 status = "disabled";
2218 llcc: system-cache-controller@1100000 {
2219 compatible = "qcom,sdm845-llcc";
2220 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2221 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2222 <0 0x01300000 0 0x50000>;
2223 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2224 "llcc3_base", "llcc_broadcast_base";
2225 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2229 compatible = "qcom,sdm845-dcc", "qcom,dcc";
2230 reg = <0x0 0x010a2000 0x0 0x1000>,
2231 <0x0 0x010ae000 0x0 0x2000>;
2235 compatible = "qcom,sdm845-llcc-bwmon";
2236 reg = <0 0x0114a000 0 0x1000>;
2237 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2238 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2240 operating-points-v2 = <&llcc_bwmon_opp_table>;
2242 llcc_bwmon_opp_table: opp-table {
2243 compatible = "operating-points-v2";
2246 * The interconnect path bandwidth taken from
2247 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2248 * interconnect. This also matches the
2249 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2250 * bus width: 4 bytes) from msm-4.9 downstream
2254 opp-peak-kBps = <800000>;
2257 opp-peak-kBps = <1804000>;
2260 opp-peak-kBps = <3072000>;
2263 opp-peak-kBps = <5412000>;
2266 opp-peak-kBps = <7216000>;
2272 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2273 reg = <0 0x01436400 0 0x600>;
2274 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2275 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
2277 operating-points-v2 = <&cpu_bwmon_opp_table>;
2279 cpu_bwmon_opp_table: opp-table {
2280 compatible = "operating-points-v2";
2283 * The interconnect path bandwidth taken from
2284 * cpu4_opp_table bandwidth for OSM L3
2285 * interconnect. This also matches the OSM L3
2286 * from bandwidth table of qcom,cpu4-l3lat-mon
2287 * (qcom,core-dev-table, bus width: 16 bytes)
2288 * from msm-4.9 downstream kernel.
2291 opp-peak-kBps = <4800000>;
2294 opp-peak-kBps = <9216000>;
2297 opp-peak-kBps = <15052800>;
2300 opp-peak-kBps = <20889600>;
2303 opp-peak-kBps = <25497600>;
2308 pcie0: pci@1c00000 {
2309 compatible = "qcom,pcie-sdm845";
2310 reg = <0 0x01c00000 0 0x2000>,
2311 <0 0x60000000 0 0xf1d>,
2312 <0 0x60000f20 0 0xa8>,
2313 <0 0x60100000 0 0x100000>,
2314 <0 0x01c07000 0 0x1000>;
2315 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2316 device_type = "pci";
2317 linux,pci-domain = <0>;
2318 bus-range = <0x00 0xff>;
2321 #address-cells = <3>;
2324 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2325 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2327 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2328 interrupt-names = "msi";
2329 #interrupt-cells = <1>;
2330 interrupt-map-mask = <0 0 0 0x7>;
2331 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2332 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2333 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2334 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2336 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2337 <&gcc GCC_PCIE_0_AUX_CLK>,
2338 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2339 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2340 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2341 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2342 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2343 clock-names = "pipe",
2351 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2352 <0x100 &apps_smmu 0x1c11 0x1>,
2353 <0x200 &apps_smmu 0x1c12 0x1>,
2354 <0x300 &apps_smmu 0x1c13 0x1>,
2355 <0x400 &apps_smmu 0x1c14 0x1>,
2356 <0x500 &apps_smmu 0x1c15 0x1>,
2357 <0x600 &apps_smmu 0x1c16 0x1>,
2358 <0x700 &apps_smmu 0x1c17 0x1>,
2359 <0x800 &apps_smmu 0x1c18 0x1>,
2360 <0x900 &apps_smmu 0x1c19 0x1>,
2361 <0xa00 &apps_smmu 0x1c1a 0x1>,
2362 <0xb00 &apps_smmu 0x1c1b 0x1>,
2363 <0xc00 &apps_smmu 0x1c1c 0x1>,
2364 <0xd00 &apps_smmu 0x1c1d 0x1>,
2365 <0xe00 &apps_smmu 0x1c1e 0x1>,
2366 <0xf00 &apps_smmu 0x1c1f 0x1>;
2368 resets = <&gcc GCC_PCIE_0_BCR>;
2369 reset-names = "pci";
2371 power-domains = <&gcc PCIE_0_GDSC>;
2373 phys = <&pcie0_lane>;
2374 phy-names = "pciephy";
2376 status = "disabled";
2379 pcie0_phy: phy@1c06000 {
2380 compatible = "qcom,sdm845-qmp-pcie-phy";
2381 reg = <0 0x01c06000 0 0x18c>;
2382 #address-cells = <2>;
2385 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2386 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2387 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2388 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2389 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2391 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2392 reset-names = "phy";
2394 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2395 assigned-clock-rates = <100000000>;
2397 status = "disabled";
2399 pcie0_lane: phy@1c06200 {
2400 reg = <0 0x01c06200 0 0x128>,
2401 <0 0x01c06400 0 0x1fc>,
2402 <0 0x01c06800 0 0x218>,
2403 <0 0x01c06600 0 0x70>;
2404 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
2405 clock-names = "pipe0";
2409 clock-output-names = "pcie_0_pipe_clk";
2413 pcie1: pci@1c08000 {
2414 compatible = "qcom,pcie-sdm845";
2415 reg = <0 0x01c08000 0 0x2000>,
2416 <0 0x40000000 0 0xf1d>,
2417 <0 0x40000f20 0 0xa8>,
2418 <0 0x40100000 0 0x100000>,
2419 <0 0x01c0c000 0 0x1000>;
2420 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2421 device_type = "pci";
2422 linux,pci-domain = <1>;
2423 bus-range = <0x00 0xff>;
2426 #address-cells = <3>;
2429 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2430 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2432 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2433 interrupt-names = "msi";
2434 #interrupt-cells = <1>;
2435 interrupt-map-mask = <0 0 0 0x7>;
2436 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2437 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2438 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2439 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2441 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2442 <&gcc GCC_PCIE_1_AUX_CLK>,
2443 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2444 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2445 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2446 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2447 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2448 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2449 clock-names = "pipe",
2458 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2459 assigned-clock-rates = <19200000>;
2461 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2462 <0x100 &apps_smmu 0x1c01 0x1>,
2463 <0x200 &apps_smmu 0x1c02 0x1>,
2464 <0x300 &apps_smmu 0x1c03 0x1>,
2465 <0x400 &apps_smmu 0x1c04 0x1>,
2466 <0x500 &apps_smmu 0x1c05 0x1>,
2467 <0x600 &apps_smmu 0x1c06 0x1>,
2468 <0x700 &apps_smmu 0x1c07 0x1>,
2469 <0x800 &apps_smmu 0x1c08 0x1>,
2470 <0x900 &apps_smmu 0x1c09 0x1>,
2471 <0xa00 &apps_smmu 0x1c0a 0x1>,
2472 <0xb00 &apps_smmu 0x1c0b 0x1>,
2473 <0xc00 &apps_smmu 0x1c0c 0x1>,
2474 <0xd00 &apps_smmu 0x1c0d 0x1>,
2475 <0xe00 &apps_smmu 0x1c0e 0x1>,
2476 <0xf00 &apps_smmu 0x1c0f 0x1>;
2478 resets = <&gcc GCC_PCIE_1_BCR>;
2479 reset-names = "pci";
2481 power-domains = <&gcc PCIE_1_GDSC>;
2483 phys = <&pcie1_lane>;
2484 phy-names = "pciephy";
2486 status = "disabled";
2489 pcie1_phy: phy@1c0a000 {
2490 compatible = "qcom,sdm845-qhp-pcie-phy";
2491 reg = <0 0x01c0a000 0 0x800>;
2492 #address-cells = <2>;
2495 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2496 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2497 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2498 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2499 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2501 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2502 reset-names = "phy";
2504 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2505 assigned-clock-rates = <100000000>;
2507 status = "disabled";
2509 pcie1_lane: phy@1c06200 {
2510 reg = <0 0x01c0a800 0 0x800>,
2511 <0 0x01c0a800 0 0x800>,
2512 <0 0x01c0b800 0 0x400>;
2513 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2514 clock-names = "pipe0";
2518 clock-output-names = "pcie_1_pipe_clk";
2522 mem_noc: interconnect@1380000 {
2523 compatible = "qcom,sdm845-mem-noc";
2524 reg = <0 0x01380000 0 0x27200>;
2525 #interconnect-cells = <2>;
2526 qcom,bcm-voters = <&apps_bcm_voter>;
2529 dc_noc: interconnect@14e0000 {
2530 compatible = "qcom,sdm845-dc-noc";
2531 reg = <0 0x014e0000 0 0x400>;
2532 #interconnect-cells = <2>;
2533 qcom,bcm-voters = <&apps_bcm_voter>;
2536 config_noc: interconnect@1500000 {
2537 compatible = "qcom,sdm845-config-noc";
2538 reg = <0 0x01500000 0 0x5080>;
2539 #interconnect-cells = <2>;
2540 qcom,bcm-voters = <&apps_bcm_voter>;
2543 system_noc: interconnect@1620000 {
2544 compatible = "qcom,sdm845-system-noc";
2545 reg = <0 0x01620000 0 0x18080>;
2546 #interconnect-cells = <2>;
2547 qcom,bcm-voters = <&apps_bcm_voter>;
2550 aggre1_noc: interconnect@16e0000 {
2551 compatible = "qcom,sdm845-aggre1-noc";
2552 reg = <0 0x016e0000 0 0x15080>;
2553 #interconnect-cells = <2>;
2554 qcom,bcm-voters = <&apps_bcm_voter>;
2557 aggre2_noc: interconnect@1700000 {
2558 compatible = "qcom,sdm845-aggre2-noc";
2559 reg = <0 0x01700000 0 0x1f300>;
2560 #interconnect-cells = <2>;
2561 qcom,bcm-voters = <&apps_bcm_voter>;
2564 mmss_noc: interconnect@1740000 {
2565 compatible = "qcom,sdm845-mmss-noc";
2566 reg = <0 0x01740000 0 0x1c100>;
2567 #interconnect-cells = <2>;
2568 qcom,bcm-voters = <&apps_bcm_voter>;
2571 ufs_mem_hc: ufshc@1d84000 {
2572 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2574 reg = <0 0x01d84000 0 0x2500>,
2575 <0 0x01d90000 0 0x8000>;
2576 reg-names = "std", "ice";
2577 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2578 phys = <&ufs_mem_phy_lanes>;
2579 phy-names = "ufsphy";
2580 lanes-per-direction = <2>;
2581 power-domains = <&gcc UFS_PHY_GDSC>;
2583 resets = <&gcc GCC_UFS_PHY_BCR>;
2584 reset-names = "rst";
2586 iommus = <&apps_smmu 0x100 0xf>;
2594 "tx_lane0_sync_clk",
2595 "rx_lane0_sync_clk",
2596 "rx_lane1_sync_clk",
2599 <&gcc GCC_UFS_PHY_AXI_CLK>,
2600 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2601 <&gcc GCC_UFS_PHY_AHB_CLK>,
2602 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2603 <&rpmhcc RPMH_CXO_CLK>,
2604 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2605 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2606 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2607 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2609 <50000000 200000000>,
2612 <37500000 150000000>,
2617 <75000000 300000000>;
2619 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
2620 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2621 interconnect-names = "ufs-ddr", "cpu-ufs";
2623 status = "disabled";
2626 ufs_mem_phy: phy@1d87000 {
2627 compatible = "qcom,sdm845-qmp-ufs-phy";
2628 reg = <0 0x01d87000 0 0x18c>;
2629 #address-cells = <2>;
2632 clock-names = "ref",
2634 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2635 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2637 resets = <&ufs_mem_hc 0>;
2638 reset-names = "ufsphy";
2639 status = "disabled";
2641 ufs_mem_phy_lanes: phy@1d87400 {
2642 reg = <0 0x01d87400 0 0x108>,
2643 <0 0x01d87600 0 0x1e0>,
2644 <0 0x01d87c00 0 0x1dc>,
2645 <0 0x01d87800 0 0x108>,
2646 <0 0x01d87a00 0 0x1e0>;
2651 cryptobam: dma-controller@1dc4000 {
2652 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2653 reg = <0 0x01dc4000 0 0x24000>;
2654 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2655 clocks = <&rpmhcc RPMH_CE_CLK>;
2656 clock-names = "bam_clk";
2659 qcom,controlled-remotely;
2660 iommus = <&apps_smmu 0x704 0x1>,
2661 <&apps_smmu 0x706 0x1>,
2662 <&apps_smmu 0x714 0x1>,
2663 <&apps_smmu 0x716 0x1>;
2666 crypto: crypto@1dfa000 {
2667 compatible = "qcom,crypto-v5.4";
2668 reg = <0 0x01dfa000 0 0x6000>;
2669 clocks = <&gcc GCC_CE1_AHB_CLK>,
2670 <&gcc GCC_CE1_AXI_CLK>,
2671 <&rpmhcc RPMH_CE_CLK>;
2672 clock-names = "iface", "bus", "core";
2673 dmas = <&cryptobam 6>, <&cryptobam 7>;
2674 dma-names = "rx", "tx";
2675 iommus = <&apps_smmu 0x704 0x1>,
2676 <&apps_smmu 0x706 0x1>,
2677 <&apps_smmu 0x714 0x1>,
2678 <&apps_smmu 0x716 0x1>;
2682 compatible = "qcom,sdm845-ipa";
2684 iommus = <&apps_smmu 0x720 0x0>,
2685 <&apps_smmu 0x722 0x0>;
2686 reg = <0 0x01e40000 0 0x7000>,
2687 <0 0x01e47000 0 0x2000>,
2688 <0 0x01e04000 0 0x2c000>;
2689 reg-names = "ipa-reg",
2693 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2694 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2695 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2696 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2697 interrupt-names = "ipa",
2702 clocks = <&rpmhcc RPMH_IPA_CLK>;
2703 clock-names = "core";
2705 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2706 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2707 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2708 interconnect-names = "memory",
2712 qcom,smem-states = <&ipa_smp2p_out 0>,
2714 qcom,smem-state-names = "ipa-clock-enabled-valid",
2715 "ipa-clock-enabled";
2717 status = "disabled";
2720 tcsr_mutex: hwlock@1f40000 {
2721 compatible = "qcom,tcsr-mutex";
2722 reg = <0 0x01f40000 0 0x20000>;
2723 #hwlock-cells = <1>;
2726 tcsr_regs_1: syscon@1f60000 {
2727 compatible = "qcom,sdm845-tcsr", "syscon";
2728 reg = <0 0x01f60000 0 0x20000>;
2731 tlmm: pinctrl@3400000 {
2732 compatible = "qcom,sdm845-pinctrl";
2733 reg = <0 0x03400000 0 0xc00000>;
2734 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2737 interrupt-controller;
2738 #interrupt-cells = <2>;
2739 gpio-ranges = <&tlmm 0 0 151>;
2740 wakeup-parent = <&pdc_intc>;
2742 cci0_default: cci0-default-state {
2744 pins = "gpio17", "gpio18";
2745 function = "cci_i2c";
2748 drive-strength = <2>; /* 2 mA */
2751 cci0_sleep: cci0-sleep-state {
2753 pins = "gpio17", "gpio18";
2754 function = "cci_i2c";
2756 drive-strength = <2>; /* 2 mA */
2760 cci1_default: cci1-default-state {
2762 pins = "gpio19", "gpio20";
2763 function = "cci_i2c";
2766 drive-strength = <2>; /* 2 mA */
2769 cci1_sleep: cci1-sleep-state {
2771 pins = "gpio19", "gpio20";
2772 function = "cci_i2c";
2774 drive-strength = <2>; /* 2 mA */
2778 qspi_clk: qspi-clk-state {
2780 function = "qspi_clk";
2783 qspi_cs0: qspi-cs0-state {
2785 function = "qspi_cs";
2788 qspi_cs1: qspi-cs1-state {
2790 function = "qspi_cs";
2793 qspi_data0: qspi-data0-state {
2795 function = "qspi_data";
2798 qspi_data1: qspi-data1-state {
2800 function = "qspi_data";
2803 qspi_data23: qspi-data23-state {
2804 pins = "gpio93", "gpio94";
2805 function = "qspi_data";
2808 qup_i2c0_default: qup-i2c0-default-state {
2809 pins = "gpio0", "gpio1";
2813 qup_i2c1_default: qup-i2c1-default-state {
2814 pins = "gpio17", "gpio18";
2818 qup_i2c2_default: qup-i2c2-default-state {
2819 pins = "gpio27", "gpio28";
2823 qup_i2c3_default: qup-i2c3-default-state {
2824 pins = "gpio41", "gpio42";
2828 qup_i2c4_default: qup-i2c4-default-state {
2829 pins = "gpio89", "gpio90";
2833 qup_i2c5_default: qup-i2c5-default-state {
2834 pins = "gpio85", "gpio86";
2838 qup_i2c6_default: qup-i2c6-default-state {
2839 pins = "gpio45", "gpio46";
2843 qup_i2c7_default: qup-i2c7-default-state {
2844 pins = "gpio93", "gpio94";
2848 qup_i2c8_default: qup-i2c8-default-state {
2849 pins = "gpio65", "gpio66";
2853 qup_i2c9_default: qup-i2c9-default-state {
2854 pins = "gpio6", "gpio7";
2858 qup_i2c10_default: qup-i2c10-default-state {
2859 pins = "gpio55", "gpio56";
2863 qup_i2c11_default: qup-i2c11-default-state {
2864 pins = "gpio31", "gpio32";
2868 qup_i2c12_default: qup-i2c12-default-state {
2869 pins = "gpio49", "gpio50";
2873 qup_i2c13_default: qup-i2c13-default-state {
2874 pins = "gpio105", "gpio106";
2878 qup_i2c14_default: qup-i2c14-default-state {
2879 pins = "gpio33", "gpio34";
2883 qup_i2c15_default: qup-i2c15-default-state {
2884 pins = "gpio81", "gpio82";
2888 qup_spi0_default: qup-spi0-default-state {
2889 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2893 qup_spi1_default: qup-spi1-default-state {
2894 pins = "gpio17", "gpio18", "gpio19", "gpio20";
2898 qup_spi2_default: qup-spi2-default-state {
2899 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2903 qup_spi3_default: qup-spi3-default-state {
2904 pins = "gpio41", "gpio42", "gpio43", "gpio44";
2908 qup_spi4_default: qup-spi4-default-state {
2909 pins = "gpio89", "gpio90", "gpio91", "gpio92";
2913 qup_spi5_default: qup-spi5-default-state {
2914 pins = "gpio85", "gpio86", "gpio87", "gpio88";
2918 qup_spi6_default: qup-spi6-default-state {
2919 pins = "gpio45", "gpio46", "gpio47", "gpio48";
2923 qup_spi7_default: qup-spi7-default-state {
2924 pins = "gpio93", "gpio94", "gpio95", "gpio96";
2928 qup_spi8_default: qup-spi8-default-state {
2929 pins = "gpio65", "gpio66", "gpio67", "gpio68";
2933 qup_spi9_default: qup-spi9-default-state {
2934 pins = "gpio6", "gpio7", "gpio4", "gpio5";
2938 qup_spi10_default: qup-spi10-default-state {
2939 pins = "gpio55", "gpio56", "gpio53", "gpio54";
2943 qup_spi11_default: qup-spi11-default-state {
2944 pins = "gpio31", "gpio32", "gpio33", "gpio34";
2948 qup_spi12_default: qup-spi12-default-state {
2949 pins = "gpio49", "gpio50", "gpio51", "gpio52";
2953 qup_spi13_default: qup-spi13-default-state {
2954 pins = "gpio105", "gpio106", "gpio107", "gpio108";
2958 qup_spi14_default: qup-spi14-default-state {
2959 pins = "gpio33", "gpio34", "gpio31", "gpio32";
2963 qup_spi15_default: qup-spi15-default-state {
2964 pins = "gpio81", "gpio82", "gpio83", "gpio84";
2968 qup_uart0_default: qup-uart0-default-state {
2969 qup_uart0_tx: tx-pins {
2974 qup_uart0_rx: rx-pins {
2980 qup_uart1_default: qup-uart1-default-state {
2981 qup_uart1_tx: tx-pins {
2986 qup_uart1_rx: rx-pins {
2992 qup_uart2_default: qup-uart2-default-state {
2993 qup_uart2_tx: tx-pins {
2998 qup_uart2_rx: rx-pins {
3004 qup_uart3_default: qup-uart3-default-state {
3005 qup_uart3_tx: tx-pins {
3010 qup_uart3_rx: rx-pins {
3016 qup_uart3_4pin: qup-uart3-4pin-state {
3017 qup_uart3_4pin_cts: cts-pins {
3022 qup_uart3_4pin_rts_tx: rts-tx-pins {
3023 pins = "gpio42", "gpio43";
3027 qup_uart3_4pin_rx: rx-pins {
3033 qup_uart4_default: qup-uart4-default-state {
3034 qup_uart4_tx: tx-pins {
3039 qup_uart4_rx: rx-pins {
3045 qup_uart5_default: qup-uart5-default-state {
3046 qup_uart5_tx: tx-pins {
3051 qup_uart5_rx: rx-pins {
3057 qup_uart6_default: qup-uart6-default-state {
3058 qup_uart6_tx: tx-pins {
3063 qup_uart6_rx: rx-pins {
3069 qup_uart6_4pin: qup-uart6-4pin-state {
3070 qup_uart6_4pin_cts: cts-pins {
3076 qup_uart6_4pin_rts_tx: rts-tx-pins {
3077 pins = "gpio46", "gpio47";
3079 drive-strength = <2>;
3083 qup_uart6_4pin_rx: rx-pins {
3090 qup_uart7_default: qup-uart7-default-state {
3091 qup_uart7_tx: tx-pins {
3096 qup_uart7_rx: rx-pins {
3102 qup_uart8_default: qup-uart8-default-state {
3103 qup_uart8_tx: tx-pins {
3108 qup_uart8_rx: rx-pins {
3114 qup_uart9_default: qup-uart9-default-state {
3115 qup_uart9_tx: tx-pins {
3120 qup_uart9_rx: rx-pins {
3126 qup_uart10_default: qup-uart10-default-state {
3127 qup_uart10_tx: tx-pins {
3132 qup_uart10_rx: rx-pins {
3138 qup_uart11_default: qup-uart11-default-state {
3139 qup_uart11_tx: tx-pins {
3144 qup_uart11_rx: rx-pins {
3150 qup_uart12_default: qup-uart12-default-state {
3151 qup_uart12_tx: tx-pins {
3156 qup_uart12_rx: rx-pins {
3162 qup_uart13_default: qup-uart13-default-state {
3163 qup_uart13_tx: tx-pins {
3168 qup_uart13_rx: rx-pins {
3174 qup_uart14_default: qup-uart14-default-state {
3175 qup_uart14_tx: tx-pins {
3180 qup_uart14_rx: rx-pins {
3186 qup_uart15_default: qup-uart15-default-state {
3187 qup_uart15_tx: tx-pins {
3192 qup_uart15_rx: rx-pins {
3198 quat_mi2s_sleep: quat-mi2s-sleep-state {
3199 pins = "gpio58", "gpio59";
3201 drive-strength = <2>;
3205 quat_mi2s_active: quat-mi2s-active-state {
3206 pins = "gpio58", "gpio59";
3207 function = "qua_mi2s";
3208 drive-strength = <8>;
3213 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3216 drive-strength = <2>;
3220 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3222 function = "qua_mi2s";
3223 drive-strength = <8>;
3227 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3230 drive-strength = <2>;
3234 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3236 function = "qua_mi2s";
3237 drive-strength = <8>;
3241 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3244 drive-strength = <2>;
3248 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3250 function = "qua_mi2s";
3251 drive-strength = <8>;
3255 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3258 drive-strength = <2>;
3262 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3264 function = "qua_mi2s";
3265 drive-strength = <8>;
3270 mss_pil: remoteproc@4080000 {
3271 compatible = "qcom,sdm845-mss-pil";
3272 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3273 reg-names = "qdsp6", "rmb";
3275 interrupts-extended =
3276 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3277 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3278 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3279 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3280 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3281 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3282 interrupt-names = "wdog", "fatal", "ready",
3283 "handover", "stop-ack",
3286 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3287 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3288 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3289 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3290 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3291 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3292 <&gcc GCC_PRNG_AHB_CLK>,
3293 <&rpmhcc RPMH_CXO_CLK>;
3294 clock-names = "iface", "bus", "mem", "gpll0_mss",
3295 "snoc_axi", "mnoc_axi", "prng", "xo";
3297 qcom,qmp = <&aoss_qmp>;
3299 qcom,smem-states = <&modem_smp2p_out 0>;
3300 qcom,smem-state-names = "stop";
3302 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3303 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3304 reset-names = "mss_restart", "pdc_reset";
3306 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3308 power-domains = <&rpmhpd SDM845_CX>,
3309 <&rpmhpd SDM845_MX>,
3310 <&rpmhpd SDM845_MSS>;
3311 power-domain-names = "cx", "mx", "mss";
3313 status = "disabled";
3316 memory-region = <&mba_region>;
3320 memory-region = <&mpss_region>;
3324 memory-region = <&mdata_mem>;
3328 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3330 qcom,remote-pid = <1>;
3331 mboxes = <&apss_shared 12>;
3335 gpucc: clock-controller@5090000 {
3336 compatible = "qcom,sdm845-gpucc";
3337 reg = <0 0x05090000 0 0x9000>;
3340 #power-domain-cells = <1>;
3341 clocks = <&rpmhcc RPMH_CXO_CLK>,
3342 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3343 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3344 clock-names = "bi_tcxo",
3345 "gcc_gpu_gpll0_clk_src",
3346 "gcc_gpu_gpll0_div_clk_src";
3349 slpi_pas: remoteproc@5c00000 {
3350 compatible = "qcom,sdm845-slpi-pas";
3351 reg = <0 0x5c00000 0 0x4000>;
3353 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
3354 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3355 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3356 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3357 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3358 interrupt-names = "wdog", "fatal", "ready",
3359 "handover", "stop-ack";
3361 clocks = <&rpmhcc RPMH_CXO_CLK>;
3364 qcom,qmp = <&aoss_qmp>;
3366 power-domains = <&rpmhpd SDM845_CX>,
3367 <&rpmhpd SDM845_MX>;
3368 power-domain-names = "lcx", "lmx";
3370 memory-region = <&slpi_mem>;
3372 qcom,smem-states = <&slpi_smp2p_out 0>;
3373 qcom,smem-state-names = "stop";
3375 status = "disabled";
3378 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
3380 qcom,remote-pid = <3>;
3381 mboxes = <&apss_shared 24>;
3384 compatible = "qcom,fastrpc";
3385 qcom,glink-channels = "fastrpcglink-apps-dsp";
3387 qcom,non-secure-domain;
3388 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA
3389 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>;
3390 memory-region = <&fastrpc_mem>;
3391 #address-cells = <1>;
3395 compatible = "qcom,fastrpc-compute-cb";
3403 compatible = "arm,coresight-stm", "arm,primecell";
3404 reg = <0 0x06002000 0 0x1000>,
3405 <0 0x16280000 0 0x180000>;
3406 reg-names = "stm-base", "stm-stimulus-base";
3408 clocks = <&aoss_qmp>;
3409 clock-names = "apb_pclk";
3422 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3423 reg = <0 0x06041000 0 0x1000>;
3425 clocks = <&aoss_qmp>;
3426 clock-names = "apb_pclk";
3430 funnel0_out: endpoint {
3432 <&merge_funnel_in0>;
3438 #address-cells = <1>;
3443 funnel0_in7: endpoint {
3444 remote-endpoint = <&stm_out>;
3451 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3452 reg = <0 0x06043000 0 0x1000>;
3454 clocks = <&aoss_qmp>;
3455 clock-names = "apb_pclk";
3459 funnel2_out: endpoint {
3461 <&merge_funnel_in2>;
3467 #address-cells = <1>;
3472 funnel2_in5: endpoint {
3474 <&apss_merge_funnel_out>;
3481 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3482 reg = <0 0x06045000 0 0x1000>;
3484 clocks = <&aoss_qmp>;
3485 clock-names = "apb_pclk";
3489 merge_funnel_out: endpoint {
3490 remote-endpoint = <&etf_in>;
3496 #address-cells = <1>;
3501 merge_funnel_in0: endpoint {
3509 merge_funnel_in2: endpoint {
3517 replicator@6046000 {
3518 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3519 reg = <0 0x06046000 0 0x1000>;
3521 clocks = <&aoss_qmp>;
3522 clock-names = "apb_pclk";
3526 replicator_out: endpoint {
3527 remote-endpoint = <&etr_in>;
3534 replicator_in: endpoint {
3535 remote-endpoint = <&etf_out>;
3542 compatible = "arm,coresight-tmc", "arm,primecell";
3543 reg = <0 0x06047000 0 0x1000>;
3545 clocks = <&aoss_qmp>;
3546 clock-names = "apb_pclk";
3558 #address-cells = <1>;
3565 <&merge_funnel_out>;
3572 compatible = "arm,coresight-tmc", "arm,primecell";
3573 reg = <0 0x06048000 0 0x1000>;
3575 clocks = <&aoss_qmp>;
3576 clock-names = "apb_pclk";
3590 compatible = "arm,coresight-etm4x", "arm,primecell";
3591 reg = <0 0x07040000 0 0x1000>;
3595 clocks = <&aoss_qmp>;
3596 clock-names = "apb_pclk";
3597 arm,coresight-loses-context-with-cpu;
3601 etm0_out: endpoint {
3610 compatible = "arm,coresight-etm4x", "arm,primecell";
3611 reg = <0 0x07140000 0 0x1000>;
3615 clocks = <&aoss_qmp>;
3616 clock-names = "apb_pclk";
3617 arm,coresight-loses-context-with-cpu;
3621 etm1_out: endpoint {
3630 compatible = "arm,coresight-etm4x", "arm,primecell";
3631 reg = <0 0x07240000 0 0x1000>;
3635 clocks = <&aoss_qmp>;
3636 clock-names = "apb_pclk";
3637 arm,coresight-loses-context-with-cpu;
3641 etm2_out: endpoint {
3650 compatible = "arm,coresight-etm4x", "arm,primecell";
3651 reg = <0 0x07340000 0 0x1000>;
3655 clocks = <&aoss_qmp>;
3656 clock-names = "apb_pclk";
3657 arm,coresight-loses-context-with-cpu;
3661 etm3_out: endpoint {
3670 compatible = "arm,coresight-etm4x", "arm,primecell";
3671 reg = <0 0x07440000 0 0x1000>;
3675 clocks = <&aoss_qmp>;
3676 clock-names = "apb_pclk";
3677 arm,coresight-loses-context-with-cpu;
3681 etm4_out: endpoint {
3690 compatible = "arm,coresight-etm4x", "arm,primecell";
3691 reg = <0 0x07540000 0 0x1000>;
3695 clocks = <&aoss_qmp>;
3696 clock-names = "apb_pclk";
3697 arm,coresight-loses-context-with-cpu;
3701 etm5_out: endpoint {
3710 compatible = "arm,coresight-etm4x", "arm,primecell";
3711 reg = <0 0x07640000 0 0x1000>;
3715 clocks = <&aoss_qmp>;
3716 clock-names = "apb_pclk";
3717 arm,coresight-loses-context-with-cpu;
3721 etm6_out: endpoint {
3730 compatible = "arm,coresight-etm4x", "arm,primecell";
3731 reg = <0 0x07740000 0 0x1000>;
3735 clocks = <&aoss_qmp>;
3736 clock-names = "apb_pclk";
3737 arm,coresight-loses-context-with-cpu;
3741 etm7_out: endpoint {
3749 funnel@7800000 { /* APSS Funnel */
3750 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3751 reg = <0 0x07800000 0 0x1000>;
3753 clocks = <&aoss_qmp>;
3754 clock-names = "apb_pclk";
3758 apss_funnel_out: endpoint {
3760 <&apss_merge_funnel_in>;
3766 #address-cells = <1>;
3771 apss_funnel_in0: endpoint {
3779 apss_funnel_in1: endpoint {
3787 apss_funnel_in2: endpoint {
3795 apss_funnel_in3: endpoint {
3803 apss_funnel_in4: endpoint {
3811 apss_funnel_in5: endpoint {
3819 apss_funnel_in6: endpoint {
3827 apss_funnel_in7: endpoint {
3836 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3837 reg = <0 0x07810000 0 0x1000>;
3839 clocks = <&aoss_qmp>;
3840 clock-names = "apb_pclk";
3844 apss_merge_funnel_out: endpoint {
3853 apss_merge_funnel_in: endpoint {
3861 sdhc_2: mmc@8804000 {
3862 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3863 reg = <0 0x08804000 0 0x1000>;
3865 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3866 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3867 interrupt-names = "hc_irq", "pwr_irq";
3869 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3870 <&gcc GCC_SDCC2_APPS_CLK>,
3871 <&rpmhcc RPMH_CXO_CLK>;
3872 clock-names = "iface", "core", "xo";
3873 iommus = <&apps_smmu 0xa0 0xf>;
3874 power-domains = <&rpmhpd SDM845_CX>;
3875 operating-points-v2 = <&sdhc2_opp_table>;
3877 status = "disabled";
3879 sdhc2_opp_table: opp-table {
3880 compatible = "operating-points-v2";
3883 opp-hz = /bits/ 64 <9600000>;
3884 required-opps = <&rpmhpd_opp_min_svs>;
3888 opp-hz = /bits/ 64 <19200000>;
3889 required-opps = <&rpmhpd_opp_low_svs>;
3893 opp-hz = /bits/ 64 <100000000>;
3894 required-opps = <&rpmhpd_opp_svs>;
3898 opp-hz = /bits/ 64 <201500000>;
3899 required-opps = <&rpmhpd_opp_svs_l1>;
3905 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3906 reg = <0 0x088df000 0 0x600>;
3907 iommus = <&apps_smmu 0x160 0x0>;
3908 #address-cells = <1>;
3910 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3911 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3912 <&gcc GCC_QSPI_CORE_CLK>;
3913 clock-names = "iface", "core";
3914 power-domains = <&rpmhpd SDM845_CX>;
3915 operating-points-v2 = <&qspi_opp_table>;
3916 status = "disabled";
3919 slim: slim-ngd@171c0000 {
3920 compatible = "qcom,slim-ngd-v2.1.0";
3921 reg = <0 0x171c0000 0 0x2c000>;
3922 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3924 dmas = <&slimbam 3>, <&slimbam 4>;
3925 dma-names = "rx", "tx";
3927 iommus = <&apps_smmu 0x1806 0x0>;
3928 #address-cells = <1>;
3930 status = "disabled";
3933 lmh_cluster1: lmh@17d70800 {
3934 compatible = "qcom,sdm845-lmh";
3935 reg = <0 0x17d70800 0 0x400>;
3936 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3938 qcom,lmh-temp-arm-millicelsius = <65000>;
3939 qcom,lmh-temp-low-millicelsius = <94500>;
3940 qcom,lmh-temp-high-millicelsius = <95000>;
3941 interrupt-controller;
3942 #interrupt-cells = <1>;
3945 lmh_cluster0: lmh@17d78800 {
3946 compatible = "qcom,sdm845-lmh";
3947 reg = <0 0x17d78800 0 0x400>;
3948 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3950 qcom,lmh-temp-arm-millicelsius = <65000>;
3951 qcom,lmh-temp-low-millicelsius = <94500>;
3952 qcom,lmh-temp-high-millicelsius = <95000>;
3953 interrupt-controller;
3954 #interrupt-cells = <1>;
3957 usb_1_hsphy: phy@88e2000 {
3958 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3959 reg = <0 0x088e2000 0 0x400>;
3960 status = "disabled";
3963 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3964 <&rpmhcc RPMH_CXO_CLK>;
3965 clock-names = "cfg_ahb", "ref";
3967 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3969 nvmem-cells = <&qusb2p_hstx_trim>;
3972 usb_2_hsphy: phy@88e3000 {
3973 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3974 reg = <0 0x088e3000 0 0x400>;
3975 status = "disabled";
3978 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3979 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "cfg_ahb", "ref";
3982 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3984 nvmem-cells = <&qusb2s_hstx_trim>;
3987 usb_1_qmpphy: phy@88e9000 {
3988 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
3989 reg = <0 0x088e9000 0 0x18c>,
3990 <0 0x088e8000 0 0x38>,
3991 <0 0x088ea000 0 0x40>;
3992 status = "disabled";
3993 #address-cells = <2>;
3997 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3998 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3999 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4000 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4001 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4003 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
4004 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
4005 reset-names = "phy", "common";
4007 usb_1_ssphy: usb3-phy@88e9200 {
4008 reg = <0 0x088e9200 0 0x128>,
4009 <0 0x088e9400 0 0x200>,
4010 <0 0x088e9c00 0 0x218>,
4011 <0 0x088e9600 0 0x128>,
4012 <0 0x088e9800 0 0x200>,
4013 <0 0x088e9a00 0 0x100>;
4016 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4017 clock-names = "pipe0";
4018 clock-output-names = "usb3_phy_pipe_clk_src";
4021 dp_phy: dp-phy@88ea200 {
4022 reg = <0 0x088ea200 0 0x200>,
4023 <0 0x088ea400 0 0x200>,
4024 <0 0x088eaa00 0 0x200>,
4025 <0 0x088ea600 0 0x200>,
4026 <0 0x088ea800 0 0x200>;
4032 usb_2_qmpphy: phy@88eb000 {
4033 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4034 reg = <0 0x088eb000 0 0x18c>;
4035 status = "disabled";
4036 #address-cells = <2>;
4040 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4041 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4042 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4043 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4044 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4046 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4047 <&gcc GCC_USB3_PHY_SEC_BCR>;
4048 reset-names = "phy", "common";
4050 usb_2_ssphy: phy@88eb200 {
4051 reg = <0 0x088eb200 0 0x128>,
4052 <0 0x088eb400 0 0x1fc>,
4053 <0 0x088eb800 0 0x218>,
4054 <0 0x088eb600 0 0x70>;
4057 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
4058 clock-names = "pipe0";
4059 clock-output-names = "usb3_uni_phy_pipe_clk_src";
4063 usb_1: usb@a6f8800 {
4064 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4065 reg = <0 0x0a6f8800 0 0x400>;
4066 status = "disabled";
4067 #address-cells = <2>;
4072 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4073 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4074 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4075 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4076 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4077 clock-names = "cfg_noc",
4083 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4084 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4085 assigned-clock-rates = <19200000>, <150000000>;
4087 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4088 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4089 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
4090 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
4091 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4092 "dm_hs_phy_irq", "dp_hs_phy_irq";
4094 power-domains = <&gcc USB30_PRIM_GDSC>;
4096 resets = <&gcc GCC_USB30_PRIM_BCR>;
4098 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4099 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4100 interconnect-names = "usb-ddr", "apps-usb";
4102 usb_1_dwc3: usb@a600000 {
4103 compatible = "snps,dwc3";
4104 reg = <0 0x0a600000 0 0xcd00>;
4105 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4106 iommus = <&apps_smmu 0x740 0>;
4107 snps,dis_u2_susphy_quirk;
4108 snps,dis_enblslpm_quirk;
4109 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4110 phy-names = "usb2-phy", "usb3-phy";
4114 usb_2: usb@a8f8800 {
4115 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4116 reg = <0 0x0a8f8800 0 0x400>;
4117 status = "disabled";
4118 #address-cells = <2>;
4123 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4124 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4125 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4126 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4127 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4128 clock-names = "cfg_noc",
4134 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4135 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4136 assigned-clock-rates = <19200000>, <150000000>;
4138 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4139 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4140 <GIC_SPI 490 IRQ_TYPE_EDGE_BOTH>,
4141 <GIC_SPI 491 IRQ_TYPE_EDGE_BOTH>;
4142 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4143 "dm_hs_phy_irq", "dp_hs_phy_irq";
4145 power-domains = <&gcc USB30_SEC_GDSC>;
4147 resets = <&gcc GCC_USB30_SEC_BCR>;
4149 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4150 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4151 interconnect-names = "usb-ddr", "apps-usb";
4153 usb_2_dwc3: usb@a800000 {
4154 compatible = "snps,dwc3";
4155 reg = <0 0x0a800000 0 0xcd00>;
4156 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4157 iommus = <&apps_smmu 0x760 0>;
4158 snps,dis_u2_susphy_quirk;
4159 snps,dis_enblslpm_quirk;
4160 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4161 phy-names = "usb2-phy", "usb3-phy";
4165 venus: video-codec@aa00000 {
4166 compatible = "qcom,sdm845-venus-v2";
4167 reg = <0 0x0aa00000 0 0xff000>;
4168 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4169 power-domains = <&videocc VENUS_GDSC>,
4170 <&videocc VCODEC0_GDSC>,
4171 <&videocc VCODEC1_GDSC>,
4172 <&rpmhpd SDM845_CX>;
4173 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4174 operating-points-v2 = <&venus_opp_table>;
4175 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4176 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4177 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4178 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4179 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4180 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4181 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4182 clock-names = "core", "iface", "bus",
4183 "vcodec0_core", "vcodec0_bus",
4184 "vcodec1_core", "vcodec1_bus";
4185 iommus = <&apps_smmu 0x10a0 0x8>,
4186 <&apps_smmu 0x10b0 0x0>;
4187 memory-region = <&venus_mem>;
4188 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4189 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4190 interconnect-names = "video-mem", "cpu-cfg";
4192 status = "disabled";
4195 compatible = "venus-decoder";
4199 compatible = "venus-encoder";
4202 venus_opp_table: opp-table {
4203 compatible = "operating-points-v2";
4206 opp-hz = /bits/ 64 <100000000>;
4207 required-opps = <&rpmhpd_opp_min_svs>;
4211 opp-hz = /bits/ 64 <200000000>;
4212 required-opps = <&rpmhpd_opp_low_svs>;
4216 opp-hz = /bits/ 64 <320000000>;
4217 required-opps = <&rpmhpd_opp_svs>;
4221 opp-hz = /bits/ 64 <380000000>;
4222 required-opps = <&rpmhpd_opp_svs_l1>;
4226 opp-hz = /bits/ 64 <444000000>;
4227 required-opps = <&rpmhpd_opp_nom>;
4231 opp-hz = /bits/ 64 <533000097>;
4232 required-opps = <&rpmhpd_opp_turbo>;
4237 videocc: clock-controller@ab00000 {
4238 compatible = "qcom,sdm845-videocc";
4239 reg = <0 0x0ab00000 0 0x10000>;
4240 clocks = <&rpmhcc RPMH_CXO_CLK>;
4241 clock-names = "bi_tcxo";
4243 #power-domain-cells = <1>;
4247 camss: camss@acb3000 {
4248 compatible = "qcom,sdm845-camss";
4250 reg = <0 0x0acb3000 0 0x1000>,
4251 <0 0x0acba000 0 0x1000>,
4252 <0 0x0acc8000 0 0x1000>,
4253 <0 0x0ac65000 0 0x1000>,
4254 <0 0x0ac66000 0 0x1000>,
4255 <0 0x0ac67000 0 0x1000>,
4256 <0 0x0ac68000 0 0x1000>,
4257 <0 0x0acaf000 0 0x4000>,
4258 <0 0x0acb6000 0 0x4000>,
4259 <0 0x0acc4000 0 0x4000>;
4260 reg-names = "csid0",
4271 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4281 interrupt-names = "csid0",
4292 power-domains = <&clock_camcc IFE_0_GDSC>,
4293 <&clock_camcc IFE_1_GDSC>,
4294 <&clock_camcc TITAN_TOP_GDSC>;
4296 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4297 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4298 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4299 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4300 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4301 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4302 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4303 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4304 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4305 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4306 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4307 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4308 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4309 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4310 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4311 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4312 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4313 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4314 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4315 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4316 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4317 <&gcc GCC_CAMERA_AHB_CLK>,
4318 <&gcc GCC_CAMERA_AXI_CLK>,
4319 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4320 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4321 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4322 <&clock_camcc CAM_CC_IFE_0_CLK>,
4323 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4324 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4325 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4326 <&clock_camcc CAM_CC_IFE_1_CLK>,
4327 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4328 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4329 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4330 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4331 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4332 clock-names = "camnoc_axi",
4343 "csiphy0_timer_src",
4346 "csiphy1_timer_src",
4349 "csiphy2_timer_src",
4352 "csiphy3_timer_src",
4369 iommus = <&apps_smmu 0x0808 0x0>,
4370 <&apps_smmu 0x0810 0x8>,
4371 <&apps_smmu 0x0c08 0x0>,
4372 <&apps_smmu 0x0c10 0x8>;
4374 status = "disabled";
4377 #address-cells = <1>;
4399 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
4400 #address-cells = <1>;
4403 reg = <0 0x0ac4a000 0 0x4000>;
4404 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4405 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4407 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4408 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4409 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4410 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4411 <&clock_camcc CAM_CC_CCI_CLK>,
4412 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4413 clock-names = "camnoc_axi",
4420 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4421 <&clock_camcc CAM_CC_CCI_CLK>;
4422 assigned-clock-rates = <80000000>, <37500000>;
4424 pinctrl-names = "default", "sleep";
4425 pinctrl-0 = <&cci0_default &cci1_default>;
4426 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4428 status = "disabled";
4430 cci_i2c0: i2c-bus@0 {
4432 clock-frequency = <1000000>;
4433 #address-cells = <1>;
4437 cci_i2c1: i2c-bus@1 {
4439 clock-frequency = <1000000>;
4440 #address-cells = <1>;
4445 clock_camcc: clock-controller@ad00000 {
4446 compatible = "qcom,sdm845-camcc";
4447 reg = <0 0x0ad00000 0 0x10000>;
4450 #power-domain-cells = <1>;
4451 clocks = <&rpmhcc RPMH_CXO_CLK>;
4452 clock-names = "bi_tcxo";
4455 mdss: display-subsystem@ae00000 {
4456 compatible = "qcom,sdm845-mdss";
4457 reg = <0 0x0ae00000 0 0x1000>;
4460 power-domains = <&dispcc MDSS_GDSC>;
4462 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4463 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4464 clock-names = "iface", "core";
4466 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4467 interrupt-controller;
4468 #interrupt-cells = <1>;
4470 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4471 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4472 interconnect-names = "mdp0-mem", "mdp1-mem";
4474 iommus = <&apps_smmu 0x880 0x8>,
4475 <&apps_smmu 0xc80 0x8>;
4477 status = "disabled";
4479 #address-cells = <2>;
4483 mdss_mdp: display-controller@ae01000 {
4484 compatible = "qcom,sdm845-dpu";
4485 reg = <0 0x0ae01000 0 0x8f000>,
4486 <0 0x0aeb0000 0 0x2008>;
4487 reg-names = "mdp", "vbif";
4489 clocks = <&gcc GCC_DISP_AXI_CLK>,
4490 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4491 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4492 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4493 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4494 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4496 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4497 assigned-clock-rates = <19200000>;
4498 operating-points-v2 = <&mdp_opp_table>;
4499 power-domains = <&rpmhpd SDM845_CX>;
4501 interrupt-parent = <&mdss>;
4505 #address-cells = <1>;
4510 dpu_intf0_out: endpoint {
4511 remote-endpoint = <&dp_in>;
4517 dpu_intf1_out: endpoint {
4518 remote-endpoint = <&mdss_dsi0_in>;
4524 dpu_intf2_out: endpoint {
4525 remote-endpoint = <&mdss_dsi1_in>;
4530 mdp_opp_table: opp-table {
4531 compatible = "operating-points-v2";
4534 opp-hz = /bits/ 64 <19200000>;
4535 required-opps = <&rpmhpd_opp_min_svs>;
4539 opp-hz = /bits/ 64 <171428571>;
4540 required-opps = <&rpmhpd_opp_low_svs>;
4544 opp-hz = /bits/ 64 <344000000>;
4545 required-opps = <&rpmhpd_opp_svs_l1>;
4549 opp-hz = /bits/ 64 <430000000>;
4550 required-opps = <&rpmhpd_opp_nom>;
4555 mdss_dp: displayport-controller@ae90000 {
4556 status = "disabled";
4557 compatible = "qcom,sdm845-dp";
4559 reg = <0 0x0ae90000 0 0x200>,
4560 <0 0x0ae90200 0 0x200>,
4561 <0 0x0ae90400 0 0x600>,
4562 <0 0x0ae90a00 0 0x600>,
4563 <0 0x0ae91000 0 0x600>;
4565 interrupt-parent = <&mdss>;
4568 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4569 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4570 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4571 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4572 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4573 clock-names = "core_iface", "core_aux", "ctrl_link",
4574 "ctrl_link_iface", "stream_pixel";
4575 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4576 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4577 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4581 operating-points-v2 = <&dp_opp_table>;
4582 power-domains = <&rpmhpd SDM845_CX>;
4585 #address-cells = <1>;
4590 remote-endpoint = <&dpu_intf0_out>;
4596 dp_out: endpoint { };
4600 dp_opp_table: opp-table {
4601 compatible = "operating-points-v2";
4604 opp-hz = /bits/ 64 <162000000>;
4605 required-opps = <&rpmhpd_opp_low_svs>;
4609 opp-hz = /bits/ 64 <270000000>;
4610 required-opps = <&rpmhpd_opp_svs>;
4614 opp-hz = /bits/ 64 <540000000>;
4615 required-opps = <&rpmhpd_opp_svs_l1>;
4619 opp-hz = /bits/ 64 <810000000>;
4620 required-opps = <&rpmhpd_opp_nom>;
4625 mdss_dsi0: dsi@ae94000 {
4626 compatible = "qcom,sdm845-dsi-ctrl",
4627 "qcom,mdss-dsi-ctrl";
4628 reg = <0 0x0ae94000 0 0x400>;
4629 reg-names = "dsi_ctrl";
4631 interrupt-parent = <&mdss>;
4634 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4635 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4636 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4637 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4638 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4639 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4640 clock-names = "byte",
4646 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4647 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4649 operating-points-v2 = <&dsi_opp_table>;
4650 power-domains = <&rpmhpd SDM845_CX>;
4652 phys = <&mdss_dsi0_phy>;
4654 status = "disabled";
4656 #address-cells = <1>;
4660 #address-cells = <1>;
4665 mdss_dsi0_in: endpoint {
4666 remote-endpoint = <&dpu_intf1_out>;
4672 mdss_dsi0_out: endpoint {
4678 mdss_dsi0_phy: phy@ae94400 {
4679 compatible = "qcom,dsi-phy-10nm";
4680 reg = <0 0x0ae94400 0 0x200>,
4681 <0 0x0ae94600 0 0x280>,
4682 <0 0x0ae94a00 0 0x1e0>;
4683 reg-names = "dsi_phy",
4690 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4691 <&rpmhcc RPMH_CXO_CLK>;
4692 clock-names = "iface", "ref";
4694 status = "disabled";
4697 mdss_dsi1: dsi@ae96000 {
4698 compatible = "qcom,sdm845-dsi-ctrl",
4699 "qcom,mdss-dsi-ctrl";
4700 reg = <0 0x0ae96000 0 0x400>;
4701 reg-names = "dsi_ctrl";
4703 interrupt-parent = <&mdss>;
4706 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4707 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4708 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4709 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4710 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4711 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4712 clock-names = "byte",
4718 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4719 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4721 operating-points-v2 = <&dsi_opp_table>;
4722 power-domains = <&rpmhpd SDM845_CX>;
4724 phys = <&mdss_dsi1_phy>;
4726 status = "disabled";
4728 #address-cells = <1>;
4732 #address-cells = <1>;
4737 mdss_dsi1_in: endpoint {
4738 remote-endpoint = <&dpu_intf2_out>;
4744 mdss_dsi1_out: endpoint {
4750 mdss_dsi1_phy: phy@ae96400 {
4751 compatible = "qcom,dsi-phy-10nm";
4752 reg = <0 0x0ae96400 0 0x200>,
4753 <0 0x0ae96600 0 0x280>,
4754 <0 0x0ae96a00 0 0x10e>;
4755 reg-names = "dsi_phy",
4762 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4763 <&rpmhcc RPMH_CXO_CLK>;
4764 clock-names = "iface", "ref";
4766 status = "disabled";
4771 compatible = "qcom,adreno-630.2", "qcom,adreno";
4773 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
4774 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4777 * Look ma, no clocks! The GPU clocks and power are
4778 * controlled entirely by the GMU
4781 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4783 iommus = <&adreno_smmu 0>;
4785 operating-points-v2 = <&gpu_opp_table>;
4789 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4790 interconnect-names = "gfx-mem";
4792 status = "disabled";
4794 gpu_opp_table: opp-table {
4795 compatible = "operating-points-v2";
4798 opp-hz = /bits/ 64 <710000000>;
4799 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4800 opp-peak-kBps = <7216000>;
4804 opp-hz = /bits/ 64 <675000000>;
4805 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4806 opp-peak-kBps = <7216000>;
4810 opp-hz = /bits/ 64 <596000000>;
4811 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4812 opp-peak-kBps = <6220000>;
4816 opp-hz = /bits/ 64 <520000000>;
4817 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4818 opp-peak-kBps = <6220000>;
4822 opp-hz = /bits/ 64 <414000000>;
4823 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4824 opp-peak-kBps = <4068000>;
4828 opp-hz = /bits/ 64 <342000000>;
4829 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4830 opp-peak-kBps = <2724000>;
4834 opp-hz = /bits/ 64 <257000000>;
4835 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4836 opp-peak-kBps = <1648000>;
4841 adreno_smmu: iommu@5040000 {
4842 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4843 reg = <0 0x05040000 0 0x10000>;
4845 #global-interrupts = <2>;
4846 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4847 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4848 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4849 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4850 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4851 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4852 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4853 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4854 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4855 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4856 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4857 <&gcc GCC_GPU_CFG_AHB_CLK>;
4858 clock-names = "bus", "iface";
4860 power-domains = <&gpucc GPU_CX_GDSC>;
4864 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4866 reg = <0 0x0506a000 0 0x30000>,
4867 <0 0x0b280000 0 0x10000>,
4868 <0 0x0b480000 0 0x10000>;
4869 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4871 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4872 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4873 interrupt-names = "hfi", "gmu";
4875 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4876 <&gpucc GPU_CC_CXO_CLK>,
4877 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4878 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4879 clock-names = "gmu", "cxo", "axi", "memnoc";
4881 power-domains = <&gpucc GPU_CX_GDSC>,
4882 <&gpucc GPU_GX_GDSC>;
4883 power-domain-names = "cx", "gx";
4885 iommus = <&adreno_smmu 5>;
4887 operating-points-v2 = <&gmu_opp_table>;
4889 status = "disabled";
4891 gmu_opp_table: opp-table {
4892 compatible = "operating-points-v2";
4895 opp-hz = /bits/ 64 <400000000>;
4896 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4900 opp-hz = /bits/ 64 <200000000>;
4901 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4906 dispcc: clock-controller@af00000 {
4907 compatible = "qcom,sdm845-dispcc";
4908 reg = <0 0x0af00000 0 0x10000>;
4909 clocks = <&rpmhcc RPMH_CXO_CLK>,
4910 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4911 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4918 clock-names = "bi_tcxo",
4919 "gcc_disp_gpll0_clk_src",
4920 "gcc_disp_gpll0_div_clk_src",
4921 "dsi0_phy_pll_out_byteclk",
4922 "dsi0_phy_pll_out_dsiclk",
4923 "dsi1_phy_pll_out_byteclk",
4924 "dsi1_phy_pll_out_dsiclk",
4925 "dp_link_clk_divsel_ten",
4926 "dp_vco_divided_clk_src_mux";
4929 #power-domain-cells = <1>;
4932 pdc_intc: interrupt-controller@b220000 {
4933 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4934 reg = <0 0x0b220000 0 0x30000>;
4935 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4936 #interrupt-cells = <2>;
4937 interrupt-parent = <&intc>;
4938 interrupt-controller;
4941 pdc_reset: reset-controller@b2e0000 {
4942 compatible = "qcom,sdm845-pdc-global";
4943 reg = <0 0x0b2e0000 0 0x20000>;
4947 tsens0: thermal-sensor@c263000 {
4948 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4949 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4950 <0 0x0c222000 0 0x1ff>; /* SROT */
4951 #qcom,sensors = <13>;
4952 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4953 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4954 interrupt-names = "uplow", "critical";
4955 #thermal-sensor-cells = <1>;
4958 tsens1: thermal-sensor@c265000 {
4959 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4960 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4961 <0 0x0c223000 0 0x1ff>; /* SROT */
4962 #qcom,sensors = <8>;
4963 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4964 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4965 interrupt-names = "uplow", "critical";
4966 #thermal-sensor-cells = <1>;
4969 aoss_reset: reset-controller@c2a0000 {
4970 compatible = "qcom,sdm845-aoss-cc";
4971 reg = <0 0x0c2a0000 0 0x31000>;
4975 aoss_qmp: power-management@c300000 {
4976 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
4977 reg = <0 0x0c300000 0 0x400>;
4978 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4979 mboxes = <&apss_shared 0>;
4984 #cooling-cells = <2>;
4988 #cooling-cells = <2>;
4993 compatible = "qcom,sdm845-rpmh-stats";
4994 reg = <0 0x0c3f0000 0 0x400>;
4997 spmi_bus: spmi@c440000 {
4998 compatible = "qcom,spmi-pmic-arb";
4999 reg = <0 0x0c440000 0 0x1100>,
5000 <0 0x0c600000 0 0x2000000>,
5001 <0 0x0e600000 0 0x100000>,
5002 <0 0x0e700000 0 0xa0000>,
5003 <0 0x0c40a000 0 0x26000>;
5004 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5005 interrupt-names = "periph_irq";
5006 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5009 #address-cells = <2>;
5011 interrupt-controller;
5012 #interrupt-cells = <4>;
5016 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5017 reg = <0 0x146bf000 0 0x1000>;
5019 #address-cells = <1>;
5022 ranges = <0 0 0x146bf000 0x1000>;
5025 compatible = "qcom,pil-reloc-info";
5030 apps_smmu: iommu@15000000 {
5031 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5032 reg = <0 0x15000000 0 0x80000>;
5034 #global-interrupts = <1>;
5035 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5036 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5037 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5038 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5039 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5040 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5041 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5042 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5043 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5045 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5046 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5047 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5048 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5049 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5050 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5051 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5052 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5053 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5054 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5056 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5057 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5058 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5059 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5060 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5061 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5062 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5063 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5064 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5065 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5066 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5067 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5068 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5069 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5070 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5071 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5072 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5073 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5074 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5075 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5076 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5077 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5078 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5079 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5080 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5081 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5082 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5083 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5084 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5085 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5086 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5087 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5088 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5089 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5090 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5091 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5092 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5093 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5094 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5095 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5096 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5097 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5102 lpasscc: clock-controller@17014000 {
5103 compatible = "qcom,sdm845-lpasscc";
5104 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5105 reg-names = "cc", "qdsp6ss";
5107 status = "disabled";
5110 gladiator_noc: interconnect@17900000 {
5111 compatible = "qcom,sdm845-gladiator-noc";
5112 reg = <0 0x17900000 0 0xd080>;
5113 #interconnect-cells = <2>;
5114 qcom,bcm-voters = <&apps_bcm_voter>;
5118 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5119 reg = <0 0x17980000 0 0x1000>;
5120 clocks = <&sleep_clk>;
5121 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5124 apss_shared: mailbox@17990000 {
5125 compatible = "qcom,sdm845-apss-shared";
5126 reg = <0 0x17990000 0 0x1000>;
5130 apps_rsc: rsc@179c0000 {
5132 compatible = "qcom,rpmh-rsc";
5133 reg = <0 0x179c0000 0 0x10000>,
5134 <0 0x179d0000 0 0x10000>,
5135 <0 0x179e0000 0 0x10000>;
5136 reg-names = "drv-0", "drv-1", "drv-2";
5137 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5140 qcom,tcs-offset = <0xd00>;
5142 qcom,tcs-config = <ACTIVE_TCS 2>,
5146 power-domains = <&CLUSTER_PD>;
5148 apps_bcm_voter: bcm-voter {
5149 compatible = "qcom,bcm-voter";
5152 rpmhcc: clock-controller {
5153 compatible = "qcom,sdm845-rpmh-clk";
5156 clocks = <&xo_board>;
5159 rpmhpd: power-controller {
5160 compatible = "qcom,sdm845-rpmhpd";
5161 #power-domain-cells = <1>;
5162 operating-points-v2 = <&rpmhpd_opp_table>;
5164 rpmhpd_opp_table: opp-table {
5165 compatible = "operating-points-v2";
5167 rpmhpd_opp_ret: opp1 {
5168 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5171 rpmhpd_opp_min_svs: opp2 {
5172 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5175 rpmhpd_opp_low_svs: opp3 {
5176 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5179 rpmhpd_opp_svs: opp4 {
5180 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5183 rpmhpd_opp_svs_l1: opp5 {
5184 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5187 rpmhpd_opp_nom: opp6 {
5188 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5191 rpmhpd_opp_nom_l1: opp7 {
5192 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5195 rpmhpd_opp_nom_l2: opp8 {
5196 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5199 rpmhpd_opp_turbo: opp9 {
5200 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5203 rpmhpd_opp_turbo_l1: opp10 {
5204 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5210 intc: interrupt-controller@17a00000 {
5211 compatible = "arm,gic-v3";
5212 #address-cells = <2>;
5215 #interrupt-cells = <3>;
5216 interrupt-controller;
5217 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5218 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5219 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5221 msi-controller@17a40000 {
5222 compatible = "arm,gic-v3-its";
5225 reg = <0 0x17a40000 0 0x20000>;
5226 status = "disabled";
5230 slimbam: dma-controller@17184000 {
5231 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5232 qcom,controlled-remotely;
5233 reg = <0 0x17184000 0 0x2a000>;
5234 num-channels = <31>;
5235 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5239 iommus = <&apps_smmu 0x1806 0x0>;
5243 #address-cells = <1>;
5245 ranges = <0 0 0 0x20000000>;
5246 compatible = "arm,armv7-timer-mem";
5247 reg = <0 0x17c90000 0 0x1000>;
5251 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5252 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5253 reg = <0x17ca0000 0x1000>,
5254 <0x17cb0000 0x1000>;
5259 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5260 reg = <0x17cc0000 0x1000>;
5261 status = "disabled";
5266 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5267 reg = <0x17cd0000 0x1000>;
5268 status = "disabled";
5273 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5274 reg = <0x17ce0000 0x1000>;
5275 status = "disabled";
5280 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5281 reg = <0x17cf0000 0x1000>;
5282 status = "disabled";
5287 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5288 reg = <0x17d00000 0x1000>;
5289 status = "disabled";
5294 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5295 reg = <0x17d10000 0x1000>;
5296 status = "disabled";
5300 osm_l3: interconnect@17d41000 {
5301 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5302 reg = <0 0x17d41000 0 0x1400>;
5304 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5305 clock-names = "xo", "alternate";
5307 #interconnect-cells = <1>;
5310 cpufreq_hw: cpufreq@17d43000 {
5311 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5312 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5313 reg-names = "freq-domain0", "freq-domain1";
5315 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5317 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5318 clock-names = "xo", "alternate";
5320 #freq-domain-cells = <1>;
5324 wifi: wifi@18800000 {
5325 compatible = "qcom,wcn3990-wifi";
5326 status = "disabled";
5327 reg = <0 0x18800000 0 0x800000>;
5328 reg-names = "membase";
5329 memory-region = <&wlan_msa_mem>;
5330 clock-names = "cxo_ref_clk_pin";
5331 clocks = <&rpmhcc RPMH_RF_CLK2>;
5333 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5334 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5335 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5336 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5337 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5338 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5339 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5340 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5341 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5342 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5343 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5344 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5345 iommus = <&apps_smmu 0x0040 0x1>;
5354 polling-delay-passive = <250>;
5355 polling-delay = <1000>;
5357 thermal-sensors = <&tsens0 1>;
5360 cpu0_alert0: trip-point0 {
5361 temperature = <90000>;
5362 hysteresis = <2000>;
5366 cpu0_alert1: trip-point1 {
5367 temperature = <95000>;
5368 hysteresis = <2000>;
5372 cpu0_crit: cpu-crit {
5373 temperature = <110000>;
5374 hysteresis = <1000>;
5381 polling-delay-passive = <250>;
5382 polling-delay = <1000>;
5384 thermal-sensors = <&tsens0 2>;
5387 cpu1_alert0: trip-point0 {
5388 temperature = <90000>;
5389 hysteresis = <2000>;
5393 cpu1_alert1: trip-point1 {
5394 temperature = <95000>;
5395 hysteresis = <2000>;
5399 cpu1_crit: cpu-crit {
5400 temperature = <110000>;
5401 hysteresis = <1000>;
5408 polling-delay-passive = <250>;
5409 polling-delay = <1000>;
5411 thermal-sensors = <&tsens0 3>;
5414 cpu2_alert0: trip-point0 {
5415 temperature = <90000>;
5416 hysteresis = <2000>;
5420 cpu2_alert1: trip-point1 {
5421 temperature = <95000>;
5422 hysteresis = <2000>;
5426 cpu2_crit: cpu-crit {
5427 temperature = <110000>;
5428 hysteresis = <1000>;
5435 polling-delay-passive = <250>;
5436 polling-delay = <1000>;
5438 thermal-sensors = <&tsens0 4>;
5441 cpu3_alert0: trip-point0 {
5442 temperature = <90000>;
5443 hysteresis = <2000>;
5447 cpu3_alert1: trip-point1 {
5448 temperature = <95000>;
5449 hysteresis = <2000>;
5453 cpu3_crit: cpu-crit {
5454 temperature = <110000>;
5455 hysteresis = <1000>;
5462 polling-delay-passive = <250>;
5463 polling-delay = <1000>;
5465 thermal-sensors = <&tsens0 7>;
5468 cpu4_alert0: trip-point0 {
5469 temperature = <90000>;
5470 hysteresis = <2000>;
5474 cpu4_alert1: trip-point1 {
5475 temperature = <95000>;
5476 hysteresis = <2000>;
5480 cpu4_crit: cpu-crit {
5481 temperature = <110000>;
5482 hysteresis = <1000>;
5489 polling-delay-passive = <250>;
5490 polling-delay = <1000>;
5492 thermal-sensors = <&tsens0 8>;
5495 cpu5_alert0: trip-point0 {
5496 temperature = <90000>;
5497 hysteresis = <2000>;
5501 cpu5_alert1: trip-point1 {
5502 temperature = <95000>;
5503 hysteresis = <2000>;
5507 cpu5_crit: cpu-crit {
5508 temperature = <110000>;
5509 hysteresis = <1000>;
5516 polling-delay-passive = <250>;
5517 polling-delay = <1000>;
5519 thermal-sensors = <&tsens0 9>;
5522 cpu6_alert0: trip-point0 {
5523 temperature = <90000>;
5524 hysteresis = <2000>;
5528 cpu6_alert1: trip-point1 {
5529 temperature = <95000>;
5530 hysteresis = <2000>;
5534 cpu6_crit: cpu-crit {
5535 temperature = <110000>;
5536 hysteresis = <1000>;
5543 polling-delay-passive = <250>;
5544 polling-delay = <1000>;
5546 thermal-sensors = <&tsens0 10>;
5549 cpu7_alert0: trip-point0 {
5550 temperature = <90000>;
5551 hysteresis = <2000>;
5555 cpu7_alert1: trip-point1 {
5556 temperature = <95000>;
5557 hysteresis = <2000>;
5561 cpu7_crit: cpu-crit {
5562 temperature = <110000>;
5563 hysteresis = <1000>;
5570 polling-delay-passive = <250>;
5571 polling-delay = <1000>;
5573 thermal-sensors = <&tsens0 0>;
5576 aoss0_alert0: trip-point0 {
5577 temperature = <90000>;
5578 hysteresis = <2000>;
5585 polling-delay-passive = <250>;
5586 polling-delay = <1000>;
5588 thermal-sensors = <&tsens0 5>;
5591 cluster0_alert0: trip-point0 {
5592 temperature = <90000>;
5593 hysteresis = <2000>;
5596 cluster0_crit: cluster0_crit {
5597 temperature = <110000>;
5598 hysteresis = <2000>;
5605 polling-delay-passive = <250>;
5606 polling-delay = <1000>;
5608 thermal-sensors = <&tsens0 6>;
5611 cluster1_alert0: trip-point0 {
5612 temperature = <90000>;
5613 hysteresis = <2000>;
5616 cluster1_crit: cluster1_crit {
5617 temperature = <110000>;
5618 hysteresis = <2000>;
5625 polling-delay-passive = <250>;
5626 polling-delay = <1000>;
5628 thermal-sensors = <&tsens0 11>;
5631 gpu1_alert0: trip-point0 {
5632 temperature = <90000>;
5633 hysteresis = <2000>;
5639 gpu-bottom-thermal {
5640 polling-delay-passive = <250>;
5641 polling-delay = <1000>;
5643 thermal-sensors = <&tsens0 12>;
5646 gpu2_alert0: trip-point0 {
5647 temperature = <90000>;
5648 hysteresis = <2000>;
5655 polling-delay-passive = <250>;
5656 polling-delay = <1000>;
5658 thermal-sensors = <&tsens1 0>;
5661 aoss1_alert0: trip-point0 {
5662 temperature = <90000>;
5663 hysteresis = <2000>;
5670 polling-delay-passive = <250>;
5671 polling-delay = <1000>;
5673 thermal-sensors = <&tsens1 1>;
5676 q6_modem_alert0: trip-point0 {
5677 temperature = <90000>;
5678 hysteresis = <2000>;
5685 polling-delay-passive = <250>;
5686 polling-delay = <1000>;
5688 thermal-sensors = <&tsens1 2>;
5691 mem_alert0: trip-point0 {
5692 temperature = <90000>;
5693 hysteresis = <2000>;
5700 polling-delay-passive = <250>;
5701 polling-delay = <1000>;
5703 thermal-sensors = <&tsens1 3>;
5706 wlan_alert0: trip-point0 {
5707 temperature = <90000>;
5708 hysteresis = <2000>;
5715 polling-delay-passive = <250>;
5716 polling-delay = <1000>;
5718 thermal-sensors = <&tsens1 4>;
5721 q6_hvx_alert0: trip-point0 {
5722 temperature = <90000>;
5723 hysteresis = <2000>;
5730 polling-delay-passive = <250>;
5731 polling-delay = <1000>;
5733 thermal-sensors = <&tsens1 5>;
5736 camera_alert0: trip-point0 {
5737 temperature = <90000>;
5738 hysteresis = <2000>;
5745 polling-delay-passive = <250>;
5746 polling-delay = <1000>;
5748 thermal-sensors = <&tsens1 6>;
5751 video_alert0: trip-point0 {
5752 temperature = <90000>;
5753 hysteresis = <2000>;
5760 polling-delay-passive = <250>;
5761 polling-delay = <1000>;
5763 thermal-sensors = <&tsens1 7>;
5766 modem_alert0: trip-point0 {
5767 temperature = <90000>;
5768 hysteresis = <2000>;
5776 compatible = "arm,armv8-timer";
5777 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
5778 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
5779 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
5780 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;