arch/arm64/boot/dts/qcom/sdm845.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SDM845 SoC device tree source
   4  *
   5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
   9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
  10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
  12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
  13 #include <dt-bindings/clock/qcom,rpmh.h>
  14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  17 #include <dt-bindings/interconnect/qcom,sdm845.h>
  18 #include <dt-bindings/interrupt-controller/arm-gic.h>
  19 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  20 #include <dt-bindings/power/qcom-rpmpd.h>
  21 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  22 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  23 #include <dt-bindings/soc/qcom,apr.h>
  24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  25 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  26 #include <dt-bindings/thermal/thermal.h>
  27
  28 / {
  29         interrupt-parent = <&intc>;
  30
  31         #address-cells = <2>;
  32         #size-cells = <2>;
  33
  34         aliases {
  35                 i2c0 = &i2c0;
  36                 i2c1 = &i2c1;
  37                 i2c2 = &i2c2;
  38                 i2c3 = &i2c3;
  39                 i2c4 = &i2c4;
  40                 i2c5 = &i2c5;
  41                 i2c6 = &i2c6;
  42                 i2c7 = &i2c7;
  43                 i2c8 = &i2c8;
  44                 i2c9 = &i2c9;
  45                 i2c10 = &i2c10;
  46                 i2c11 = &i2c11;
  47                 i2c12 = &i2c12;
  48                 i2c13 = &i2c13;
  49                 i2c14 = &i2c14;
  50                 i2c15 = &i2c15;
  51                 spi0 = &spi0;
  52                 spi1 = &spi1;
  53                 spi2 = &spi2;
  54                 spi3 = &spi3;
  55                 spi4 = &spi4;
  56                 spi5 = &spi5;
  57                 spi6 = &spi6;
  58                 spi7 = &spi7;
  59                 spi8 = &spi8;
  60                 spi9 = &spi9;
  61                 spi10 = &spi10;
  62                 spi11 = &spi11;
  63                 spi12 = &spi12;
  64                 spi13 = &spi13;
  65                 spi14 = &spi14;
  66                 spi15 = &spi15;
  67         };
  68
  69         chosen { };
  70
  71         memory@80000000 {
  72                 device_type = "memory";
  73                 /* We expect the bootloader to fill in the size */
  74                 reg = <0 0x80000000 0 0>;
  75         };
  76
  77         reserved-memory {
  78                 #address-cells = <2>;
  79                 #size-cells = <2>;
  80                 ranges;
  81
  82                 hyp_mem: memory@85700000 {
  83                         reg = <0 0x85700000 0 0x600000>;
  84                         no-map;
  85                 };
  86
  87                 xbl_mem: memory@85e00000 {
  88                         reg = <0 0x85e00000 0 0x100000>;
  89                         no-map;
  90                 };
  91
  92                 aop_mem: memory@85fc0000 {
  93                         reg = <0 0x85fc0000 0 0x20000>;
  94                         no-map;
  95                 };
  96
  97                 aop_cmd_db_mem: memory@85fe0000 {
  98                         compatible = "qcom,cmd-db";
  99                         reg = <0x0 0x85fe0000 0 0x20000>;
 100                         no-map;
 101                 };
 102
 103                 smem@86000000 {
 104                         compatible = "qcom,smem";
 105                         reg = <0x0 0x86000000 0 0x200000>;
 106                         no-map;
 107                         hwlocks = <&tcsr_mutex 3>;
 108                 };
 109
 110                 tz_mem: memory@86200000 {
 111                         reg = <0 0x86200000 0 0x2d00000>;
 112                         no-map;
 113                 };
 114
 115                 rmtfs_mem: memory@88f00000 {
 116                         compatible = "qcom,rmtfs-mem";
 117                         reg = <0 0x88f00000 0 0x200000>;
 118                         no-map;
 119
 120                         qcom,client-id = <1>;
 121                         qcom,vmid = <15>;
 122                 };
 123
 124                 qseecom_mem: memory@8ab00000 {
 125                         reg = <0 0x8ab00000 0 0x1400000>;
 126                         no-map;
 127                 };
 128
 129                 camera_mem: memory@8bf00000 {
 130                         reg = <0 0x8bf00000 0 0x500000>;
 131                         no-map;
 132                 };
 133
 134                 ipa_fw_mem: memory@8c400000 {
 135                         reg = <0 0x8c400000 0 0x10000>;
 136                         no-map;
 137                 };
 138
 139                 ipa_gsi_mem: memory@8c410000 {
 140                         reg = <0 0x8c410000 0 0x5000>;
 141                         no-map;
 142                 };
 143
 144                 gpu_mem: memory@8c415000 {
 145                         reg = <0 0x8c415000 0 0x2000>;
 146                         no-map;
 147                 };
 148
 149                 adsp_mem: memory@8c500000 {
 150                         reg = <0 0x8c500000 0 0x1a00000>;
 151                         no-map;
 152                 };
 153
 154                 wlan_msa_mem: memory@8df00000 {
 155                         reg = <0 0x8df00000 0 0x100000>;
 156                         no-map;
 157                 };
 158
 159                 mpss_region: memory@8e000000 {
 160                         reg = <0 0x8e000000 0 0x7800000>;
 161                         no-map;
 162                 };
 163
 164                 venus_mem: memory@95800000 {
 165                         reg = <0 0x95800000 0 0x500000>;
 166                         no-map;
 167                 };
 168
 169                 cdsp_mem: memory@95d00000 {
 170                         reg = <0 0x95d00000 0 0x800000>;
 171                         no-map;
 172                 };
 173
 174                 mba_region: memory@96500000 {
 175                         reg = <0 0x96500000 0 0x200000>;
 176                         no-map;
 177                 };
 178
 179                 slpi_mem: memory@96700000 {
 180                         reg = <0 0x96700000 0 0x1400000>;
 181                         no-map;
 182                 };
 183
 184                 spss_mem: memory@97b00000 {
 185                         reg = <0 0x97b00000 0 0x100000>;
 186                         no-map;
 187                 };
 188         };
 189
 190         cpus {
 191                 #address-cells = <2>;
 192                 #size-cells = <0>;
 193
 194                 CPU0: cpu@0 {
 195                         device_type = "cpu";
 196                         compatible = "qcom,kryo385";
 197                         reg = <0x0 0x0>;
 198                         enable-method = "psci";
 199                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 200                                            &LITTLE_CPU_SLEEP_1
 201                                            &CLUSTER_SLEEP_0>;
 202                         capacity-dmips-mhz = <607>;
 203                         dynamic-power-coefficient = <100>;
 204                         qcom,freq-domain = <&cpufreq_hw 0>;
 205                         operating-points-v2 = <&cpu0_opp_table>;
 206                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 207                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 208                         #cooling-cells = <2>;
 209                         next-level-cache = <&L2_0>;
 210                         L2_0: l2-cache {
 211                                 compatible = "cache";
 212                                 next-level-cache = <&L3_0>;
 213                                 L3_0: l3-cache {
 214                                       compatible = "cache";
 215                                 };
 216                         };
 217                 };
 218
 219                 CPU1: cpu@100 {
 220                         device_type = "cpu";
 221                         compatible = "qcom,kryo385";
 222                         reg = <0x0 0x100>;
 223                         enable-method = "psci";
 224                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 225                                            &LITTLE_CPU_SLEEP_1
 226                                            &CLUSTER_SLEEP_0>;
 227                         capacity-dmips-mhz = <607>;
 228                         dynamic-power-coefficient = <100>;
 229                         qcom,freq-domain = <&cpufreq_hw 0>;
 230                         operating-points-v2 = <&cpu0_opp_table>;
 231                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 232                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 233                         #cooling-cells = <2>;
 234                         next-level-cache = <&L2_100>;
 235                         L2_100: l2-cache {
 236                                 compatible = "cache";
 237                                 next-level-cache = <&L3_0>;
 238                         };
 239                 };
 240
 241                 CPU2: cpu@200 {
 242                         device_type = "cpu";
 243                         compatible = "qcom,kryo385";
 244                         reg = <0x0 0x200>;
 245                         enable-method = "psci";
 246                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 247                                            &LITTLE_CPU_SLEEP_1
 248                                            &CLUSTER_SLEEP_0>;
 249                         capacity-dmips-mhz = <607>;
 250                         dynamic-power-coefficient = <100>;
 251                         qcom,freq-domain = <&cpufreq_hw 0>;
 252                         operating-points-v2 = <&cpu0_opp_table>;
 253                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 254                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 255                         #cooling-cells = <2>;
 256                         next-level-cache = <&L2_200>;
 257                         L2_200: l2-cache {
 258                                 compatible = "cache";
 259                                 next-level-cache = <&L3_0>;
 260                         };
 261                 };
 262
 263                 CPU3: cpu@300 {
 264                         device_type = "cpu";
 265                         compatible = "qcom,kryo385";
 266                         reg = <0x0 0x300>;
 267                         enable-method = "psci";
 268                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 269                                            &LITTLE_CPU_SLEEP_1
 270                                            &CLUSTER_SLEEP_0>;
 271                         capacity-dmips-mhz = <607>;
 272                         dynamic-power-coefficient = <100>;
 273                         qcom,freq-domain = <&cpufreq_hw 0>;
 274                         operating-points-v2 = <&cpu0_opp_table>;
 275                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 276                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 277                         #cooling-cells = <2>;
 278                         next-level-cache = <&L2_300>;
 279                         L2_300: l2-cache {
 280                                 compatible = "cache";
 281                                 next-level-cache = <&L3_0>;
 282                         };
 283                 };
 284
 285                 CPU4: cpu@400 {
 286                         device_type = "cpu";
 287                         compatible = "qcom,kryo385";
 288                         reg = <0x0 0x400>;
 289                         enable-method = "psci";
 290                         capacity-dmips-mhz = <1024>;
 291                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 292                                            &BIG_CPU_SLEEP_1
 293                                            &CLUSTER_SLEEP_0>;
 294                         dynamic-power-coefficient = <396>;
 295                         qcom,freq-domain = <&cpufreq_hw 1>;
 296                         operating-points-v2 = <&cpu4_opp_table>;
 297                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 298                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 299                         #cooling-cells = <2>;
 300                         next-level-cache = <&L2_400>;
 301                         L2_400: l2-cache {
 302                                 compatible = "cache";
 303                                 next-level-cache = <&L3_0>;
 304                         };
 305                 };
 306
 307                 CPU5: cpu@500 {
 308                         device_type = "cpu";
 309                         compatible = "qcom,kryo385";
 310                         reg = <0x0 0x500>;
 311                         enable-method = "psci";
 312                         capacity-dmips-mhz = <1024>;
 313                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 314                                            &BIG_CPU_SLEEP_1
 315                                            &CLUSTER_SLEEP_0>;
 316                         dynamic-power-coefficient = <396>;
 317                         qcom,freq-domain = <&cpufreq_hw 1>;
 318                         operating-points-v2 = <&cpu4_opp_table>;
 319                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 320                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 321                         #cooling-cells = <2>;
 322                         next-level-cache = <&L2_500>;
 323                         L2_500: l2-cache {
 324                                 compatible = "cache";
 325                                 next-level-cache = <&L3_0>;
 326                         };
 327                 };
 328
 329                 CPU6: cpu@600 {
 330                         device_type = "cpu";
 331                         compatible = "qcom,kryo385";
 332                         reg = <0x0 0x600>;
 333                         enable-method = "psci";
 334                         capacity-dmips-mhz = <1024>;
 335                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 336                                            &BIG_CPU_SLEEP_1
 337                                            &CLUSTER_SLEEP_0>;
 338                         dynamic-power-coefficient = <396>;
 339                         qcom,freq-domain = <&cpufreq_hw 1>;
 340                         operating-points-v2 = <&cpu4_opp_table>;
 341                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 342                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 343                         #cooling-cells = <2>;
 344                         next-level-cache = <&L2_600>;
 345                         L2_600: l2-cache {
 346                                 compatible = "cache";
 347                                 next-level-cache = <&L3_0>;
 348                         };
 349                 };
 350
 351                 CPU7: cpu@700 {
 352                         device_type = "cpu";
 353                         compatible = "qcom,kryo385";
 354                         reg = <0x0 0x700>;
 355                         enable-method = "psci";
 356                         capacity-dmips-mhz = <1024>;
 357                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 358                                            &BIG_CPU_SLEEP_1
 359                                            &CLUSTER_SLEEP_0>;
 360                         dynamic-power-coefficient = <396>;
 361                         qcom,freq-domain = <&cpufreq_hw 1>;
 362                         operating-points-v2 = <&cpu4_opp_table>;
 363                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 364                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 365                         #cooling-cells = <2>;
 366                         next-level-cache = <&L2_700>;
 367                         L2_700: l2-cache {
 368                                 compatible = "cache";
 369                                 next-level-cache = <&L3_0>;
 370                         };
 371                 };
 372
 373                 cpu-map {
 374                         cluster0 {
 375                                 core0 {
 376                                         cpu = <&CPU0>;
 377                                 };
 378
 379                                 core1 {
 380                                         cpu = <&CPU1>;
 381                                 };
 382
 383                                 core2 {
 384                                         cpu = <&CPU2>;
 385                                 };
 386
 387                                 core3 {
 388                                         cpu = <&CPU3>;
 389                                 };
 390
 391                                 core4 {
 392                                         cpu = <&CPU4>;
 393                                 };
 394
 395                                 core5 {
 396                                         cpu = <&CPU5>;
 397                                 };
 398
 399                                 core6 {
 400                                         cpu = <&CPU6>;
 401                                 };
 402
 403                                 core7 {
 404                                         cpu = <&CPU7>;
 405                                 };
 406                         };
 407                 };
 408
 409                 idle-states {
 410                         entry-method = "psci";
 411
 412                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 413                                 compatible = "arm,idle-state";
 414                                 idle-state-name = "little-power-down";
 415                                 arm,psci-suspend-param = <0x40000003>;
 416                                 entry-latency-us = <350>;
 417                                 exit-latency-us = <461>;
 418                                 min-residency-us = <1890>;
 419                                 local-timer-stop;
 420                         };
 421
 422                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 423                                 compatible = "arm,idle-state";
 424                                 idle-state-name = "little-rail-power-down";
 425                                 arm,psci-suspend-param = <0x40000004>;
 426                                 entry-latency-us = <360>;
 427                                 exit-latency-us = <531>;
 428                                 min-residency-us = <3934>;
 429                                 local-timer-stop;
 430                         };
 431
 432                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 433                                 compatible = "arm,idle-state";
 434                                 idle-state-name = "big-power-down";
 435                                 arm,psci-suspend-param = <0x40000003>;
 436                                 entry-latency-us = <264>;
 437                                 exit-latency-us = <621>;
 438                                 min-residency-us = <952>;
 439                                 local-timer-stop;
 440                         };
 441
 442                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 443                                 compatible = "arm,idle-state";
 444                                 idle-state-name = "big-rail-power-down";
 445                                 arm,psci-suspend-param = <0x40000004>;
 446                                 entry-latency-us = <702>;
 447                                 exit-latency-us = <1061>;
 448                                 min-residency-us = <4488>;
 449                                 local-timer-stop;
 450                         };
 451
 452                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 453                                 compatible = "arm,idle-state";
 454                                 idle-state-name = "cluster-power-down";
 455                                 arm,psci-suspend-param = <0x400000F4>;
 456                                 entry-latency-us = <3263>;
 457                                 exit-latency-us = <6562>;
 458                                 min-residency-us = <9987>;
 459                                 local-timer-stop;
 460                         };
 461                 };
 462         };
 463
 464         cpu0_opp_table: cpu0_opp_table {
 465                 compatible = "operating-points-v2";
 466                 opp-shared;
 467
 468                 cpu0_opp1: opp-300000000 {
 469                         opp-hz = /bits/ 64 <300000000>;
 470                         opp-peak-kBps = <800000 4800000>;
 471                 };
 472
 473                 cpu0_opp2: opp-403200000 {
 474                         opp-hz = /bits/ 64 <403200000>;
 475                         opp-peak-kBps = <800000 4800000>;
 476                 };
 477
 478                 cpu0_opp3: opp-480000000 {
 479                         opp-hz = /bits/ 64 <480000000>;
 480                         opp-peak-kBps = <800000 6451200>;
 481                 };
 482
 483                 cpu0_opp4: opp-576000000 {
 484                         opp-hz = /bits/ 64 <576000000>;
 485                         opp-peak-kBps = <800000 6451200>;
 486                 };
 487
 488                 cpu0_opp5: opp-652800000 {
 489                         opp-hz = /bits/ 64 <652800000>;
 490                         opp-peak-kBps = <800000 7680000>;
 491                 };
 492
 493                 cpu0_opp6: opp-748800000 {
 494                         opp-hz = /bits/ 64 <748800000>;
 495                         opp-peak-kBps = <1804000 9216000>;
 496                 };
 497
 498                 cpu0_opp7: opp-825600000 {
 499                         opp-hz = /bits/ 64 <825600000>;
 500                         opp-peak-kBps = <1804000 9216000>;
 501                 };
 502
 503                 cpu0_opp8: opp-902400000 {
 504                         opp-hz = /bits/ 64 <902400000>;
 505                         opp-peak-kBps = <1804000 10444800>;
 506                 };
 507
 508                 cpu0_opp9: opp-979200000 {
 509                         opp-hz = /bits/ 64 <979200000>;
 510                         opp-peak-kBps = <1804000 11980800>;
 511                 };
 512
 513                 cpu0_opp10: opp-1056000000 {
 514                         opp-hz = /bits/ 64 <1056000000>;
 515                         opp-peak-kBps = <1804000 11980800>;
 516                 };
 517
 518                 cpu0_opp11: opp-1132800000 {
 519                         opp-hz = /bits/ 64 <1132800000>;
 520                         opp-peak-kBps = <2188000 13516800>;
 521                 };
 522
 523                 cpu0_opp12: opp-1228800000 {
 524                         opp-hz = /bits/ 64 <1228800000>;
 525                         opp-peak-kBps = <2188000 15052800>;
 526                 };
 527
 528                 cpu0_opp13: opp-1324800000 {
 529                         opp-hz = /bits/ 64 <1324800000>;
 530                         opp-peak-kBps = <2188000 16588800>;
 531                 };
 532
 533                 cpu0_opp14: opp-1420800000 {
 534                         opp-hz = /bits/ 64 <1420800000>;
 535                         opp-peak-kBps = <3072000 18124800>;
 536                 };
 537
 538                 cpu0_opp15: opp-1516800000 {
 539                         opp-hz = /bits/ 64 <1516800000>;
 540                         opp-peak-kBps = <3072000 19353600>;
 541                 };
 542
 543                 cpu0_opp16: opp-1612800000 {
 544                         opp-hz = /bits/ 64 <1612800000>;
 545                         opp-peak-kBps = <4068000 19353600>;
 546                 };
 547
 548                 cpu0_opp17: opp-1689600000 {
 549                         opp-hz = /bits/ 64 <1689600000>;
 550                         opp-peak-kBps = <4068000 20889600>;
 551                 };
 552
 553                 cpu0_opp18: opp-1766400000 {
 554                         opp-hz = /bits/ 64 <1766400000>;
 555                         opp-peak-kBps = <4068000 22425600>;
 556                 };
 557         };
 558
 559         cpu4_opp_table: cpu4_opp_table {
 560                 compatible = "operating-points-v2";
 561                 opp-shared;
 562
 563                 cpu4_opp1: opp-300000000 {
 564                         opp-hz = /bits/ 64 <300000000>;
 565                         opp-peak-kBps = <800000 4800000>;
 566                 };
 567
 568                 cpu4_opp2: opp-403200000 {
 569                         opp-hz = /bits/ 64 <403200000>;
 570                         opp-peak-kBps = <800000 4800000>;
 571                 };
 572
 573                 cpu4_opp3: opp-480000000 {
 574                         opp-hz = /bits/ 64 <480000000>;
 575                         opp-peak-kBps = <1804000 4800000>;
 576                 };
 577
 578                 cpu4_opp4: opp-576000000 {
 579                         opp-hz = /bits/ 64 <576000000>;
 580                         opp-peak-kBps = <1804000 4800000>;
 581                 };
 582
 583                 cpu4_opp5: opp-652800000 {
 584                         opp-hz = /bits/ 64 <652800000>;
 585                         opp-peak-kBps = <1804000 4800000>;
 586                 };
 587
 588                 cpu4_opp6: opp-748800000 {
 589                         opp-hz = /bits/ 64 <748800000>;
 590                         opp-peak-kBps = <1804000 4800000>;
 591                 };
 592
 593                 cpu4_opp7: opp-825600000 {
 594                         opp-hz = /bits/ 64 <825600000>;
 595                         opp-peak-kBps = <2188000 9216000>;
 596                 };
 597
 598                 cpu4_opp8: opp-902400000 {
 599                         opp-hz = /bits/ 64 <902400000>;
 600                         opp-peak-kBps = <2188000 9216000>;
 601                 };
 602
 603                 cpu4_opp9: opp-979200000 {
 604                         opp-hz = /bits/ 64 <979200000>;
 605                         opp-peak-kBps = <2188000 9216000>;
 606                 };
 607
 608                 cpu4_opp10: opp-1056000000 {
 609                         opp-hz = /bits/ 64 <1056000000>;
 610                         opp-peak-kBps = <3072000 9216000>;
 611                 };
 612
 613                 cpu4_opp11: opp-1132800000 {
 614                         opp-hz = /bits/ 64 <1132800000>;
 615                         opp-peak-kBps = <3072000 11980800>;
 616                 };
 617
 618                 cpu4_opp12: opp-1209600000 {
 619                         opp-hz = /bits/ 64 <1209600000>;
 620                         opp-peak-kBps = <4068000 11980800>;
 621                 };
 622
 623                 cpu4_opp13: opp-1286400000 {
 624                         opp-hz = /bits/ 64 <1286400000>;
 625                         opp-peak-kBps = <4068000 11980800>;
 626                 };
 627
 628                 cpu4_opp14: opp-1363200000 {
 629                         opp-hz = /bits/ 64 <1363200000>;
 630                         opp-peak-kBps = <4068000 15052800>;
 631                 };
 632
 633                 cpu4_opp15: opp-1459200000 {
 634                         opp-hz = /bits/ 64 <1459200000>;
 635                         opp-peak-kBps = <4068000 15052800>;
 636                 };
 637
 638                 cpu4_opp16: opp-1536000000 {
 639                         opp-hz = /bits/ 64 <1536000000>;
 640                         opp-peak-kBps = <5412000 15052800>;
 641                 };
 642
 643                 cpu4_opp17: opp-1612800000 {
 644                         opp-hz = /bits/ 64 <1612800000>;
 645                         opp-peak-kBps = <5412000 15052800>;
 646                 };
 647
 648                 cpu4_opp18: opp-1689600000 {
 649                         opp-hz = /bits/ 64 <1689600000>;
 650                         opp-peak-kBps = <5412000 19353600>;
 651                 };
 652
 653                 cpu4_opp19: opp-1766400000 {
 654                         opp-hz = /bits/ 64 <1766400000>;
 655                         opp-peak-kBps = <6220000 19353600>;
 656                 };
 657
 658                 cpu4_opp20: opp-1843200000 {
 659                         opp-hz = /bits/ 64 <1843200000>;
 660                         opp-peak-kBps = <6220000 19353600>;
 661                 };
 662
 663                 cpu4_opp21: opp-1920000000 {
 664                         opp-hz = /bits/ 64 <1920000000>;
 665                         opp-peak-kBps = <7216000 19353600>;
 666                 };
 667
 668                 cpu4_opp22: opp-1996800000 {
 669                         opp-hz = /bits/ 64 <1996800000>;
 670                         opp-peak-kBps = <7216000 20889600>;
 671                 };
 672
 673                 cpu4_opp23: opp-2092800000 {
 674                         opp-hz = /bits/ 64 <2092800000>;
 675                         opp-peak-kBps = <7216000 20889600>;
 676                 };
 677
 678                 cpu4_opp24: opp-2169600000 {
 679                         opp-hz = /bits/ 64 <2169600000>;
 680                         opp-peak-kBps = <7216000 20889600>;
 681                 };
 682
 683                 cpu4_opp25: opp-2246400000 {
 684                         opp-hz = /bits/ 64 <2246400000>;
 685                         opp-peak-kBps = <7216000 20889600>;
 686                 };
 687
 688                 cpu4_opp26: opp-2323200000 {
 689                         opp-hz = /bits/ 64 <2323200000>;
 690                         opp-peak-kBps = <7216000 20889600>;
 691                 };
 692
 693                 cpu4_opp27: opp-2400000000 {
 694                         opp-hz = /bits/ 64 <2400000000>;
 695                         opp-peak-kBps = <7216000 22425600>;
 696                 };
 697
 698                 cpu4_opp28: opp-2476800000 {
 699                         opp-hz = /bits/ 64 <2476800000>;
 700                         opp-peak-kBps = <7216000 22425600>;
 701                 };
 702
 703                 cpu4_opp29: opp-2553600000 {
 704                         opp-hz = /bits/ 64 <2553600000>;
 705                         opp-peak-kBps = <7216000 22425600>;
 706                 };
 707
 708                 cpu4_opp30: opp-2649600000 {
 709                         opp-hz = /bits/ 64 <2649600000>;
 710                         opp-peak-kBps = <7216000 22425600>;
 711                 };
 712
 713                 cpu4_opp31: opp-2745600000 {
 714                         opp-hz = /bits/ 64 <2745600000>;
 715                         opp-peak-kBps = <7216000 25497600>;
 716                 };
 717
 718                 cpu4_opp32: opp-2803200000 {
 719                         opp-hz = /bits/ 64 <2803200000>;
 720                         opp-peak-kBps = <7216000 25497600>;
 721                 };
 722         };
 723
 724         pmu {
 725                 compatible = "arm,armv8-pmuv3";
 726                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 727         };
 728
 729         timer {
 730                 compatible = "arm,armv8-timer";
 731                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 732                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 733                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 734                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 735         };
 736
 737         clocks {
 738                 xo_board: xo-board {
 739                         compatible = "fixed-clock";
 740                         #clock-cells = <0>;
 741                         clock-frequency = <38400000>;
 742                         clock-output-names = "xo_board";
 743                 };
 744
 745                 sleep_clk: sleep-clk {
 746                         compatible = "fixed-clock";
 747                         #clock-cells = <0>;
 748                         clock-frequency = <32764>;
 749                 };
 750         };
 751
 752         firmware {
 753                 scm {
 754                         compatible = "qcom,scm-sdm845", "qcom,scm";
 755                 };
 756         };
 757
 758         adsp_pas: remoteproc-adsp {
 759                 compatible = "qcom,sdm845-adsp-pas";
 760
 761                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 762                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 763                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 764                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 765                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 766                 interrupt-names = "wdog", "fatal", "ready",
 767                                   "handover", "stop-ack";
 768
 769                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 770                 clock-names = "xo";
 771
 772                 memory-region = <&adsp_mem>;
 773
 774                 qcom,qmp = <&aoss_qmp>;
 775
 776                 qcom,smem-states = <&adsp_smp2p_out 0>;
 777                 qcom,smem-state-names = "stop";
 778
 779                 status = "disabled";
 780
 781                 glink-edge {
 782                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 783                         label = "lpass";
 784                         qcom,remote-pid = <2>;
 785                         mboxes = <&apss_shared 8>;
 786
 787                         apr {
 788                                 compatible = "qcom,apr-v2";
 789                                 qcom,glink-channels = "apr_audio_svc";
 790                                 qcom,apr-domain = <APR_DOMAIN_ADSP>;
 791                                 #address-cells = <1>;
 792                                 #size-cells = <0>;
 793                                 qcom,intents = <512 20>;
 794
 795                                 apr-service@3 {
 796                                         reg = <APR_SVC_ADSP_CORE>;
 797                                         compatible = "qcom,q6core";
 798                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 799                                 };
 800
 801                                 q6afe: apr-service@4 {
 802                                         compatible = "qcom,q6afe";
 803                                         reg = <APR_SVC_AFE>;
 804                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 805                                         q6afedai: dais {
 806                                                 compatible = "qcom,q6afe-dais";
 807                                                 #address-cells = <1>;
 808                                                 #size-cells = <0>;
 809                                                 #sound-dai-cells = <1>;
 810                                         };
 811                                 };
 812
 813                                 q6asm: apr-service@7 {
 814                                         compatible = "qcom,q6asm";
 815                                         reg = <APR_SVC_ASM>;
 816                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 817                                         q6asmdai: dais {
 818                                                 compatible = "qcom,q6asm-dais";
 819                                                 #address-cells = <1>;
 820                                                 #size-cells = <0>;
 821                                                 #sound-dai-cells = <1>;
 822                                                 iommus = <&apps_smmu 0x1821 0x0>;
 823                                         };
 824                                 };
 825
 826                                 q6adm: apr-service@8 {
 827                                         compatible = "qcom,q6adm";
 828                                         reg = <APR_SVC_ADM>;
 829                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 830                                         q6routing: routing {
 831                                                 compatible = "qcom,q6adm-routing";
 832                                                 #sound-dai-cells = <0>;
 833                                         };
 834                                 };
 835                         };
 836
 837                         fastrpc {
 838                                 compatible = "qcom,fastrpc";
 839                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 840                                 label = "adsp";
 841                                 #address-cells = <1>;
 842                                 #size-cells = <0>;
 843
 844                                 compute-cb@3 {
 845                                         compatible = "qcom,fastrpc-compute-cb";
 846                                         reg = <3>;
 847                                         iommus = <&apps_smmu 0x1823 0x0>;
 848                                 };
 849
 850                                 compute-cb@4 {
 851                                         compatible = "qcom,fastrpc-compute-cb";
 852                                         reg = <4>;
 853                                         iommus = <&apps_smmu 0x1824 0x0>;
 854                                 };
 855                         };
 856                 };
 857         };
 858
 859         cdsp_pas: remoteproc-cdsp {
 860                 compatible = "qcom,sdm845-cdsp-pas";
 861
 862                 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 863                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 864                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 865                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 866                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 867                 interrupt-names = "wdog", "fatal", "ready",
 868                                   "handover", "stop-ack";
 869
 870                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 871                 clock-names = "xo";
 872
 873                 memory-region = <&cdsp_mem>;
 874
 875                 qcom,qmp = <&aoss_qmp>;
 876
 877                 qcom,smem-states = <&cdsp_smp2p_out 0>;
 878                 qcom,smem-state-names = "stop";
 879
 880                 status = "disabled";
 881
 882                 glink-edge {
 883                         interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
 884                         label = "turing";
 885                         qcom,remote-pid = <5>;
 886                         mboxes = <&apss_shared 4>;
 887                         fastrpc {
 888                                 compatible = "qcom,fastrpc";
 889                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 890                                 label = "cdsp";
 891                                 #address-cells = <1>;
 892                                 #size-cells = <0>;
 893
 894                                 compute-cb@1 {
 895                                         compatible = "qcom,fastrpc-compute-cb";
 896                                         reg = <1>;
 897                                         iommus = <&apps_smmu 0x1401 0x30>;
 898                                 };
 899
 900                                 compute-cb@2 {
 901                                         compatible = "qcom,fastrpc-compute-cb";
 902                                         reg = <2>;
 903                                         iommus = <&apps_smmu 0x1402 0x30>;
 904                                 };
 905
 906                                 compute-cb@3 {
 907                                         compatible = "qcom,fastrpc-compute-cb";
 908                                         reg = <3>;
 909                                         iommus = <&apps_smmu 0x1403 0x30>;
 910                                 };
 911
 912                                 compute-cb@4 {
 913                                         compatible = "qcom,fastrpc-compute-cb";
 914                                         reg = <4>;
 915                                         iommus = <&apps_smmu 0x1404 0x30>;
 916                                 };
 917
 918                                 compute-cb@5 {
 919                                         compatible = "qcom,fastrpc-compute-cb";
 920                                         reg = <5>;
 921                                         iommus = <&apps_smmu 0x1405 0x30>;
 922                                 };
 923
 924                                 compute-cb@6 {
 925                                         compatible = "qcom,fastrpc-compute-cb";
 926                                         reg = <6>;
 927                                         iommus = <&apps_smmu 0x1406 0x30>;
 928                                 };
 929
 930                                 compute-cb@7 {
 931                                         compatible = "qcom,fastrpc-compute-cb";
 932                                         reg = <7>;
 933                                         iommus = <&apps_smmu 0x1407 0x30>;
 934                                 };
 935
 936                                 compute-cb@8 {
 937                                         compatible = "qcom,fastrpc-compute-cb";
 938                                         reg = <8>;
 939                                         iommus = <&apps_smmu 0x1408 0x30>;
 940                                 };
 941                         };
 942                 };
 943         };
 944
 945         tcsr_mutex: hwlock {
 946                 compatible = "qcom,tcsr-mutex";
 947                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 948                 #hwlock-cells = <1>;
 949         };
 950
 951         smp2p-cdsp {
 952                 compatible = "qcom,smp2p";
 953                 qcom,smem = <94>, <432>;
 954
 955                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 956
 957                 mboxes = <&apss_shared 6>;
 958
 959                 qcom,local-pid = <0>;
 960                 qcom,remote-pid = <5>;
 961
 962                 cdsp_smp2p_out: master-kernel {
 963                         qcom,entry-name = "master-kernel";
 964                         #qcom,smem-state-cells = <1>;
 965                 };
 966
 967                 cdsp_smp2p_in: slave-kernel {
 968                         qcom,entry-name = "slave-kernel";
 969
 970                         interrupt-controller;
 971                         #interrupt-cells = <2>;
 972                 };
 973         };
 974
 975         smp2p-lpass {
 976                 compatible = "qcom,smp2p";
 977                 qcom,smem = <443>, <429>;
 978
 979                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 980
 981                 mboxes = <&apss_shared 10>;
 982
 983                 qcom,local-pid = <0>;
 984                 qcom,remote-pid = <2>;
 985
 986                 adsp_smp2p_out: master-kernel {
 987                         qcom,entry-name = "master-kernel";
 988                         #qcom,smem-state-cells = <1>;
 989                 };
 990
 991                 adsp_smp2p_in: slave-kernel {
 992                         qcom,entry-name = "slave-kernel";
 993
 994                         interrupt-controller;
 995                         #interrupt-cells = <2>;
 996                 };
 997         };
 998
 999         smp2p-mpss {
1000                 compatible = "qcom,smp2p";
1001                 qcom,smem = <435>, <428>;
1002                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1003                 mboxes = <&apss_shared 14>;
1004                 qcom,local-pid = <0>;
1005                 qcom,remote-pid = <1>;
1006
1007                 modem_smp2p_out: master-kernel {
1008                         qcom,entry-name = "master-kernel";
1009                         #qcom,smem-state-cells = <1>;
1010                 };
1011
1012                 modem_smp2p_in: slave-kernel {
1013                         qcom,entry-name = "slave-kernel";
1014                         interrupt-controller;
1015                         #interrupt-cells = <2>;
1016                 };
1017
1018                 ipa_smp2p_out: ipa-ap-to-modem {
1019                         qcom,entry-name = "ipa";
1020                         #qcom,smem-state-cells = <1>;
1021                 };
1022
1023                 ipa_smp2p_in: ipa-modem-to-ap {
1024                         qcom,entry-name = "ipa";
1025                         interrupt-controller;
1026                         #interrupt-cells = <2>;
1027                 };
1028         };
1029
1030         smp2p-slpi {
1031                 compatible = "qcom,smp2p";
1032                 qcom,smem = <481>, <430>;
1033                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1034                 mboxes = <&apss_shared 26>;
1035                 qcom,local-pid = <0>;
1036                 qcom,remote-pid = <3>;
1037
1038                 slpi_smp2p_out: master-kernel {
1039                         qcom,entry-name = "master-kernel";
1040                         #qcom,smem-state-cells = <1>;
1041                 };
1042
1043                 slpi_smp2p_in: slave-kernel {
1044                         qcom,entry-name = "slave-kernel";
1045                         interrupt-controller;
1046                         #interrupt-cells = <2>;
1047                 };
1048         };
1049
1050         psci {
1051                 compatible = "arm,psci-1.0";
1052                 method = "smc";
1053         };
1054
1055         soc: soc@0 {
1056                 #address-cells = <2>;
1057                 #size-cells = <2>;
1058                 ranges = <0 0 0 0 0x10 0>;
1059                 dma-ranges = <0 0 0 0 0x10 0>;
1060                 compatible = "simple-bus";
1061
1062                 gcc: clock-controller@100000 {
1063                         compatible = "qcom,gcc-sdm845";
1064                         reg = <0 0x00100000 0 0x1f0000>;
1065                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1066                                  <&rpmhcc RPMH_CXO_CLK_A>,
1067                                  <&sleep_clk>,
1068                                  <&pcie0_lane>,
1069                                  <&pcie1_lane>;
1070                         clock-names = "bi_tcxo",
1071                                       "bi_tcxo_ao",
1072                                       "sleep_clk",
1073                                       "pcie_0_pipe_clk",
1074                                       "pcie_1_pipe_clk";
1075                         #clock-cells = <1>;
1076                         #reset-cells = <1>;
1077                         #power-domain-cells = <1>;
1078                 };
1079
1080                 qfprom@784000 {
1081                         compatible = "qcom,qfprom";
1082                         reg = <0 0x00784000 0 0x8ff>;
1083                         #address-cells = <1>;
1084                         #size-cells = <1>;
1085
1086                         qusb2p_hstx_trim: hstx-trim-primary@1eb {
1087                                 reg = <0x1eb 0x1>;
1088                                 bits = <1 4>;
1089                         };
1090
1091                         qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1092                                 reg = <0x1eb 0x2>;
1093                                 bits = <6 4>;
1094                         };
1095                 };
1096
1097                 rng: rng@793000 {
1098                         compatible = "qcom,prng-ee";
1099                         reg = <0 0x00793000 0 0x1000>;
1100                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
1101                         clock-names = "core";
1102                 };
1103
1104                 qup_opp_table: qup-opp-table {
1105                         compatible = "operating-points-v2";
1106
1107                         opp-50000000 {
1108                                 opp-hz = /bits/ 64 <50000000>;
1109                                 required-opps = <&rpmhpd_opp_min_svs>;
1110                         };
1111
1112                         opp-75000000 {
1113                                 opp-hz = /bits/ 64 <75000000>;
1114                                 required-opps = <&rpmhpd_opp_low_svs>;
1115                         };
1116
1117                         opp-100000000 {
1118                                 opp-hz = /bits/ 64 <100000000>;
1119                                 required-opps = <&rpmhpd_opp_svs>;
1120                         };
1121
1122                         opp-128000000 {
1123                                 opp-hz = /bits/ 64 <128000000>;
1124                                 required-opps = <&rpmhpd_opp_nom>;
1125                         };
1126                 };
1127
1128                 qupv3_id_0: geniqup@8c0000 {
1129                         compatible = "qcom,geni-se-qup";
1130                         reg = <0 0x008c0000 0 0x6000>;
1131                         clock-names = "m-ahb", "s-ahb";
1132                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1133                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1134                         iommus = <&apps_smmu 0x3 0x0>;
1135                         #address-cells = <2>;
1136                         #size-cells = <2>;
1137                         ranges;
1138                         interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1139                         interconnect-names = "qup-core";
1140                         status = "disabled";
1141
1142                         i2c0: i2c@880000 {
1143                                 compatible = "qcom,geni-i2c";
1144                                 reg = <0 0x00880000 0 0x4000>;
1145                                 clock-names = "se";
1146                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1147                                 pinctrl-names = "default";
1148                                 pinctrl-0 = <&qup_i2c0_default>;
1149                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1150                                 #address-cells = <1>;
1151                                 #size-cells = <0>;
1152                                 power-domains = <&rpmhpd SDM845_CX>;
1153                                 operating-points-v2 = <&qup_opp_table>;
1154                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1155                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1156                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1157                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1158                                 status = "disabled";
1159                         };
1160
1161                         spi0: spi@880000 {
1162                                 compatible = "qcom,geni-spi";
1163                                 reg = <0 0x00880000 0 0x4000>;
1164                                 clock-names = "se";
1165                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1166                                 pinctrl-names = "default";
1167                                 pinctrl-0 = <&qup_spi0_default>;
1168                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1169                                 #address-cells = <1>;
1170                                 #size-cells = <0>;
1171                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1172                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1173                                 interconnect-names = "qup-core", "qup-config";
1174                                 status = "disabled";
1175                         };
1176
1177                         uart0: serial@880000 {
1178                                 compatible = "qcom,geni-uart";
1179                                 reg = <0 0x00880000 0 0x4000>;
1180                                 clock-names = "se";
1181                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1182                                 pinctrl-names = "default";
1183                                 pinctrl-0 = <&qup_uart0_default>;
1184                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1185                                 power-domains = <&rpmhpd SDM845_CX>;
1186                                 operating-points-v2 = <&qup_opp_table>;
1187                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1188                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1189                                 interconnect-names = "qup-core", "qup-config";
1190                                 status = "disabled";
1191                         };
1192
1193                         i2c1: i2c@884000 {
1194                                 compatible = "qcom,geni-i2c";
1195                                 reg = <0 0x00884000 0 0x4000>;
1196                                 clock-names = "se";
1197                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1198                                 pinctrl-names = "default";
1199                                 pinctrl-0 = <&qup_i2c1_default>;
1200                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1201                                 #address-cells = <1>;
1202                                 #size-cells = <0>;
1203                                 power-domains = <&rpmhpd SDM845_CX>;
1204                                 operating-points-v2 = <&qup_opp_table>;
1205                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1206                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1207                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1208                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209                                 status = "disabled";
1210                         };
1211
1212                         spi1: spi@884000 {
1213                                 compatible = "qcom,geni-spi";
1214                                 reg = <0 0x00884000 0 0x4000>;
1215                                 clock-names = "se";
1216                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1217                                 pinctrl-names = "default";
1218                                 pinctrl-0 = <&qup_spi1_default>;
1219                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1220                                 #address-cells = <1>;
1221                                 #size-cells = <0>;
1222                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1223                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1224                                 interconnect-names = "qup-core", "qup-config";
1225                                 status = "disabled";
1226                         };
1227
1228                         uart1: serial@884000 {
1229                                 compatible = "qcom,geni-uart";
1230                                 reg = <0 0x00884000 0 0x4000>;
1231                                 clock-names = "se";
1232                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1233                                 pinctrl-names = "default";
1234                                 pinctrl-0 = <&qup_uart1_default>;
1235                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1236                                 power-domains = <&rpmhpd SDM845_CX>;
1237                                 operating-points-v2 = <&qup_opp_table>;
1238                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1239                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1240                                 interconnect-names = "qup-core", "qup-config";
1241                                 status = "disabled";
1242                         };
1243
1244                         i2c2: i2c@888000 {
1245                                 compatible = "qcom,geni-i2c";
1246                                 reg = <0 0x00888000 0 0x4000>;
1247                                 clock-names = "se";
1248                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1249                                 pinctrl-names = "default";
1250                                 pinctrl-0 = <&qup_i2c2_default>;
1251                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1252                                 #address-cells = <1>;
1253                                 #size-cells = <0>;
1254                                 power-domains = <&rpmhpd SDM845_CX>;
1255                                 operating-points-v2 = <&qup_opp_table>;
1256                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1257                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1258                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1259                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1260                                 status = "disabled";
1261                         };
1262
1263                         spi2: spi@888000 {
1264                                 compatible = "qcom,geni-spi";
1265                                 reg = <0 0x00888000 0 0x4000>;
1266                                 clock-names = "se";
1267                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1268                                 pinctrl-names = "default";
1269                                 pinctrl-0 = <&qup_spi2_default>;
1270                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1271                                 #address-cells = <1>;
1272                                 #size-cells = <0>;
1273                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1274                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1275                                 interconnect-names = "qup-core", "qup-config";
1276                                 status = "disabled";
1277                         };
1278
1279                         uart2: serial@888000 {
1280                                 compatible = "qcom,geni-uart";
1281                                 reg = <0 0x00888000 0 0x4000>;
1282                                 clock-names = "se";
1283                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1284                                 pinctrl-names = "default";
1285                                 pinctrl-0 = <&qup_uart2_default>;
1286                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1287                                 power-domains = <&rpmhpd SDM845_CX>;
1288                                 operating-points-v2 = <&qup_opp_table>;
1289                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1290                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1291                                 interconnect-names = "qup-core", "qup-config";
1292                                 status = "disabled";
1293                         };
1294
1295                         i2c3: i2c@88c000 {
1296                                 compatible = "qcom,geni-i2c";
1297                                 reg = <0 0x0088c000 0 0x4000>;
1298                                 clock-names = "se";
1299                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1300                                 pinctrl-names = "default";
1301                                 pinctrl-0 = <&qup_i2c3_default>;
1302                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1303                                 #address-cells = <1>;
1304                                 #size-cells = <0>;
1305                                 power-domains = <&rpmhpd SDM845_CX>;
1306                                 operating-points-v2 = <&qup_opp_table>;
1307                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1308                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1309                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1310                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1311                                 status = "disabled";
1312                         };
1313
1314                         spi3: spi@88c000 {
1315                                 compatible = "qcom,geni-spi";
1316                                 reg = <0 0x0088c000 0 0x4000>;
1317                                 clock-names = "se";
1318                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1319                                 pinctrl-names = "default";
1320                                 pinctrl-0 = <&qup_spi3_default>;
1321                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1322                                 #address-cells = <1>;
1323                                 #size-cells = <0>;
1324                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1325                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1326                                 interconnect-names = "qup-core", "qup-config";
1327                                 status = "disabled";
1328                         };
1329
1330                         uart3: serial@88c000 {
1331                                 compatible = "qcom,geni-uart";
1332                                 reg = <0 0x0088c000 0 0x4000>;
1333                                 clock-names = "se";
1334                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1335                                 pinctrl-names = "default";
1336                                 pinctrl-0 = <&qup_uart3_default>;
1337                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1338                                 power-domains = <&rpmhpd SDM845_CX>;
1339                                 operating-points-v2 = <&qup_opp_table>;
1340                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1341                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1342                                 interconnect-names = "qup-core", "qup-config";
1343                                 status = "disabled";
1344                         };
1345
1346                         i2c4: i2c@890000 {
1347                                 compatible = "qcom,geni-i2c";
1348                                 reg = <0 0x00890000 0 0x4000>;
1349                                 clock-names = "se";
1350                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1351                                 pinctrl-names = "default";
1352                                 pinctrl-0 = <&qup_i2c4_default>;
1353                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1354                                 #address-cells = <1>;
1355                                 #size-cells = <0>;
1356                                 power-domains = <&rpmhpd SDM845_CX>;
1357                                 operating-points-v2 = <&qup_opp_table>;
1358                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1359                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1360                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1361                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1362                                 status = "disabled";
1363                         };
1364
1365                         spi4: spi@890000 {
1366                                 compatible = "qcom,geni-spi";
1367                                 reg = <0 0x00890000 0 0x4000>;
1368                                 clock-names = "se";
1369                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1370                                 pinctrl-names = "default";
1371                                 pinctrl-0 = <&qup_spi4_default>;
1372                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1373                                 #address-cells = <1>;
1374                                 #size-cells = <0>;
1375                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1376                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1377                                 interconnect-names = "qup-core", "qup-config";
1378                                 status = "disabled";
1379                         };
1380
1381                         uart4: serial@890000 {
1382                                 compatible = "qcom,geni-uart";
1383                                 reg = <0 0x00890000 0 0x4000>;
1384                                 clock-names = "se";
1385                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1386                                 pinctrl-names = "default";
1387                                 pinctrl-0 = <&qup_uart4_default>;
1388                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1389                                 power-domains = <&rpmhpd SDM845_CX>;
1390                                 operating-points-v2 = <&qup_opp_table>;
1391                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1392                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1393                                 interconnect-names = "qup-core", "qup-config";
1394                                 status = "disabled";
1395                         };
1396
1397                         i2c5: i2c@894000 {
1398                                 compatible = "qcom,geni-i2c";
1399                                 reg = <0 0x00894000 0 0x4000>;
1400                                 clock-names = "se";
1401                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1402                                 pinctrl-names = "default";
1403                                 pinctrl-0 = <&qup_i2c5_default>;
1404                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1405                                 #address-cells = <1>;
1406                                 #size-cells = <0>;
1407                                 power-domains = <&rpmhpd SDM845_CX>;
1408                                 operating-points-v2 = <&qup_opp_table>;
1409                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1410                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1411                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1412                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1413                                 status = "disabled";
1414                         };
1415
1416                         spi5: spi@894000 {
1417                                 compatible = "qcom,geni-spi";
1418                                 reg = <0 0x00894000 0 0x4000>;
1419                                 clock-names = "se";
1420                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1421                                 pinctrl-names = "default";
1422                                 pinctrl-0 = <&qup_spi5_default>;
1423                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1424                                 #address-cells = <1>;
1425                                 #size-cells = <0>;
1426                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1427                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1428                                 interconnect-names = "qup-core", "qup-config";
1429                                 status = "disabled";
1430                         };
1431
1432                         uart5: serial@894000 {
1433                                 compatible = "qcom,geni-uart";
1434                                 reg = <0 0x00894000 0 0x4000>;
1435                                 clock-names = "se";
1436                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1437                                 pinctrl-names = "default";
1438                                 pinctrl-0 = <&qup_uart5_default>;
1439                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1440                                 power-domains = <&rpmhpd SDM845_CX>;
1441                                 operating-points-v2 = <&qup_opp_table>;
1442                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1443                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1444                                 interconnect-names = "qup-core", "qup-config";
1445                                 status = "disabled";
1446                         };
1447
1448                         i2c6: i2c@898000 {
1449                                 compatible = "qcom,geni-i2c";
1450                                 reg = <0 0x00898000 0 0x4000>;
1451                                 clock-names = "se";
1452                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1453                                 pinctrl-names = "default";
1454                                 pinctrl-0 = <&qup_i2c6_default>;
1455                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1456                                 #address-cells = <1>;
1457                                 #size-cells = <0>;
1458                                 power-domains = <&rpmhpd SDM845_CX>;
1459                                 operating-points-v2 = <&qup_opp_table>;
1460                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1461                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1462                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1463                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1464                                 status = "disabled";
1465                         };
1466
1467                         spi6: spi@898000 {
1468                                 compatible = "qcom,geni-spi";
1469                                 reg = <0 0x00898000 0 0x4000>;
1470                                 clock-names = "se";
1471                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1472                                 pinctrl-names = "default";
1473                                 pinctrl-0 = <&qup_spi6_default>;
1474                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1475                                 #address-cells = <1>;
1476                                 #size-cells = <0>;
1477                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1478                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1479                                 interconnect-names = "qup-core", "qup-config";
1480                                 status = "disabled";
1481                         };
1482
1483                         uart6: serial@898000 {
1484                                 compatible = "qcom,geni-uart";
1485                                 reg = <0 0x00898000 0 0x4000>;
1486                                 clock-names = "se";
1487                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1488                                 pinctrl-names = "default";
1489                                 pinctrl-0 = <&qup_uart6_default>;
1490                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1491                                 power-domains = <&rpmhpd SDM845_CX>;
1492                                 operating-points-v2 = <&qup_opp_table>;
1493                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1494                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1495                                 interconnect-names = "qup-core", "qup-config";
1496                                 status = "disabled";
1497                         };
1498
1499                         i2c7: i2c@89c000 {
1500                                 compatible = "qcom,geni-i2c";
1501                                 reg = <0 0x0089c000 0 0x4000>;
1502                                 clock-names = "se";
1503                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1504                                 pinctrl-names = "default";
1505                                 pinctrl-0 = <&qup_i2c7_default>;
1506                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1507                                 #address-cells = <1>;
1508                                 #size-cells = <0>;
1509                                 power-domains = <&rpmhpd SDM845_CX>;
1510                                 operating-points-v2 = <&qup_opp_table>;
1511                                 status = "disabled";
1512                         };
1513
1514                         spi7: spi@89c000 {
1515                                 compatible = "qcom,geni-spi";
1516                                 reg = <0 0x0089c000 0 0x4000>;
1517                                 clock-names = "se";
1518                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1519                                 pinctrl-names = "default";
1520                                 pinctrl-0 = <&qup_spi7_default>;
1521                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1522                                 #address-cells = <1>;
1523                                 #size-cells = <0>;
1524                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1525                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1526                                 interconnect-names = "qup-core", "qup-config";
1527                                 status = "disabled";
1528                         };
1529
1530                         uart7: serial@89c000 {
1531                                 compatible = "qcom,geni-uart";
1532                                 reg = <0 0x0089c000 0 0x4000>;
1533                                 clock-names = "se";
1534                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1535                                 pinctrl-names = "default";
1536                                 pinctrl-0 = <&qup_uart7_default>;
1537                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1538                                 power-domains = <&rpmhpd SDM845_CX>;
1539                                 operating-points-v2 = <&qup_opp_table>;
1540                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1541                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1542                                 interconnect-names = "qup-core", "qup-config";
1543                                 status = "disabled";
1544                         };
1545                 };
1546
1547                 qupv3_id_1: geniqup@ac0000 {
1548                         compatible = "qcom,geni-se-qup";
1549                         reg = <0 0x00ac0000 0 0x6000>;
1550                         clock-names = "m-ahb", "s-ahb";
1551                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1552                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1553                         iommus = <&apps_smmu 0x6c3 0x0>;
1554                         #address-cells = <2>;
1555                         #size-cells = <2>;
1556                         ranges;
1557                         interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1558                         interconnect-names = "qup-core";
1559                         status = "disabled";
1560
1561                         i2c8: i2c@a80000 {
1562                                 compatible = "qcom,geni-i2c";
1563                                 reg = <0 0x00a80000 0 0x4000>;
1564                                 clock-names = "se";
1565                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1566                                 pinctrl-names = "default";
1567                                 pinctrl-0 = <&qup_i2c8_default>;
1568                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1569                                 #address-cells = <1>;
1570                                 #size-cells = <0>;
1571                                 power-domains = <&rpmhpd SDM845_CX>;
1572                                 operating-points-v2 = <&qup_opp_table>;
1573                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1574                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1575                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1576                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577                                 status = "disabled";
1578                         };
1579
1580                         spi8: spi@a80000 {
1581                                 compatible = "qcom,geni-spi";
1582                                 reg = <0 0x00a80000 0 0x4000>;
1583                                 clock-names = "se";
1584                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1585                                 pinctrl-names = "default";
1586                                 pinctrl-0 = <&qup_spi8_default>;
1587                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1588                                 #address-cells = <1>;
1589                                 #size-cells = <0>;
1590                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1591                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1592                                 interconnect-names = "qup-core", "qup-config";
1593                                 status = "disabled";
1594                         };
1595
1596                         uart8: serial@a80000 {
1597                                 compatible = "qcom,geni-uart";
1598                                 reg = <0 0x00a80000 0 0x4000>;
1599                                 clock-names = "se";
1600                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1601                                 pinctrl-names = "default";
1602                                 pinctrl-0 = <&qup_uart8_default>;
1603                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1604                                 power-domains = <&rpmhpd SDM845_CX>;
1605                                 operating-points-v2 = <&qup_opp_table>;
1606                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1607                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1608                                 interconnect-names = "qup-core", "qup-config";
1609                                 status = "disabled";
1610                         };
1611
1612                         i2c9: i2c@a84000 {
1613                                 compatible = "qcom,geni-i2c";
1614                                 reg = <0 0x00a84000 0 0x4000>;
1615                                 clock-names = "se";
1616                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1617                                 pinctrl-names = "default";
1618                                 pinctrl-0 = <&qup_i2c9_default>;
1619                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1620                                 #address-cells = <1>;
1621                                 #size-cells = <0>;
1622                                 power-domains = <&rpmhpd SDM845_CX>;
1623                                 operating-points-v2 = <&qup_opp_table>;
1624                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1625                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1626                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1627                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1628                                 status = "disabled";
1629                         };
1630
1631                         spi9: spi@a84000 {
1632                                 compatible = "qcom,geni-spi";
1633                                 reg = <0 0x00a84000 0 0x4000>;
1634                                 clock-names = "se";
1635                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1636                                 pinctrl-names = "default";
1637                                 pinctrl-0 = <&qup_spi9_default>;
1638                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1639                                 #address-cells = <1>;
1640                                 #size-cells = <0>;
1641                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1642                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1643                                 interconnect-names = "qup-core", "qup-config";
1644                                 status = "disabled";
1645                         };
1646
1647                         uart9: serial@a84000 {
1648                                 compatible = "qcom,geni-debug-uart";
1649                                 reg = <0 0x00a84000 0 0x4000>;
1650                                 clock-names = "se";
1651                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1652                                 pinctrl-names = "default";
1653                                 pinctrl-0 = <&qup_uart9_default>;
1654                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1655                                 power-domains = <&rpmhpd SDM845_CX>;
1656                                 operating-points-v2 = <&qup_opp_table>;
1657                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1658                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1659                                 interconnect-names = "qup-core", "qup-config";
1660                                 status = "disabled";
1661                         };
1662
1663                         i2c10: i2c@a88000 {
1664                                 compatible = "qcom,geni-i2c";
1665                                 reg = <0 0x00a88000 0 0x4000>;
1666                                 clock-names = "se";
1667                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1668                                 pinctrl-names = "default";
1669                                 pinctrl-0 = <&qup_i2c10_default>;
1670                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1671                                 #address-cells = <1>;
1672                                 #size-cells = <0>;
1673                                 power-domains = <&rpmhpd SDM845_CX>;
1674                                 operating-points-v2 = <&qup_opp_table>;
1675                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1676                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1677                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1678                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1679                                 status = "disabled";
1680                         };
1681
1682                         spi10: spi@a88000 {
1683                                 compatible = "qcom,geni-spi";
1684                                 reg = <0 0x00a88000 0 0x4000>;
1685                                 clock-names = "se";
1686                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1687                                 pinctrl-names = "default";
1688                                 pinctrl-0 = <&qup_spi10_default>;
1689                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1690                                 #address-cells = <1>;
1691                                 #size-cells = <0>;
1692                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1693                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1694                                 interconnect-names = "qup-core", "qup-config";
1695                                 status = "disabled";
1696                         };
1697
1698                         uart10: serial@a88000 {
1699                                 compatible = "qcom,geni-uart";
1700                                 reg = <0 0x00a88000 0 0x4000>;
1701                                 clock-names = "se";
1702                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1703                                 pinctrl-names = "default";
1704                                 pinctrl-0 = <&qup_uart10_default>;
1705                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1706                                 power-domains = <&rpmhpd SDM845_CX>;
1707                                 operating-points-v2 = <&qup_opp_table>;
1708                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1709                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1710                                 interconnect-names = "qup-core", "qup-config";
1711                                 status = "disabled";
1712                         };
1713
1714                         i2c11: i2c@a8c000 {
1715                                 compatible = "qcom,geni-i2c";
1716                                 reg = <0 0x00a8c000 0 0x4000>;
1717                                 clock-names = "se";
1718                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1719                                 pinctrl-names = "default";
1720                                 pinctrl-0 = <&qup_i2c11_default>;
1721                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1722                                 #address-cells = <1>;
1723                                 #size-cells = <0>;
1724                                 power-domains = <&rpmhpd SDM845_CX>;
1725                                 operating-points-v2 = <&qup_opp_table>;
1726                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1727                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1728                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1729                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1730                                 status = "disabled";
1731                         };
1732
1733                         spi11: spi@a8c000 {
1734                                 compatible = "qcom,geni-spi";
1735                                 reg = <0 0x00a8c000 0 0x4000>;
1736                                 clock-names = "se";
1737                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1738                                 pinctrl-names = "default";
1739                                 pinctrl-0 = <&qup_spi11_default>;
1740                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1741                                 #address-cells = <1>;
1742                                 #size-cells = <0>;
1743                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1744                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1745                                 interconnect-names = "qup-core", "qup-config";
1746                                 status = "disabled";
1747                         };
1748
1749                         uart11: serial@a8c000 {
1750                                 compatible = "qcom,geni-uart";
1751                                 reg = <0 0x00a8c000 0 0x4000>;
1752                                 clock-names = "se";
1753                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1754                                 pinctrl-names = "default";
1755                                 pinctrl-0 = <&qup_uart11_default>;
1756                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1757                                 power-domains = <&rpmhpd SDM845_CX>;
1758                                 operating-points-v2 = <&qup_opp_table>;
1759                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1760                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1761                                 interconnect-names = "qup-core", "qup-config";
1762                                 status = "disabled";
1763                         };
1764
1765                         i2c12: i2c@a90000 {
1766                                 compatible = "qcom,geni-i2c";
1767                                 reg = <0 0x00a90000 0 0x4000>;
1768                                 clock-names = "se";
1769                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1770                                 pinctrl-names = "default";
1771                                 pinctrl-0 = <&qup_i2c12_default>;
1772                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1773                                 #address-cells = <1>;
1774                                 #size-cells = <0>;
1775                                 power-domains = <&rpmhpd SDM845_CX>;
1776                                 operating-points-v2 = <&qup_opp_table>;
1777                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1778                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1779                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1780                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1781                                 status = "disabled";
1782                         };
1783
1784                         spi12: spi@a90000 {
1785                                 compatible = "qcom,geni-spi";
1786                                 reg = <0 0x00a90000 0 0x4000>;
1787                                 clock-names = "se";
1788                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1789                                 pinctrl-names = "default";
1790                                 pinctrl-0 = <&qup_spi12_default>;
1791                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1792                                 #address-cells = <1>;
1793                                 #size-cells = <0>;
1794                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1795                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1796                                 interconnect-names = "qup-core", "qup-config";
1797                                 status = "disabled";
1798                         };
1799
1800                         uart12: serial@a90000 {
1801                                 compatible = "qcom,geni-uart";
1802                                 reg = <0 0x00a90000 0 0x4000>;
1803                                 clock-names = "se";
1804                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1805                                 pinctrl-names = "default";
1806                                 pinctrl-0 = <&qup_uart12_default>;
1807                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1808                                 power-domains = <&rpmhpd SDM845_CX>;
1809                                 operating-points-v2 = <&qup_opp_table>;
1810                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1811                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1812                                 interconnect-names = "qup-core", "qup-config";
1813                                 status = "disabled";
1814                         };
1815
1816                         i2c13: i2c@a94000 {
1817                                 compatible = "qcom,geni-i2c";
1818                                 reg = <0 0x00a94000 0 0x4000>;
1819                                 clock-names = "se";
1820                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1821                                 pinctrl-names = "default";
1822                                 pinctrl-0 = <&qup_i2c13_default>;
1823                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1824                                 #address-cells = <1>;
1825                                 #size-cells = <0>;
1826                                 power-domains = <&rpmhpd SDM845_CX>;
1827                                 operating-points-v2 = <&qup_opp_table>;
1828                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1829                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1830                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1831                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1832                                 status = "disabled";
1833                         };
1834
1835                         spi13: spi@a94000 {
1836                                 compatible = "qcom,geni-spi";
1837                                 reg = <0 0x00a94000 0 0x4000>;
1838                                 clock-names = "se";
1839                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1840                                 pinctrl-names = "default";
1841                                 pinctrl-0 = <&qup_spi13_default>;
1842                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1843                                 #address-cells = <1>;
1844                                 #size-cells = <0>;
1845                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1846                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1847                                 interconnect-names = "qup-core", "qup-config";
1848                                 status = "disabled";
1849                         };
1850
1851                         uart13: serial@a94000 {
1852                                 compatible = "qcom,geni-uart";
1853                                 reg = <0 0x00a94000 0 0x4000>;
1854                                 clock-names = "se";
1855                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1856                                 pinctrl-names = "default";
1857                                 pinctrl-0 = <&qup_uart13_default>;
1858                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1859                                 power-domains = <&rpmhpd SDM845_CX>;
1860                                 operating-points-v2 = <&qup_opp_table>;
1861                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1862                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1863                                 interconnect-names = "qup-core", "qup-config";
1864                                 status = "disabled";
1865                         };
1866
1867                         i2c14: i2c@a98000 {
1868                                 compatible = "qcom,geni-i2c";
1869                                 reg = <0 0x00a98000 0 0x4000>;
1870                                 clock-names = "se";
1871                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1872                                 pinctrl-names = "default";
1873                                 pinctrl-0 = <&qup_i2c14_default>;
1874                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1875                                 #address-cells = <1>;
1876                                 #size-cells = <0>;
1877                                 power-domains = <&rpmhpd SDM845_CX>;
1878                                 operating-points-v2 = <&qup_opp_table>;
1879                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1880                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1881                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1882                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1883                                 status = "disabled";
1884                         };
1885
1886                         spi14: spi@a98000 {
1887                                 compatible = "qcom,geni-spi";
1888                                 reg = <0 0x00a98000 0 0x4000>;
1889                                 clock-names = "se";
1890                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1891                                 pinctrl-names = "default";
1892                                 pinctrl-0 = <&qup_spi14_default>;
1893                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1894                                 #address-cells = <1>;
1895                                 #size-cells = <0>;
1896                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1897                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1898                                 interconnect-names = "qup-core", "qup-config";
1899                                 status = "disabled";
1900                         };
1901
1902                         uart14: serial@a98000 {
1903                                 compatible = "qcom,geni-uart";
1904                                 reg = <0 0x00a98000 0 0x4000>;
1905                                 clock-names = "se";
1906                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1907                                 pinctrl-names = "default";
1908                                 pinctrl-0 = <&qup_uart14_default>;
1909                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1910                                 power-domains = <&rpmhpd SDM845_CX>;
1911                                 operating-points-v2 = <&qup_opp_table>;
1912                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1913                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1914                                 interconnect-names = "qup-core", "qup-config";
1915                                 status = "disabled";
1916                         };
1917
1918                         i2c15: i2c@a9c000 {
1919                                 compatible = "qcom,geni-i2c";
1920                                 reg = <0 0x00a9c000 0 0x4000>;
1921                                 clock-names = "se";
1922                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1923                                 pinctrl-names = "default";
1924                                 pinctrl-0 = <&qup_i2c15_default>;
1925                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1926                                 #address-cells = <1>;
1927                                 #size-cells = <0>;
1928                                 power-domains = <&rpmhpd SDM845_CX>;
1929                                 operating-points-v2 = <&qup_opp_table>;
1930                                 status = "disabled";
1931                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1932                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1933                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1934                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1935                         };
1936
1937                         spi15: spi@a9c000 {
1938                                 compatible = "qcom,geni-spi";
1939                                 reg = <0 0x00a9c000 0 0x4000>;
1940                                 clock-names = "se";
1941                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1942                                 pinctrl-names = "default";
1943                                 pinctrl-0 = <&qup_spi15_default>;
1944                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1945                                 #address-cells = <1>;
1946                                 #size-cells = <0>;
1947                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1948                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1949                                 interconnect-names = "qup-core", "qup-config";
1950                                 status = "disabled";
1951                         };
1952
1953                         uart15: serial@a9c000 {
1954                                 compatible = "qcom,geni-uart";
1955                                 reg = <0 0x00a9c000 0 0x4000>;
1956                                 clock-names = "se";
1957                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1958                                 pinctrl-names = "default";
1959                                 pinctrl-0 = <&qup_uart15_default>;
1960                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1961                                 power-domains = <&rpmhpd SDM845_CX>;
1962                                 operating-points-v2 = <&qup_opp_table>;
1963                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1964                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1965                                 interconnect-names = "qup-core", "qup-config";
1966                                 status = "disabled";
1967                         };
1968                 };
1969
1970                 system-cache-controller@1100000 {
1971                         compatible = "qcom,sdm845-llcc";
1972                         reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1973                         reg-names = "llcc_base", "llcc_broadcast_base";
1974                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1975                 };
1976
1977                 pcie0: pci@1c00000 {
1978                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
1979                         reg = <0 0x01c00000 0 0x2000>,
1980                               <0 0x60000000 0 0xf1d>,
1981                               <0 0x60000f20 0 0xa8>,
1982                               <0 0x60100000 0 0x100000>;
1983                         reg-names = "parf", "dbi", "elbi", "config";
1984                         device_type = "pci";
1985                         linux,pci-domain = <0>;
1986                         bus-range = <0x00 0xff>;
1987                         num-lanes = <1>;
1988
1989                         #address-cells = <3>;
1990                         #size-cells = <2>;
1991
1992                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1993                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
1994
1995                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1996                         interrupt-names = "msi";
1997                         #interrupt-cells = <1>;
1998                         interrupt-map-mask = <0 0 0 0x7>;
1999                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2000                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2001                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2002                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2003
2004                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2005                                  <&gcc GCC_PCIE_0_AUX_CLK>,
2006                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2007                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2008                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2009                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2010                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2011                         clock-names = "pipe",
2012                                       "aux",
2013                                       "cfg",
2014                                       "bus_master",
2015                                       "bus_slave",
2016                                       "slave_q2a",
2017                                       "tbu";
2018
2019                         iommus = <&apps_smmu 0x1c10 0xf>;
2020                         iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
2021                                     <0x100 &apps_smmu 0x1c11 0x1>,
2022                                     <0x200 &apps_smmu 0x1c12 0x1>,
2023                                     <0x300 &apps_smmu 0x1c13 0x1>,
2024                                     <0x400 &apps_smmu 0x1c14 0x1>,
2025                                     <0x500 &apps_smmu 0x1c15 0x1>,
2026                                     <0x600 &apps_smmu 0x1c16 0x1>,
2027                                     <0x700 &apps_smmu 0x1c17 0x1>,
2028                                     <0x800 &apps_smmu 0x1c18 0x1>,
2029                                     <0x900 &apps_smmu 0x1c19 0x1>,
2030                                     <0xa00 &apps_smmu 0x1c1a 0x1>,
2031                                     <0xb00 &apps_smmu 0x1c1b 0x1>,
2032                                     <0xc00 &apps_smmu 0x1c1c 0x1>,
2033                                     <0xd00 &apps_smmu 0x1c1d 0x1>,
2034                                     <0xe00 &apps_smmu 0x1c1e 0x1>,
2035                                     <0xf00 &apps_smmu 0x1c1f 0x1>;
2036
2037                         resets = <&gcc GCC_PCIE_0_BCR>;
2038                         reset-names = "pci";
2039
2040                         power-domains = <&gcc PCIE_0_GDSC>;
2041
2042                         phys = <&pcie0_lane>;
2043                         phy-names = "pciephy";
2044
2045                         status = "disabled";
2046                 };
2047
2048                 pcie0_phy: phy@1c06000 {
2049                         compatible = "qcom,sdm845-qmp-pcie-phy";
2050                         reg = <0 0x01c06000 0 0x18c>;
2051                         #address-cells = <2>;
2052                         #size-cells = <2>;
2053                         ranges;
2054                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2055                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2056                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
2057                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2058                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2059
2060                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2061                         reset-names = "phy";
2062
2063                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2064                         assigned-clock-rates = <100000000>;
2065
2066                         status = "disabled";
2067
2068                         pcie0_lane: phy@1c06200 {
2069                                 reg = <0 0x01c06200 0 0x128>,
2070                                       <0 0x01c06400 0 0x1fc>,
2071                                       <0 0x01c06800 0 0x218>,
2072                                       <0 0x01c06600 0 0x70>;
2073                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
2074                                 clock-names = "pipe0";
2075
2076                                 #clock-cells = <0>;
2077                                 #phy-cells = <0>;
2078                                 clock-output-names = "pcie_0_pipe_clk";
2079                         };
2080                 };
2081
2082                 pcie1: pci@1c08000 {
2083                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2084                         reg = <0 0x01c08000 0 0x2000>,
2085                               <0 0x40000000 0 0xf1d>,
2086                               <0 0x40000f20 0 0xa8>,
2087                               <0 0x40100000 0 0x100000>;
2088                         reg-names = "parf", "dbi", "elbi", "config";
2089                         device_type = "pci";
2090                         linux,pci-domain = <1>;
2091                         bus-range = <0x00 0xff>;
2092                         num-lanes = <1>;
2093
2094                         #address-cells = <3>;
2095                         #size-cells = <2>;
2096
2097                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2098                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2099
2100                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2101                         interrupt-names = "msi";
2102                         #interrupt-cells = <1>;
2103                         interrupt-map-mask = <0 0 0 0x7>;
2104                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2105                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2106                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2107                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2108
2109                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2110                                  <&gcc GCC_PCIE_1_AUX_CLK>,
2111                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2112                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2113                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2114                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2115                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2116                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2117                         clock-names = "pipe",
2118                                       "aux",
2119                                       "cfg",
2120                                       "bus_master",
2121                                       "bus_slave",
2122                                       "slave_q2a",
2123                                       "ref",
2124                                       "tbu";
2125
2126                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2127                         assigned-clock-rates = <19200000>;
2128
2129                         iommus = <&apps_smmu 0x1c00 0xf>;
2130                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
2131                                     <0x100 &apps_smmu 0x1c01 0x1>,
2132                                     <0x200 &apps_smmu 0x1c02 0x1>,
2133                                     <0x300 &apps_smmu 0x1c03 0x1>,
2134                                     <0x400 &apps_smmu 0x1c04 0x1>,
2135                                     <0x500 &apps_smmu 0x1c05 0x1>,
2136                                     <0x600 &apps_smmu 0x1c06 0x1>,
2137                                     <0x700 &apps_smmu 0x1c07 0x1>,
2138                                     <0x800 &apps_smmu 0x1c08 0x1>,
2139                                     <0x900 &apps_smmu 0x1c09 0x1>,
2140                                     <0xa00 &apps_smmu 0x1c0a 0x1>,
2141                                     <0xb00 &apps_smmu 0x1c0b 0x1>,
2142                                     <0xc00 &apps_smmu 0x1c0c 0x1>,
2143                                     <0xd00 &apps_smmu 0x1c0d 0x1>,
2144                                     <0xe00 &apps_smmu 0x1c0e 0x1>,
2145                                     <0xf00 &apps_smmu 0x1c0f 0x1>;
2146
2147                         resets = <&gcc GCC_PCIE_1_BCR>;
2148                         reset-names = "pci";
2149
2150                         power-domains = <&gcc PCIE_1_GDSC>;
2151
2152                         phys = <&pcie1_lane>;
2153                         phy-names = "pciephy";
2154
2155                         status = "disabled";
2156                 };
2157
2158                 pcie1_phy: phy@1c0a000 {
2159                         compatible = "qcom,sdm845-qhp-pcie-phy";
2160                         reg = <0 0x01c0a000 0 0x800>;
2161                         #address-cells = <2>;
2162                         #size-cells = <2>;
2163                         ranges;
2164                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2165                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2166                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2167                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2168                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2169
2170                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2171                         reset-names = "phy";
2172
2173                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2174                         assigned-clock-rates = <100000000>;
2175
2176                         status = "disabled";
2177
2178                         pcie1_lane: phy@1c06200 {
2179                                 reg = <0 0x01c0a800 0 0x800>,
2180                                       <0 0x01c0a800 0 0x800>,
2181                                       <0 0x01c0b800 0 0x400>;
2182                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2183                                 clock-names = "pipe0";
2184
2185                                 #clock-cells = <0>;
2186                                 #phy-cells = <0>;
2187                                 clock-output-names = "pcie_1_pipe_clk";
2188                         };
2189                 };
2190
2191                 mem_noc: interconnect@1380000 {
2192                         compatible = "qcom,sdm845-mem-noc";
2193                         reg = <0 0x01380000 0 0x27200>;
2194                         #interconnect-cells = <2>;
2195                         qcom,bcm-voters = <&apps_bcm_voter>;
2196                 };
2197
2198                 dc_noc: interconnect@14e0000 {
2199                         compatible = "qcom,sdm845-dc-noc";
2200                         reg = <0 0x014e0000 0 0x400>;
2201                         #interconnect-cells = <2>;
2202                         qcom,bcm-voters = <&apps_bcm_voter>;
2203                 };
2204
2205                 config_noc: interconnect@1500000 {
2206                         compatible = "qcom,sdm845-config-noc";
2207                         reg = <0 0x01500000 0 0x5080>;
2208                         #interconnect-cells = <2>;
2209                         qcom,bcm-voters = <&apps_bcm_voter>;
2210                 };
2211
2212                 system_noc: interconnect@1620000 {
2213                         compatible = "qcom,sdm845-system-noc";
2214                         reg = <0 0x01620000 0 0x18080>;
2215                         #interconnect-cells = <2>;
2216                         qcom,bcm-voters = <&apps_bcm_voter>;
2217                 };
2218
2219                 aggre1_noc: interconnect@16e0000 {
2220                         compatible = "qcom,sdm845-aggre1-noc";
2221                         reg = <0 0x016e0000 0 0x15080>;
2222                         #interconnect-cells = <2>;
2223                         qcom,bcm-voters = <&apps_bcm_voter>;
2224                 };
2225
2226                 aggre2_noc: interconnect@1700000 {
2227                         compatible = "qcom,sdm845-aggre2-noc";
2228                         reg = <0 0x01700000 0 0x1f300>;
2229                         #interconnect-cells = <2>;
2230                         qcom,bcm-voters = <&apps_bcm_voter>;
2231                 };
2232
2233                 mmss_noc: interconnect@1740000 {
2234                         compatible = "qcom,sdm845-mmss-noc";
2235                         reg = <0 0x01740000 0 0x1c100>;
2236                         #interconnect-cells = <2>;
2237                         qcom,bcm-voters = <&apps_bcm_voter>;
2238                 };
2239
2240                 ufs_mem_hc: ufshc@1d84000 {
2241                         compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2242                                      "jedec,ufs-2.0";
2243                         reg = <0 0x01d84000 0 0x2500>,
2244                               <0 0x01d90000 0 0x8000>;
2245                         reg-names = "std", "ice";
2246                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2247                         phys = <&ufs_mem_phy_lanes>;
2248                         phy-names = "ufsphy";
2249                         lanes-per-direction = <2>;
2250                         power-domains = <&gcc UFS_PHY_GDSC>;
2251                         #reset-cells = <1>;
2252                         resets = <&gcc GCC_UFS_PHY_BCR>;
2253                         reset-names = "rst";
2254
2255                         iommus = <&apps_smmu 0x100 0xf>;
2256
2257                         clock-names =
2258                                 "core_clk",
2259                                 "bus_aggr_clk",
2260                                 "iface_clk",
2261                                 "core_clk_unipro",
2262                                 "ref_clk",
2263                                 "tx_lane0_sync_clk",
2264                                 "rx_lane0_sync_clk",
2265                                 "rx_lane1_sync_clk",
2266                                 "ice_core_clk";
2267                         clocks =
2268                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2269                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2270                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2271                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2272                                 <&rpmhcc RPMH_CXO_CLK>,
2273                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2274                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2275                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2276                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2277                         freq-table-hz =
2278                                 <50000000 200000000>,
2279                                 <0 0>,
2280                                 <0 0>,
2281                                 <37500000 150000000>,
2282                                 <0 0>,
2283                                 <0 0>,
2284                                 <0 0>,
2285                                 <0 0>,
2286                                 <0 300000000>;
2287
2288                         status = "disabled";
2289                 };
2290
2291                 ufs_mem_phy: phy@1d87000 {
2292                         compatible = "qcom,sdm845-qmp-ufs-phy";
2293                         reg = <0 0x01d87000 0 0x18c>;
2294                         #address-cells = <2>;
2295                         #size-cells = <2>;
2296                         ranges;
2297                         clock-names = "ref",
2298                                       "ref_aux";
2299                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2300                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2301
2302                         resets = <&ufs_mem_hc 0>;
2303                         reset-names = "ufsphy";
2304                         status = "disabled";
2305
2306                         ufs_mem_phy_lanes: phy@1d87400 {
2307                                 reg = <0 0x01d87400 0 0x108>,
2308                                       <0 0x01d87600 0 0x1e0>,
2309                                       <0 0x01d87c00 0 0x1dc>,
2310                                       <0 0x01d87800 0 0x108>,
2311                                       <0 0x01d87a00 0 0x1e0>;
2312                                 #phy-cells = <0>;
2313                         };
2314                 };
2315
2316                 cryptobam: dma-controller@1dc4000 {
2317                         compatible = "qcom,bam-v1.7.0";
2318                         reg = <0 0x01dc4000 0 0x24000>;
2319                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2320                         clocks = <&rpmhcc RPMH_CE_CLK>;
2321                         clock-names = "bam_clk";
2322                         #dma-cells = <1>;
2323                         qcom,ee = <0>;
2324                         qcom,controlled-remotely;
2325                         iommus = <&apps_smmu 0x704 0x1>,
2326                                  <&apps_smmu 0x706 0x1>,
2327                                  <&apps_smmu 0x714 0x1>,
2328                                  <&apps_smmu 0x716 0x1>;
2329                 };
2330
2331                 crypto: crypto@1dfa000 {
2332                         compatible = "qcom,crypto-v5.4";
2333                         reg = <0 0x01dfa000 0 0x6000>;
2334                         clocks = <&gcc GCC_CE1_AHB_CLK>,
2335                                  <&gcc GCC_CE1_AXI_CLK>,
2336                                  <&rpmhcc RPMH_CE_CLK>;
2337                         clock-names = "iface", "bus", "core";
2338                         dmas = <&cryptobam 6>, <&cryptobam 7>;
2339                         dma-names = "rx", "tx";
2340                         iommus = <&apps_smmu 0x704 0x1>,
2341                                  <&apps_smmu 0x706 0x1>,
2342                                  <&apps_smmu 0x714 0x1>,
2343                                  <&apps_smmu 0x716 0x1>;
2344                 };
2345
2346                 ipa: ipa@1e40000 {
2347                         compatible = "qcom,sdm845-ipa";
2348
2349                         iommus = <&apps_smmu 0x720 0x0>,
2350                                  <&apps_smmu 0x722 0x0>;
2351                         reg = <0 0x1e40000 0 0x7000>,
2352                               <0 0x1e47000 0 0x2000>,
2353                               <0 0x1e04000 0 0x2c000>;
2354                         reg-names = "ipa-reg",
2355                                     "ipa-shared",
2356                                     "gsi";
2357
2358                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2359                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2360                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2361                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2362                         interrupt-names = "ipa",
2363                                           "gsi",
2364                                           "ipa-clock-query",
2365                                           "ipa-setup-ready";
2366
2367                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2368                         clock-names = "core";
2369
2370                         interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2371                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2372                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2373                         interconnect-names = "memory",
2374                                              "imem",
2375                                              "config";
2376
2377                         qcom,smem-states = <&ipa_smp2p_out 0>,
2378                                            <&ipa_smp2p_out 1>;
2379                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2380                                                 "ipa-clock-enabled";
2381
2382                         status = "disabled";
2383                 };
2384
2385                 tcsr_mutex_regs: syscon@1f40000 {
2386                         compatible = "syscon";
2387                         reg = <0 0x01f40000 0 0x40000>;
2388                 };
2389
2390                 tlmm: pinctrl@3400000 {
2391                         compatible = "qcom,sdm845-pinctrl";
2392                         reg = <0 0x03400000 0 0xc00000>;
2393                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2394                         gpio-controller;
2395                         #gpio-cells = <2>;
2396                         interrupt-controller;
2397                         #interrupt-cells = <2>;
2398                         gpio-ranges = <&tlmm 0 0 151>;
2399                         wakeup-parent = <&pdc_intc>;
2400
2401                         cci0_default: cci0-default {
2402                                 /* SDA, SCL */
2403                                 pins = "gpio17", "gpio18";
2404                                 function = "cci_i2c";
2405
2406                                 bias-pull-up;
2407                                 drive-strength = <2>; /* 2 mA */
2408                         };
2409
2410                         cci0_sleep: cci0-sleep {
2411                                 /* SDA, SCL */
2412                                 pins = "gpio17", "gpio18";
2413                                 function = "cci_i2c";
2414
2415                                 drive-strength = <2>; /* 2 mA */
2416                                 bias-pull-down;
2417                         };
2418
2419                         cci1_default: cci1-default {
2420                                 /* SDA, SCL */
2421                                 pins = "gpio19", "gpio20";
2422                                 function = "cci_i2c";
2423
2424                                 bias-pull-up;
2425                                 drive-strength = <2>; /* 2 mA */
2426                         };
2427
2428                         cci1_sleep: cci1-sleep {
2429                                 /* SDA, SCL */
2430                                 pins = "gpio19", "gpio20";
2431                                 function = "cci_i2c";
2432
2433                                 drive-strength = <2>; /* 2 mA */
2434                                 bias-pull-down;
2435                         };
2436
2437                         qspi_clk: qspi-clk {
2438                                 pinmux {
2439                                         pins = "gpio95";
2440                                         function = "qspi_clk";
2441                                 };
2442                         };
2443
2444                         qspi_cs0: qspi-cs0 {
2445                                 pinmux {
2446                                         pins = "gpio90";
2447                                         function = "qspi_cs";
2448                                 };
2449                         };
2450
2451                         qspi_cs1: qspi-cs1 {
2452                                 pinmux {
2453                                         pins = "gpio89";
2454                                         function = "qspi_cs";
2455                                 };
2456                         };
2457
2458                         qspi_data01: qspi-data01 {
2459                                 pinmux-data {
2460                                         pins = "gpio91", "gpio92";
2461                                         function = "qspi_data";
2462                                 };
2463                         };
2464
2465                         qspi_data12: qspi-data12 {
2466                                 pinmux-data {
2467                                         pins = "gpio93", "gpio94";
2468                                         function = "qspi_data";
2469                                 };
2470                         };
2471
2472                         qup_i2c0_default: qup-i2c0-default {
2473                                 pinmux {
2474                                         pins = "gpio0", "gpio1";
2475                                         function = "qup0";
2476                                 };
2477                         };
2478
2479                         qup_i2c1_default: qup-i2c1-default {
2480                                 pinmux {
2481                                         pins = "gpio17", "gpio18";
2482                                         function = "qup1";
2483                                 };
2484                         };
2485
2486                         qup_i2c2_default: qup-i2c2-default {
2487                                 pinmux {
2488                                         pins = "gpio27", "gpio28";
2489                                         function = "qup2";
2490                                 };
2491                         };
2492
2493                         qup_i2c3_default: qup-i2c3-default {
2494                                 pinmux {
2495                                         pins = "gpio41", "gpio42";
2496                                         function = "qup3";
2497                                 };
2498                         };
2499
2500                         qup_i2c4_default: qup-i2c4-default {
2501                                 pinmux {
2502                                         pins = "gpio89", "gpio90";
2503                                         function = "qup4";
2504                                 };
2505                         };
2506
2507                         qup_i2c5_default: qup-i2c5-default {
2508                                 pinmux {
2509                                         pins = "gpio85", "gpio86";
2510                                         function = "qup5";
2511                                 };
2512                         };
2513
2514                         qup_i2c6_default: qup-i2c6-default {
2515                                 pinmux {
2516                                         pins = "gpio45", "gpio46";
2517                                         function = "qup6";
2518                                 };
2519                         };
2520
2521                         qup_i2c7_default: qup-i2c7-default {
2522                                 pinmux {
2523                                         pins = "gpio93", "gpio94";
2524                                         function = "qup7";
2525                                 };
2526                         };
2527
2528                         qup_i2c8_default: qup-i2c8-default {
2529                                 pinmux {
2530                                         pins = "gpio65", "gpio66";
2531                                         function = "qup8";
2532                                 };
2533                         };
2534
2535                         qup_i2c9_default: qup-i2c9-default {
2536                                 pinmux {
2537                                         pins = "gpio6", "gpio7";
2538                                         function = "qup9";
2539                                 };
2540                         };
2541
2542                         qup_i2c10_default: qup-i2c10-default {
2543                                 pinmux {
2544                                         pins = "gpio55", "gpio56";
2545                                         function = "qup10";
2546                                 };
2547                         };
2548
2549                         qup_i2c11_default: qup-i2c11-default {
2550                                 pinmux {
2551                                         pins = "gpio31", "gpio32";
2552                                         function = "qup11";
2553                                 };
2554                         };
2555
2556                         qup_i2c12_default: qup-i2c12-default {
2557                                 pinmux {
2558                                         pins = "gpio49", "gpio50";
2559                                         function = "qup12";
2560                                 };
2561                         };
2562
2563                         qup_i2c13_default: qup-i2c13-default {
2564                                 pinmux {
2565                                         pins = "gpio105", "gpio106";
2566                                         function = "qup13";
2567                                 };
2568                         };
2569
2570                         qup_i2c14_default: qup-i2c14-default {
2571                                 pinmux {
2572                                         pins = "gpio33", "gpio34";
2573                                         function = "qup14";
2574                                 };
2575                         };
2576
2577                         qup_i2c15_default: qup-i2c15-default {
2578                                 pinmux {
2579                                         pins = "gpio81", "gpio82";
2580                                         function = "qup15";
2581                                 };
2582                         };
2583
2584                         qup_spi0_default: qup-spi0-default {
2585                                 pinmux {
2586                                         pins = "gpio0", "gpio1",
2587                                                "gpio2", "gpio3";
2588                                         function = "qup0";
2589                                 };
2590                         };
2591
2592                         qup_spi1_default: qup-spi1-default {
2593                                 pinmux {
2594                                         pins = "gpio17", "gpio18",
2595                                                "gpio19", "gpio20";
2596                                         function = "qup1";
2597                                 };
2598                         };
2599
2600                         qup_spi2_default: qup-spi2-default {
2601                                 pinmux {
2602                                         pins = "gpio27", "gpio28",
2603                                                "gpio29", "gpio30";
2604                                         function = "qup2";
2605                                 };
2606                         };
2607
2608                         qup_spi3_default: qup-spi3-default {
2609                                 pinmux {
2610                                         pins = "gpio41", "gpio42",
2611                                                "gpio43", "gpio44";
2612                                         function = "qup3";
2613                                 };
2614                         };
2615
2616                         qup_spi4_default: qup-spi4-default {
2617                                 pinmux {
2618                                         pins = "gpio89", "gpio90",
2619                                                "gpio91", "gpio92";
2620                                         function = "qup4";
2621                                 };
2622                         };
2623
2624                         qup_spi5_default: qup-spi5-default {
2625                                 pinmux {
2626                                         pins = "gpio85", "gpio86",
2627                                                "gpio87", "gpio88";
2628                                         function = "qup5";
2629                                 };
2630                         };
2631
2632                         qup_spi6_default: qup-spi6-default {
2633                                 pinmux {
2634                                         pins = "gpio45", "gpio46",
2635                                                "gpio47", "gpio48";
2636                                         function = "qup6";
2637                                 };
2638                         };
2639
2640                         qup_spi7_default: qup-spi7-default {
2641                                 pinmux {
2642                                         pins = "gpio93", "gpio94",
2643                                                "gpio95", "gpio96";
2644                                         function = "qup7";
2645                                 };
2646                         };
2647
2648                         qup_spi8_default: qup-spi8-default {
2649                                 pinmux {
2650                                         pins = "gpio65", "gpio66",
2651                                                "gpio67", "gpio68";
2652                                         function = "qup8";
2653                                 };
2654                         };
2655
2656                         qup_spi9_default: qup-spi9-default {
2657                                 pinmux {
2658                                         pins = "gpio6", "gpio7",
2659                                                "gpio4", "gpio5";
2660                                         function = "qup9";
2661                                 };
2662                         };
2663
2664                         qup_spi10_default: qup-spi10-default {
2665                                 pinmux {
2666                                         pins = "gpio55", "gpio56",
2667                                                "gpio53", "gpio54";
2668                                         function = "qup10";
2669                                 };
2670                         };
2671
2672                         qup_spi11_default: qup-spi11-default {
2673                                 pinmux {
2674                                         pins = "gpio31", "gpio32",
2675                                                "gpio33", "gpio34";
2676                                         function = "qup11";
2677                                 };
2678                         };
2679
2680                         qup_spi12_default: qup-spi12-default {
2681                                 pinmux {
2682                                         pins = "gpio49", "gpio50",
2683                                                "gpio51", "gpio52";
2684                                         function = "qup12";
2685                                 };
2686                         };
2687
2688                         qup_spi13_default: qup-spi13-default {
2689                                 pinmux {
2690                                         pins = "gpio105", "gpio106",
2691                                                "gpio107", "gpio108";
2692                                         function = "qup13";
2693                                 };
2694                         };
2695
2696                         qup_spi14_default: qup-spi14-default {
2697                                 pinmux {
2698                                         pins = "gpio33", "gpio34",
2699                                                "gpio31", "gpio32";
2700                                         function = "qup14";
2701                                 };
2702                         };
2703
2704                         qup_spi15_default: qup-spi15-default {
2705                                 pinmux {
2706                                         pins = "gpio81", "gpio82",
2707                                                "gpio83", "gpio84";
2708                                         function = "qup15";
2709                                 };
2710                         };
2711
2712                         qup_uart0_default: qup-uart0-default {
2713                                 pinmux {
2714                                         pins = "gpio2", "gpio3";
2715                                         function = "qup0";
2716                                 };
2717                         };
2718
2719                         qup_uart1_default: qup-uart1-default {
2720                                 pinmux {
2721                                         pins = "gpio19", "gpio20";
2722                                         function = "qup1";
2723                                 };
2724                         };
2725
2726                         qup_uart2_default: qup-uart2-default {
2727                                 pinmux {
2728                                         pins = "gpio29", "gpio30";
2729                                         function = "qup2";
2730                                 };
2731                         };
2732
2733                         qup_uart3_default: qup-uart3-default {
2734                                 pinmux {
2735                                         pins = "gpio43", "gpio44";
2736                                         function = "qup3";
2737                                 };
2738                         };
2739
2740                         qup_uart4_default: qup-uart4-default {
2741                                 pinmux {
2742                                         pins = "gpio91", "gpio92";
2743                                         function = "qup4";
2744                                 };
2745                         };
2746
2747                         qup_uart5_default: qup-uart5-default {
2748                                 pinmux {
2749                                         pins = "gpio87", "gpio88";
2750                                         function = "qup5";
2751                                 };
2752                         };
2753
2754                         qup_uart6_default: qup-uart6-default {
2755                                 pinmux {
2756                                         pins = "gpio47", "gpio48";
2757                                         function = "qup6";
2758                                 };
2759                         };
2760
2761                         qup_uart7_default: qup-uart7-default {
2762                                 pinmux {
2763                                         pins = "gpio95", "gpio96";
2764                                         function = "qup7";
2765                                 };
2766                         };
2767
2768                         qup_uart8_default: qup-uart8-default {
2769                                 pinmux {
2770                                         pins = "gpio67", "gpio68";
2771                                         function = "qup8";
2772                                 };
2773                         };
2774
2775                         qup_uart9_default: qup-uart9-default {
2776                                 pinmux {
2777                                         pins = "gpio4", "gpio5";
2778                                         function = "qup9";
2779                                 };
2780                         };
2781
2782                         qup_uart10_default: qup-uart10-default {
2783                                 pinmux {
2784                                         pins = "gpio53", "gpio54";
2785                                         function = "qup10";
2786                                 };
2787                         };
2788
2789                         qup_uart11_default: qup-uart11-default {
2790                                 pinmux {
2791                                         pins = "gpio33", "gpio34";
2792                                         function = "qup11";
2793                                 };
2794                         };
2795
2796                         qup_uart12_default: qup-uart12-default {
2797                                 pinmux {
2798                                         pins = "gpio51", "gpio52";
2799                                         function = "qup12";
2800                                 };
2801                         };
2802
2803                         qup_uart13_default: qup-uart13-default {
2804                                 pinmux {
2805                                         pins = "gpio107", "gpio108";
2806                                         function = "qup13";
2807                                 };
2808                         };
2809
2810                         qup_uart14_default: qup-uart14-default {
2811                                 pinmux {
2812                                         pins = "gpio31", "gpio32";
2813                                         function = "qup14";
2814                                 };
2815                         };
2816
2817                         qup_uart15_default: qup-uart15-default {
2818                                 pinmux {
2819                                         pins = "gpio83", "gpio84";
2820                                         function = "qup15";
2821                                 };
2822                         };
2823
2824                         quat_mi2s_sleep: quat_mi2s_sleep {
2825                                 mux {
2826                                         pins = "gpio58", "gpio59";
2827                                         function = "gpio";
2828                                 };
2829
2830                                 config {
2831                                         pins = "gpio58", "gpio59";
2832                                         drive-strength = <2>;
2833                                         bias-pull-down;
2834                                         input-enable;
2835                                 };
2836                         };
2837
2838                         quat_mi2s_active: quat_mi2s_active {
2839                                 mux {
2840                                         pins = "gpio58", "gpio59";
2841                                         function = "qua_mi2s";
2842                                 };
2843
2844                                 config {
2845                                         pins = "gpio58", "gpio59";
2846                                         drive-strength = <8>;
2847                                         bias-disable;
2848                                         output-high;
2849                                 };
2850                         };
2851
2852                         quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
2853                                 mux {
2854                                         pins = "gpio60";
2855                                         function = "gpio";
2856                                 };
2857
2858                                 config {
2859                                         pins = "gpio60";
2860                                         drive-strength = <2>;
2861                                         bias-pull-down;
2862                                         input-enable;
2863                                 };
2864                         };
2865
2866                         quat_mi2s_sd0_active: quat_mi2s_sd0_active {
2867                                 mux {
2868                                         pins = "gpio60";
2869                                         function = "qua_mi2s";
2870                                 };
2871
2872                                 config {
2873                                         pins = "gpio60";
2874                                         drive-strength = <8>;
2875                                         bias-disable;
2876                                 };
2877                         };
2878
2879                         quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
2880                                 mux {
2881                                         pins = "gpio61";
2882                                         function = "gpio";
2883                                 };
2884
2885                                 config {
2886                                         pins = "gpio61";
2887                                         drive-strength = <2>;
2888                                         bias-pull-down;
2889                                         input-enable;
2890                                 };
2891                         };
2892
2893                         quat_mi2s_sd1_active: quat_mi2s_sd1_active {
2894                                 mux {
2895                                         pins = "gpio61";
2896                                         function = "qua_mi2s";
2897                                 };
2898
2899                                 config {
2900                                         pins = "gpio61";
2901                                         drive-strength = <8>;
2902                                         bias-disable;
2903                                 };
2904                         };
2905
2906                         quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
2907                                 mux {
2908                                         pins = "gpio62";
2909                                         function = "gpio";
2910                                 };
2911
2912                                 config {
2913                                         pins = "gpio62";
2914                                         drive-strength = <2>;
2915                                         bias-pull-down;
2916                                         input-enable;
2917                                 };
2918                         };
2919
2920                         quat_mi2s_sd2_active: quat_mi2s_sd2_active {
2921                                 mux {
2922                                         pins = "gpio62";
2923                                         function = "qua_mi2s";
2924                                 };
2925
2926                                 config {
2927                                         pins = "gpio62";
2928                                         drive-strength = <8>;
2929                                         bias-disable;
2930                                 };
2931                         };
2932
2933                         quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
2934                                 mux {
2935                                         pins = "gpio63";
2936                                         function = "gpio";
2937                                 };
2938
2939                                 config {
2940                                         pins = "gpio63";
2941                                         drive-strength = <2>;
2942                                         bias-pull-down;
2943                                         input-enable;
2944                                 };
2945                         };
2946
2947                         quat_mi2s_sd3_active: quat_mi2s_sd3_active {
2948                                 mux {
2949                                         pins = "gpio63";
2950                                         function = "qua_mi2s";
2951                                 };
2952
2953                                 config {
2954                                         pins = "gpio63";
2955                                         drive-strength = <8>;
2956                                         bias-disable;
2957                                 };
2958                         };
2959                 };
2960
2961                 mss_pil: remoteproc@4080000 {
2962                         compatible = "qcom,sdm845-mss-pil";
2963                         reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
2964                         reg-names = "qdsp6", "rmb";
2965
2966                         interrupts-extended =
2967                                 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2968                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2969                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2970                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2971                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2972                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2973                         interrupt-names = "wdog", "fatal", "ready",
2974                                           "handover", "stop-ack",
2975                                           "shutdown-ack";
2976
2977                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2978                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2979                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
2980                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
2981                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2982                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2983                                  <&gcc GCC_PRNG_AHB_CLK>,
2984                                  <&rpmhcc RPMH_CXO_CLK>;
2985                         clock-names = "iface", "bus", "mem", "gpll0_mss",
2986                                       "snoc_axi", "mnoc_axi", "prng", "xo";
2987
2988                         qcom,qmp = <&aoss_qmp>;
2989
2990                         qcom,smem-states = <&modem_smp2p_out 0>;
2991                         qcom,smem-state-names = "stop";
2992
2993                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2994                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
2995                         reset-names = "mss_restart", "pdc_reset";
2996
2997                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2998
2999                         power-domains = <&rpmhpd SDM845_CX>,
3000                                         <&rpmhpd SDM845_MX>,
3001                                         <&rpmhpd SDM845_MSS>;
3002                         power-domain-names = "cx", "mx", "mss";
3003
3004                         status = "disabled";
3005
3006                         mba {
3007                                 memory-region = <&mba_region>;
3008                         };
3009
3010                         mpss {
3011                                 memory-region = <&mpss_region>;
3012                         };
3013
3014                         glink-edge {
3015                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3016                                 label = "modem";
3017                                 qcom,remote-pid = <1>;
3018                                 mboxes = <&apss_shared 12>;
3019                         };
3020                 };
3021
3022                 gpucc: clock-controller@5090000 {
3023                         compatible = "qcom,sdm845-gpucc";
3024                         reg = <0 0x05090000 0 0x9000>;
3025                         #clock-cells = <1>;
3026                         #reset-cells = <1>;
3027                         #power-domain-cells = <1>;
3028                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3029                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3030                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3031                         clock-names = "bi_tcxo",
3032                                       "gcc_gpu_gpll0_clk_src",
3033                                       "gcc_gpu_gpll0_div_clk_src";
3034                 };
3035
3036                 stm@6002000 {
3037                         compatible = "arm,coresight-stm", "arm,primecell";
3038                         reg = <0 0x06002000 0 0x1000>,
3039                               <0 0x16280000 0 0x180000>;
3040                         reg-names = "stm-base", "stm-stimulus-base";
3041
3042                         clocks = <&aoss_qmp>;
3043                         clock-names = "apb_pclk";
3044
3045                         out-ports {
3046                                 port {
3047                                         stm_out: endpoint {
3048                                                 remote-endpoint =
3049                                                   <&funnel0_in7>;
3050                                         };
3051                                 };
3052                         };
3053                 };
3054
3055                 funnel@6041000 {
3056                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3057                         reg = <0 0x06041000 0 0x1000>;
3058
3059                         clocks = <&aoss_qmp>;
3060                         clock-names = "apb_pclk";
3061
3062                         out-ports {
3063                                 port {
3064                                         funnel0_out: endpoint {
3065                                                 remote-endpoint =
3066                                                   <&merge_funnel_in0>;
3067                                         };
3068                                 };
3069                         };
3070
3071                         in-ports {
3072                                 #address-cells = <1>;
3073                                 #size-cells = <0>;
3074
3075                                 port@7 {
3076                                         reg = <7>;
3077                                         funnel0_in7: endpoint {
3078                                                 remote-endpoint = <&stm_out>;
3079                                         };
3080                                 };
3081                         };
3082                 };
3083
3084                 funnel@6043000 {
3085                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3086                         reg = <0 0x06043000 0 0x1000>;
3087
3088                         clocks = <&aoss_qmp>;
3089                         clock-names = "apb_pclk";
3090
3091                         out-ports {
3092                                 port {
3093                                         funnel2_out: endpoint {
3094                                                 remote-endpoint =
3095                                                   <&merge_funnel_in2>;
3096                                         };
3097                                 };
3098                         };
3099
3100                         in-ports {
3101                                 #address-cells = <1>;
3102                                 #size-cells = <0>;
3103
3104                                 port@5 {
3105                                         reg = <5>;
3106                                         funnel2_in5: endpoint {
3107                                                 remote-endpoint =
3108                                                   <&apss_merge_funnel_out>;
3109                                         };
3110                                 };
3111                         };
3112                 };
3113
3114                 funnel@6045000 {
3115                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3116                         reg = <0 0x06045000 0 0x1000>;
3117
3118                         clocks = <&aoss_qmp>;
3119                         clock-names = "apb_pclk";
3120
3121                         out-ports {
3122                                 port {
3123                                         merge_funnel_out: endpoint {
3124                                                 remote-endpoint = <&etf_in>;
3125                                         };
3126                                 };
3127                         };
3128
3129                         in-ports {
3130                                 #address-cells = <1>;
3131                                 #size-cells = <0>;
3132
3133                                 port@0 {
3134                                         reg = <0>;
3135                                         merge_funnel_in0: endpoint {
3136                                                 remote-endpoint =
3137                                                   <&funnel0_out>;
3138                                         };
3139                                 };
3140
3141                                 port@2 {
3142                                         reg = <2>;
3143                                         merge_funnel_in2: endpoint {
3144                                                 remote-endpoint =
3145                                                   <&funnel2_out>;
3146                                         };
3147                                 };
3148                         };
3149                 };
3150
3151                 replicator@6046000 {
3152                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3153                         reg = <0 0x06046000 0 0x1000>;
3154
3155                         clocks = <&aoss_qmp>;
3156                         clock-names = "apb_pclk";
3157
3158                         out-ports {
3159                                 port {
3160                                         replicator_out: endpoint {
3161                                                 remote-endpoint = <&etr_in>;
3162                                         };
3163                                 };
3164                         };
3165
3166                         in-ports {
3167                                 port {
3168                                         replicator_in: endpoint {
3169                                                 remote-endpoint = <&etf_out>;
3170                                         };
3171                                 };
3172                         };
3173                 };
3174
3175                 etf@6047000 {
3176                         compatible = "arm,coresight-tmc", "arm,primecell";
3177                         reg = <0 0x06047000 0 0x1000>;
3178
3179                         clocks = <&aoss_qmp>;
3180                         clock-names = "apb_pclk";
3181
3182                         out-ports {
3183                                 port {
3184                                         etf_out: endpoint {
3185                                                 remote-endpoint =
3186                                                   <&replicator_in>;
3187                                         };
3188                                 };
3189                         };
3190
3191                         in-ports {
3192                                 #address-cells = <1>;
3193                                 #size-cells = <0>;
3194
3195                                 port@1 {
3196                                         reg = <1>;
3197                                         etf_in: endpoint {
3198                                                 remote-endpoint =
3199                                                   <&merge_funnel_out>;
3200                                         };
3201                                 };
3202                         };
3203                 };
3204
3205                 etr@6048000 {
3206                         compatible = "arm,coresight-tmc", "arm,primecell";
3207                         reg = <0 0x06048000 0 0x1000>;
3208
3209                         clocks = <&aoss_qmp>;
3210                         clock-names = "apb_pclk";
3211                         arm,scatter-gather;
3212
3213                         in-ports {
3214                                 port {
3215                                         etr_in: endpoint {
3216                                                 remote-endpoint =
3217                                                   <&replicator_out>;
3218                                         };
3219                                 };
3220                         };
3221                 };
3222
3223                 etm@7040000 {
3224                         compatible = "arm,coresight-etm4x", "arm,primecell";
3225                         reg = <0 0x07040000 0 0x1000>;
3226
3227                         cpu = <&CPU0>;
3228
3229                         clocks = <&aoss_qmp>;
3230                         clock-names = "apb_pclk";
3231                         arm,coresight-loses-context-with-cpu;
3232
3233                         out-ports {
3234                                 port {
3235                                         etm0_out: endpoint {
3236                                                 remote-endpoint =
3237                                                   <&apss_funnel_in0>;
3238                                         };
3239                                 };
3240                         };
3241                 };
3242
3243                 etm@7140000 {
3244                         compatible = "arm,coresight-etm4x", "arm,primecell";
3245                         reg = <0 0x07140000 0 0x1000>;
3246
3247                         cpu = <&CPU1>;
3248
3249                         clocks = <&aoss_qmp>;
3250                         clock-names = "apb_pclk";
3251                         arm,coresight-loses-context-with-cpu;
3252
3253                         out-ports {
3254                                 port {
3255                                         etm1_out: endpoint {
3256                                                 remote-endpoint =
3257                                                   <&apss_funnel_in1>;
3258                                         };
3259                                 };
3260                         };
3261                 };
3262
3263                 etm@7240000 {
3264                         compatible = "arm,coresight-etm4x", "arm,primecell";
3265                         reg = <0 0x07240000 0 0x1000>;
3266
3267                         cpu = <&CPU2>;
3268
3269                         clocks = <&aoss_qmp>;
3270                         clock-names = "apb_pclk";
3271                         arm,coresight-loses-context-with-cpu;
3272
3273                         out-ports {
3274                                 port {
3275                                         etm2_out: endpoint {
3276                                                 remote-endpoint =
3277                                                   <&apss_funnel_in2>;
3278                                         };
3279                                 };
3280                         };
3281                 };
3282
3283                 etm@7340000 {
3284                         compatible = "arm,coresight-etm4x", "arm,primecell";
3285                         reg = <0 0x07340000 0 0x1000>;
3286
3287                         cpu = <&CPU3>;
3288
3289                         clocks = <&aoss_qmp>;
3290                         clock-names = "apb_pclk";
3291                         arm,coresight-loses-context-with-cpu;
3292
3293                         out-ports {
3294                                 port {
3295                                         etm3_out: endpoint {
3296                                                 remote-endpoint =
3297                                                   <&apss_funnel_in3>;
3298                                         };
3299                                 };
3300                         };
3301                 };
3302
3303                 etm@7440000 {
3304                         compatible = "arm,coresight-etm4x", "arm,primecell";
3305                         reg = <0 0x07440000 0 0x1000>;
3306
3307                         cpu = <&CPU4>;
3308
3309                         clocks = <&aoss_qmp>;
3310                         clock-names = "apb_pclk";
3311                         arm,coresight-loses-context-with-cpu;
3312
3313                         out-ports {
3314                                 port {
3315                                         etm4_out: endpoint {
3316                                                 remote-endpoint =
3317                                                   <&apss_funnel_in4>;
3318                                         };
3319                                 };
3320                         };
3321                 };
3322
3323                 etm@7540000 {
3324                         compatible = "arm,coresight-etm4x", "arm,primecell";
3325                         reg = <0 0x07540000 0 0x1000>;
3326
3327                         cpu = <&CPU5>;
3328
3329                         clocks = <&aoss_qmp>;
3330                         clock-names = "apb_pclk";
3331                         arm,coresight-loses-context-with-cpu;
3332
3333                         out-ports {
3334                                 port {
3335                                         etm5_out: endpoint {
3336                                                 remote-endpoint =
3337                                                   <&apss_funnel_in5>;
3338                                         };
3339                                 };
3340                         };
3341                 };
3342
3343                 etm@7640000 {
3344                         compatible = "arm,coresight-etm4x", "arm,primecell";
3345                         reg = <0 0x07640000 0 0x1000>;
3346
3347                         cpu = <&CPU6>;
3348
3349                         clocks = <&aoss_qmp>;
3350                         clock-names = "apb_pclk";
3351                         arm,coresight-loses-context-with-cpu;
3352
3353                         out-ports {
3354                                 port {
3355                                         etm6_out: endpoint {
3356                                                 remote-endpoint =
3357                                                   <&apss_funnel_in6>;
3358                                         };
3359                                 };
3360                         };
3361                 };
3362
3363                 etm@7740000 {
3364                         compatible = "arm,coresight-etm4x", "arm,primecell";
3365                         reg = <0 0x07740000 0 0x1000>;
3366
3367                         cpu = <&CPU7>;
3368
3369                         clocks = <&aoss_qmp>;
3370                         clock-names = "apb_pclk";
3371                         arm,coresight-loses-context-with-cpu;
3372
3373                         out-ports {
3374                                 port {
3375                                         etm7_out: endpoint {
3376                                                 remote-endpoint =
3377                                                   <&apss_funnel_in7>;
3378                                         };
3379                                 };
3380                         };
3381                 };
3382
3383                 funnel@7800000 { /* APSS Funnel */
3384                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3385                         reg = <0 0x07800000 0 0x1000>;
3386
3387                         clocks = <&aoss_qmp>;
3388                         clock-names = "apb_pclk";
3389
3390                         out-ports {
3391                                 port {
3392                                         apss_funnel_out: endpoint {
3393                                                 remote-endpoint =
3394                                                   <&apss_merge_funnel_in>;
3395                                         };
3396                                 };
3397                         };
3398
3399                         in-ports {
3400                                 #address-cells = <1>;
3401                                 #size-cells = <0>;
3402
3403                                 port@0 {
3404                                         reg = <0>;
3405                                         apss_funnel_in0: endpoint {
3406                                                 remote-endpoint =
3407                                                   <&etm0_out>;
3408                                         };
3409                                 };
3410
3411                                 port@1 {
3412                                         reg = <1>;
3413                                         apss_funnel_in1: endpoint {
3414                                                 remote-endpoint =
3415                                                   <&etm1_out>;
3416                                         };
3417                                 };
3418
3419                                 port@2 {
3420                                         reg = <2>;
3421                                         apss_funnel_in2: endpoint {
3422                                                 remote-endpoint =
3423                                                   <&etm2_out>;
3424                                         };
3425                                 };
3426
3427                                 port@3 {
3428                                         reg = <3>;
3429                                         apss_funnel_in3: endpoint {
3430                                                 remote-endpoint =
3431                                                   <&etm3_out>;
3432                                         };
3433                                 };
3434
3435                                 port@4 {
3436                                         reg = <4>;
3437                                         apss_funnel_in4: endpoint {
3438                                                 remote-endpoint =
3439                                                   <&etm4_out>;
3440                                         };
3441                                 };
3442
3443                                 port@5 {
3444                                         reg = <5>;
3445                                         apss_funnel_in5: endpoint {
3446                                                 remote-endpoint =
3447                                                   <&etm5_out>;
3448                                         };
3449                                 };
3450
3451                                 port@6 {
3452                                         reg = <6>;
3453                                         apss_funnel_in6: endpoint {
3454                                                 remote-endpoint =
3455                                                   <&etm6_out>;
3456                                         };
3457                                 };
3458
3459                                 port@7 {
3460                                         reg = <7>;
3461                                         apss_funnel_in7: endpoint {
3462                                                 remote-endpoint =
3463                                                   <&etm7_out>;
3464                                         };
3465                                 };
3466                         };
3467                 };
3468
3469                 funnel@7810000 {
3470                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3471                         reg = <0 0x07810000 0 0x1000>;
3472
3473                         clocks = <&aoss_qmp>;
3474                         clock-names = "apb_pclk";
3475
3476                         out-ports {
3477                                 port {
3478                                         apss_merge_funnel_out: endpoint {
3479                                                 remote-endpoint =
3480                                                   <&funnel2_in5>;
3481                                         };
3482                                 };
3483                         };
3484
3485                         in-ports {
3486                                 port {
3487                                         apss_merge_funnel_in: endpoint {
3488                                                 remote-endpoint =
3489                                                   <&apss_funnel_out>;
3490                                         };
3491                                 };
3492                         };
3493                 };
3494
3495                 sdhc_2: sdhci@8804000 {
3496                         compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3497                         reg = <0 0x08804000 0 0x1000>;
3498
3499                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3500                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3501                         interrupt-names = "hc_irq", "pwr_irq";
3502
3503                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3504                                  <&gcc GCC_SDCC2_APPS_CLK>,
3505                                  <&rpmhcc RPMH_CXO_CLK>;
3506                         clock-names = "iface", "core", "xo";
3507                         iommus = <&apps_smmu 0xa0 0xf>;
3508                         power-domains = <&rpmhpd SDM845_CX>;
3509                         operating-points-v2 = <&sdhc2_opp_table>;
3510
3511                         status = "disabled";
3512
3513                         sdhc2_opp_table: sdhc2-opp-table {
3514                                 compatible = "operating-points-v2";
3515
3516                                 opp-9600000 {
3517                                         opp-hz = /bits/ 64 <9600000>;
3518                                         required-opps = <&rpmhpd_opp_min_svs>;
3519                                 };
3520
3521                                 opp-19200000 {
3522                                         opp-hz = /bits/ 64 <19200000>;
3523                                         required-opps = <&rpmhpd_opp_low_svs>;
3524                                 };
3525
3526                                 opp-100000000 {
3527                                         opp-hz = /bits/ 64 <100000000>;
3528                                         required-opps = <&rpmhpd_opp_svs>;
3529                                 };
3530
3531                                 opp-201500000 {
3532                                         opp-hz = /bits/ 64 <201500000>;
3533                                         required-opps = <&rpmhpd_opp_svs_l1>;
3534                                 };
3535                         };
3536                 };
3537
3538                 qspi_opp_table: qspi-opp-table {
3539                         compatible = "operating-points-v2";
3540
3541                         opp-19200000 {
3542                                 opp-hz = /bits/ 64 <19200000>;
3543                                 required-opps = <&rpmhpd_opp_min_svs>;
3544                         };
3545
3546                         opp-100000000 {
3547                                 opp-hz = /bits/ 64 <100000000>;
3548                                 required-opps = <&rpmhpd_opp_low_svs>;
3549                         };
3550
3551                         opp-150000000 {
3552                                 opp-hz = /bits/ 64 <150000000>;
3553                                 required-opps = <&rpmhpd_opp_svs>;
3554                         };
3555
3556                         opp-300000000 {
3557                                 opp-hz = /bits/ 64 <300000000>;
3558                                 required-opps = <&rpmhpd_opp_nom>;
3559                         };
3560                 };
3561
3562                 qspi: spi@88df000 {
3563                         compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3564                         reg = <0 0x088df000 0 0x600>;
3565                         #address-cells = <1>;
3566                         #size-cells = <0>;
3567                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3568                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3569                                  <&gcc GCC_QSPI_CORE_CLK>;
3570                         clock-names = "iface", "core";
3571                         power-domains = <&rpmhpd SDM845_CX>;
3572                         operating-points-v2 = <&qspi_opp_table>;
3573                         status = "disabled";
3574                 };
3575
3576                 slim: slim@171c0000 {
3577                         compatible = "qcom,slim-ngd-v2.1.0";
3578                         reg = <0 0x171c0000 0 0x2c000>;
3579                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3580
3581                         qcom,apps-ch-pipes = <0x780000>;
3582                         qcom,ea-pc = <0x270>;
3583                         status = "okay";
3584                         dmas =  <&slimbam 3>, <&slimbam 4>,
3585                                 <&slimbam 5>, <&slimbam 6>;
3586                         dma-names = "rx", "tx", "tx2", "rx2";
3587
3588                         iommus = <&apps_smmu 0x1806 0x0>;
3589                         #address-cells = <1>;
3590                         #size-cells = <0>;
3591
3592                         ngd@1 {
3593                                 reg = <1>;
3594                                 #address-cells = <2>;
3595                                 #size-cells = <0>;
3596
3597                                 wcd9340_ifd: ifd@0{
3598                                         compatible = "slim217,250";
3599                                         reg  = <0 0>;
3600                                 };
3601
3602                                 wcd9340: codec@1{
3603                                         compatible = "slim217,250";
3604                                         reg  = <1 0>;
3605                                         slim-ifc-dev  = <&wcd9340_ifd>;
3606
3607                                         #sound-dai-cells = <1>;
3608
3609                                         interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3610                                         interrupt-controller;
3611                                         #interrupt-cells = <1>;
3612
3613                                         #clock-cells = <0>;
3614                                         clock-frequency = <9600000>;
3615                                         clock-output-names = "mclk";
3616                                         qcom,micbias1-millivolt = <1800>;
3617                                         qcom,micbias2-millivolt = <1800>;
3618                                         qcom,micbias3-millivolt = <1800>;
3619                                         qcom,micbias4-millivolt = <1800>;
3620
3621                                         #address-cells = <1>;
3622                                         #size-cells = <1>;
3623
3624                                         wcdgpio: gpio-controller@42 {
3625                                                 compatible = "qcom,wcd9340-gpio";
3626                                                 gpio-controller;
3627                                                 #gpio-cells = <2>;
3628                                                 reg = <0x42 0x2>;
3629                                         };
3630
3631                                         swm: swm@c85 {
3632                                                 compatible = "qcom,soundwire-v1.3.0";
3633                                                 reg = <0xc85 0x40>;
3634                                                 interrupts-extended = <&wcd9340 20>;
3635
3636                                                 qcom,dout-ports = <6>;
3637                                                 qcom,din-ports  = <2>;
3638                                                 qcom,ports-sinterval-low =/bits/ 8  <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3639                                                 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3640                                                 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3641
3642                                                 #sound-dai-cells = <1>;
3643                                                 clocks = <&wcd9340>;
3644                                                 clock-names = "iface";
3645                                                 #address-cells = <2>;
3646                                                 #size-cells = <0>;
3647
3648
3649                                         };
3650                                 };
3651                         };
3652                 };
3653
3654                 lmh_cluster1: lmh@17d70800 {
3655                         compatible = "qcom,sdm845-lmh";
3656                         reg = <0 0x17d70800 0 0x400>;
3657                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3658                         cpus = <&CPU4>;
3659                         qcom,lmh-temp-arm-millicelsius = <65000>;
3660                         qcom,lmh-temp-low-millicelsius = <94500>;
3661                         qcom,lmh-temp-high-millicelsius = <95000>;
3662                         interrupt-controller;
3663                         #interrupt-cells = <1>;
3664                 };
3665
3666                 lmh_cluster0: lmh@17d78800 {
3667                         compatible = "qcom,sdm845-lmh";
3668                         reg = <0 0x17d78800 0 0x400>;
3669                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3670                         cpus = <&CPU0>;
3671                         qcom,lmh-temp-arm-millicelsius = <65000>;
3672                         qcom,lmh-temp-low-millicelsius = <94500>;
3673                         qcom,lmh-temp-high-millicelsius = <95000>;
3674                         interrupt-controller;
3675                         #interrupt-cells = <1>;
3676                 };
3677
3678                 sound: sound {
3679                 };
3680
3681                 usb_1_hsphy: phy@88e2000 {
3682                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3683                         reg = <0 0x088e2000 0 0x400>;
3684                         status = "disabled";
3685                         #phy-cells = <0>;
3686
3687                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3688                                  <&rpmhcc RPMH_CXO_CLK>;
3689                         clock-names = "cfg_ahb", "ref";
3690
3691                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3692
3693                         nvmem-cells = <&qusb2p_hstx_trim>;
3694                 };
3695
3696                 usb_2_hsphy: phy@88e3000 {
3697                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3698                         reg = <0 0x088e3000 0 0x400>;
3699                         status = "disabled";
3700                         #phy-cells = <0>;
3701
3702                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3703                                  <&rpmhcc RPMH_CXO_CLK>;
3704                         clock-names = "cfg_ahb", "ref";
3705
3706                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3707
3708                         nvmem-cells = <&qusb2s_hstx_trim>;
3709                 };
3710
3711                 usb_1_qmpphy: phy@88e9000 {
3712                         compatible = "qcom,sdm845-qmp-usb3-phy";
3713                         reg = <0 0x088e9000 0 0x18c>,
3714                               <0 0x088e8000 0 0x10>;
3715                         status = "disabled";
3716                         #address-cells = <2>;
3717                         #size-cells = <2>;
3718                         ranges;
3719
3720                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3721                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3722                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3723                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3724                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3725
3726                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3727                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3728                         reset-names = "phy", "common";
3729
3730                         usb_1_ssphy: phy@88e9200 {
3731                                 reg = <0 0x088e9200 0 0x128>,
3732                                       <0 0x088e9400 0 0x200>,
3733                                       <0 0x088e9c00 0 0x218>,
3734                                       <0 0x088e9600 0 0x128>,
3735                                       <0 0x088e9800 0 0x200>,
3736                                       <0 0x088e9a00 0 0x100>;
3737                                 #clock-cells = <0>;
3738                                 #phy-cells = <0>;
3739                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3740                                 clock-names = "pipe0";
3741                                 clock-output-names = "usb3_phy_pipe_clk_src";
3742                         };
3743                 };
3744
3745                 usb_2_qmpphy: phy@88eb000 {
3746                         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3747                         reg = <0 0x088eb000 0 0x18c>;
3748                         status = "disabled";
3749                         #address-cells = <2>;
3750                         #size-cells = <2>;
3751                         ranges;
3752
3753                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3754                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3755                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3756                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3757                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3758
3759                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3760                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3761                         reset-names = "phy", "common";
3762
3763                         usb_2_ssphy: phy@88eb200 {
3764                                 reg = <0 0x088eb200 0 0x128>,
3765                                       <0 0x088eb400 0 0x1fc>,
3766                                       <0 0x088eb800 0 0x218>,
3767                                       <0 0x088eb600 0 0x70>;
3768                                 #clock-cells = <0>;
3769                                 #phy-cells = <0>;
3770                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3771                                 clock-names = "pipe0";
3772                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3773                         };
3774                 };
3775
3776                 usb_1: usb@a6f8800 {
3777                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3778                         reg = <0 0x0a6f8800 0 0x400>;
3779                         status = "disabled";
3780                         #address-cells = <2>;
3781                         #size-cells = <2>;
3782                         ranges;
3783                         dma-ranges;
3784
3785                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3786                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3787                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3788                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3789                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
3790                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3791                                       "sleep";
3792
3793                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3794                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3795                         assigned-clock-rates = <19200000>, <150000000>;
3796
3797                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3798                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3799                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3800                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3801                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3802                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3803
3804                         power-domains = <&gcc USB30_PRIM_GDSC>;
3805
3806                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3807
3808                         interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
3809                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3810                         interconnect-names = "usb-ddr", "apps-usb";
3811
3812                         usb_1_dwc3: dwc3@a600000 {
3813                                 compatible = "snps,dwc3";
3814                                 reg = <0 0x0a600000 0 0xcd00>;
3815                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3816                                 iommus = <&apps_smmu 0x740 0>;
3817                                 snps,dis_u2_susphy_quirk;
3818                                 snps,dis_enblslpm_quirk;
3819                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3820                                 phy-names = "usb2-phy", "usb3-phy";
3821                         };
3822                 };
3823
3824                 usb_2: usb@a8f8800 {
3825                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
3826                         reg = <0 0x0a8f8800 0 0x400>;
3827                         status = "disabled";
3828                         #address-cells = <2>;
3829                         #size-cells = <2>;
3830                         ranges;
3831                         dma-ranges;
3832
3833                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3834                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3835                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3836                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3837                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>;
3838                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3839                                       "sleep";
3840
3841                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3842                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3843                         assigned-clock-rates = <19200000>, <150000000>;
3844
3845                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3846                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3847                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3848                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3849                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3850                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3851
3852                         power-domains = <&gcc USB30_SEC_GDSC>;
3853
3854                         resets = <&gcc GCC_USB30_SEC_BCR>;
3855
3856                         interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
3857                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3858                         interconnect-names = "usb-ddr", "apps-usb";
3859
3860                         usb_2_dwc3: dwc3@a800000 {
3861                                 compatible = "snps,dwc3";
3862                                 reg = <0 0x0a800000 0 0xcd00>;
3863                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3864                                 iommus = <&apps_smmu 0x760 0>;
3865                                 snps,dis_u2_susphy_quirk;
3866                                 snps,dis_enblslpm_quirk;
3867                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3868                                 phy-names = "usb2-phy", "usb3-phy";
3869                         };
3870                 };
3871
3872                 venus: video-codec@aa00000 {
3873                         compatible = "qcom,sdm845-venus-v2";
3874                         reg = <0 0x0aa00000 0 0xff000>;
3875                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3876                         power-domains = <&videocc VENUS_GDSC>,
3877                                         <&videocc VCODEC0_GDSC>,
3878                                         <&videocc VCODEC1_GDSC>,
3879                                         <&rpmhpd SDM845_CX>;
3880                         power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
3881                         operating-points-v2 = <&venus_opp_table>;
3882                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3883                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3884                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3885                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3886                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
3887                                  <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
3888                                  <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
3889                         clock-names = "core", "iface", "bus",
3890                                       "vcodec0_core", "vcodec0_bus",
3891                                       "vcodec1_core", "vcodec1_bus";
3892                         iommus = <&apps_smmu 0x10a0 0x8>,
3893                                  <&apps_smmu 0x10b0 0x0>;
3894                         memory-region = <&venus_mem>;
3895                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
3896                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3897                         interconnect-names = "video-mem", "cpu-cfg";
3898
3899                         status = "disabled";
3900
3901                         video-core0 {
3902                                 compatible = "venus-decoder";
3903                         };
3904
3905                         video-core1 {
3906                                 compatible = "venus-encoder";
3907                         };
3908
3909                         venus_opp_table: venus-opp-table {
3910                                 compatible = "operating-points-v2";
3911
3912                                 opp-100000000 {
3913                                         opp-hz = /bits/ 64 <100000000>;
3914                                         required-opps = <&rpmhpd_opp_min_svs>;
3915                                 };
3916
3917                                 opp-200000000 {
3918                                         opp-hz = /bits/ 64 <200000000>;
3919                                         required-opps = <&rpmhpd_opp_low_svs>;
3920                                 };
3921
3922                                 opp-320000000 {
3923                                         opp-hz = /bits/ 64 <320000000>;
3924                                         required-opps = <&rpmhpd_opp_svs>;
3925                                 };
3926
3927                                 opp-380000000 {
3928                                         opp-hz = /bits/ 64 <380000000>;
3929                                         required-opps = <&rpmhpd_opp_svs_l1>;
3930                                 };
3931
3932                                 opp-444000000 {
3933                                         opp-hz = /bits/ 64 <444000000>;
3934                                         required-opps = <&rpmhpd_opp_nom>;
3935                                 };
3936
3937                                 opp-533000097 {
3938                                         opp-hz = /bits/ 64 <533000097>;
3939                                         required-opps = <&rpmhpd_opp_turbo>;
3940                                 };
3941                         };
3942                 };
3943
3944                 videocc: clock-controller@ab00000 {
3945                         compatible = "qcom,sdm845-videocc";
3946                         reg = <0 0x0ab00000 0 0x10000>;
3947                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3948                         clock-names = "bi_tcxo";
3949                         #clock-cells = <1>;
3950                         #power-domain-cells = <1>;
3951                         #reset-cells = <1>;
3952                 };
3953
3954                 camss: camss@a00000 {
3955                         compatible = "qcom,sdm845-camss";
3956
3957                         reg = <0 0xacb3000 0 0x1000>,
3958                                 <0 0xacba000 0 0x1000>,
3959                                 <0 0xacc8000 0 0x1000>,
3960                                 <0 0xac65000 0 0x1000>,
3961                                 <0 0xac66000 0 0x1000>,
3962                                 <0 0xac67000 0 0x1000>,
3963                                 <0 0xac68000 0 0x1000>,
3964                                 <0 0xacaf000 0 0x4000>,
3965                                 <0 0xacb6000 0 0x4000>,
3966                                 <0 0xacc4000 0 0x4000>;
3967                         reg-names = "csid0",
3968                                 "csid1",
3969                                 "csid2",
3970                                 "csiphy0",
3971                                 "csiphy1",
3972                                 "csiphy2",
3973                                 "csiphy3",
3974                                 "vfe0",
3975                                 "vfe1",
3976                                 "vfe_lite";
3977
3978                         interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3979                                 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3980                                 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3981                                 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3982                                 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3983                                 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3984                                 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3985                                 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3986                                 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3987                                 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
3988                         interrupt-names = "csid0",
3989                                 "csid1",
3990                                 "csid2",
3991                                 "csiphy0",
3992                                 "csiphy1",
3993                                 "csiphy2",
3994                                 "csiphy3",
3995                                 "vfe0",
3996                                 "vfe1",
3997                                 "vfe_lite";
3998
3999                         power-domains = <&clock_camcc IFE_0_GDSC>,
4000                                 <&clock_camcc IFE_1_GDSC>,
4001                                 <&clock_camcc TITAN_TOP_GDSC>;
4002
4003                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4004                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4005                                 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4006                                 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4007                                 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4008                                 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4009                                 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4010                                 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4011                                 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4012                                 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4013                                 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4014                                 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4015                                 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4016                                 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4017                                 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4018                                 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4019                                 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4020                                 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4021                                 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4022                                 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4023                                 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4024                                 <&gcc GCC_CAMERA_AHB_CLK>,
4025                                 <&gcc GCC_CAMERA_AXI_CLK>,
4026                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4027                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4028                                 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4029                                 <&clock_camcc CAM_CC_IFE_0_CLK>,
4030                                 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4031                                 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4032                                 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4033                                 <&clock_camcc CAM_CC_IFE_1_CLK>,
4034                                 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4035                                 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4036                                 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4037                                 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4038                                 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4039                         clock-names = "camnoc_axi",
4040                                 "cpas_ahb",
4041                                 "cphy_rx_src",
4042                                 "csi0",
4043                                 "csi0_src",
4044                                 "csi1",
4045                                 "csi1_src",
4046                                 "csi2",
4047                                 "csi2_src",
4048                                 "csiphy0",
4049                                 "csiphy0_timer",
4050                                 "csiphy0_timer_src",
4051                                 "csiphy1",
4052                                 "csiphy1_timer",
4053                                 "csiphy1_timer_src",
4054                                 "csiphy2",
4055                                 "csiphy2_timer",
4056                                 "csiphy2_timer_src",
4057                                 "csiphy3",
4058                                 "csiphy3_timer",
4059                                 "csiphy3_timer_src",
4060                                 "gcc_camera_ahb",
4061                                 "gcc_camera_axi",
4062                                 "slow_ahb_src",
4063                                 "soc_ahb",
4064                                 "vfe0_axi",
4065                                 "vfe0",
4066                                 "vfe0_cphy_rx",
4067                                 "vfe0_src",
4068                                 "vfe1_axi",
4069                                 "vfe1",
4070                                 "vfe1_cphy_rx",
4071                                 "vfe1_src",
4072                                 "vfe_lite",
4073                                 "vfe_lite_cphy_rx",
4074                                 "vfe_lite_src";
4075
4076                         iommus = <&apps_smmu 0x0808 0x0>,
4077                                  <&apps_smmu 0x0810 0x8>,
4078                                  <&apps_smmu 0x0c08 0x0>,
4079                                  <&apps_smmu 0x0c10 0x8>;
4080
4081                         status = "disabled";
4082
4083                         ports {
4084                                 #address-cells = <1>;
4085                                 #size-cells = <0>;
4086                         };
4087                 };
4088
4089                 cci: cci@ac4a000 {
4090                         compatible = "qcom,sdm845-cci";
4091                         #address-cells = <1>;
4092                         #size-cells = <0>;
4093
4094                         reg = <0 0x0ac4a000 0 0x4000>;
4095                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4096                         power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4097
4098                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4099                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4100                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4101                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4102                                 <&clock_camcc CAM_CC_CCI_CLK>,
4103                                 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4104                         clock-names = "camnoc_axi",
4105                                 "soc_ahb",
4106                                 "slow_ahb_src",
4107                                 "cpas_ahb",
4108                                 "cci",
4109                                 "cci_src";
4110
4111                         assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4112                                 <&clock_camcc CAM_CC_CCI_CLK>;
4113                         assigned-clock-rates = <80000000>, <37500000>;
4114
4115                         pinctrl-names = "default", "sleep";
4116                         pinctrl-0 = <&cci0_default &cci1_default>;
4117                         pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4118
4119                         status = "disabled";
4120
4121                         cci_i2c0: i2c-bus@0 {
4122                                 reg = <0>;
4123                                 clock-frequency = <1000000>;
4124                                 #address-cells = <1>;
4125                                 #size-cells = <0>;
4126                         };
4127
4128                         cci_i2c1: i2c-bus@1 {
4129                                 reg = <1>;
4130                                 clock-frequency = <1000000>;
4131                                 #address-cells = <1>;
4132                                 #size-cells = <0>;
4133                         };
4134                 };
4135
4136                 clock_camcc: clock-controller@ad00000 {
4137                         compatible = "qcom,sdm845-camcc";
4138                         reg = <0 0x0ad00000 0 0x10000>;
4139                         #clock-cells = <1>;
4140                         #reset-cells = <1>;
4141                         #power-domain-cells = <1>;
4142                 };
4143
4144                 dsi_opp_table: dsi-opp-table {
4145                         compatible = "operating-points-v2";
4146
4147                         opp-19200000 {
4148                                 opp-hz = /bits/ 64 <19200000>;
4149                                 required-opps = <&rpmhpd_opp_min_svs>;
4150                         };
4151
4152                         opp-180000000 {
4153                                 opp-hz = /bits/ 64 <180000000>;
4154                                 required-opps = <&rpmhpd_opp_low_svs>;
4155                         };
4156
4157                         opp-275000000 {
4158                                 opp-hz = /bits/ 64 <275000000>;
4159                                 required-opps = <&rpmhpd_opp_svs>;
4160                         };
4161
4162                         opp-328580000 {
4163                                 opp-hz = /bits/ 64 <328580000>;
4164                                 required-opps = <&rpmhpd_opp_svs_l1>;
4165                         };
4166
4167                         opp-358000000 {
4168                                 opp-hz = /bits/ 64 <358000000>;
4169                                 required-opps = <&rpmhpd_opp_nom>;
4170                         };
4171                 };
4172
4173                 mdss: mdss@ae00000 {
4174                         compatible = "qcom,sdm845-mdss";
4175                         reg = <0 0x0ae00000 0 0x1000>;
4176                         reg-names = "mdss";
4177
4178                         power-domains = <&dispcc MDSS_GDSC>;
4179
4180                         clocks = <&gcc GCC_DISP_AHB_CLK>,
4181                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
4182                         clock-names = "iface", "core";
4183
4184                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
4185                         assigned-clock-rates = <300000000>;
4186
4187                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4188                         interrupt-controller;
4189                         #interrupt-cells = <1>;
4190
4191                         interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4192                                         <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4193                         interconnect-names = "mdp0-mem", "mdp1-mem";
4194
4195                         iommus = <&apps_smmu 0x880 0x8>,
4196                                  <&apps_smmu 0xc80 0x8>;
4197
4198                         status = "disabled";
4199
4200                         #address-cells = <2>;
4201                         #size-cells = <2>;
4202                         ranges;
4203
4204                         mdss_mdp: mdp@ae01000 {
4205                                 compatible = "qcom,sdm845-dpu";
4206                                 reg = <0 0x0ae01000 0 0x8f000>,
4207                                       <0 0x0aeb0000 0 0x2008>;
4208                                 reg-names = "mdp", "vbif";
4209
4210                                 clocks = <&gcc GCC_DISP_AXI_CLK>,
4211                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4212                                          <&dispcc DISP_CC_MDSS_AXI_CLK>,
4213                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
4214                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4215                                 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4216
4217                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4218                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4219                                 assigned-clock-rates = <300000000>,
4220                                                        <19200000>;
4221                                 operating-points-v2 = <&mdp_opp_table>;
4222                                 power-domains = <&rpmhpd SDM845_CX>;
4223
4224                                 interrupt-parent = <&mdss>;
4225                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4226
4227                                 ports {
4228                                         #address-cells = <1>;
4229                                         #size-cells = <0>;
4230
4231                                         port@0 {
4232                                                 reg = <0>;
4233                                                 dpu_intf1_out: endpoint {
4234                                                         remote-endpoint = <&dsi0_in>;
4235                                                 };
4236                                         };
4237
4238                                         port@1 {
4239                                                 reg = <1>;
4240                                                 dpu_intf2_out: endpoint {
4241                                                         remote-endpoint = <&dsi1_in>;
4242                                                 };
4243                                         };
4244                                 };
4245
4246                                 mdp_opp_table: mdp-opp-table {
4247                                         compatible = "operating-points-v2";
4248
4249                                         opp-19200000 {
4250                                                 opp-hz = /bits/ 64 <19200000>;
4251                                                 required-opps = <&rpmhpd_opp_min_svs>;
4252                                         };
4253
4254                                         opp-171428571 {
4255                                                 opp-hz = /bits/ 64 <171428571>;
4256                                                 required-opps = <&rpmhpd_opp_low_svs>;
4257                                         };
4258
4259                                         opp-344000000 {
4260                                                 opp-hz = /bits/ 64 <344000000>;
4261                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4262                                         };
4263
4264                                         opp-430000000 {
4265                                                 opp-hz = /bits/ 64 <430000000>;
4266                                                 required-opps = <&rpmhpd_opp_nom>;
4267                                         };
4268                                 };
4269                         };
4270
4271                         dsi0: dsi@ae94000 {
4272                                 compatible = "qcom,mdss-dsi-ctrl";
4273                                 reg = <0 0x0ae94000 0 0x400>;
4274                                 reg-names = "dsi_ctrl";
4275
4276                                 interrupt-parent = <&mdss>;
4277                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4278
4279                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4280                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4281                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4282                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4283                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4284                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4285                                 clock-names = "byte",
4286                                               "byte_intf",
4287                                               "pixel",
4288                                               "core",
4289                                               "iface",
4290                                               "bus";
4291                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4292                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4293
4294                                 operating-points-v2 = <&dsi_opp_table>;
4295                                 power-domains = <&rpmhpd SDM845_CX>;
4296
4297                                 phys = <&dsi0_phy>;
4298                                 phy-names = "dsi";
4299
4300                                 status = "disabled";
4301
4302                                 #address-cells = <1>;
4303                                 #size-cells = <0>;
4304
4305                                 ports {
4306                                         #address-cells = <1>;
4307                                         #size-cells = <0>;
4308
4309                                         port@0 {
4310                                                 reg = <0>;
4311                                                 dsi0_in: endpoint {
4312                                                         remote-endpoint = <&dpu_intf1_out>;
4313                                                 };
4314                                         };
4315
4316                                         port@1 {
4317                                                 reg = <1>;
4318                                                 dsi0_out: endpoint {
4319                                                 };
4320                                         };
4321                                 };
4322                         };
4323
4324                         dsi0_phy: dsi-phy@ae94400 {
4325                                 compatible = "qcom,dsi-phy-10nm";
4326                                 reg = <0 0x0ae94400 0 0x200>,
4327                                       <0 0x0ae94600 0 0x280>,
4328                                       <0 0x0ae94a00 0 0x1e0>;
4329                                 reg-names = "dsi_phy",
4330                                             "dsi_phy_lane",
4331                                             "dsi_pll";
4332
4333                                 #clock-cells = <1>;
4334                                 #phy-cells = <0>;
4335
4336                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4337                                          <&rpmhcc RPMH_CXO_CLK>;
4338                                 clock-names = "iface", "ref";
4339
4340                                 status = "disabled";
4341                         };
4342
4343                         dsi1: dsi@ae96000 {
4344                                 compatible = "qcom,mdss-dsi-ctrl";
4345                                 reg = <0 0x0ae96000 0 0x400>;
4346                                 reg-names = "dsi_ctrl";
4347
4348                                 interrupt-parent = <&mdss>;
4349                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4350
4351                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4352                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4353                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4354                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4355                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4356                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4357                                 clock-names = "byte",
4358                                               "byte_intf",
4359                                               "pixel",
4360                                               "core",
4361                                               "iface",
4362                                               "bus";
4363                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4364                                 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4365
4366                                 operating-points-v2 = <&dsi_opp_table>;
4367                                 power-domains = <&rpmhpd SDM845_CX>;
4368
4369                                 phys = <&dsi1_phy>;
4370                                 phy-names = "dsi";
4371
4372                                 status = "disabled";
4373
4374                                 #address-cells = <1>;
4375                                 #size-cells = <0>;
4376
4377                                 ports {
4378                                         #address-cells = <1>;
4379                                         #size-cells = <0>;
4380
4381                                         port@0 {
4382                                                 reg = <0>;
4383                                                 dsi1_in: endpoint {
4384                                                         remote-endpoint = <&dpu_intf2_out>;
4385                                                 };
4386                                         };
4387
4388                                         port@1 {
4389                                                 reg = <1>;
4390                                                 dsi1_out: endpoint {
4391                                                 };
4392                                         };
4393                                 };
4394                         };
4395
4396                         dsi1_phy: dsi-phy@ae96400 {
4397                                 compatible = "qcom,dsi-phy-10nm";
4398                                 reg = <0 0x0ae96400 0 0x200>,
4399                                       <0 0x0ae96600 0 0x280>,
4400                                       <0 0x0ae96a00 0 0x10e>;
4401                                 reg-names = "dsi_phy",
4402                                             "dsi_phy_lane",
4403                                             "dsi_pll";
4404
4405                                 #clock-cells = <1>;
4406                                 #phy-cells = <0>;
4407
4408                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4409                                          <&rpmhcc RPMH_CXO_CLK>;
4410                                 clock-names = "iface", "ref";
4411
4412                                 status = "disabled";
4413                         };
4414                 };
4415
4416                 gpu: gpu@5000000 {
4417                         compatible = "qcom,adreno-630.2", "qcom,adreno";
4418                         #stream-id-cells = <16>;
4419
4420                         reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4421                         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4422
4423                         /*
4424                          * Look ma, no clocks! The GPU clocks and power are
4425                          * controlled entirely by the GMU
4426                          */
4427
4428                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4429
4430                         iommus = <&adreno_smmu 0>;
4431
4432                         operating-points-v2 = <&gpu_opp_table>;
4433
4434                         qcom,gmu = <&gmu>;
4435
4436                         interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4437                         interconnect-names = "gfx-mem";
4438
4439                         status = "disabled";
4440
4441                         gpu_opp_table: opp-table {
4442                                 compatible = "operating-points-v2";
4443
4444                                 opp-710000000 {
4445                                         opp-hz = /bits/ 64 <710000000>;
4446                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4447                                         opp-peak-kBps = <7216000>;
4448                                 };
4449
4450                                 opp-675000000 {
4451                                         opp-hz = /bits/ 64 <675000000>;
4452                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4453                                         opp-peak-kBps = <7216000>;
4454                                 };
4455
4456                                 opp-596000000 {
4457                                         opp-hz = /bits/ 64 <596000000>;
4458                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4459                                         opp-peak-kBps = <6220000>;
4460                                 };
4461
4462                                 opp-520000000 {
4463                                         opp-hz = /bits/ 64 <520000000>;
4464                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4465                                         opp-peak-kBps = <6220000>;
4466                                 };
4467
4468                                 opp-414000000 {
4469                                         opp-hz = /bits/ 64 <414000000>;
4470                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4471                                         opp-peak-kBps = <4068000>;
4472                                 };
4473
4474                                 opp-342000000 {
4475                                         opp-hz = /bits/ 64 <342000000>;
4476                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4477                                         opp-peak-kBps = <2724000>;
4478                                 };
4479
4480                                 opp-257000000 {
4481                                         opp-hz = /bits/ 64 <257000000>;
4482                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4483                                         opp-peak-kBps = <1648000>;
4484                                 };
4485                         };
4486                 };
4487
4488                 adreno_smmu: iommu@5040000 {
4489                         compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4490                         reg = <0 0x5040000 0 0x10000>;
4491                         #iommu-cells = <1>;
4492                         #global-interrupts = <2>;
4493                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4494                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4495                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4496                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4497                                      <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4498                                      <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4499                                      <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4500                                      <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4501                                      <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4502                                      <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4503                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4504                                  <&gcc GCC_GPU_CFG_AHB_CLK>;
4505                         clock-names = "bus", "iface";
4506
4507                         power-domains = <&gpucc GPU_CX_GDSC>;
4508                 };
4509
4510                 gmu: gmu@506a000 {
4511                         compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4512
4513                         reg = <0 0x506a000 0 0x30000>,
4514                               <0 0xb280000 0 0x10000>,
4515                               <0 0xb480000 0 0x10000>;
4516                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4517
4518                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4519                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4520                         interrupt-names = "hfi", "gmu";
4521
4522                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4523                                  <&gpucc GPU_CC_CXO_CLK>,
4524                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4525                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4526                         clock-names = "gmu", "cxo", "axi", "memnoc";
4527
4528                         power-domains = <&gpucc GPU_CX_GDSC>,
4529                                         <&gpucc GPU_GX_GDSC>;
4530                         power-domain-names = "cx", "gx";
4531
4532                         iommus = <&adreno_smmu 5>;
4533
4534                         operating-points-v2 = <&gmu_opp_table>;
4535
4536                         status = "disabled";
4537
4538                         gmu_opp_table: opp-table {
4539                                 compatible = "operating-points-v2";
4540
4541                                 opp-400000000 {
4542                                         opp-hz = /bits/ 64 <400000000>;
4543                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4544                                 };
4545
4546                                 opp-200000000 {
4547                                         opp-hz = /bits/ 64 <200000000>;
4548                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4549                                 };
4550                         };
4551                 };
4552
4553                 dispcc: clock-controller@af00000 {
4554                         compatible = "qcom,sdm845-dispcc";
4555                         reg = <0 0x0af00000 0 0x10000>;
4556                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4557                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4558                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4559                                  <&dsi0_phy 0>,
4560                                  <&dsi0_phy 1>,
4561                                  <&dsi1_phy 0>,
4562                                  <&dsi1_phy 1>,
4563                                  <0>,
4564                                  <0>;
4565                         clock-names = "bi_tcxo",
4566                                       "gcc_disp_gpll0_clk_src",
4567                                       "gcc_disp_gpll0_div_clk_src",
4568                                       "dsi0_phy_pll_out_byteclk",
4569                                       "dsi0_phy_pll_out_dsiclk",
4570                                       "dsi1_phy_pll_out_byteclk",
4571                                       "dsi1_phy_pll_out_dsiclk",
4572                                       "dp_link_clk_divsel_ten",
4573                                       "dp_vco_divided_clk_src_mux";
4574                         #clock-cells = <1>;
4575                         #reset-cells = <1>;
4576                         #power-domain-cells = <1>;
4577                 };
4578
4579                 pdc_intc: interrupt-controller@b220000 {
4580                         compatible = "qcom,sdm845-pdc", "qcom,pdc";
4581                         reg = <0 0x0b220000 0 0x30000>;
4582                         qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4583                         #interrupt-cells = <2>;
4584                         interrupt-parent = <&intc>;
4585                         interrupt-controller;
4586                 };
4587
4588                 pdc_reset: reset-controller@b2e0000 {
4589                         compatible = "qcom,sdm845-pdc-global";
4590                         reg = <0 0x0b2e0000 0 0x20000>;
4591                         #reset-cells = <1>;
4592                 };
4593
4594                 tsens0: thermal-sensor@c263000 {
4595                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4596                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4597                               <0 0x0c222000 0 0x1ff>; /* SROT */
4598                         #qcom,sensors = <13>;
4599                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4600                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4601                         interrupt-names = "uplow", "critical";
4602                         #thermal-sensor-cells = <1>;
4603                 };
4604
4605                 tsens1: thermal-sensor@c265000 {
4606                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4607                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4608                               <0 0x0c223000 0 0x1ff>; /* SROT */
4609                         #qcom,sensors = <8>;
4610                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4611                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4612                         interrupt-names = "uplow", "critical";
4613                         #thermal-sensor-cells = <1>;
4614                 };
4615
4616                 aoss_reset: reset-controller@c2a0000 {
4617                         compatible = "qcom,sdm845-aoss-cc";
4618                         reg = <0 0x0c2a0000 0 0x31000>;
4619                         #reset-cells = <1>;
4620                 };
4621
4622                 aoss_qmp: power-controller@c300000 {
4623                         compatible = "qcom,sdm845-aoss-qmp";
4624                         reg = <0 0x0c300000 0 0x100000>;
4625                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4626                         mboxes = <&apss_shared 0>;
4627
4628                         #clock-cells = <0>;
4629
4630                         cx_cdev: cx {
4631                                 #cooling-cells = <2>;
4632                         };
4633
4634                         ebi_cdev: ebi {
4635                                 #cooling-cells = <2>;
4636                         };
4637                 };
4638
4639                 spmi_bus: spmi@c440000 {
4640                         compatible = "qcom,spmi-pmic-arb";
4641                         reg = <0 0x0c440000 0 0x1100>,
4642                               <0 0x0c600000 0 0x2000000>,
4643                               <0 0x0e600000 0 0x100000>,
4644                               <0 0x0e700000 0 0xa0000>,
4645                               <0 0x0c40a000 0 0x26000>;
4646                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4647                         interrupt-names = "periph_irq";
4648                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4649                         qcom,ee = <0>;
4650                         qcom,channel = <0>;
4651                         #address-cells = <2>;
4652                         #size-cells = <0>;
4653                         interrupt-controller;
4654                         #interrupt-cells = <4>;
4655                         cell-index = <0>;
4656                 };
4657
4658                 imem@146bf000 {
4659                         compatible = "simple-mfd";
4660                         reg = <0 0x146bf000 0 0x1000>;
4661
4662                         #address-cells = <1>;
4663                         #size-cells = <1>;
4664
4665                         ranges = <0 0 0x146bf000 0x1000>;
4666
4667                         pil-reloc@94c {
4668                                 compatible = "qcom,pil-reloc-info";
4669                                 reg = <0x94c 0xc8>;
4670                         };
4671                 };
4672
4673                 apps_smmu: iommu@15000000 {
4674                         compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
4675                         reg = <0 0x15000000 0 0x80000>;
4676                         #iommu-cells = <2>;
4677                         #global-interrupts = <1>;
4678                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4679                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
4680                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4681                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4682                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4683                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4684                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4685                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4686                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4687                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4688                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4689                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4690                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4691                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4692                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4693                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4694                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4695                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4696                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4697                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4698                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4699                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4700                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4701                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4702                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4703                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4704                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4705                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4706                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4707                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4708                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4709                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4710                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4711                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4712                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4713                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4714                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4715                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4716                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4717                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4718                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4719                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4720                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4721                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4722                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4723                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4724                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4725                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4726                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4727                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4728                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4729                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4730                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4731                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4732                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4733                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4734                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4735                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4736                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4737                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4738                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4739                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4740                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4741                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4742                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
4743                 };
4744
4745                 lpasscc: clock-controller@17014000 {
4746                         compatible = "qcom,sdm845-lpasscc";
4747                         reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
4748                         reg-names = "cc", "qdsp6ss";
4749                         #clock-cells = <1>;
4750                         status = "disabled";
4751                 };
4752
4753                 gladiator_noc: interconnect@17900000 {
4754                         compatible = "qcom,sdm845-gladiator-noc";
4755                         reg = <0 0x17900000 0 0xd080>;
4756                         #interconnect-cells = <2>;
4757                         qcom,bcm-voters = <&apps_bcm_voter>;
4758                 };
4759
4760                 watchdog@17980000 {
4761                         compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
4762                         reg = <0 0x17980000 0 0x1000>;
4763                         clocks = <&sleep_clk>;
4764                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4765                 };
4766
4767                 apss_shared: mailbox@17990000 {
4768                         compatible = "qcom,sdm845-apss-shared";
4769                         reg = <0 0x17990000 0 0x1000>;
4770                         #mbox-cells = <1>;
4771                 };
4772
4773                 apps_rsc: rsc@179c0000 {
4774                         label = "apps_rsc";
4775                         compatible = "qcom,rpmh-rsc";
4776                         reg = <0 0x179c0000 0 0x10000>,
4777                               <0 0x179d0000 0 0x10000>,
4778                               <0 0x179e0000 0 0x10000>;
4779                         reg-names = "drv-0", "drv-1", "drv-2";
4780                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4781                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4782                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4783                         qcom,tcs-offset = <0xd00>;
4784                         qcom,drv-id = <2>;
4785                         qcom,tcs-config = <ACTIVE_TCS  2>,
4786                                           <SLEEP_TCS   3>,
4787                                           <WAKE_TCS    3>,
4788                                           <CONTROL_TCS 1>;
4789
4790                         apps_bcm_voter: bcm-voter {
4791                                 compatible = "qcom,bcm-voter";
4792                         };
4793
4794                         rpmhcc: clock-controller {
4795                                 compatible = "qcom,sdm845-rpmh-clk";
4796                                 #clock-cells = <1>;
4797                                 clock-names = "xo";
4798                                 clocks = <&xo_board>;
4799                         };
4800
4801                         rpmhpd: power-controller {
4802                                 compatible = "qcom,sdm845-rpmhpd";
4803                                 #power-domain-cells = <1>;
4804                                 operating-points-v2 = <&rpmhpd_opp_table>;
4805
4806                                 rpmhpd_opp_table: opp-table {
4807                                         compatible = "operating-points-v2";
4808
4809                                         rpmhpd_opp_ret: opp1 {
4810                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4811                                         };
4812
4813                                         rpmhpd_opp_min_svs: opp2 {
4814                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4815                                         };
4816
4817                                         rpmhpd_opp_low_svs: opp3 {
4818                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4819                                         };
4820
4821                                         rpmhpd_opp_svs: opp4 {
4822                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4823                                         };
4824
4825                                         rpmhpd_opp_svs_l1: opp5 {
4826                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4827                                         };
4828
4829                                         rpmhpd_opp_nom: opp6 {
4830                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4831                                         };
4832
4833                                         rpmhpd_opp_nom_l1: opp7 {
4834                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4835                                         };
4836
4837                                         rpmhpd_opp_nom_l2: opp8 {
4838                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4839                                         };
4840
4841                                         rpmhpd_opp_turbo: opp9 {
4842                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4843                                         };
4844
4845                                         rpmhpd_opp_turbo_l1: opp10 {
4846                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4847                                         };
4848                                 };
4849                         };
4850                 };
4851
4852                 intc: interrupt-controller@17a00000 {
4853                         compatible = "arm,gic-v3";
4854                         #address-cells = <2>;
4855                         #size-cells = <2>;
4856                         ranges;
4857                         #interrupt-cells = <3>;
4858                         interrupt-controller;
4859                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
4860                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
4861                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4862
4863                         msi-controller@17a40000 {
4864                                 compatible = "arm,gic-v3-its";
4865                                 msi-controller;
4866                                 #msi-cells = <1>;
4867                                 reg = <0 0x17a40000 0 0x20000>;
4868                                 status = "disabled";
4869                         };
4870                 };
4871
4872                 slimbam: dma-controller@17184000 {
4873                         compatible = "qcom,bam-v1.7.0";
4874                         qcom,controlled-remotely;
4875                         reg = <0 0x17184000 0 0x2a000>;
4876                         num-channels  = <31>;
4877                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
4878                         #dma-cells = <1>;
4879                         qcom,ee = <1>;
4880                         qcom,num-ees = <2>;
4881                         iommus = <&apps_smmu 0x1806 0x0>;
4882                 };
4883
4884                 timer@17c90000 {
4885                         #address-cells = <2>;
4886                         #size-cells = <2>;
4887                         ranges;
4888                         compatible = "arm,armv7-timer-mem";
4889                         reg = <0 0x17c90000 0 0x1000>;
4890
4891                         frame@17ca0000 {
4892                                 frame-number = <0>;
4893                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
4894                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4895                                 reg = <0 0x17ca0000 0 0x1000>,
4896                                       <0 0x17cb0000 0 0x1000>;
4897                         };
4898
4899                         frame@17cc0000 {
4900                                 frame-number = <1>;
4901                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
4902                                 reg = <0 0x17cc0000 0 0x1000>;
4903                                 status = "disabled";
4904                         };
4905
4906                         frame@17cd0000 {
4907                                 frame-number = <2>;
4908                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4909                                 reg = <0 0x17cd0000 0 0x1000>;
4910                                 status = "disabled";
4911                         };
4912
4913                         frame@17ce0000 {
4914                                 frame-number = <3>;
4915                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4916                                 reg = <0 0x17ce0000 0 0x1000>;
4917                                 status = "disabled";
4918                         };
4919
4920                         frame@17cf0000 {
4921                                 frame-number = <4>;
4922                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4923                                 reg = <0 0x17cf0000 0 0x1000>;
4924                                 status = "disabled";
4925                         };
4926
4927                         frame@17d00000 {
4928                                 frame-number = <5>;
4929                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4930                                 reg = <0 0x17d00000 0 0x1000>;
4931                                 status = "disabled";
4932                         };
4933
4934                         frame@17d10000 {
4935                                 frame-number = <6>;
4936                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4937                                 reg = <0 0x17d10000 0 0x1000>;
4938                                 status = "disabled";
4939                         };
4940                 };
4941
4942                 osm_l3: interconnect@17d41000 {
4943                         compatible = "qcom,sdm845-osm-l3";
4944                         reg = <0 0x17d41000 0 0x1400>;
4945
4946                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4947                         clock-names = "xo", "alternate";
4948
4949                         #interconnect-cells = <1>;
4950                 };
4951
4952                 cpufreq_hw: cpufreq@17d43000 {
4953                         compatible = "qcom,cpufreq-hw";
4954                         reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
4955                         reg-names = "freq-domain0", "freq-domain1";
4956
4957                         interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
4958
4959                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4960                         clock-names = "xo", "alternate";
4961
4962                         #freq-domain-cells = <1>;
4963                 };
4964
4965                 wifi: wifi@18800000 {
4966                         compatible = "qcom,wcn3990-wifi";
4967                         status = "disabled";
4968                         reg = <0 0x18800000 0 0x800000>;
4969                         reg-names = "membase";
4970                         memory-region = <&wlan_msa_mem>;
4971                         clock-names = "cxo_ref_clk_pin";
4972                         clocks = <&rpmhcc RPMH_RF_CLK2>;
4973                         interrupts =
4974                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4975                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4976                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4977                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4978                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4979                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4980                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4981                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4982                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4983                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4984                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4985                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4986                         iommus = <&apps_smmu 0x0040 0x1>;
4987                 };
4988         };
4989
4990         thermal-zones {
4991                 cpu0-thermal {
4992                         polling-delay-passive = <250>;
4993                         polling-delay = <1000>;
4994
4995                         thermal-sensors = <&tsens0 1>;
4996
4997                         trips {
4998                                 cpu0_alert0: trip-point0 {
4999                                         temperature = <90000>;
5000                                         hysteresis = <2000>;
5001                                         type = "passive";
5002                                 };
5003
5004                                 cpu0_alert1: trip-point1 {
5005                                         temperature = <95000>;
5006                                         hysteresis = <2000>;
5007                                         type = "passive";
5008                                 };
5009
5010                                 cpu0_crit: cpu_crit {
5011                                         temperature = <110000>;
5012                                         hysteresis = <1000>;
5013                                         type = "critical";
5014                                 };
5015                         };
5016                 };
5017
5018                 cpu1-thermal {
5019                         polling-delay-passive = <250>;
5020                         polling-delay = <1000>;
5021
5022                         thermal-sensors = <&tsens0 2>;
5023
5024                         trips {
5025                                 cpu1_alert0: trip-point0 {
5026                                         temperature = <90000>;
5027                                         hysteresis = <2000>;
5028                                         type = "passive";
5029                                 };
5030
5031                                 cpu1_alert1: trip-point1 {
5032                                         temperature = <95000>;
5033                                         hysteresis = <2000>;
5034                                         type = "passive";
5035                                 };
5036
5037                                 cpu1_crit: cpu_crit {
5038                                         temperature = <110000>;
5039                                         hysteresis = <1000>;
5040                                         type = "critical";
5041                                 };
5042                         };
5043                 };
5044
5045                 cpu2-thermal {
5046                         polling-delay-passive = <250>;
5047                         polling-delay = <1000>;
5048
5049                         thermal-sensors = <&tsens0 3>;
5050
5051                         trips {
5052                                 cpu2_alert0: trip-point0 {
5053                                         temperature = <90000>;
5054                                         hysteresis = <2000>;
5055                                         type = "passive";
5056                                 };
5057
5058                                 cpu2_alert1: trip-point1 {
5059                                         temperature = <95000>;
5060                                         hysteresis = <2000>;
5061                                         type = "passive";
5062                                 };
5063
5064                                 cpu2_crit: cpu_crit {
5065                                         temperature = <110000>;
5066                                         hysteresis = <1000>;
5067                                         type = "critical";
5068                                 };
5069                         };
5070                 };
5071
5072                 cpu3-thermal {
5073                         polling-delay-passive = <250>;
5074                         polling-delay = <1000>;
5075
5076                         thermal-sensors = <&tsens0 4>;
5077
5078                         trips {
5079                                 cpu3_alert0: trip-point0 {
5080                                         temperature = <90000>;
5081                                         hysteresis = <2000>;
5082                                         type = "passive";
5083                                 };
5084
5085                                 cpu3_alert1: trip-point1 {
5086                                         temperature = <95000>;
5087                                         hysteresis = <2000>;
5088                                         type = "passive";
5089                                 };
5090
5091                                 cpu3_crit: cpu_crit {
5092                                         temperature = <110000>;
5093                                         hysteresis = <1000>;
5094                                         type = "critical";
5095                                 };
5096                         };
5097                 };
5098
5099                 cpu4-thermal {
5100                         polling-delay-passive = <250>;
5101                         polling-delay = <1000>;
5102
5103                         thermal-sensors = <&tsens0 7>;
5104
5105                         trips {
5106                                 cpu4_alert0: trip-point0 {
5107                                         temperature = <90000>;
5108                                         hysteresis = <2000>;
5109                                         type = "passive";
5110                                 };
5111
5112                                 cpu4_alert1: trip-point1 {
5113                                         temperature = <95000>;
5114                                         hysteresis = <2000>;
5115                                         type = "passive";
5116                                 };
5117
5118                                 cpu4_crit: cpu_crit {
5119                                         temperature = <110000>;
5120                                         hysteresis = <1000>;
5121                                         type = "critical";
5122                                 };
5123                         };
5124                 };
5125
5126                 cpu5-thermal {
5127                         polling-delay-passive = <250>;
5128                         polling-delay = <1000>;
5129
5130                         thermal-sensors = <&tsens0 8>;
5131
5132                         trips {
5133                                 cpu5_alert0: trip-point0 {
5134                                         temperature = <90000>;
5135                                         hysteresis = <2000>;
5136                                         type = "passive";
5137                                 };
5138
5139                                 cpu5_alert1: trip-point1 {
5140                                         temperature = <95000>;
5141                                         hysteresis = <2000>;
5142                                         type = "passive";
5143                                 };
5144
5145                                 cpu5_crit: cpu_crit {
5146                                         temperature = <110000>;
5147                                         hysteresis = <1000>;
5148                                         type = "critical";
5149                                 };
5150                         };
5151                 };
5152
5153                 cpu6-thermal {
5154                         polling-delay-passive = <250>;
5155                         polling-delay = <1000>;
5156
5157                         thermal-sensors = <&tsens0 9>;
5158
5159                         trips {
5160                                 cpu6_alert0: trip-point0 {
5161                                         temperature = <90000>;
5162                                         hysteresis = <2000>;
5163                                         type = "passive";
5164                                 };
5165
5166                                 cpu6_alert1: trip-point1 {
5167                                         temperature = <95000>;
5168                                         hysteresis = <2000>;
5169                                         type = "passive";
5170                                 };
5171
5172                                 cpu6_crit: cpu_crit {
5173                                         temperature = <110000>;
5174                                         hysteresis = <1000>;
5175                                         type = "critical";
5176                                 };
5177                         };
5178                 };
5179
5180                 cpu7-thermal {
5181                         polling-delay-passive = <250>;
5182                         polling-delay = <1000>;
5183
5184                         thermal-sensors = <&tsens0 10>;
5185
5186                         trips {
5187                                 cpu7_alert0: trip-point0 {
5188                                         temperature = <90000>;
5189                                         hysteresis = <2000>;
5190                                         type = "passive";
5191                                 };
5192
5193                                 cpu7_alert1: trip-point1 {
5194                                         temperature = <95000>;
5195                                         hysteresis = <2000>;
5196                                         type = "passive";
5197                                 };
5198
5199                                 cpu7_crit: cpu_crit {
5200                                         temperature = <110000>;
5201                                         hysteresis = <1000>;
5202                                         type = "critical";
5203                                 };
5204                         };
5205                 };
5206
5207                 aoss0-thermal {
5208                         polling-delay-passive = <250>;
5209                         polling-delay = <1000>;
5210
5211                         thermal-sensors = <&tsens0 0>;
5212
5213                         trips {
5214                                 aoss0_alert0: trip-point0 {
5215                                         temperature = <90000>;
5216                                         hysteresis = <2000>;
5217                                         type = "hot";
5218                                 };
5219                         };
5220                 };
5221
5222                 cluster0-thermal {
5223                         polling-delay-passive = <250>;
5224                         polling-delay = <1000>;
5225
5226                         thermal-sensors = <&tsens0 5>;
5227
5228                         trips {
5229                                 cluster0_alert0: trip-point0 {
5230                                         temperature = <90000>;
5231                                         hysteresis = <2000>;
5232                                         type = "hot";
5233                                 };
5234                                 cluster0_crit: cluster0_crit {
5235                                         temperature = <110000>;
5236                                         hysteresis = <2000>;
5237                                         type = "critical";
5238                                 };
5239                         };
5240                 };
5241
5242                 cluster1-thermal {
5243                         polling-delay-passive = <250>;
5244                         polling-delay = <1000>;
5245
5246                         thermal-sensors = <&tsens0 6>;
5247
5248                         trips {
5249                                 cluster1_alert0: trip-point0 {
5250                                         temperature = <90000>;
5251                                         hysteresis = <2000>;
5252                                         type = "hot";
5253                                 };
5254                                 cluster1_crit: cluster1_crit {
5255                                         temperature = <110000>;
5256                                         hysteresis = <2000>;
5257                                         type = "critical";
5258                                 };
5259                         };
5260                 };
5261
5262                 gpu-thermal-top {
5263                         polling-delay-passive = <250>;
5264                         polling-delay = <1000>;
5265
5266                         thermal-sensors = <&tsens0 11>;
5267
5268                         trips {
5269                                 gpu1_alert0: trip-point0 {
5270                                         temperature = <90000>;
5271                                         hysteresis = <2000>;
5272                                         type = "hot";
5273                                 };
5274                         };
5275                 };
5276
5277                 gpu-thermal-bottom {
5278                         polling-delay-passive = <250>;
5279                         polling-delay = <1000>;
5280
5281                         thermal-sensors = <&tsens0 12>;
5282
5283                         trips {
5284                                 gpu2_alert0: trip-point0 {
5285                                         temperature = <90000>;
5286                                         hysteresis = <2000>;
5287                                         type = "hot";
5288                                 };
5289                         };
5290                 };
5291
5292                 aoss1-thermal {
5293                         polling-delay-passive = <250>;
5294                         polling-delay = <1000>;
5295
5296                         thermal-sensors = <&tsens1 0>;
5297
5298                         trips {
5299                                 aoss1_alert0: trip-point0 {
5300                                         temperature = <90000>;
5301                                         hysteresis = <2000>;
5302                                         type = "hot";
5303                                 };
5304                         };
5305                 };
5306
5307                 q6-modem-thermal {
5308                         polling-delay-passive = <250>;
5309                         polling-delay = <1000>;
5310
5311                         thermal-sensors = <&tsens1 1>;
5312
5313                         trips {
5314                                 q6_modem_alert0: trip-point0 {
5315                                         temperature = <90000>;
5316                                         hysteresis = <2000>;
5317                                         type = "hot";
5318                                 };
5319                         };
5320                 };
5321
5322                 mem-thermal {
5323                         polling-delay-passive = <250>;
5324                         polling-delay = <1000>;
5325
5326                         thermal-sensors = <&tsens1 2>;
5327
5328                         trips {
5329                                 mem_alert0: trip-point0 {
5330                                         temperature = <90000>;
5331                                         hysteresis = <2000>;
5332                                         type = "hot";
5333                                 };
5334                         };
5335                 };
5336
5337                 wlan-thermal {
5338                         polling-delay-passive = <250>;
5339                         polling-delay = <1000>;
5340
5341                         thermal-sensors = <&tsens1 3>;
5342
5343                         trips {
5344                                 wlan_alert0: trip-point0 {
5345                                         temperature = <90000>;
5346                                         hysteresis = <2000>;
5347                                         type = "hot";
5348                                 };
5349                         };
5350                 };
5351
5352                 q6-hvx-thermal {
5353                         polling-delay-passive = <250>;
5354                         polling-delay = <1000>;
5355
5356                         thermal-sensors = <&tsens1 4>;
5357
5358                         trips {
5359                                 q6_hvx_alert0: trip-point0 {
5360                                         temperature = <90000>;
5361                                         hysteresis = <2000>;
5362                                         type = "hot";
5363                                 };
5364                         };
5365                 };
5366
5367                 camera-thermal {
5368                         polling-delay-passive = <250>;
5369                         polling-delay = <1000>;
5370
5371                         thermal-sensors = <&tsens1 5>;
5372
5373                         trips {
5374                                 camera_alert0: trip-point0 {
5375                                         temperature = <90000>;
5376                                         hysteresis = <2000>;
5377                                         type = "hot";
5378                                 };
5379                         };
5380                 };
5381
5382                 video-thermal {
5383                         polling-delay-passive = <250>;
5384                         polling-delay = <1000>;
5385
5386                         thermal-sensors = <&tsens1 6>;
5387
5388                         trips {
5389                                 video_alert0: trip-point0 {
5390                                         temperature = <90000>;
5391                                         hysteresis = <2000>;
5392                                         type = "hot";
5393                                 };
5394                         };
5395                 };
5396
5397                 modem-thermal {
5398                         polling-delay-passive = <250>;
5399                         polling-delay = <1000>;
5400
5401                         thermal-sensors = <&tsens1 7>;
5402
5403                         trips {
5404                                 modem_alert0: trip-point0 {
5405                                         temperature = <90000>;
5406                                         hysteresis = <2000>;
5407                                         type = "hot";
5408                                 };
5409                         };
5410                 };
5411         };
5412 };