arch/arm64/boot/dts/qcom/sdm670.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SDM670 SoC device tree source, adapted from SDM845 SoC device tree
   4  *
   5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   6  * Copyright (c) 2022, Richard Acayan. All rights reserved.
   7  */
   8
   9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/dma/qcom-gpi.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  16 #include <dt-bindings/power/qcom-rpmpd.h>
  17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  18
  19 / {
  20         interrupt-parent = <&intc>;
  21
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         aliases { };
  26
  27         chosen { };
  28
  29         cpus {
  30                 #address-cells = <2>;
  31                 #size-cells = <0>;
  32
  33                 CPU0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "qcom,kryo360";
  36                         reg = <0x0 0x0>;
  37                         enable-method = "psci";
  38                         power-domains = <&CPU_PD0>;
  39                         power-domain-names = "psci";
  40                         next-level-cache = <&L2_0>;
  41                         L2_0: l2-cache {
  42                                 compatible = "cache";
  43                                 next-level-cache = <&L3_0>;
  44                                 cache-level = <2>;
  45                                 cache-unified;
  46                                 L3_0: l3-cache {
  47                                         compatible = "cache";
  48                                         cache-level = <3>;
  49                                         cache-unified;
  50                                 };
  51                         };
  52                 };
  53
  54                 CPU1: cpu@100 {
  55                         device_type = "cpu";
  56                         compatible = "qcom,kryo360";
  57                         reg = <0x0 0x100>;
  58                         enable-method = "psci";
  59                         power-domains = <&CPU_PD1>;
  60                         power-domain-names = "psci";
  61                         next-level-cache = <&L2_100>;
  62                         L2_100: l2-cache {
  63                                 compatible = "cache";
  64                                 cache-level = <2>;
  65                                 cache-unified;
  66                                 next-level-cache = <&L3_0>;
  67                         };
  68                 };
  69
  70                 CPU2: cpu@200 {
  71                         device_type = "cpu";
  72                         compatible = "qcom,kryo360";
  73                         reg = <0x0 0x200>;
  74                         enable-method = "psci";
  75                         power-domains = <&CPU_PD2>;
  76                         power-domain-names = "psci";
  77                         next-level-cache = <&L2_200>;
  78                         L2_200: l2-cache {
  79                                 compatible = "cache";
  80                                 cache-level = <2>;
  81                                 cache-unified;
  82                                 next-level-cache = <&L3_0>;
  83                         };
  84                 };
  85
  86                 CPU3: cpu@300 {
  87                         device_type = "cpu";
  88                         compatible = "qcom,kryo360";
  89                         reg = <0x0 0x300>;
  90                         enable-method = "psci";
  91                         power-domains = <&CPU_PD3>;
  92                         power-domain-names = "psci";
  93                         next-level-cache = <&L2_300>;
  94                         L2_300: l2-cache {
  95                                 compatible = "cache";
  96                                 cache-level = <2>;
  97                                 cache-unified;
  98                                 next-level-cache = <&L3_0>;
  99                         };
 100                 };
 101
 102                 CPU4: cpu@400 {
 103                         device_type = "cpu";
 104                         compatible = "qcom,kryo360";
 105                         reg = <0x0 0x400>;
 106                         enable-method = "psci";
 107                         power-domains = <&CPU_PD4>;
 108                         power-domain-names = "psci";
 109                         next-level-cache = <&L2_400>;
 110                         L2_400: l2-cache {
 111                                 compatible = "cache";
 112                                 cache-level = <2>;
 113                                 cache-unified;
 114                                 next-level-cache = <&L3_0>;
 115                         };
 116                 };
 117
 118                 CPU5: cpu@500 {
 119                         device_type = "cpu";
 120                         compatible = "qcom,kryo360";
 121                         reg = <0x0 0x500>;
 122                         enable-method = "psci";
 123                         power-domains = <&CPU_PD5>;
 124                         power-domain-names = "psci";
 125                         next-level-cache = <&L2_500>;
 126                         L2_500: l2-cache {
 127                                 compatible = "cache";
 128                                 cache-level = <2>;
 129                                 cache-unified;
 130                                 next-level-cache = <&L3_0>;
 131                         };
 132                 };
 133
 134                 CPU6: cpu@600 {
 135                         device_type = "cpu";
 136                         compatible = "qcom,kryo360";
 137                         reg = <0x0 0x600>;
 138                         enable-method = "psci";
 139                         power-domains = <&CPU_PD6>;
 140                         power-domain-names = "psci";
 141                         next-level-cache = <&L2_600>;
 142                         L2_600: l2-cache {
 143                                 compatible = "cache";
 144                                 cache-level = <2>;
 145                                 cache-unified;
 146                                 next-level-cache = <&L3_0>;
 147                         };
 148                 };
 149
 150                 CPU7: cpu@700 {
 151                         device_type = "cpu";
 152                         compatible = "qcom,kryo360";
 153                         reg = <0x0 0x700>;
 154                         enable-method = "psci";
 155                         power-domains = <&CPU_PD7>;
 156                         power-domain-names = "psci";
 157                         next-level-cache = <&L2_700>;
 158                         L2_700: l2-cache {
 159                                 compatible = "cache";
 160                                 cache-level = <2>;
 161                                 cache-unified;
 162                                 next-level-cache = <&L3_0>;
 163                         };
 164                 };
 165
 166                 cpu-map {
 167                         cluster0 {
 168                                 core0 {
 169                                         cpu = <&CPU0>;
 170                                 };
 171
 172                                 core1 {
 173                                         cpu = <&CPU1>;
 174                                 };
 175
 176                                 core2 {
 177                                         cpu = <&CPU2>;
 178                                 };
 179
 180                                 core3 {
 181                                         cpu = <&CPU3>;
 182                                 };
 183
 184                                 core4 {
 185                                         cpu = <&CPU4>;
 186                                 };
 187
 188                                 core5 {
 189                                         cpu = <&CPU5>;
 190                                 };
 191
 192                                 core6 {
 193                                         cpu = <&CPU6>;
 194                                 };
 195
 196                                 core7 {
 197                                         cpu = <&CPU7>;
 198                                 };
 199                         };
 200                 };
 201
 202                 idle-states {
 203                         entry-method = "psci";
 204
 205                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 206                                 compatible = "arm,idle-state";
 207                                 idle-state-name = "little-rail-power-collapse";
 208                                 arm,psci-suspend-param = <0x40000004>;
 209                                 entry-latency-us = <702>;
 210                                 exit-latency-us = <915>;
 211                                 min-residency-us = <1617>;
 212                                 local-timer-stop;
 213                         };
 214
 215                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 216                                 compatible = "arm,idle-state";
 217                                 idle-state-name = "big-rail-power-collapse";
 218                                 arm,psci-suspend-param = <0x40000004>;
 219                                 entry-latency-us = <526>;
 220                                 exit-latency-us = <1854>;
 221                                 min-residency-us = <2380>;
 222                                 local-timer-stop;
 223                         };
 224                 };
 225
 226                 domain-idle-states {
 227                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 228                                 compatible = "domain-idle-state";
 229                                 arm,psci-suspend-param = <0x4100c244>;
 230                                 entry-latency-us = <3263>;
 231                                 exit-latency-us = <6562>;
 232                                 min-residency-us = <9825>;
 233                         };
 234                 };
 235         };
 236
 237         firmware {
 238                 scm {
 239                         compatible = "qcom,scm-sdm670", "qcom,scm";
 240                 };
 241         };
 242
 243         memory@80000000 {
 244                 device_type = "memory";
 245                 /* We expect the bootloader to fill in the size */
 246                 reg = <0x0 0x80000000 0x0 0x0>;
 247         };
 248
 249         psci {
 250                 compatible = "arm,psci-1.0";
 251                 method = "smc";
 252
 253                 CPU_PD0: power-domain-cpu0 {
 254                         #power-domain-cells = <0>;
 255                         power-domains = <&CLUSTER_PD>;
 256                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 257                 };
 258
 259                 CPU_PD1: power-domain-cpu1 {
 260                         #power-domain-cells = <0>;
 261                         power-domains = <&CLUSTER_PD>;
 262                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 263                 };
 264
 265                 CPU_PD2: power-domain-cpu2 {
 266                         #power-domain-cells = <0>;
 267                         power-domains = <&CLUSTER_PD>;
 268                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 269                 };
 270
 271                 CPU_PD3: power-domain-cpu3 {
 272                         #power-domain-cells = <0>;
 273                         power-domains = <&CLUSTER_PD>;
 274                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 275                 };
 276
 277                 CPU_PD4: power-domain-cpu4 {
 278                         #power-domain-cells = <0>;
 279                         power-domains = <&CLUSTER_PD>;
 280                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 281                 };
 282
 283                 CPU_PD5: power-domain-cpu5 {
 284                         #power-domain-cells = <0>;
 285                         power-domains = <&CLUSTER_PD>;
 286                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 287                 };
 288
 289                 CPU_PD6: power-domain-cpu6 {
 290                         #power-domain-cells = <0>;
 291                         power-domains = <&CLUSTER_PD>;
 292                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 293                 };
 294
 295                 CPU_PD7: power-domain-cpu7 {
 296                         #power-domain-cells = <0>;
 297                         power-domains = <&CLUSTER_PD>;
 298                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 299                 };
 300
 301                 CLUSTER_PD: power-domain-cluster {
 302                         #power-domain-cells = <0>;
 303                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 304                 };
 305         };
 306
 307         reserved-memory {
 308                 #address-cells = <2>;
 309                 #size-cells = <2>;
 310                 ranges;
 311
 312                 hyp_mem: hyp-mem@85700000 {
 313                         reg = <0 0x85700000 0 0x600000>;
 314                         no-map;
 315                 };
 316
 317                 xbl_mem: xbl-mem@85e00000 {
 318                         reg = <0 0x85e00000 0 0x100000>;
 319                         no-map;
 320                 };
 321
 322                 aop_mem: aop-mem@85fc0000 {
 323                         reg = <0 0x85fc0000 0 0x20000>;
 324                         no-map;
 325                 };
 326
 327                 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
 328                         compatible = "qcom,cmd-db";
 329                         reg = <0 0x85fe0000 0 0x20000>;
 330                         no-map;
 331                 };
 332
 333                 camera_mem: camera-mem@8ab00000 {
 334                         reg = <0 0x8ab00000 0 0x500000>;
 335                         no-map;
 336                 };
 337
 338                 mpss_region: mpss@8b000000 {
 339                         reg = <0 0x8b000000 0 0x7e00000>;
 340                         no-map;
 341                 };
 342
 343                 venus_mem: venus@92e00000 {
 344                         reg = <0 0x92e00000 0 0x500000>;
 345                         no-map;
 346                 };
 347
 348                 wlan_msa_mem: wlan-msa@93300000 {
 349                         reg = <0 0x93300000 0 0x100000>;
 350                         no-map;
 351                 };
 352
 353                 cdsp_mem: cdsp@93400000 {
 354                         reg = <0 0x93400000 0 0x800000>;
 355                         no-map;
 356                 };
 357
 358                 mba_region: mba@93c00000 {
 359                         reg = <0 0x93c00000 0 0x200000>;
 360                         no-map;
 361                 };
 362
 363                 adsp_mem: adsp@93e00000 {
 364                         reg = <0 0x93e00000 0 0x1e00000>;
 365                         no-map;
 366                 };
 367
 368                 ipa_fw_mem: ipa-fw@95c00000 {
 369                         reg = <0 0x95c00000 0 0x10000>;
 370                         no-map;
 371                 };
 372
 373                 ipa_gsi_mem: ipa-gsi@95c10000 {
 374                         reg = <0 0x95c10000 0 0x5000>;
 375                         no-map;
 376                 };
 377
 378                 gpu_mem: gpu@95c15000 {
 379                         reg = <0 0x95c15000 0 0x2000>;
 380                         no-map;
 381                 };
 382
 383                 spss_mem: spss@97b00000 {
 384                         reg = <0 0x97b00000 0 0x100000>;
 385                         no-map;
 386                 };
 387
 388                 qseecom_mem: qseecom@9e400000 {
 389                         reg = <0 0x9e400000 0 0x1400000>;
 390                         no-map;
 391                 };
 392         };
 393
 394         timer {
 395                 compatible = "arm,armv8-timer";
 396                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 397                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 398                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 399                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 400         };
 401
 402         soc: soc@0 {
 403                 #address-cells = <2>;
 404                 #size-cells = <2>;
 405                 ranges = <0 0 0 0 0x10 0>;
 406                 dma-ranges = <0 0 0 0 0x10 0>;
 407                 compatible = "simple-bus";
 408
 409                 gcc: clock-controller@100000 {
 410                         compatible = "qcom,gcc-sdm670";
 411                         reg = <0 0x00100000 0 0x1f0000>;
 412                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 413                                  <&rpmhcc RPMH_CXO_CLK_A>,
 414                                  <&sleep_clk>;
 415                         clock-names = "bi_tcxo",
 416                                       "bi_tcxo_ao",
 417                                       "sleep_clk";
 418                         #clock-cells = <1>;
 419                         #reset-cells = <1>;
 420                         #power-domain-cells = <1>;
 421                 };
 422
 423                 qfprom: qfprom@784000 {
 424                         compatible = "qcom,sdm670-qfprom", "qcom,qfprom";
 425                         reg = <0 0x00784000 0 0x1000>;
 426                         #address-cells = <1>;
 427                         #size-cells = <1>;
 428
 429                         qusb2_hstx_trim: hstx-trim@1eb {
 430                                 reg = <0x1eb 0x1>;
 431                                 bits = <1 4>;
 432                         };
 433                 };
 434
 435                 sdhc_1: mmc@7c4000 {
 436                         compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
 437                         reg = <0 0x007c4000 0 0x1000>,
 438                               <0 0x007c5000 0 0x1000>,
 439                               <0 0x007c8000 0 0x8000>;
 440                         reg-names = "hc", "cqhci", "ice";
 441
 442                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 443                                      <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
 444                         interrupt-names = "hc_irq", "pwr_irq";
 445
 446                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 447                                  <&gcc GCC_SDCC1_APPS_CLK>,
 448                                  <&rpmhcc RPMH_CXO_CLK>,
 449                                  <&gcc GCC_SDCC1_ICE_CORE_CLK>,
 450                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
 451                         clock-names = "iface", "core", "xo", "ice", "bus";
 452                         interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>,
 453                                         <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>;
 454                         interconnect-names = "sdhc-ddr", "cpu-sdhc";
 455                         operating-points-v2 = <&sdhc1_opp_table>;
 456
 457                         iommus = <&apps_smmu 0x140 0xf>;
 458
 459                         pinctrl-names = "default", "sleep";
 460                         pinctrl-0 = <&sdc1_state_on>;
 461                         pinctrl-1 = <&sdc1_state_off>;
 462                         power-domains = <&rpmhpd SDM670_CX>;
 463
 464                         bus-width = <8>;
 465                         non-removable;
 466
 467                         status = "disabled";
 468
 469                         sdhc1_opp_table: opp-table {
 470                                 compatible = "operating-points-v2";
 471
 472                                 opp-20000000 {
 473                                         opp-hz = /bits/ 64 <20000000>;
 474                                         required-opps = <&rpmhpd_opp_min_svs>;
 475                                         opp-peak-kBps = <80000 80000>;
 476                                         opp-avg-kBps = <52286 80000>;
 477                                 };
 478
 479                                 opp-50000000 {
 480                                         opp-hz = /bits/ 64 <50000000>;
 481                                         required-opps = <&rpmhpd_opp_low_svs>;
 482                                         opp-peak-kBps = <200000 100000>;
 483                                         opp-avg-kBps = <130718 100000>;
 484                                 };
 485
 486                                 opp-100000000 {
 487                                         opp-hz = /bits/ 64 <100000000>;
 488                                         required-opps = <&rpmhpd_opp_svs>;
 489                                         opp-peak-kBps = <200000 130000>;
 490                                         opp-avg-kBps = <130718 130000>;
 491                                 };
 492
 493                                 opp-384000000 {
 494                                         opp-hz = /bits/ 64 <384000000>;
 495                                         required-opps = <&rpmhpd_opp_nom>;
 496                                         opp-peak-kBps = <4096000 4096000>;
 497                                         opp-avg-kBps = <1338562 1338562>;
 498                                 };
 499                         };
 500                 };
 501
 502                 gpi_dma0: dma-controller@800000 {
 503                         #dma-cells = <3>;
 504                         compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
 505                         reg = <0 0x00800000 0 0x60000>;
 506                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 507                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 508                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 509                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 510                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 511                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 512                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 513                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 514                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 515                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 516                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 517                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 518                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 519                         dma-channels = <13>;
 520                         dma-channel-mask = <0xfa>;
 521                         iommus = <&apps_smmu 0x16 0x0>;
 522                         status = "disabled";
 523                 };
 524
 525                 qupv3_id_0: geniqup@8c0000 {
 526                         compatible = "qcom,geni-se-qup";
 527                         reg = <0 0x008c0000 0 0x6000>;
 528                         clock-names = "m-ahb", "s-ahb";
 529                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 530                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 531                         iommus = <&apps_smmu 0x3 0x0>;
 532                         #address-cells = <2>;
 533                         #size-cells = <2>;
 534                         ranges;
 535                         interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>;
 536                         interconnect-names = "qup-core";
 537                         status = "disabled";
 538
 539                         i2c0: i2c@880000 {
 540                                 compatible = "qcom,geni-i2c";
 541                                 reg = <0 0x00880000 0 0x4000>;
 542                                 clock-names = "se";
 543                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 544                                 pinctrl-names = "default";
 545                                 pinctrl-0 = <&qup_i2c0_default>;
 546                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 547                                 #address-cells = <1>;
 548                                 #size-cells = <0>;
 549                                 power-domains = <&rpmhpd SDM670_CX>;
 550                                 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
 551                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
 552                                                 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
 553                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 554                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 555                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 556                                 dma-names = "tx", "rx";
 557                                 status = "disabled";
 558                         };
 559
 560                         i2c1: i2c@884000 {
 561                                 compatible = "qcom,geni-i2c";
 562                                 reg = <0 0x00884000 0 0x4000>;
 563                                 clock-names = "se";
 564                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 565                                 pinctrl-names = "default";
 566                                 pinctrl-0 = <&qup_i2c1_default>;
 567                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 568                                 #address-cells = <1>;
 569                                 #size-cells = <0>;
 570                                 power-domains = <&rpmhpd SDM670_CX>;
 571                                 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
 572                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
 573                                                 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
 574                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 575                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 576                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 577                                 dma-names = "tx", "rx";
 578                                 status = "disabled";
 579                         };
 580
 581                         i2c2: i2c@888000 {
 582                                 compatible = "qcom,geni-i2c";
 583                                 reg = <0 0x00888000 0 0x4000>;
 584                                 clock-names = "se";
 585                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 586                                 pinctrl-names = "default";
 587                                 pinctrl-0 = <&qup_i2c2_default>;
 588                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 589                                 #address-cells = <1>;
 590                                 #size-cells = <0>;
 591                                 power-domains = <&rpmhpd SDM670_CX>;
 592                                 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
 593                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
 594                                                 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
 595                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 596                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
 597                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
 598                                 dma-names = "tx", "rx";
 599                                 status = "disabled";
 600                         };
 601
 602                         i2c3: i2c@88c000 {
 603                                 compatible = "qcom,geni-i2c";
 604                                 reg = <0 0x0088c000 0 0x4000>;
 605                                 clock-names = "se";
 606                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 607                                 pinctrl-names = "default";
 608                                 pinctrl-0 = <&qup_i2c3_default>;
 609                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 610                                 #address-cells = <1>;
 611                                 #size-cells = <0>;
 612                                 power-domains = <&rpmhpd SDM670_CX>;
 613                                 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
 614                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
 615                                                 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
 616                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 617                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
 618                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
 619                                 dma-names = "tx", "rx";
 620                                 status = "disabled";
 621                         };
 622
 623                         i2c4: i2c@890000 {
 624                                 compatible = "qcom,geni-i2c";
 625                                 reg = <0 0x00890000 0 0x4000>;
 626                                 clock-names = "se";
 627                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 628                                 pinctrl-names = "default";
 629                                 pinctrl-0 = <&qup_i2c4_default>;
 630                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 631                                 #address-cells = <1>;
 632                                 #size-cells = <0>;
 633                                 power-domains = <&rpmhpd SDM670_CX>;
 634                                 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
 635                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
 636                                                 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
 637                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 638                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
 639                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
 640                                 dma-names = "tx", "rx";
 641                                 status = "disabled";
 642                         };
 643
 644                         i2c5: i2c@894000 {
 645                                 compatible = "qcom,geni-i2c";
 646                                 reg = <0 0x00894000 0 0x4000>;
 647                                 clock-names = "se";
 648                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 649                                 pinctrl-names = "default";
 650                                 pinctrl-0 = <&qup_i2c5_default>;
 651                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 652                                 #address-cells = <1>;
 653                                 #size-cells = <0>;
 654                                 power-domains = <&rpmhpd SDM670_CX>;
 655                                 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
 656                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
 657                                                 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
 658                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 659                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
 660                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
 661                                 dma-names = "tx", "rx";
 662                                 status = "disabled";
 663                         };
 664
 665                         i2c6: i2c@898000 {
 666                                 compatible = "qcom,geni-i2c";
 667                                 reg = <0 0x00898000 0 0x4000>;
 668                                 clock-names = "se";
 669                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 670                                 pinctrl-names = "default";
 671                                 pinctrl-0 = <&qup_i2c6_default>;
 672                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 673                                 #address-cells = <1>;
 674                                 #size-cells = <0>;
 675                                 power-domains = <&rpmhpd SDM670_CX>;
 676                                 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
 677                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
 678                                                 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
 679                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 680                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
 681                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
 682                                 dma-names = "tx", "rx";
 683                                 status = "disabled";
 684                         };
 685
 686                         i2c7: i2c@89c000 {
 687                                 compatible = "qcom,geni-i2c";
 688                                 reg = <0 0x0089c000 0 0x4000>;
 689                                 clock-names = "se";
 690                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 691                                 pinctrl-names = "default";
 692                                 pinctrl-0 = <&qup_i2c7_default>;
 693                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 694                                 #address-cells = <1>;
 695                                 #size-cells = <0>;
 696                                 power-domains = <&rpmhpd SDM670_CX>;
 697                                 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
 698                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
 699                                                 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
 700                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 701                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
 702                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
 703                                 dma-names = "tx", "rx";
 704                                 status = "disabled";
 705                         };
 706                 };
 707
 708                 gpi_dma1: dma-controller@a00000 {
 709                         #dma-cells = <3>;
 710                         compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
 711                         reg = <0 0x00a00000 0 0x60000>;
 712                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 713                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 714                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
 715                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
 716                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 717                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 718                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
 719                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
 720                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
 721                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
 722                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
 723                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
 724                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 725                         dma-channels = <13>;
 726                         dma-channel-mask = <0xfa>;
 727                         iommus = <&apps_smmu 0x6d6 0x0>;
 728                         status = "disabled";
 729                 };
 730
 731                 qupv3_id_1: geniqup@ac0000 {
 732                         compatible = "qcom,geni-se-qup";
 733                         reg = <0 0x00ac0000 0 0x6000>;
 734                         clock-names = "m-ahb", "s-ahb";
 735                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 736                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 737                         iommus = <&apps_smmu 0x6c3 0x0>;
 738                         #address-cells = <2>;
 739                         #size-cells = <2>;
 740                         ranges;
 741                         interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>;
 742                         interconnect-names = "qup-core";
 743                         status = "disabled";
 744
 745                         i2c8: i2c@a80000 {
 746                                 compatible = "qcom,geni-i2c";
 747                                 reg = <0 0x00a80000 0 0x4000>;
 748                                 clock-names = "se";
 749                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 750                                 pinctrl-names = "default";
 751                                 pinctrl-0 = <&qup_i2c8_default>;
 752                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 753                                 #address-cells = <1>;
 754                                 #size-cells = <0>;
 755                                 power-domains = <&rpmhpd SDM670_CX>;
 756                                 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
 757                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
 758                                                 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
 759                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 760                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
 761                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
 762                                 dma-names = "tx", "rx";
 763                                 status = "disabled";
 764                         };
 765
 766                         i2c9: i2c@a84000 {
 767                                 compatible = "qcom,geni-i2c";
 768                                 reg = <0 0x00a84000 0 0x4000>;
 769                                 clock-names = "se";
 770                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 771                                 pinctrl-names = "default";
 772                                 pinctrl-0 = <&qup_i2c9_default>;
 773                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 774                                 #address-cells = <1>;
 775                                 #size-cells = <0>;
 776                                 power-domains = <&rpmhpd SDM670_CX>;
 777                                 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
 778                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
 779                                                 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
 780                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 781                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
 782                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
 783                                 dma-names = "tx", "rx";
 784                                 status = "disabled";
 785                         };
 786
 787                         i2c10: i2c@a88000 {
 788                                 compatible = "qcom,geni-i2c";
 789                                 reg = <0 0x00a88000 0 0x4000>;
 790                                 clock-names = "se";
 791                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 792                                 pinctrl-names = "default";
 793                                 pinctrl-0 = <&qup_i2c10_default>;
 794                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 795                                 #address-cells = <1>;
 796                                 #size-cells = <0>;
 797                                 power-domains = <&rpmhpd SDM670_CX>;
 798                                 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
 799                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
 800                                                 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
 801                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 802                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
 803                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
 804                                 dma-names = "tx", "rx";
 805                                 status = "disabled";
 806                         };
 807
 808                         i2c11: i2c@a8c000 {
 809                                 compatible = "qcom,geni-i2c";
 810                                 reg = <0 0x00a8c000 0 0x4000>;
 811                                 clock-names = "se";
 812                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
 813                                 pinctrl-names = "default";
 814                                 pinctrl-0 = <&qup_i2c11_default>;
 815                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 816                                 #address-cells = <1>;
 817                                 #size-cells = <0>;
 818                                 power-domains = <&rpmhpd SDM670_CX>;
 819                                 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
 820                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
 821                                                 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
 822                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 823                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
 824                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
 825                                 dma-names = "tx", "rx";
 826                                 status = "disabled";
 827                         };
 828
 829                         i2c12: i2c@a90000 {
 830                                 compatible = "qcom,geni-i2c";
 831                                 reg = <0 0x00a90000 0 0x4000>;
 832                                 clock-names = "se";
 833                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 834                                 pinctrl-names = "default";
 835                                 pinctrl-0 = <&qup_i2c12_default>;
 836                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 837                                 #address-cells = <1>;
 838                                 #size-cells = <0>;
 839                                 power-domains = <&rpmhpd SDM670_CX>;
 840                                 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
 841                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
 842                                                 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
 843                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 844                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
 845                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
 846                                 dma-names = "tx", "rx";
 847                                 status = "disabled";
 848                         };
 849
 850                         i2c13: i2c@a94000 {
 851                                 compatible = "qcom,geni-i2c";
 852                                 reg = <0 0x00a94000 0 0x4000>;
 853                                 clock-names = "se";
 854                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 855                                 pinctrl-names = "default";
 856                                 pinctrl-0 = <&qup_i2c13_default>;
 857                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 858                                 #address-cells = <1>;
 859                                 #size-cells = <0>;
 860                                 power-domains = <&rpmhpd SDM670_CX>;
 861                                 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
 862                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
 863                                                 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
 864                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 865                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
 866                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
 867                                 dma-names = "tx", "rx";
 868                                 status = "disabled";
 869                         };
 870
 871                         i2c14: i2c@a98000 {
 872                                 compatible = "qcom,geni-i2c";
 873                                 reg = <0 0x00a98000 0 0x4000>;
 874                                 clock-names = "se";
 875                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
 876                                 pinctrl-names = "default";
 877                                 pinctrl-0 = <&qup_i2c14_default>;
 878                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 879                                 #address-cells = <1>;
 880                                 #size-cells = <0>;
 881                                 power-domains = <&rpmhpd SDM670_CX>;
 882                                 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
 883                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
 884                                                 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
 885                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 886                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
 887                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
 888                                 dma-names = "tx", "rx";
 889                                 status = "disabled";
 890                         };
 891
 892                         i2c15: i2c@a9c000 {
 893                                 compatible = "qcom,geni-i2c";
 894                                 reg = <0 0x00a9c000 0 0x4000>;
 895                                 clock-names = "se";
 896                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
 897                                 pinctrl-names = "default";
 898                                 pinctrl-0 = <&qup_i2c15_default>;
 899                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
 900                                 #address-cells = <1>;
 901                                 #size-cells = <0>;
 902                                 power-domains = <&rpmhpd SDM670_CX>;
 903                                 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
 904                                                 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
 905                                                 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
 906                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 907                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
 908                                        <&gpi_dma1 1 7 QCOM_GPI_I2C>;
 909                                 dma-names = "tx", "rx";
 910                                 status = "disabled";
 911                         };
 912                 };
 913
 914                 mem_noc: interconnect@1380000 {
 915                         compatible = "qcom,sdm670-mem-noc";
 916                         reg = <0 0x01380000 0 0x27200>;
 917                         #interconnect-cells = <2>;
 918                         qcom,bcm-voters = <&apps_bcm_voter>;
 919                 };
 920
 921                 dc_noc: interconnect@14e0000 {
 922                         compatible = "qcom,sdm670-dc-noc";
 923                         reg = <0 0x014e0000 0 0x400>;
 924                         #interconnect-cells = <2>;
 925                         qcom,bcm-voters = <&apps_bcm_voter>;
 926                 };
 927
 928                 config_noc: interconnect@1500000 {
 929                         compatible = "qcom,sdm670-config-noc";
 930                         reg = <0 0x01500000 0 0x5080>;
 931                         #interconnect-cells = <2>;
 932                         qcom,bcm-voters = <&apps_bcm_voter>;
 933                 };
 934
 935                 system_noc: interconnect@1620000 {
 936                         compatible = "qcom,sdm670-system-noc";
 937                         reg = <0 0x01620000 0 0x18080>;
 938                         #interconnect-cells = <2>;
 939                         qcom,bcm-voters = <&apps_bcm_voter>;
 940                 };
 941
 942                 aggre1_noc: interconnect@16e0000 {
 943                         compatible = "qcom,sdm670-aggre1-noc";
 944                         reg = <0 0x016e0000 0 0x15080>;
 945                         #interconnect-cells = <2>;
 946                         qcom,bcm-voters = <&apps_bcm_voter>;
 947                 };
 948
 949                 aggre2_noc: interconnect@1700000 {
 950                         compatible = "qcom,sdm670-aggre2-noc";
 951                         reg = <0 0x01700000 0 0x1f300>;
 952                         #interconnect-cells = <2>;
 953                         qcom,bcm-voters = <&apps_bcm_voter>;
 954                 };
 955
 956                 mmss_noc: interconnect@1740000 {
 957                         compatible = "qcom,sdm670-mmss-noc";
 958                         reg = <0 0x01740000 0 0x1c100>;
 959                         #interconnect-cells = <2>;
 960                         qcom,bcm-voters = <&apps_bcm_voter>;
 961                 };
 962
 963                 tlmm: pinctrl@3400000 {
 964                         compatible = "qcom,sdm670-tlmm";
 965                         reg = <0 0x03400000 0 0xc00000>;
 966                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 967                         gpio-controller;
 968                         #gpio-cells = <2>;
 969                         interrupt-controller;
 970                         #interrupt-cells = <2>;
 971                         gpio-ranges = <&tlmm 0 0 151>;
 972
 973                         qup_i2c0_default: qup-i2c0-default-state {
 974                                 pins = "gpio0", "gpio1";
 975                                 function = "qup0";
 976                         };
 977
 978                         qup_i2c1_default: qup-i2c1-default-state {
 979                                 pins = "gpio17", "gpio18";
 980                                 function = "qup1";
 981                         };
 982
 983                         qup_i2c2_default: qup-i2c2-default-state {
 984                                 pins = "gpio27", "gpio28";
 985                                 function = "qup2";
 986                         };
 987
 988                         qup_i2c3_default: qup-i2c3-default-state {
 989                                 pins = "gpio41", "gpio42";
 990                                 function = "qup3";
 991                         };
 992
 993                         qup_i2c4_default: qup-i2c4-default-state {
 994                                 pins = "gpio89", "gpio90";
 995                                 function = "qup4";
 996                         };
 997
 998                         qup_i2c5_default: qup-i2c5-default-state {
 999                                 pins = "gpio85", "gpio86";
1000                                 function = "qup5";
1001                         };
1002
1003                         qup_i2c6_default: qup-i2c6-default-state {
1004                                 pins = "gpio45", "gpio46";
1005                                 function = "qup6";
1006                         };
1007
1008                         qup_i2c7_default: qup-i2c7-default-state {
1009                                 pins = "gpio93", "gpio94";
1010                                 function = "qup7";
1011                         };
1012
1013                         qup_i2c8_default: qup-i2c8-default-state {
1014                                 pins = "gpio65", "gpio66";
1015                                 function = "qup8";
1016                         };
1017
1018                         qup_i2c9_default: qup-i2c9-default-state {
1019                                 pins = "gpio6", "gpio7";
1020                                 function = "qup9";
1021                         };
1022
1023                         qup_i2c10_default: qup-i2c10-default-state {
1024                                 pins = "gpio55", "gpio56";
1025                                 function = "qup10";
1026                         };
1027
1028                         qup_i2c11_default: qup-i2c11-default-state {
1029                                 pins = "gpio31", "gpio32";
1030                                 function = "qup11";
1031                         };
1032
1033                         qup_i2c12_default: qup-i2c12-default-state {
1034                                 pins = "gpio49", "gpio50";
1035                                 function = "qup12";
1036                         };
1037
1038                         qup_i2c13_default: qup-i2c13-default-state {
1039                                 pins = "gpio105", "gpio106";
1040                                 function = "qup13";
1041                         };
1042
1043                         qup_i2c14_default: qup-i2c14-default-state {
1044                                 pins = "gpio33", "gpio34";
1045                                 function = "qup14";
1046                         };
1047
1048                         qup_i2c15_default: qup-i2c15-default-state {
1049                                 pins = "gpio81", "gpio82";
1050                                 function = "qup15";
1051                         };
1052
1053                         sdc1_state_on: sdc1-on-state {
1054                                 clk-pins {
1055                                         pins = "sdc1_clk";
1056                                         bias-disable;
1057                                         drive-strength = <16>;
1058                                 };
1059
1060                                 cmd-pins {
1061                                         pins = "sdc1_cmd";
1062                                         bias-pull-up;
1063                                         drive-strength = <10>;
1064                                 };
1065
1066                                 data-pins {
1067                                         pins = "sdc1_data";
1068                                         bias-pull-up;
1069                                         drive-strength = <10>;
1070                                 };
1071
1072                                 rclk-pins {
1073                                         pins = "sdc1_rclk";
1074                                         bias-pull-down;
1075                                 };
1076                         };
1077
1078                         sdc1_state_off: sdc1-off-state {
1079                                 clk-pins {
1080                                         pins = "sdc1_clk";
1081                                         bias-disable;
1082                                         drive-strength = <2>;
1083                                 };
1084
1085                                 cmd-pins {
1086                                         pins = "sdc1_cmd";
1087                                         bias-pull-up;
1088                                         drive-strength = <2>;
1089                                 };
1090
1091                                 data-pins {
1092                                         pins = "sdc1_data";
1093                                         bias-pull-up;
1094                                         drive-strength = <2>;
1095                                 };
1096
1097                                 rclk-pins {
1098                                         pins = "sdc1_rclk";
1099                                         bias-pull-down;
1100                                 };
1101                         };
1102                 };
1103
1104                 usb_1_hsphy: phy@88e2000 {
1105                         compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
1106                         reg = <0 0x088e2000 0 0x400>;
1107                         #phy-cells = <0>;
1108
1109                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1110                                  <&rpmhcc RPMH_CXO_CLK>;
1111                         clock-names = "cfg_ahb", "ref";
1112
1113                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1114
1115                         nvmem-cells = <&qusb2_hstx_trim>;
1116
1117                         status = "disabled";
1118                 };
1119
1120                 usb_1: usb@a6f8800 {
1121                         compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
1122                         reg = <0 0x0a6f8800 0 0x400>;
1123                         #address-cells = <2>;
1124                         #size-cells = <2>;
1125                         ranges;
1126                         dma-ranges;
1127
1128                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1129                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1130                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1131                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1132                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1133                         clock-names = "cfg_noc",
1134                                       "core",
1135                                       "iface",
1136                                       "sleep",
1137                                       "mock_utmi";
1138
1139                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1140                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1141                         assigned-clock-rates = <19200000>, <150000000>;
1142
1143                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1144                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
1145                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
1146                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
1147                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
1148                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
1149
1150                         power-domains = <&gcc USB30_PRIM_GDSC>;
1151
1152                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1153
1154                         interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>,
1155                                         <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1156                         interconnect-names = "usb-ddr", "apps-usb";
1157
1158                         status = "disabled";
1159
1160                         usb_1_dwc3: usb@a600000 {
1161                                 compatible = "snps,dwc3";
1162                                 reg = <0 0x0a600000 0 0xcd00>;
1163                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1164                                 iommus = <&apps_smmu 0x740 0>;
1165                                 snps,dis_u2_susphy_quirk;
1166                                 snps,dis_enblslpm_quirk;
1167                                 phys = <&usb_1_hsphy>;
1168                                 phy-names = "usb2-phy";
1169                         };
1170                 };
1171
1172                 spmi_bus: spmi@c440000 {
1173                         compatible = "qcom,spmi-pmic-arb";
1174                         reg = <0 0x0c440000 0 0x1100>,
1175                               <0 0x0c600000 0 0x2000000>,
1176                               <0 0x0e600000 0 0x100000>,
1177                               <0 0x0e700000 0 0xa0000>,
1178                               <0 0x0c40a000 0 0x26000>;
1179                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1180                         interrupt-names = "periph_irq";
1181                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
1182                         qcom,ee = <0>;
1183                         qcom,channel = <0>;
1184                         #address-cells = <2>;
1185                         #size-cells = <0>;
1186                         interrupt-controller;
1187                         #interrupt-cells = <4>;
1188                 };
1189
1190                 apps_smmu: iommu@15000000 {
1191                         compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1192                         reg = <0 0x15000000 0 0x80000>;
1193                         #iommu-cells = <2>;
1194                         #global-interrupts = <1>;
1195                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1196                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1197                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1198                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1199                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1200                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1201                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1202                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1203                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1204                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1205                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1206                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1207                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1208                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1209                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1210                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1211                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1212                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1213                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1214                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1215                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1216                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1217                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1218                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1219                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1220                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1221                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1222                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1223                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1224                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1225                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1226                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1227                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1228                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1229                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1230                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1231                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1232                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1233                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1234                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1235                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1236                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1237                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1238                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1239                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1240                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1241                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1242                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1243                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1244                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1245                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1246                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1247                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1248                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1249                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1250                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1251                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1252                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1253                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1254                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1255                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1256                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1257                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1258                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1259                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1260                 };
1261
1262                 gladiator_noc: interconnect@17900000 {
1263                         compatible = "qcom,sdm670-gladiator-noc";
1264                         reg = <0 0x17900000 0 0xd080>;
1265                         #interconnect-cells = <2>;
1266                         qcom,bcm-voters = <&apps_bcm_voter>;
1267                 };
1268
1269                 apps_rsc: rsc@179c0000 {
1270                         compatible = "qcom,rpmh-rsc";
1271                         reg = <0 0x179c0000 0 0x10000>,
1272                               <0 0x179d0000 0 0x10000>,
1273                               <0 0x179e0000 0 0x10000>;
1274                         reg-names = "drv-0", "drv-1", "drv-2";
1275                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1276                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1277                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1278                         label = "apps_rsc";
1279                         qcom,tcs-offset = <0xd00>;
1280                         qcom,drv-id = <2>;
1281                         qcom,tcs-config = <ACTIVE_TCS  2>,
1282                                           <SLEEP_TCS   3>,
1283                                           <WAKE_TCS    3>,
1284                                           <CONTROL_TCS 1>;
1285                         power-domains = <&CLUSTER_PD>;
1286
1287                         apps_bcm_voter: bcm-voter {
1288                                 compatible = "qcom,bcm-voter";
1289                         };
1290
1291                         rpmhcc: clock-controller {
1292                                 compatible = "qcom,sdm670-rpmh-clk";
1293                                 #clock-cells = <1>;
1294                                 clock-names = "xo";
1295                                 clocks = <&xo_board>;
1296                         };
1297
1298                         rpmhpd: power-controller {
1299                                 compatible = "qcom,sdm670-rpmhpd";
1300                                 #power-domain-cells = <1>;
1301                                 operating-points-v2 = <&rpmhpd_opp_table>;
1302
1303                                 rpmhpd_opp_table: opp-table {
1304                                         compatible = "operating-points-v2";
1305
1306                                         rpmhpd_opp_ret: opp1 {
1307                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1308                                         };
1309
1310                                         rpmhpd_opp_min_svs: opp2 {
1311                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1312                                         };
1313
1314                                         rpmhpd_opp_low_svs: opp3 {
1315                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1316                                         };
1317
1318                                         rpmhpd_opp_svs: opp4 {
1319                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1320                                         };
1321
1322                                         rpmhpd_opp_svs_l1: opp5 {
1323                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1324                                         };
1325
1326                                         rpmhpd_opp_nom: opp6 {
1327                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1328                                         };
1329
1330                                         rpmhpd_opp_nom_l1: opp7 {
1331                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1332                                         };
1333
1334                                         rpmhpd_opp_nom_l2: opp8 {
1335                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1336                                         };
1337
1338                                         rpmhpd_opp_turbo: opp9 {
1339                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1340                                         };
1341
1342                                         rpmhpd_opp_turbo_l1: opp10 {
1343                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1344                                         };
1345                                 };
1346                         };
1347                 };
1348
1349                 intc: interrupt-controller@17a00000 {
1350                         compatible = "arm,gic-v3";
1351                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
1352                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
1353                         interrupt-controller;
1354                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1355                         #interrupt-cells = <3>;
1356                 };
1357         };
1358 };