1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/soc/qcom,apr.h>
17 interrupt-parent = <&intc>;
26 compatible = "fixed-clock";
28 clock-frequency = <19200000>;
29 clock-output-names = "xo_board";
32 sleep_clk: sleep-clk {
33 compatible = "fixed-clock";
35 clock-frequency = <32764>;
36 clock-output-names = "sleep_clk";
46 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 cpu-idle-states = <&PERF_CPU_SLEEP_0
53 &PERF_CLUSTER_SLEEP_2>;
54 capacity-dmips-mhz = <1126>;
56 next-level-cache = <&L2_1>;
65 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 cpu-idle-states = <&PERF_CPU_SLEEP_0
72 &PERF_CLUSTER_SLEEP_2>;
73 capacity-dmips-mhz = <1126>;
75 next-level-cache = <&L2_1>;
80 compatible = "arm,cortex-a53";
82 enable-method = "psci";
83 cpu-idle-states = <&PERF_CPU_SLEEP_0
87 &PERF_CLUSTER_SLEEP_2>;
88 capacity-dmips-mhz = <1126>;
90 next-level-cache = <&L2_1>;
95 compatible = "arm,cortex-a53";
97 enable-method = "psci";
98 cpu-idle-states = <&PERF_CPU_SLEEP_0
100 &PERF_CLUSTER_SLEEP_0
101 &PERF_CLUSTER_SLEEP_1
102 &PERF_CLUSTER_SLEEP_2>;
103 capacity-dmips-mhz = <1126>;
104 #cooling-cells = <2>;
105 next-level-cache = <&L2_1>;
110 compatible = "arm,cortex-a53";
112 enable-method = "psci";
113 cpu-idle-states = <&PWR_CPU_SLEEP_0
117 &PWR_CLUSTER_SLEEP_2>;
118 capacity-dmips-mhz = <1024>;
119 #cooling-cells = <2>;
120 next-level-cache = <&L2_0>;
122 compatible = "cache";
129 compatible = "arm,cortex-a53";
131 enable-method = "psci";
132 cpu-idle-states = <&PWR_CPU_SLEEP_0
136 &PWR_CLUSTER_SLEEP_2>;
137 capacity-dmips-mhz = <1024>;
138 #cooling-cells = <2>;
139 next-level-cache = <&L2_0>;
144 compatible = "arm,cortex-a53";
146 enable-method = "psci";
147 cpu-idle-states = <&PWR_CPU_SLEEP_0
151 &PWR_CLUSTER_SLEEP_2>;
152 capacity-dmips-mhz = <1024>;
153 #cooling-cells = <2>;
154 next-level-cache = <&L2_0>;
159 compatible = "arm,cortex-a53";
161 enable-method = "psci";
162 cpu-idle-states = <&PWR_CPU_SLEEP_0
166 &PWR_CLUSTER_SLEEP_2>;
167 capacity-dmips-mhz = <1024>;
168 #cooling-cells = <2>;
169 next-level-cache = <&L2_0>;
211 entry-method = "psci";
213 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
214 compatible = "arm,idle-state";
215 idle-state-name = "pwr-retention";
216 arm,psci-suspend-param = <0x40000002>;
217 entry-latency-us = <338>;
218 exit-latency-us = <423>;
219 min-residency-us = <200>;
222 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
223 compatible = "arm,idle-state";
224 idle-state-name = "pwr-power-collapse";
225 arm,psci-suspend-param = <0x40000003>;
226 entry-latency-us = <515>;
227 exit-latency-us = <1821>;
228 min-residency-us = <1000>;
232 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
233 compatible = "arm,idle-state";
234 idle-state-name = "perf-retention";
235 arm,psci-suspend-param = <0x40000002>;
236 entry-latency-us = <154>;
237 exit-latency-us = <87>;
238 min-residency-us = <200>;
241 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
242 compatible = "arm,idle-state";
243 idle-state-name = "perf-power-collapse";
244 arm,psci-suspend-param = <0x40000003>;
245 entry-latency-us = <262>;
246 exit-latency-us = <301>;
247 min-residency-us = <1000>;
251 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
252 compatible = "arm,idle-state";
253 idle-state-name = "pwr-cluster-dynamic-retention";
254 arm,psci-suspend-param = <0x400000F2>;
255 entry-latency-us = <284>;
256 exit-latency-us = <384>;
257 min-residency-us = <9987>;
261 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
262 compatible = "arm,idle-state";
263 idle-state-name = "pwr-cluster-retention";
264 arm,psci-suspend-param = <0x400000F3>;
265 entry-latency-us = <338>;
266 exit-latency-us = <423>;
267 min-residency-us = <9987>;
271 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
272 compatible = "arm,idle-state";
273 idle-state-name = "pwr-cluster-retention";
274 arm,psci-suspend-param = <0x400000F4>;
275 entry-latency-us = <515>;
276 exit-latency-us = <1821>;
277 min-residency-us = <9987>;
281 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
282 compatible = "arm,idle-state";
283 idle-state-name = "perf-cluster-dynamic-retention";
284 arm,psci-suspend-param = <0x400000F2>;
285 entry-latency-us = <272>;
286 exit-latency-us = <329>;
287 min-residency-us = <9987>;
291 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
292 compatible = "arm,idle-state";
293 idle-state-name = "perf-cluster-retention";
294 arm,psci-suspend-param = <0x400000F3>;
295 entry-latency-us = <332>;
296 exit-latency-us = <368>;
297 min-residency-us = <9987>;
301 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
302 compatible = "arm,idle-state";
303 idle-state-name = "perf-cluster-retention";
304 arm,psci-suspend-param = <0x400000F4>;
305 entry-latency-us = <545>;
306 exit-latency-us = <1609>;
307 min-residency-us = <9987>;
315 compatible = "qcom,scm-msm8998", "qcom,scm";
320 device_type = "memory";
321 /* We expect the bootloader to fill in the reg */
322 reg = <0x0 0x80000000 0x0 0x0>;
326 compatible = "arm,armv8-pmuv3";
327 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
331 compatible = "arm,psci-1.0";
336 #address-cells = <2>;
340 wlan_msa_guard: wlan-msa-guard@85600000 {
341 reg = <0x0 0x85600000 0x0 0x100000>;
345 wlan_msa_mem: wlan-msa-mem@85700000 {
346 reg = <0x0 0x85700000 0x0 0x100000>;
350 qhee_code: qhee-code@85800000 {
351 reg = <0x0 0x85800000 0x0 0x600000>;
355 rmtfs_mem: memory@85e00000 {
356 compatible = "qcom,rmtfs-mem";
357 reg = <0x0 0x85e00000 0x0 0x200000>;
360 qcom,client-id = <1>;
364 smem_region: smem-mem@86000000 {
365 reg = <0 0x86000000 0 0x200000>;
369 tz_mem: memory@86200000 {
370 reg = <0x0 0x86200000 0x0 0x3300000>;
374 mpss_region: mpss@8ac00000 {
375 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
379 adsp_region: adsp@92a00000 {
380 reg = <0x0 0x92a00000 0x0 0x1e00000>;
384 mba_region: mba@94800000 {
385 reg = <0x0 0x94800000 0x0 0x200000>;
389 buffer_mem: tzbuffer@94a00000 {
390 reg = <0x0 0x94a00000 0x0 0x100000>;
394 venus_region: venus@9f800000 {
395 reg = <0x0 0x9f800000 0x0 0x800000>;
399 adsp_mem: adsp-region@f6000000 {
400 reg = <0x0 0xf6000000 0x0 0x800000>;
404 qseecom_mem: qseecom-region@f6800000 {
405 reg = <0x0 0xf6800000 0x0 0x1400000>;
409 zap_shader_region: gpu@fed00000 {
410 compatible = "shared-dma-pool";
411 reg = <0x0 0xfed00000 0x0 0xa00000>;
417 compatible = "qcom,glink-rpm";
419 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
420 qcom,rpm-msg-ram = <&rpm_msg_ram>;
421 mboxes = <&apcs_glb 0>;
423 rpm_requests: rpm-requests {
424 compatible = "qcom,rpm-sdm660";
425 qcom,glink-channels = "rpm_requests";
427 rpmcc: clock-controller {
428 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
432 rpmpd: power-controller {
433 compatible = "qcom,sdm660-rpmpd";
434 #power-domain-cells = <1>;
435 operating-points-v2 = <&rpmpd_opp_table>;
437 rpmpd_opp_table: opp-table {
438 compatible = "operating-points-v2";
440 rpmpd_opp_ret: opp1 {
441 opp-level = <RPM_SMD_LEVEL_RETENTION>;
444 rpmpd_opp_ret_plus: opp2 {
445 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
448 rpmpd_opp_min_svs: opp3 {
449 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
452 rpmpd_opp_low_svs: opp4 {
453 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
456 rpmpd_opp_svs: opp5 {
457 opp-level = <RPM_SMD_LEVEL_SVS>;
460 rpmpd_opp_svs_plus: opp6 {
461 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
464 rpmpd_opp_nom: opp7 {
465 opp-level = <RPM_SMD_LEVEL_NOM>;
468 rpmpd_opp_nom_plus: opp8 {
469 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
472 rpmpd_opp_turbo: opp9 {
473 opp-level = <RPM_SMD_LEVEL_TURBO>;
481 compatible = "qcom,smem";
482 memory-region = <&smem_region>;
483 hwlocks = <&tcsr_mutex 3>;
487 compatible = "qcom,smp2p";
488 qcom,smem = <443>, <429>;
489 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
490 mboxes = <&apcs_glb 10>;
491 qcom,local-pid = <0>;
492 qcom,remote-pid = <2>;
494 adsp_smp2p_out: master-kernel {
495 qcom,entry-name = "master-kernel";
496 #qcom,smem-state-cells = <1>;
499 adsp_smp2p_in: slave-kernel {
500 qcom,entry-name = "slave-kernel";
501 interrupt-controller;
502 #interrupt-cells = <2>;
507 compatible = "qcom,smp2p";
508 qcom,smem = <435>, <428>;
509 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
510 mboxes = <&apcs_glb 14>;
511 qcom,local-pid = <0>;
512 qcom,remote-pid = <1>;
514 modem_smp2p_out: master-kernel {
515 qcom,entry-name = "master-kernel";
516 #qcom,smem-state-cells = <1>;
519 modem_smp2p_in: slave-kernel {
520 qcom,entry-name = "slave-kernel";
521 interrupt-controller;
522 #interrupt-cells = <2>;
527 #address-cells = <1>;
529 ranges = <0 0 0 0xffffffff>;
530 compatible = "simple-bus";
532 gcc: clock-controller@100000 {
533 compatible = "qcom,gcc-sdm630";
536 #power-domain-cells = <1>;
537 reg = <0x00100000 0x94000>;
539 clock-names = "xo", "sleep_clk";
540 clocks = <&xo_board>,
544 rpm_msg_ram: memory@778000 {
545 compatible = "qcom,rpm-msg-ram";
546 reg = <0x00778000 0x7000>;
549 qfprom: qfprom@780000 {
550 compatible = "qcom,qfprom";
551 reg = <0x00780000 0x621c>;
552 #address-cells = <1>;
555 qusb2_hstx_trim: hstx-trim@240 {
560 gpu_speed_bin: gpu-speed-bin@41a0 {
567 compatible = "qcom,prng-ee";
568 reg = <0x00793000 0x1000>;
569 clocks = <&gcc GCC_PRNG_AHB_CLK>;
570 clock-names = "core";
573 bimc: interconnect@1008000 {
574 compatible = "qcom,sdm660-bimc";
575 reg = <0x01008000 0x78000>;
576 #interconnect-cells = <1>;
577 clock-names = "bus", "bus_a";
578 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
579 <&rpmcc RPM_SMD_BIMC_A_CLK>;
583 compatible = "qcom,pshold";
584 reg = <0x010ac000 0x4>;
587 cnoc: interconnect@1500000 {
588 compatible = "qcom,sdm660-cnoc";
589 reg = <0x01500000 0x10000>;
590 #interconnect-cells = <1>;
591 clock-names = "bus", "bus_a";
592 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
593 <&rpmcc RPM_SMD_CNOC_A_CLK>;
596 snoc: interconnect@1626000 {
597 compatible = "qcom,sdm660-snoc";
598 reg = <0x01626000 0x7090>;
599 #interconnect-cells = <1>;
600 clock-names = "bus", "bus_a";
601 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
602 <&rpmcc RPM_SMD_SNOC_A_CLK>;
605 anoc2_smmu: iommu@16c0000 {
606 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
607 reg = <0x016c0000 0x40000>;
609 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
610 assigned-clock-rates = <1000>;
611 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
613 #global-interrupts = <2>;
617 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
622 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
623 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
624 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
625 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
626 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
653 a2noc: interconnect@1704000 {
654 compatible = "qcom,sdm660-a2noc";
655 reg = <0x01704000 0xc100>;
656 #interconnect-cells = <1>;
657 clock-names = "bus", "bus_a";
658 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
659 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
662 mnoc: interconnect@1745000 {
663 compatible = "qcom,sdm660-mnoc";
664 reg = <0x01745000 0xA010>;
665 #interconnect-cells = <1>;
666 clock-names = "bus", "bus_a", "iface";
667 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
668 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
672 tsens: thermal-sensor@10ae000 {
673 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
674 reg = <0x010ae000 0x1000>, /* TM */
675 <0x010ad000 0x1000>; /* SROT */
676 #qcom,sensors = <12>;
677 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
679 interrupt-names = "uplow", "critical";
680 #thermal-sensor-cells = <1>;
683 tcsr_mutex_regs: syscon@1f40000 {
684 compatible = "syscon";
685 reg = <0x01f40000 0x40000>;
688 tlmm: pinctrl@3100000 {
689 compatible = "qcom,sdm630-pinctrl";
690 reg = <0x03100000 0x400000>,
691 <0x03500000 0x400000>,
692 <0x03900000 0x400000>;
693 reg-names = "south", "center", "north";
694 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
696 gpio-ranges = <&tlmm 0 0 114>;
698 interrupt-controller;
699 #interrupt-cells = <2>;
701 blsp1_uart1_default: blsp1-uart1-default {
702 pins = "gpio0", "gpio1", "gpio2", "gpio3";
703 drive-strength = <2>;
707 blsp1_uart1_sleep: blsp1-uart1-sleep {
708 pins = "gpio0", "gpio1", "gpio2", "gpio3";
709 drive-strength = <2>;
713 blsp1_uart2_default: blsp1-uart2-default {
714 pins = "gpio4", "gpio5";
715 drive-strength = <2>;
719 blsp2_uart1_default: blsp2-uart1-active {
721 pins = "gpio16", "gpio19";
722 function = "blsp_uart5";
723 drive-strength = <2>;
729 * Avoid garbage data while BT module
730 * is powered off or not driving signal
733 function = "blsp_uart5";
734 drive-strength = <2>;
739 /* Match the pull of the BT module */
741 function = "blsp_uart5";
742 drive-strength = <2>;
747 blsp2_uart1_sleep: blsp2-uart1-sleep {
751 drive-strength = <2>;
756 pins = "gpio17", "gpio18", "gpio19";
758 drive-strength = <2>;
763 i2c1_default: i2c1-default {
764 pins = "gpio2", "gpio3";
765 function = "blsp_i2c1";
766 drive-strength = <2>;
770 i2c1_sleep: i2c1-sleep {
771 pins = "gpio2", "gpio3";
772 function = "blsp_i2c1";
773 drive-strength = <2>;
777 i2c2_default: i2c2-default {
778 pins = "gpio6", "gpio7";
779 function = "blsp_i2c2";
780 drive-strength = <2>;
784 i2c2_sleep: i2c2-sleep {
785 pins = "gpio6", "gpio7";
786 function = "blsp_i2c2";
787 drive-strength = <2>;
791 i2c3_default: i2c3-default {
792 pins = "gpio10", "gpio11";
793 function = "blsp_i2c3";
794 drive-strength = <2>;
798 i2c3_sleep: i2c3-sleep {
799 pins = "gpio10", "gpio11";
800 function = "blsp_i2c3";
801 drive-strength = <2>;
805 i2c4_default: i2c4-default {
806 pins = "gpio14", "gpio15";
807 function = "blsp_i2c4";
808 drive-strength = <2>;
812 i2c4_sleep: i2c4-sleep {
813 pins = "gpio14", "gpio15";
814 function = "blsp_i2c4";
815 drive-strength = <2>;
819 i2c5_default: i2c5-default {
820 pins = "gpio18", "gpio19";
821 function = "blsp_i2c5";
822 drive-strength = <2>;
826 i2c5_sleep: i2c5-sleep {
827 pins = "gpio18", "gpio19";
828 function = "blsp_i2c5";
829 drive-strength = <2>;
833 i2c6_default: i2c6-default {
834 pins = "gpio22", "gpio23";
835 function = "blsp_i2c6";
836 drive-strength = <2>;
840 i2c6_sleep: i2c6-sleep {
841 pins = "gpio22", "gpio23";
842 function = "blsp_i2c6";
843 drive-strength = <2>;
847 i2c7_default: i2c7-default {
848 pins = "gpio26", "gpio27";
849 function = "blsp_i2c7";
850 drive-strength = <2>;
854 i2c7_sleep: i2c7-sleep {
855 pins = "gpio26", "gpio27";
856 function = "blsp_i2c7";
857 drive-strength = <2>;
861 i2c8_default: i2c8-default {
862 pins = "gpio30", "gpio31";
863 function = "blsp_i2c8";
864 drive-strength = <2>;
868 i2c8_sleep: i2c8-sleep {
869 pins = "gpio30", "gpio31";
870 function = "blsp_i2c8";
871 drive-strength = <2>;
875 cci0_default: cci0_default {
877 pins = "gpio36","gpio37";
878 function = "cci_i2c";
882 pins = "gpio36","gpio37";
884 drive-strength = <2>;
888 cci1_default: cci1_default {
890 pins = "gpio38","gpio39";
891 function = "cci_i2c";
895 pins = "gpio38","gpio39";
897 drive-strength = <2>;
901 sdc1_state_on: sdc1-on {
905 drive-strength = <16>;
911 drive-strength = <10>;
917 drive-strength = <10>;
926 sdc1_state_off: sdc1-off {
930 drive-strength = <2>;
936 drive-strength = <2>;
942 drive-strength = <2>;
951 sdc2_state_on: sdc2-on {
955 drive-strength = <16>;
961 drive-strength = <10>;
967 drive-strength = <10>;
973 drive-strength = <2>;
977 sdc2_state_off: sdc2-off {
981 drive-strength = <2>;
987 drive-strength = <2>;
993 drive-strength = <2>;
999 drive-strength = <2>;
1004 adreno_gpu: gpu@5000000 {
1005 compatible = "qcom,adreno-508.0", "qcom,adreno";
1006 #stream-id-cells = <16>;
1008 reg = <0x05000000 0x40000>;
1009 reg-names = "kgsl_3d0_reg_memory";
1011 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1014 <&gpucc GPUCC_RBBMTIMER_CLK>,
1015 <&gcc GCC_BIMC_GFX_CLK>,
1016 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1017 <&gpucc GPUCC_RBCPR_CLK>,
1018 <&gpucc GPUCC_GFX3D_CLK>;
1020 clock-names = "iface",
1027 power-domains = <&rpmpd SDM660_VDDMX>;
1028 iommus = <&kgsl_smmu 0>;
1030 nvmem-cells = <&gpu_speed_bin>;
1031 nvmem-cell-names = "speed_bin";
1033 interconnects = <&gnoc 1 &bimc 5>;
1034 interconnect-names = "gfx-mem";
1036 operating-points-v2 = <&gpu_sdm630_opp_table>;
1038 gpu_sdm630_opp_table: opp-table {
1039 compatible = "operating-points-v2";
1041 opp-hz = /bits/ 64 <775000000>;
1042 opp-level = <RPM_SMD_LEVEL_TURBO>;
1043 opp-peak-kBps = <5412000>;
1044 opp-supported-hw = <0xA2>;
1047 opp-hz = /bits/ 64 <647000000>;
1048 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1049 opp-peak-kBps = <4068000>;
1050 opp-supported-hw = <0xFF>;
1053 opp-hz = /bits/ 64 <588000000>;
1054 opp-level = <RPM_SMD_LEVEL_NOM>;
1055 opp-peak-kBps = <3072000>;
1056 opp-supported-hw = <0xFF>;
1059 opp-hz = /bits/ 64 <465000000>;
1060 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1061 opp-peak-kBps = <2724000>;
1062 opp-supported-hw = <0xFF>;
1065 opp-hz = /bits/ 64 <370000000>;
1066 opp-level = <RPM_SMD_LEVEL_SVS>;
1067 opp-peak-kBps = <2188000>;
1068 opp-supported-hw = <0xFF>;
1071 opp-hz = /bits/ 64 <240000000>;
1072 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1073 opp-peak-kBps = <1648000>;
1074 opp-supported-hw = <0xFF>;
1077 opp-hz = /bits/ 64 <160000000>;
1078 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1079 opp-peak-kBps = <1200000>;
1080 opp-supported-hw = <0xFF>;
1085 kgsl_smmu: iommu@5040000 {
1086 compatible = "qcom,sdm630-smmu-v2",
1087 "qcom,adreno-smmu", "qcom,smmu-v2";
1088 reg = <0x05040000 0x10000>;
1091 * GX GDSC parent is CX. We need to bring up CX for SMMU
1092 * but we need both up for Adreno. On the other hand, we
1093 * need to manage the GX rpmpd domain in the adreno driver.
1094 * Enable CX/GX GDSCs here so that we can manage just the GX
1095 * RPM Power Domain in the Adreno driver.
1097 power-domains = <&gpucc GPU_GX_GDSC>;
1098 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1099 <&gcc GCC_BIMC_GFX_CLK>,
1100 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1101 clock-names = "iface", "mem", "mem_iface";
1102 #global-interrupts = <2>;
1106 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1115 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
1118 status = "disabled";
1121 gpucc: clock-controller@5065000 {
1122 compatible = "qcom,gpucc-sdm630";
1125 #power-domain-cells = <1>;
1126 reg = <0x05065000 0x9038>;
1128 clocks = <&xo_board>,
1129 <&gcc GCC_GPU_GPLL0_CLK>,
1130 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1132 "gcc_gpu_gpll0_clk",
1133 "gcc_gpu_gpll0_div_clk";
1134 status = "disabled";
1137 lpass_smmu: iommu@5100000 {
1138 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1139 reg = <0x05100000 0x40000>;
1142 #global-interrupts = <2>;
1144 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1150 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1151 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1152 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1165 status = "disabled";
1168 spmi_bus: spmi@800f000 {
1169 compatible = "qcom,spmi-pmic-arb";
1170 reg = <0x0800f000 0x1000>,
1171 <0x08400000 0x1000000>,
1172 <0x09400000 0x1000000>,
1173 <0x0a400000 0x220000>,
1174 <0x0800a000 0x3000>;
1175 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1176 interrupt-names = "periph_irq";
1177 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1180 #address-cells = <2>;
1182 interrupt-controller;
1183 #interrupt-cells = <4>;
1188 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1189 reg = <0x0a8f8800 0x400>;
1190 status = "disabled";
1191 #address-cells = <1>;
1195 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1196 <&gcc GCC_USB30_MASTER_CLK>,
1197 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1198 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
1199 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1200 <&gcc GCC_USB30_SLEEP_CLK>;
1201 clock-names = "cfg_noc", "core", "iface", "bus",
1202 "mock_utmi", "sleep";
1204 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1205 <&gcc GCC_USB30_MASTER_CLK>,
1206 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1207 assigned-clock-rates = <19200000>, <120000000>,
1210 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1212 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1214 power-domains = <&gcc USB_30_GDSC>;
1215 qcom,select-utmi-as-pipe-clk;
1217 resets = <&gcc GCC_USB_30_BCR>;
1219 usb3_dwc3: usb@a800000 {
1220 compatible = "snps,dwc3";
1221 reg = <0x0a800000 0xc8d0>;
1222 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1223 snps,dis_u2_susphy_quirk;
1224 snps,dis_enblslpm_quirk;
1227 * SDM630 technically supports USB3 but I
1228 * haven't seen any devices making use of it.
1230 maximum-speed = "high-speed";
1232 phy-names = "usb2-phy";
1233 snps,hird-threshold = /bits/ 8 <0>;
1237 qusb2phy: phy@c012000 {
1238 compatible = "qcom,sdm660-qusb2-phy";
1239 reg = <0x0c012000 0x180>;
1242 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1243 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1244 clock-names = "cfg_ahb", "ref";
1246 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1247 nvmem-cells = <&qusb2_hstx_trim>;
1248 status = "disabled";
1251 sdhc_2: sdhci@c084000 {
1252 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1253 reg = <0x0c084000 0x1000>;
1256 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1258 interrupt-names = "hc_irq", "pwr_irq";
1261 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1262 <&gcc GCC_SDCC2_AHB_CLK>,
1264 clock-names = "core", "iface", "xo";
1266 interconnects = <&a2noc 3 &a2noc 10>,
1268 operating-points-v2 = <&sdhc2_opp_table>;
1270 pinctrl-names = "default", "sleep";
1271 pinctrl-0 = <&sdc2_state_on>;
1272 pinctrl-1 = <&sdc2_state_off>;
1273 power-domains = <&rpmpd SDM660_VDDCX>;
1275 status = "disabled";
1277 sdhc2_opp_table: opp-table {
1278 compatible = "operating-points-v2";
1281 opp-hz = /bits/ 64 <50000000>;
1282 required-opps = <&rpmpd_opp_low_svs>;
1283 opp-peak-kBps = <200000 140000>;
1284 opp-avg-kBps = <130718 133320>;
1287 opp-hz = /bits/ 64 <100000000>;
1288 required-opps = <&rpmpd_opp_svs>;
1289 opp-peak-kBps = <250000 160000>;
1290 opp-avg-kBps = <196078 150000>;
1293 opp-hz = /bits/ 64 <200000000>;
1294 required-opps = <&rpmpd_opp_nom>;
1295 opp-peak-kBps = <4096000 4096000>;
1296 opp-avg-kBps = <1338562 1338562>;
1301 sdhc_1: sdhci@c0c4000 {
1302 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1303 reg = <0x0c0c4000 0x1000>,
1304 <0x0c0c5000 0x1000>,
1305 <0x0c0c8000 0x8000>;
1306 reg-names = "hc", "cqhci", "ice";
1308 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1309 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1310 interrupt-names = "hc_irq", "pwr_irq";
1312 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
1313 <&gcc GCC_SDCC1_AHB_CLK>,
1315 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1316 clock-names = "core", "iface", "xo", "ice";
1318 interconnects = <&a2noc 2 &a2noc 10>,
1320 interconnect-names = "sdhc1-ddr", "cpu-sdhc1";
1321 operating-points-v2 = <&sdhc1_opp_table>;
1322 pinctrl-names = "default", "sleep";
1323 pinctrl-0 = <&sdc1_state_on>;
1324 pinctrl-1 = <&sdc1_state_off>;
1325 power-domains = <&rpmpd SDM660_VDDCX>;
1330 status = "disabled";
1332 sdhc1_opp_table: opp-table {
1333 compatible = "operating-points-v2";
1336 opp-hz = /bits/ 64 <50000000>;
1337 required-opps = <&rpmpd_opp_low_svs>;
1338 opp-peak-kBps = <200000 140000>;
1339 opp-avg-kBps = <130718 133320>;
1342 opp-hz = /bits/ 64 <100000000>;
1343 required-opps = <&rpmpd_opp_svs>;
1344 opp-peak-kBps = <250000 160000>;
1345 opp-avg-kBps = <196078 150000>;
1348 opp-hz = /bits/ 64 <384000000>;
1349 required-opps = <&rpmpd_opp_nom>;
1350 opp-peak-kBps = <4096000 4096000>;
1351 opp-avg-kBps = <1338562 1338562>;
1356 mmcc: clock-controller@c8c0000 {
1357 compatible = "qcom,mmcc-sdm630";
1358 reg = <0x0c8c0000 0x40000>;
1361 #power-domain-cells = <1>;
1370 "dp_link_2x_clk_divsel_five",
1371 "dp_vco_divided_clk_src_mux";
1372 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1374 <&gcc GCC_MMSS_GPLL0_CLK>,
1375 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
1384 dsi_opp_table: dsi-opp-table {
1385 compatible = "operating-points-v2";
1388 opp-hz = /bits/ 64 <131250000>;
1389 required-opps = <&rpmpd_opp_svs>;
1393 opp-hz = /bits/ 64 <210000000>;
1394 required-opps = <&rpmpd_opp_svs_plus>;
1398 opp-hz = /bits/ 64 <262500000>;
1399 required-opps = <&rpmpd_opp_nom>;
1403 mdss: mdss@c900000 {
1404 compatible = "qcom,mdss";
1405 reg = <0x0c900000 0x1000>,
1406 <0x0c9b0000 0x1040>;
1407 reg-names = "mdss_phys", "vbif_phys";
1409 power-domains = <&mmcc MDSS_GDSC>;
1411 clocks = <&mmcc MDSS_AHB_CLK>,
1412 <&mmcc MDSS_AXI_CLK>,
1413 <&mmcc MDSS_VSYNC_CLK>,
1414 <&mmcc MDSS_MDP_CLK>;
1415 clock-names = "iface",
1420 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1422 interrupt-controller;
1423 #interrupt-cells = <1>;
1425 #address-cells = <1>;
1428 status = "disabled";
1431 compatible = "qcom,mdp5";
1432 reg = <0x0c901000 0x89000>;
1433 reg-names = "mdp_phys";
1435 interrupt-parent = <&mdss>;
1436 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1438 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1439 <&mmcc MDSS_VSYNC_CLK>;
1440 assigned-clock-rates = <300000000>,
1442 clocks = <&mmcc MDSS_AHB_CLK>,
1443 <&mmcc MDSS_AXI_CLK>,
1444 <&mmcc MDSS_MDP_CLK>,
1445 <&mmcc MDSS_VSYNC_CLK>;
1446 clock-names = "iface",
1451 interconnects = <&mnoc 2 &bimc 5>,
1454 interconnect-names = "mdp0-mem",
1457 iommus = <&mmss_smmu 0>;
1458 operating-points-v2 = <&mdp_opp_table>;
1459 power-domains = <&rpmpd SDM660_VDDCX>;
1462 #address-cells = <1>;
1467 mdp5_intf1_out: endpoint {
1468 remote-endpoint = <&dsi0_in>;
1473 mdp_opp_table: mdp-opp {
1474 compatible = "operating-points-v2";
1477 opp-hz = /bits/ 64 <150000000>;
1478 opp-peak-kBps = <320000 320000 76800>;
1479 required-opps = <&rpmpd_opp_low_svs>;
1482 opp-hz = /bits/ 64 <275000000>;
1483 opp-peak-kBps = <6400000 6400000 160000>;
1484 required-opps = <&rpmpd_opp_svs>;
1487 opp-hz = /bits/ 64 <300000000>;
1488 opp-peak-kBps = <6400000 6400000 190000>;
1489 required-opps = <&rpmpd_opp_svs_plus>;
1492 opp-hz = /bits/ 64 <330000000>;
1493 opp-peak-kBps = <6400000 6400000 240000>;
1494 required-opps = <&rpmpd_opp_nom>;
1497 opp-hz = /bits/ 64 <412500000>;
1498 opp-peak-kBps = <6400000 6400000 320000>;
1499 required-opps = <&rpmpd_opp_turbo>;
1505 compatible = "qcom,mdss-dsi-ctrl";
1506 reg = <0x0c994000 0x400>;
1507 reg-names = "dsi_ctrl";
1509 operating-points-v2 = <&dsi_opp_table>;
1510 power-domains = <&rpmpd SDM660_VDDCX>;
1512 interrupt-parent = <&mdss>;
1513 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1515 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1516 <&mmcc PCLK0_CLK_SRC>;
1517 assigned-clock-parents = <&dsi0_phy 0>,
1520 clocks = <&mmcc MDSS_MDP_CLK>,
1521 <&mmcc MDSS_BYTE0_CLK>,
1522 <&mmcc MDSS_BYTE0_INTF_CLK>,
1523 <&mmcc MNOC_AHB_CLK>,
1524 <&mmcc MDSS_AHB_CLK>,
1525 <&mmcc MDSS_AXI_CLK>,
1526 <&mmcc MISC_AHB_CLK>,
1527 <&mmcc MDSS_PCLK0_CLK>,
1528 <&mmcc MDSS_ESC0_CLK>;
1529 clock-names = "mdp_core",
1543 #address-cells = <1>;
1549 remote-endpoint = <&mdp5_intf1_out>;
1555 dsi0_out: endpoint {
1561 dsi0_phy: dsi-phy@c994400 {
1562 compatible = "qcom,dsi-phy-14nm-660";
1563 reg = <0x0c994400 0x100>,
1566 reg-names = "dsi_phy",
1573 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1574 clock-names = "iface", "ref";
1578 blsp1_dma: dma-controller@c144000 {
1579 compatible = "qcom,bam-v1.7.0";
1580 reg = <0x0c144000 0x1f000>;
1581 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1582 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1583 clock-names = "bam_clk";
1586 qcom,controlled-remotely;
1587 num-channels = <18>;
1591 blsp1_uart1: serial@c16f000 {
1592 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1593 reg = <0x0c16f000 0x200>;
1594 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1595 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1596 <&gcc GCC_BLSP1_AHB_CLK>;
1597 clock-names = "core", "iface";
1598 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1599 dma-names = "tx", "rx";
1600 pinctrl-names = "default", "sleep";
1601 pinctrl-0 = <&blsp1_uart1_default>;
1602 pinctrl-1 = <&blsp1_uart1_sleep>;
1603 status = "disabled";
1606 blsp1_uart2: serial@c170000 {
1607 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1608 reg = <0x0c170000 0x1000>;
1609 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1610 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1611 <&gcc GCC_BLSP1_AHB_CLK>;
1612 clock-names = "core", "iface";
1613 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1614 dma-names = "tx", "rx";
1615 pinctrl-names = "default";
1616 pinctrl-0 = <&blsp1_uart2_default>;
1617 status = "disabled";
1620 blsp_i2c1: i2c@c175000 {
1621 compatible = "qcom,i2c-qup-v2.2.1";
1622 reg = <0x0c175000 0x600>;
1623 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1625 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1626 <&gcc GCC_BLSP1_AHB_CLK>;
1627 clock-names = "core", "iface";
1628 clock-frequency = <400000>;
1629 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1630 dma-names = "tx", "rx";
1632 pinctrl-names = "default", "sleep";
1633 pinctrl-0 = <&i2c1_default>;
1634 pinctrl-1 = <&i2c1_sleep>;
1635 #address-cells = <1>;
1637 status = "disabled";
1640 blsp_i2c2: i2c@c176000 {
1641 compatible = "qcom,i2c-qup-v2.2.1";
1642 reg = <0x0c176000 0x600>;
1643 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1645 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1646 <&gcc GCC_BLSP1_AHB_CLK>;
1647 clock-names = "core", "iface";
1648 clock-frequency = <400000>;
1649 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1650 dma-names = "tx", "rx";
1652 pinctrl-names = "default", "sleep";
1653 pinctrl-0 = <&i2c2_default>;
1654 pinctrl-1 = <&i2c2_sleep>;
1655 #address-cells = <1>;
1657 status = "disabled";
1660 blsp_i2c3: i2c@c177000 {
1661 compatible = "qcom,i2c-qup-v2.2.1";
1662 reg = <0x0c177000 0x600>;
1663 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1665 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1666 <&gcc GCC_BLSP1_AHB_CLK>;
1667 clock-names = "core", "iface";
1668 clock-frequency = <400000>;
1669 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1670 dma-names = "tx", "rx";
1672 pinctrl-names = "default", "sleep";
1673 pinctrl-0 = <&i2c3_default>;
1674 pinctrl-1 = <&i2c3_sleep>;
1675 #address-cells = <1>;
1677 status = "disabled";
1680 blsp_i2c4: i2c@c178000 {
1681 compatible = "qcom,i2c-qup-v2.2.1";
1682 reg = <0x0c178000 0x600>;
1683 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1685 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1686 <&gcc GCC_BLSP1_AHB_CLK>;
1687 clock-names = "core", "iface";
1688 clock-frequency = <400000>;
1689 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
1690 dma-names = "tx", "rx";
1692 pinctrl-names = "default", "sleep";
1693 pinctrl-0 = <&i2c4_default>;
1694 pinctrl-1 = <&i2c4_sleep>;
1695 #address-cells = <1>;
1697 status = "disabled";
1700 blsp2_dma: dma-controller@c184000 {
1701 compatible = "qcom,bam-v1.7.0";
1702 reg = <0x0c184000 0x1f000>;
1703 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1704 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1705 clock-names = "bam_clk";
1708 qcom,controlled-remotely;
1709 num-channels = <18>;
1713 blsp2_uart1: serial@c1af000 {
1714 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1715 reg = <0x0c1af000 0x200>;
1716 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1717 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1718 <&gcc GCC_BLSP2_AHB_CLK>;
1719 clock-names = "core", "iface";
1720 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1721 dma-names = "tx", "rx";
1722 pinctrl-names = "default", "sleep";
1723 pinctrl-0 = <&blsp2_uart1_default>;
1724 pinctrl-1 = <&blsp2_uart1_sleep>;
1725 status = "disabled";
1728 blsp_i2c5: i2c@c1b5000 {
1729 compatible = "qcom,i2c-qup-v2.2.1";
1730 reg = <0x0c1b5000 0x600>;
1731 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1733 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1734 <&gcc GCC_BLSP2_AHB_CLK>;
1735 clock-names = "core", "iface";
1736 clock-frequency = <400000>;
1737 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1738 dma-names = "tx", "rx";
1740 pinctrl-names = "default", "sleep";
1741 pinctrl-0 = <&i2c5_default>;
1742 pinctrl-1 = <&i2c5_sleep>;
1743 #address-cells = <1>;
1745 status = "disabled";
1748 blsp_i2c6: i2c@c1b6000 {
1749 compatible = "qcom,i2c-qup-v2.2.1";
1750 reg = <0x0c1b6000 0x600>;
1751 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1753 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1754 <&gcc GCC_BLSP2_AHB_CLK>;
1755 clock-names = "core", "iface";
1756 clock-frequency = <400000>;
1757 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1758 dma-names = "tx", "rx";
1760 pinctrl-names = "default", "sleep";
1761 pinctrl-0 = <&i2c6_default>;
1762 pinctrl-1 = <&i2c6_sleep>;
1763 #address-cells = <1>;
1765 status = "disabled";
1768 blsp_i2c7: i2c@c1b7000 {
1769 compatible = "qcom,i2c-qup-v2.2.1";
1770 reg = <0x0c1b7000 0x600>;
1771 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1773 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1774 <&gcc GCC_BLSP2_AHB_CLK>;
1775 clock-names = "core", "iface";
1776 clock-frequency = <400000>;
1777 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1778 dma-names = "tx", "rx";
1780 pinctrl-names = "default", "sleep";
1781 pinctrl-0 = <&i2c7_default>;
1782 pinctrl-1 = <&i2c7_sleep>;
1783 #address-cells = <1>;
1785 status = "disabled";
1788 blsp_i2c8: i2c@c1b8000 {
1789 compatible = "qcom,i2c-qup-v2.2.1";
1790 reg = <0x0c1b8000 0x600>;
1791 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1793 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1794 <&gcc GCC_BLSP2_AHB_CLK>;
1795 clock-names = "core", "iface";
1796 clock-frequency = <400000>;
1797 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1798 dma-names = "tx", "rx";
1800 pinctrl-names = "default", "sleep";
1801 pinctrl-0 = <&i2c8_default>;
1802 pinctrl-1 = <&i2c8_sleep>;
1803 #address-cells = <1>;
1805 status = "disabled";
1809 compatible = "simple-mfd";
1810 reg = <0x146bf000 0x1000>;
1812 #address-cells = <1>;
1815 ranges = <0 0x146bf000 0x1000>;
1818 compatible = "qcom,pil-reloc-info";
1823 camss: camss@ca00000 {
1824 compatible = "qcom,sdm660-camss";
1825 reg = <0x0c824000 0x1000>,
1827 <0x0c825000 0x1000>,
1829 <0x0c826000 0x1000>,
1837 <0x0ca10000 0x1000>,
1838 <0x0ca14000 0x1000>;
1839 reg-names = "csiphy0",
1853 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1854 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1855 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1856 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1857 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1858 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1859 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1860 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1861 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1862 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1863 interrupt-names = "csiphy0",
1873 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1874 <&mmcc THROTTLE_CAMSS_AXI_CLK>,
1875 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1876 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1877 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1878 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1879 <&mmcc CAMSS_CSI0_AHB_CLK>,
1880 <&mmcc CAMSS_CSI0_CLK>,
1881 <&mmcc CAMSS_CPHY_CSID0_CLK>,
1882 <&mmcc CAMSS_CSI0PIX_CLK>,
1883 <&mmcc CAMSS_CSI0RDI_CLK>,
1884 <&mmcc CAMSS_CSI1_AHB_CLK>,
1885 <&mmcc CAMSS_CSI1_CLK>,
1886 <&mmcc CAMSS_CPHY_CSID1_CLK>,
1887 <&mmcc CAMSS_CSI1PIX_CLK>,
1888 <&mmcc CAMSS_CSI1RDI_CLK>,
1889 <&mmcc CAMSS_CSI2_AHB_CLK>,
1890 <&mmcc CAMSS_CSI2_CLK>,
1891 <&mmcc CAMSS_CPHY_CSID2_CLK>,
1892 <&mmcc CAMSS_CSI2PIX_CLK>,
1893 <&mmcc CAMSS_CSI2RDI_CLK>,
1894 <&mmcc CAMSS_CSI3_AHB_CLK>,
1895 <&mmcc CAMSS_CSI3_CLK>,
1896 <&mmcc CAMSS_CPHY_CSID3_CLK>,
1897 <&mmcc CAMSS_CSI3PIX_CLK>,
1898 <&mmcc CAMSS_CSI3RDI_CLK>,
1899 <&mmcc CAMSS_AHB_CLK>,
1900 <&mmcc CAMSS_VFE0_CLK>,
1901 <&mmcc CAMSS_CSI_VFE0_CLK>,
1902 <&mmcc CAMSS_VFE0_AHB_CLK>,
1903 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1904 <&mmcc CAMSS_VFE1_CLK>,
1905 <&mmcc CAMSS_CSI_VFE1_CLK>,
1906 <&mmcc CAMSS_VFE1_AHB_CLK>,
1907 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1908 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
1909 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>,
1910 <&mmcc CSIPHY_AHB2CRIF_CLK>,
1911 <&mmcc CAMSS_CPHY_CSID0_CLK>,
1912 <&mmcc CAMSS_CPHY_CSID1_CLK>,
1913 <&mmcc CAMSS_CPHY_CSID2_CLK>,
1914 <&mmcc CAMSS_CPHY_CSID3_CLK>;
1915 clock-names = "top_ahb",
1957 interconnects = <&mnoc 5 &bimc 5>;
1958 interconnect-names = "vfe-mem";
1959 iommus = <&mmss_smmu 0xc00>,
1963 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
1964 <&mmcc CAMSS_VFE1_GDSC>;
1965 status = "disabled";
1968 #address-cells = <1>;
1974 compatible = "qcom,msm8996-cci";
1975 #address-cells = <1>;
1977 reg = <0x0ca0c000 0x1000>;
1978 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1980 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1981 <&mmcc CAMSS_CCI_CLK>;
1982 assigned-clock-rates = <80800000>, <37500000>;
1983 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1984 <&mmcc CAMSS_CCI_AHB_CLK>,
1985 <&mmcc CAMSS_CCI_CLK>,
1986 <&mmcc CAMSS_AHB_CLK>;
1987 clock-names = "camss_top_ahb",
1992 pinctrl-names = "default";
1993 pinctrl-0 = <&cci0_default &cci1_default>;
1994 power-domains = <&mmcc CAMSS_TOP_GDSC>;
1995 status = "disabled";
1997 cci_i2c0: i2c-bus@0 {
1999 clock-frequency = <400000>;
2000 #address-cells = <1>;
2004 cci_i2c1: i2c-bus@1 {
2006 clock-frequency = <400000>;
2007 #address-cells = <1>;
2012 mmss_smmu: iommu@cd00000 {
2013 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2014 reg = <0x0cd00000 0x40000>;
2016 clocks = <&mmcc MNOC_AHB_CLK>,
2017 <&mmcc BIMC_SMMU_AHB_CLK>,
2018 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
2019 <&mmcc BIMC_SMMU_AXI_CLK>;
2020 clock-names = "iface-mm", "iface-smmu",
2021 "bus-mm", "bus-smmu";
2022 #global-interrupts = <2>;
2026 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2027 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2029 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2031 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2032 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2033 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2034 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2035 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2036 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2037 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2038 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2039 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2040 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2042 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2043 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2044 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2045 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2046 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2047 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2048 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
2049 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
2050 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2051 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2052 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
2054 status = "disabled";
2057 adsp_pil: remoteproc@15700000 {
2058 compatible = "qcom,sdm660-adsp-pas";
2059 reg = <0x15700000 0x4040>;
2061 interrupts-extended =
2062 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2063 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2064 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2065 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2066 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2067 interrupt-names = "wdog", "fatal", "ready",
2068 "handover", "stop-ack";
2070 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2073 memory-region = <&adsp_region>;
2074 power-domains = <&rpmpd SDM660_VDDCX>;
2075 power-domain-names = "cx";
2077 qcom,smem-states = <&adsp_smp2p_out 0>;
2078 qcom,smem-state-names = "stop";
2081 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2084 mboxes = <&apcs_glb 9>;
2085 qcom,remote-pid = <2>;
2086 #address-cells = <1>;
2090 compatible = "qcom,apr-v2";
2091 qcom,glink-channels = "apr_audio_svc";
2092 qcom,apr-domain = <APR_DOMAIN_ADSP>;
2093 #address-cells = <1>;
2097 reg = <APR_SVC_ADSP_CORE>;
2098 compatible = "qcom,q6core";
2101 q6afe: apr-service@4 {
2102 compatible = "qcom,q6afe";
2103 reg = <APR_SVC_AFE>;
2105 compatible = "qcom,q6afe-dais";
2106 #address-cells = <1>;
2108 #sound-dai-cells = <1>;
2112 q6asm: apr-service@7 {
2113 compatible = "qcom,q6asm";
2114 reg = <APR_SVC_ASM>;
2116 compatible = "qcom,q6asm-dais";
2117 #address-cells = <1>;
2119 #sound-dai-cells = <1>;
2120 iommus = <&lpass_smmu 1>;
2124 q6adm: apr-service@8 {
2125 compatible = "qcom,q6adm";
2126 reg = <APR_SVC_ADM>;
2127 q6routing: routing {
2128 compatible = "qcom,q6adm-routing";
2129 #sound-dai-cells = <0>;
2136 gnoc: interconnect@17900000 {
2137 compatible = "qcom,sdm660-gnoc";
2138 reg = <0x17900000 0xe000>;
2139 #interconnect-cells = <1>;
2141 * This one apparently features no clocks,
2142 * so let's not mess with the driver needlessly
2144 clock-names = "bus", "bus_a";
2145 clocks = <&xo_board>, <&xo_board>;
2148 apcs_glb: mailbox@17911000 {
2149 compatible = "qcom,sdm660-apcs-hmss-global";
2150 reg = <0x17911000 0x1000>;
2156 #address-cells = <1>;
2159 compatible = "arm,armv7-timer-mem";
2160 reg = <0x17920000 0x1000>;
2161 clock-frequency = <19200000>;
2165 interrupts = <0 8 0x4>,
2167 reg = <0x17921000 0x1000>,
2168 <0x17922000 0x1000>;
2173 interrupts = <0 9 0x4>;
2174 reg = <0x17923000 0x1000>;
2175 status = "disabled";
2180 interrupts = <0 10 0x4>;
2181 reg = <0x17924000 0x1000>;
2182 status = "disabled";
2187 interrupts = <0 11 0x4>;
2188 reg = <0x17925000 0x1000>;
2189 status = "disabled";
2194 interrupts = <0 12 0x4>;
2195 reg = <0x17926000 0x1000>;
2196 status = "disabled";
2201 interrupts = <0 13 0x4>;
2202 reg = <0x17927000 0x1000>;
2203 status = "disabled";
2208 interrupts = <0 14 0x4>;
2209 reg = <0x17928000 0x1000>;
2210 status = "disabled";
2214 intc: interrupt-controller@17a00000 {
2215 compatible = "arm,gic-v3";
2216 reg = <0x17a00000 0x10000>, /* GICD */
2217 <0x17b00000 0x100000>; /* GICR * 8 */
2218 #interrupt-cells = <3>;
2219 #address-cells = <1>;
2222 interrupt-controller;
2223 #redistributor-regions = <1>;
2224 redistributor-stride = <0x0 0x20000>;
2225 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2229 tcsr_mutex: hwlock {
2230 compatible = "qcom,tcsr-mutex";
2231 syscon = <&tcsr_mutex_regs 0 0x1000>;
2232 #hwlock-cells = <1>;
2240 polling-delay-passive = <250>;
2241 polling-delay = <1000>;
2243 thermal-sensors = <&tsens 0>;
2246 aoss_alert0: trip-point0 {
2247 temperature = <105000>;
2248 hysteresis = <1000>;
2255 polling-delay-passive = <250>;
2256 polling-delay = <1000>;
2258 thermal-sensors = <&tsens 1>;
2261 cpuss0_alert0: trip-point0 {
2262 temperature = <125000>;
2263 hysteresis = <1000>;
2270 polling-delay-passive = <250>;
2271 polling-delay = <1000>;
2273 thermal-sensors = <&tsens 2>;
2276 cpuss1_alert0: trip-point0 {
2277 temperature = <125000>;
2278 hysteresis = <1000>;
2285 polling-delay-passive = <250>;
2286 polling-delay = <1000>;
2288 thermal-sensors = <&tsens 3>;
2291 cpu0_alert0: trip-point0 {
2292 temperature = <70000>;
2293 hysteresis = <1000>;
2297 cpu0_crit: cpu_crit {
2298 temperature = <110000>;
2299 hysteresis = <1000>;
2306 polling-delay-passive = <250>;
2307 polling-delay = <1000>;
2309 thermal-sensors = <&tsens 4>;
2312 cpu1_alert0: trip-point0 {
2313 temperature = <70000>;
2314 hysteresis = <1000>;
2318 cpu1_crit: cpu_crit {
2319 temperature = <110000>;
2320 hysteresis = <1000>;
2327 polling-delay-passive = <250>;
2328 polling-delay = <1000>;
2330 thermal-sensors = <&tsens 5>;
2333 cpu2_alert0: trip-point0 {
2334 temperature = <70000>;
2335 hysteresis = <1000>;
2339 cpu2_crit: cpu_crit {
2340 temperature = <110000>;
2341 hysteresis = <1000>;
2348 polling-delay-passive = <250>;
2349 polling-delay = <1000>;
2351 thermal-sensors = <&tsens 6>;
2354 cpu3_alert0: trip-point0 {
2355 temperature = <70000>;
2356 hysteresis = <1000>;
2360 cpu3_crit: cpu_crit {
2361 temperature = <110000>;
2362 hysteresis = <1000>;
2369 * According to what downstream DTS says,
2370 * the entire power efficient cluster has
2371 * only a single thermal sensor.
2374 pwr-cluster-thermal {
2375 polling-delay-passive = <250>;
2376 polling-delay = <1000>;
2378 thermal-sensors = <&tsens 7>;
2381 pwr_cluster_alert0: trip-point0 {
2382 temperature = <70000>;
2383 hysteresis = <1000>;
2387 pwr_cluster_crit: cpu_crit {
2388 temperature = <110000>;
2389 hysteresis = <1000>;
2396 polling-delay-passive = <250>;
2397 polling-delay = <1000>;
2399 thermal-sensors = <&tsens 8>;
2402 gpu_alert0: trip-point0 {
2403 temperature = <90000>;
2404 hysteresis = <1000>;
2412 compatible = "arm,armv8-timer";
2413 interrupts = <GIC_PPI 1 0xf08>,